Another 16 L2C patches

So, in response to Matt Porter's complaint about breaking prima2, here's another 16 patches which changes the way the L2 cache is initialised on many platforms. This series moves towards a situation where the generic code initialises the L2 cache itself, with as little help as possible from board specific code.

A number of platforms are left alone because they're more complex - these should still eventually be converted.

At some point in the near future, I will see about sorting out their ordering wrt the previous patch set. For the time being, they apply on top of the existing l2c changes.

 arch/arm/include/asm/mach/arch.h  |  3 +++
 arch/arm/kernel/irq.c             | 12 ++++++++++++
 arch/arm/mach-bcm/bcm_5301x.c     |  9 ++-------
 arch/arm/mach-berlin/berlin.c     | 17 ++++++-----------
 arch/arm/mach-exynos/exynos.c     |  8 ++------
 arch/arm/mach-highbank/highbank.c |  9 +++------
 arch/arm/mach-imx/mach-vf610.c    |  9 ++-------
 arch/arm/mach-mvebu/board-v7.c    |  9 ++++++---
 arch/arm/mach-nomadik/cpu-8815.c  | 13 +++----------
 arch/arm/mach-prima2/Makefile     |  1 -
 arch/arm/mach-prima2/common.c     |  6 ++++++
 arch/arm/mach-prima2/l2x0.c       | 17 -----------------
 arch/arm/mach-rockchip/rockchip.c |  9 ++-------
 arch/arm/mach-socfpga/socfpga.c   |  9 ++-------
 arch/arm/mach-sti/board-dt.c      | 20 +++++---------------
 arch/arm/mach-tegra/tegra.c       | 12 +++---------
 arch/arm/mach-vexpress/v2m.c      |  3 ++-
 arch/arm/mach-zynq/common.c       |  8 +++-----
 18 files changed, 62 insertions(+), 112 deletions(-)

FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly
improving, and getting towards what was expected from it.

---
 arch/arm/mach-bcm/bcm_5301x.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

index edff69761e04..6bc9c31b1b0b 100644
@@ -45,7 +45,7 @@ static void __init bcm5301x_init_early(void)
 
 static void __init bcm5301x_dt_init(void)
 {
-	l2x0_of_init(0, ~0UL);
+	l2x0_of_init(0, ~0);
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 

1.8.3.1

Add a hook into the core ARM code to perform L2 cache initialisation in a platform independent manner. Platforms still get to indicate their auxiliary control register values and mask, but the initialisation call will now be made from generic code.

---
 arch/arm/include/asm/mach/arch.h |  3 +++
 arch/arm/kernel/irq.c            | 12 ++++++++++++
 2 files changed, 15 insertions(+)

index 17a3fa2979e8..5249cc3c52f4 100644
@@ -45,6 +45,9 @@ struct machine_desc {
 	unsigned char		reserve_lp1 :1;	/* never has lp1	*/
 	unsigned char		reserve_lp2 :1;	/* never has lp2	*/
 	enum reboot_mode	reboot_mode;	/* default restart mode	*/
+	unsigned		l2c_aux_val;	/* L2 cache aux value	*/
+	unsigned		l2c_aux_mask;	/* L2 cache aux mask	*/
+	void			(*l2c_write_sec)(unsigned long, unsigned);
 	struct smp_operations	*smp;		/* SMP operations	*/
 	bool			(*smp_init)(void);
 	void			(*fixup)(struct tag *, char **,

index 9723d17b8f38..2c4257604513 100644
@@ -37,6 +37,7 @@
 #include <linux/proc_fs.h>
 #include <linux/export.h>
 
+#include <asm/hardware/cache-l2x0.h>
 #include <asm/exception.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>

@@ -115,10 +116,21 @@ EXPORT_SYMBOL_GPL(set_irq_flags);
 
 void __init init_IRQ(void)
 {
+	int ret;
+
 	if (IS_ENABLED(CONFIG_OF) && !machine_desc->init_irq)
 		irqchip_init();
 	else
 		machine_desc->init_irq();
+
+	if (IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_CACHE_L2X0) &&
+	    (machine_desc->l2c_aux_mask || machine_desc->l2c_aux_val)) {
+		outer_cache.write_sec = machine_desc->l2c_write_sec;
+		ret = l2x0_of_init(machine_desc->l2c_aux_val,
+				   machine_desc->l2c_aux_mask);
+		if (ret)
+			pr_err("L2C: failed to init: %d\n", ret);
+	}
 }
 
 #ifdef CONFIG_MULTI_IRQ_HANDLER

1.8.3.1

[...]

Calling it with both set to zero results in the auxiliary control register being cleared to zero. We don't want that to happen.

FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly
improving, and getting towards what was expected from it.

Right, but we can make the core L2 init code only write aux ctrl if (aux_val && ~aux_mask). Then you don't have to add the values on a bunch of platforms.

Rob

I would rather add them right now rather than introduce new logic which _could_ potentially change the behaviour for an existing platform. Maybe that's an improvement to come after this series is merged, but I'm already up to almost 100 patches in this series right now, and I'll be damned if I'm going to change the behaviour of this stuff even more as part of a single series.

FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly
improving, and getting towards what was expected from it.

This also allows us to eliminate the .init_machine function.

---
 arch/arm/mach-rockchip/rockchip.c | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

index d252efe3747b..138b9975313a 100644
@@ -24,12 +24,6 @@
 #include <asm/hardware/cache-l2x0.h>
 #include "core.h"
 
-static void __init rockchip_dt_init(void)
-{
-	l2x0_of_init(0, ~0);
-	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-
 static const char * const rockchip_board_dt_compat[] = {
 	"rockchip,rk2928",
 	"rockchip,rk3066a",

@@ -39,7 +33,8 @@ static const char * const rockchip_board_dt_compat[] = {
 };
 
 DT_MACHINE_START(ROCKCHIP_DT, "Rockchip Cortex-A9 (Device Tree)")
+	.l2c_aux_val	= 0,
+	.l2c_aux_mask	= ~0,
 	.smp		= smp_ops(rockchip_smp_ops),
-	.init_machine	= rockchip_dt_init,
 	.dt_compat	= rockchip_board_dt_compat,
 MACHINE_END

1.8.3.1

This also allows us to eliminate the .init_machine function.

---
 arch/arm/mach-nomadik/cpu-8815.c | 13 +++----------
 1 file changed, 3 insertions(+), 10 deletions(-)

index 0f245bcc6b7e..9116ca476d7c 100644
@@ -143,23 +143,16 @@ static int __init cpu8815_mmcsd_init(void)
 }
 device_initcall(cpu8815_mmcsd_init);
 
-static void __init cpu8815_init_of(void)
-{
-#ifdef CONFIG_CACHE_L2X0
-	/* At full speed latency must be >=2, so 0x249 in low bits */
-	l2x0_of_init(0x00700249, 0xfe0fefff);
-#endif
-	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-
 static const char * cpu8815_board_compat[] = {
 	"calaosystems,usb-s8815",
 	NULL,
 };
 
 DT_MACHINE_START(NOMADIK_DT, "Nomadik STn8815")
+	/* At full speed latency must be >=2, so 0x249 in low bits */
+	.l2c_aux_val	= 0x00700249,
+	.l2c_aux_mask	= 0xfe0fefff,
 	.map_io		= cpu8815_map_io,
-	.init_machine	= cpu8815_init_of,
 	.restart	= cpu8815_restart,
 	.dt_compat      = cpu8815_board_compat,
 MACHINE_END

1.8.3.1

---
 arch/arm/mach-zynq/common.c | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

index 1e617a6dedc3..d1e992e6403e 100644
@@ -67,11 +67,6 @@ static void __init zynq_init_machine(void)
 {
 	struct platform_device_info devinfo = { .name = "cpufreq-cpu0", };
 
-	/*
-	 * 64KB way size, 8-way associativity, parity disabled
-	 */
-	l2x0_of_init(0x02000000, 0xf0ffffff);
-
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 
 	platform_device_register(&zynq_cpuidle_device);

@@ -133,6 +128,9 @@ static const char * const zynq_dt_match[] = {
 };
 
 DT_MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")
+	/* 64KB way size, 8-way associativity, parity disabled */
+	.l2c_aux_val	= 0x02000000,
+	.l2c_aux_mask	= 0xf0ffffff,
 	.smp		= smp_ops(zynq_smp_ops),
 	.map_io		= zynq_map_io,
 	.init_irq	= zynq_irq_init,

1.8.3.1

---
 arch/arm/mach-highbank/highbank.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

index 245e588859ec..8c35ae4ff176 100644
@@ -66,12 +66,6 @@ static void __init highbank_init_irq(void)
 
 	if (of_find_compatible_node(NULL, NULL, "arm,cortex-a9"))
 		highbank_scu_map_io();
-
-	/* Enable PL310 L2 Cache controller */
-	if (IS_ENABLED(CONFIG_CACHE_L2X0)) {
-		outer_cache.write_sec = highbank_l2c310_write_sec;
-		l2x0_of_init(0, ~0);
-	}
 }
 
 static void highbank_power_off(void)

@@ -185,6 +179,9 @@ DT_MACHINE_START(HIGHBANK, "Highbank")
 #if defined(CONFIG_ZONE_DMA) && defined(CONFIG_ARM_LPAE)
 	.dma_zone_size	= (4ULL * SZ_1G),
 #endif
+	.l2c_aux_val	= 0,
+	.l2c_aux_mask	= ~0,
+	.l2c_write_sec	= highbank_l2c310_write_sec,
 	.init_irq	= highbank_init_irq,
 	.init_machine	= highbank_init,
 	.dt_compat	= highbank_match,

1.8.3.1

---
 arch/arm/mach-tegra/tegra.c | 12 +++---------
 1 file changed, 3 insertions(+), 9 deletions(-)

index 1bc49f9db015..d90065e2552a 100644
@@ -70,20 +70,12 @@ u32 tegra_uart_config[3] = {
 	0,
 };
 
-static void __init tegra_init_cache(void)
-{
-#ifdef CONFIG_CACHE_L2X0
-	l2x0_of_init(0x3c400001, 0xc20fc3fe);
-#endif
-}
-
 static void __init tegra_init_early(void)
 {
 	of_register_trusted_foundations();
 	tegra_apb_io_init();
 	tegra_init_fuse();
 	tegra_cpu_reset_handler_init();
-	tegra_init_cache();
 	tegra_powergate_init();
 	tegra_hotplug_init();
 }

@@ -171,8 +163,10 @@ static const char * const tegra_dt_board_compat[] = {
 };
 
 DT_MACHINE_START(TEGRA_DT, "NVIDIA Tegra SoC (Flattened Device Tree)")
-	.map_io		= tegra_map_common_io,
 	.smp		= smp_ops(tegra_smp_ops),
+	.l2c_aux_val	= 0x3c400001,
+	.l2c_aux_mask	= 0xc20fc3fe,
+	.map_io		= tegra_map_common_io,
 	.init_early	= tegra_init_early,
 	.init_irq	= tegra_dt_init_irq,
 	.init_machine	= tegra_dt_init,

1.8.3.1

I moved it quite simply because I keep entries in order:

        unsigned                l2c_aux_val;    /* L2 cache aux value   */
        unsigned                l2c_aux_mask;   /* L2 cache aux mask    */
        void                    (*l2c_write_sec)(unsigned long, unsigned);
        struct smp_operations   *smp;           /* SMP operations       */
        bool                    (*smp_init)(void);
        void                    (*fixup)(struct tag *, char **,
                                         struct meminfo *);
        void                    (*init_meminfo)(void);
        void                    (*reserve)(void);/* reserve mem blocks  */
        void                    (*map_io)(void);/* IO mapping function  */
        void                    (*init_early)(void);

And the order of declaration in there (for the functions after "smp") is the order in which they are called during kernel initialisation. Platforms randomising their declarations is... silly. And yes, I'll move those l2c ones before .smp.

FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly
improving, and getting towards what was expected from it.

Along with this change, we can delete l2x0.c from prima2.

---
 arch/arm/mach-prima2/Makefile |  1 -
 arch/arm/mach-prima2/common.c |  6 ++++++
 arch/arm/mach-prima2/l2x0.c   | 17 -----------------
 3 files changed, 6 insertions(+), 18 deletions(-)
 delete mode 100644 arch/arm/mach-prima2/l2x0.c

index 7a6b4a323125..8846e7d87ea5 100644
@@ -2,7 +2,6 @@ obj-y += rstc.o
 obj-y += common.o
 obj-y += rtciobrg.o
 obj-$(CONFIG_DEBUG_LL) += lluart.o
-obj-$(CONFIG_CACHE_L2X0) += l2x0.o
 obj-$(CONFIG_SUSPEND) += pm.o sleep.o
 obj-$(CONFIG_SMP) += platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)  += hotplug.o

index 47c7819edb9b..1cdb8b565cfe 100644
@@ -34,6 +34,8 @@ static const char *atlas6_dt_match[] __initconst = {
 
 DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)")
 	/* Maintainer: Barry Song <[email protected]> */
+	.l2c_aux_val	= 0,
+	.l2c_aux_mask	= ~0,
 	.map_io         = sirfsoc_map_io,
 	.init_late	= sirfsoc_init_late,
 	.dt_compat      = atlas6_dt_match,

@@ -48,6 +50,8 @@ static const char *prima2_dt_match[] __initconst = {
 
 DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
 	/* Maintainer: Barry Song <[email protected]> */
+	.l2c_aux_val	= 0,
+	.l2c_aux_mask	= ~0,
 	.map_io         = sirfsoc_map_io,
 	.dma_zone_size	= SZ_256M,
 	.init_late	= sirfsoc_init_late,

@@ -64,6 +68,8 @@ static const char *marco_dt_match[] __initconst = {
 DT_MACHINE_START(MARCO_DT, "Generic MARCO (Flattened Device Tree)")
 	/* Maintainer: Barry Song <[email protected]> */
 	.smp            = smp_ops(sirfsoc_smp_ops),
+	.l2c_aux_val	= 0,
+	.l2c_aux_mask	= ~0,
 	.map_io         = sirfsoc_map_io,
 	.init_late	= sirfsoc_init_late,
 	.dt_compat      = marco_dt_match,

deleted file mode 100644
index 09f68f046830..000000000000
@@ -1,17 +0,0 @@
-/*
- * l2 cache initialization for CSR SiRFprimaII
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <asm/hardware/cache-l2x0.h>
-
-static int __init sirfsoc_l2x0_init(void)
-{
-	return l2x0_of_init(0, ~0);
-}
-early_initcall(sirfsoc_l2x0_init);

1.8.3.1

I can confirm that this approach fixes the boot failure on bcm281xx and bcm21664 against the previous set of l2c patches in -next.

Thanks,
Matt

Great, rather than taking that tested-by, I'll rework the patches such that we avoid the breakage through the patch series.

The resulting patch series is now around 100 patches long...

FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly
improving, and getting towards what was expected from it.

---
 arch/arm/mach-vexpress/v2m.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

index 4f8b8cb17ff5..b2fea70d412d 100644
@@ -432,7 +432,6 @@ static const struct of_device_id v2m_dt_bus_match[] __initconst = {
 
 static void __init v2m_dt_init(void)
 {
-	l2x0_of_init(0x00400000, 0xfe0fffff);
 	of_platform_populate(NULL, v2m_dt_bus_match, NULL, NULL);
 }
 

@@ -443,6 +442,8 @@ static const char * const v2m_dt_match[] __initconst = {
 
 DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express")
 	.dt_compat	= v2m_dt_match,
+	.l2c_aux_val	= 0x00400000,
+	.l2c_aux_mask	= 0xfe0fffff,
 	.smp		= smp_ops(vexpress_smp_ops),
 	.smp_init	= smp_init_ops(vexpress_smp_init_ops),
 	.map_io		= v2m_dt_map_io,

1.8.3.1

---
 arch/arm/mach-mvebu/board-v7.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

index c6bd79f64744..48169caa56ea 100644
@@ -59,9 +59,6 @@ static void __init mvebu_timer_and_clk_init(void)
 	clocksource_of_init();
 	coherency_init();
 	BUG_ON(mvebu_mbus_dt_init());
-#ifdef CONFIG_CACHE_L2X0
-	l2x0_of_init(0, ~0);
-#endif
 
 	if (of_machine_is_compatible("marvell,armada375"))
 		hook_fault_code(16 + 6, armada_375_external_abort_wa, SIGBUS, 0,

@@ -109,6 +106,8 @@ static const char * const armada_370_xp_dt_compat[] = {
 };
 
 DT_MACHINE_START(ARMADA_370_XP_DT, "Marvell Armada 370/XP (Device Tree)")
+	.l2c_aux_val	= 0,
+	.l2c_aux_mask	= ~0,
 	.smp		= smp_ops(armada_xp_smp_ops),
 	.init_machine	= mvebu_dt_init,
 	.init_time	= mvebu_timer_and_clk_init,

@@ -122,6 +121,8 @@ static const char * const armada_375_dt_compat[] = {
 };
 
 DT_MACHINE_START(ARMADA_375_DT, "Marvell Armada 375 (Device Tree)")
+	.l2c_aux_val	= 0,
+	.l2c_aux_mask	= ~0,
 	.init_time	= mvebu_timer_and_clk_init,
 	.restart	= mvebu_restart,
 	.dt_compat	= armada_375_dt_compat,

@@ -134,6 +135,8 @@ static const char * const armada_38x_dt_compat[] = {
 };
 
 DT_MACHINE_START(ARMADA_38X_DT, "Marvell Armada 380/385 (Device Tree)")
+	.l2c_aux_val	= 0,
+	.l2c_aux_mask	= ~0,
 	.init_time	= mvebu_timer_and_clk_init,
 	.restart	= mvebu_restart,
 	.dt_compat	= armada_38x_dt_compat,

1.8.3.1

This also allows us to eliminate the .init_machine function.

---
 arch/arm/mach-bcm/bcm_5301x.c | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

index 6bc9c31b1b0b..e9bcbdbce555 100644
@@ -43,19 +43,14 @@ static void __init bcm5301x_init_early(void)
 			"imprecise external abort");
 }
 
-static void __init bcm5301x_dt_init(void)
-{
-	l2x0_of_init(0, ~0);
-	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-
 static const char __initconst *bcm5301x_dt_compat[] = {
 	"brcm,bcm4708",
 	NULL,
 };
 
 DT_MACHINE_START(BCM5301X, "BCM5301X")
+	.l2c_aux_val	= 0,
+	.l2c_aux_mask	= ~0,
 	.init_early	= bcm5301x_init_early,
-	.init_machine	= bcm5301x_dt_init,
 	.dt_compat	= bcm5301x_dt_compat,
 MACHINE_END

1.8.3.1

Since the .init_irq method only calls irqchip_init, we can remove that too.

---
 arch/arm/mach-imx/mach-vf610.c | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

index 6288a9690e78..c44602758120 100644
@@ -20,19 +20,14 @@ static void __init vf610_init_machine(void)
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
-static void __init vf610_init_irq(void)
-{
-	l2x0_of_init(0, ~0);
-	irqchip_init();
-}
-
 static const char *vf610_dt_compat[] __initconst = {
 	"fsl,vf610",
 	NULL,
 };
 
 DT_MACHINE_START(VYBRID_VF610, "Freescale Vybrid VF610 (Device Tree)")
-	.init_irq	= vf610_init_irq,
+	.l2c_aux_val	= 0,
+	.l2c_aux_mask	= ~0,
 	.init_machine   = vf610_init_machine,
 	.dt_compat	= vf610_dt_compat,
 	.restart	= mxc_restart,

1.8.3.1

We can remove the .init_machine as it becomes the generic version.

---
 arch/arm/mach-sti/board-dt.c | 20 +++++---------------
 1 file changed, 5 insertions(+), 15 deletions(-)

index cf716ae10726..4924d2214be6 100644
@@ -14,19 +14,6 @@
 
 #include "smp.h"
 
-void __init stih41x_l2x0_init(void)
-{
-	l2x0_of_init(L2C_AUX_CTRL_SHARED_OVERRIDE |
-		     L310_AUX_CTRL_DATA_PREFETCH |
-		     L310_AUX_CTRL_INSTR_PREFETCH, 0xc00f0fff);
-}
-
-static void __init stih41x_machine_init(void)
-{
-	stih41x_l2x0_init();
-	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-
 static const char *stih41x_dt_match[] __initdata = {
 	"st,stih415",
 	"st,stih416",

@@ -34,7 +21,10 @@ static const char *stih41x_dt_match[] __initdata = {
 };
 
 DT_MACHINE_START(STM, "STiH415/416 SoC with Flattened Device Tree")
-	.init_machine	= stih41x_machine_init,
-	.smp		= smp_ops(sti_smp_ops),
 	.dt_compat	= stih41x_dt_match,
+	.l2c_aux_val	= L2C_AUX_CTRL_SHARED_OVERRIDE |
+			  L310_AUX_CTRL_DATA_PREFETCH |
+			  L310_AUX_CTRL_INSTR_PREFETCH,
+	.l2c_aux_mask	= 0xc00f0fff,
+	.smp		= smp_ops(sti_smp_ops),
 MACHINE_END

1.8.3.1

exynos was unconditionally calling the L2 cache initialisation from an early_initcall. This breaks multiplatform kernels. Thankfully, converting to generic l2c initialisation fixes this.

---
 arch/arm/mach-exynos/exynos.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

index fbfc29df3299..a763c0862da9 100644
@@ -316,12 +316,6 @@ static int __init exynos_core_init(void)
 }
 core_initcall(exynos_core_init);
 
-static int __init exynos4_l2x0_cache_init(void)
-{
-	return l2x0_of_init(0x3c400001, 0xc20fffff);
-}
-early_initcall(exynos4_l2x0_cache_init);
-
 static void __init exynos_dt_machine_init(void)
 {
 	struct device_node *i2c_np;

@@ -387,6 +381,8 @@ static void __init exynos_reserve(void)
 DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)")
 	/* Maintainer: Thomas Abraham <[email protected]> */
 	/* Maintainer: Kukjin Kim <[email protected]> */
+	.l2c_aux_val	= 0x3c400001,
+	.l2c_aux_mask	= 0xc20fffff,
 	.smp		= smp_ops(exynos_smp_ops),
 	.map_io		= exynos_init_io,
 	.init_early	= exynos_firmware_init,

1.8.3.1

---
 arch/arm/mach-socfpga/socfpga.c | 9 ++-------
 1 file changed, 2 insertions(+), 7 deletions(-)

index 9bbb8177f247..adbf38314ca8 100644
@@ -98,22 +98,17 @@ static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
 	writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
 }
 
-static void __init socfpga_cyclone5_init(void)
-{
-	l2x0_of_init(0, ~0);
-	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-
 static const char *altera_dt_match[] = {
 	"altr,socfpga",
 	NULL
 };
 
 DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
+	.l2c_aux_val	= 0,
+	.l2c_aux_mask	= ~0,
 	.smp		= smp_ops(socfpga_smp_ops),
 	.map_io		= socfpga_map_io,
 	.init_irq	= socfpga_init_irq,
-	.init_machine	= socfpga_cyclone5_init,
 	.restart	= socfpga_cyclone5_restart,
 	.dt_compat	= altera_dt_match,
 MACHINE_END

1.8.3.1

---
 arch/arm/mach-berlin/berlin.c | 17 ++++++-----------
 1 file changed, 6 insertions(+), 11 deletions(-)

index 6709d2a6bec8..ac181c6797ee 100644
@@ -18,16 +18,6 @@
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/arch.h>
 
-static void __init berlin_init_machine(void)
-{
-	/*
-	 * with DT probing for L2CCs, berlin_init_machine can be removed.
-	 * Note: 88DE3005 (Armada 1500-mini) uses pl310 l2cc
-	 */
-	l2x0_of_init(0x30c00000, 0xfeffffff);
-	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-
 static const char * const berlin_dt_compat[] = {
 	"marvell,berlin",
 	NULL,

@@ -35,5 +25,10 @@ static const char * const berlin_dt_compat[] = {
 
 DT_MACHINE_START(BERLIN_DT, "Marvell Berlin")
 	.dt_compat	= berlin_dt_compat,
-	.init_machine	= berlin_init_machine,
+	/*
+	 * with DT probing for L2CCs, berlin_init_machine can be removed.
+	 * Note: 88DE3005 (Armada 1500-mini) uses pl310 l2cc
+	 */
+	.l2c_aux_val	= 0x30c00000,
+	.l2c_aux_mask	= 0xfeffffff,
 MACHINE_END

1.8.3.1

Are "the existing l2c changes" in next-20140428? If not, is there a git branch I can pull to test the whole thing, rather than tracking down and applying "the existing l2c changes" first?

I guess they must be in linux-next, since this series applies cleanly on top of it.

So, patches 2/16 ("ARM: l2c: add platform independent core L2 cache initialisation") and 7/16 ("ARM: l2c: convert tegra to generic l2c initialisation"),

(On an NVIDIA Tegra20 Seaboard/Springbank board, on top of next-20140428)

I do see one error in dmesg during boot, but it doesn't appear to negatively affect operation in brief testing, and is present in linux-next without this series anyway. Is this message a problem?

^^^^^^ this is logged at error level

Correct, it's an error because on Tegra you explicitly set bit 0 in the auxiliary control register, which is pointless unless the feature is also enabled in the Cortex-A9 control register as well.

Rather than trying to track down everyone who does this, and then end up in a long discussion about it, I'm just going to make the kernel print an error message as a result, it's just wrong to set random bits in device control registers without first properly understanding what they're doing.

FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly
improving, and getting towards what was expected from it.

(Dropping most people from CC since this sub-thread is a Tegra-specific discussion)

...

Please forgive my almost complete lack of knowledge re: cache controllers. Is the correct fix for this:

a) To remove bit 0 from the aux_val passed to l2x0_of_init()

b) To set some BIT(3) in the Cortex-A9 auxcr, so this feature is enabled there too.

And if (b), I assume that's something that the bootloader should be doing, not the kernel?

Thanks.

See "Full line of zero write."

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0246h/CJACBHHB.html#CJADBCJJ

which makes it (a). The reverse steps are required when disabling the L2 cache controller.

If we decide that we encounter a platform which needs this feature disabled, the correct way to deal with that is to add a L2C-310 specific property to DT, and not to try to crowbar it in via the L2C aux control register masks (which should never have been exposed to platforms using DT.)

FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly
improving, and getting towards what was expected from it.

Do you say that simply because to make use of this feature, it also needs to be enabled in the A9 but no code in the kernel is currently doing that? Or, because enabling the feature stops the cache controller from supporting strongly ordered writes?

It seems like the condition this error message detects is benign; the cache controller is prepared to receive these transactions, but the A9 will never send them. Nothing can go wrong in this case, I believe, although admittedly it's a pointless configuration.

Equally, given the required enable sequence in that document, won't this error always get printed if BIT(0) is sent in aux_val; before the bit is enabled in the cache controller, the associated bit in the A9 /should/ be disabled. It seems like the test in the kernel should simply check if BIT(0) is set in aux_val and ignore the value in the A9 completely, if you want to ban people from enabling this feature via aux_val. Or, are there some platforms where something outside (before) the kernel enables the feature in the A9 even before the kernel cache init code runs, and you want to avoid printing the error in that case?

I assume /disabled/enabled/ there?

Yes, it's benign, but it's an unnecessary difference between platforms which stands in the way of trying to clean this crap up.

This is what I've been moaning about for a while: totally pointless differences between platforms which then stand in the way of future cleanups, because it's impossible to tell whether a difference is there because it's required or because (speaking plainly) the maintainer didn't have any clue what they were doing when the wrote the code.

The L2 cache code has suffered a lot from cargo cult programming, and other sloppiness - so yes, while it's benign, we can now also have a benign warning to encourage people not to do this kind of stuff.

The point here is that if we are going to enable various Cortex-A9 optimisations, the way it _should_ be done is that the L2 cache code makes that decision based on the revision of the parts found, and the only control which platforms should ever have is one to say "this feature is broken on platform X, please don't enable it" which that done via DT, and not via random values passed via an initialisation interface.

So, what this error is all about is:

- the platform maintainer decided to set bit 0 which enables a cortex-a9 specific feature, which is useless given that the enable bit in cortex-a9 is disabled.

- the platform maintainer is setting bits without thinking.

- platform maintainers copy code from other platforms without thinking (just look at all the crap uses of L2X0_AUX_CTRL_MASK which is only suitable for L2C-210, but gets used on everything.)

So once one person does it, it ends up propagating to other platforms, and the problem just spreads.

You're asking questions I have no answer to - and this is the whole problem here. Platform maintainers go off in their own tiny worlds, with blinkers on, doing their own crap without really knowing what the hell they're doing.

I've *no* clue whether there's a platform which gets this wrong and enables the FLZ bit in the CA9 control register. Given the kind of crap that we have in the kernel - with platforms just deciding to set bit 0 of the L2 cache auxiliary control register without taking any time to think, I have no reason to doubt that someone hasn't tried crap like that, and I have no doubt that it _could_ have worked for someone sufficiently to get into the kernel.

This is the whole problem: I have no idea what kind of bollocks platform maintainers do in their spare time.

Frankly, this is another in the long list of arm-soc failures: this is something that should have been fixed a /long/ time ago - it's far more important than getting rid of silly timex.h header files, and the problem is more pervasive. Instead, it was left, and left and left, and the problem has grown bigger and bigger.

So no, I'm not offering any sympathy here to anyone, partly because of the shere amount of effort that the L2 cache series has taken to get this far - and it's now soo big that it in itself is starting to become unmanageable. And with many platform maintainers not really taking an interest in it when it has been posted, I'm at the point where I just don't give a that much of a damn about their platform code unless they take an interest and help do some testing.

No, I meant what I said. Enable the optimistions by default. If someone whinges, we'll fix it, but *only* if it causes a failure. Any other solution is total madness, and doesn't get much in the way of interest.

It's easy to ignore a plea for help. It's impossible to ignore if it causes a problem.

We're only at this point _because_ I've forced people to take an interest in this code. I know most platform maintainers would rather not think about it, as evidenced by the wide-spread cargo-cult programming that has been going on here. The only way to get this sorted is to ram this kind of thing down people's throats. Yes, it's not a nice way to do it, but it's the only way.

Also, remember that I don't have these huge board farms that Olof and Kevin have - in comparison I'm a pauper when it comes to platforms I can directly test. This makes my job that much harder, especially when platform maintainers are uncooperative, and is why I resort to pushing such stuff into linux-next to _force_ the issue, after I've completed what testing I can do here, and given it a run through Olof's build system.

Olof's system is useless for remote debugging though, so it is of little value other than seeing how many platforms succeed or fail.

FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly
improving, and getting towards what was expected from it.

Am Montag, 28. April 2014, 17:56:31 schrieb Russell King - ARM Linux:

Patches 2/16 ("ARM: l2c: add platform independent core L2 cache initialisation") and 3/16 ("ARM: l2c: convert rockchip to generic l2c initialisation") applied on a linux-next from 20140428,