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arm: vf610: add DDR_SEL_PAD_CONTR register

PATCH New stefan at agner.ch 2 participants 2 messages Apr 23, 2014 – May 25, 2014

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stefan at agner.ch

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#0 lore raw

PATCH 1/1 arm: vf610: add DDR_SEL_PAD_CONTR register

From: Stefan Agner <[email protected]>

Set DDR_SEL_PAD_CONTR register explicitly to DDR3 which solves RAM issues with newer silicon (1.1). This register was added in revision 4 of the Vybrid Reference Manual.

Signed-off-by Stefan Agner <[email protected]>
---
 arch/arm/include/asm/arch-vf610/imx-regs.h | 1 +
 board/freescale/vf610twr/vf610twr.c        | 3 ++-
 2 files changed, 3 insertions(+), 1 deletion(-)
arch/arm/include/asm/arch-vf610/imx-regs.h +1 -0
index c2f9761..0c28e1b 100644
@@ -215,6 +215,7 @@
 #define DDRMC_CR139_PHY_WRLV_EN(v)			((v) & 0xff)
 #define DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(v)	(((v) & 0x1f) << 27)
 #define DDRMC_CR154_PAD_ZQ_MODE(v)			(((v) & 0x3) << 21)
+#define DDRMC_CR154_DDR_SEL_PAD_CONTR(v)		(((v) & 0x3) << 18)
 #define DDRMC_CR155_AXI0_AWCACHE			(1 << 10)
 #define DDRMC_CR155_PAD_ODT_BYTE1(v)			((v) & 0x7)
 #define DDRMC_CR158_TWR(v)				((v) & 0x3f)
board/freescale/vf610twr/vf610twr.c +2 -1
index 4ee74c0..d64d3aa 100644
@@ -217,7 +217,8 @@ void ddr_ctrl_init(void)
 		&ddrmr->cr[139]);
 
 	writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
-		DDRMC_CR154_PAD_ZQ_MODE(1), &ddrmr->cr[154]);
+		DDRMC_CR154_PAD_ZQ_MODE(1) |
+		DDRMC_CR154_DDR_SEL_PAD_CONTR(3), &ddrmr->cr[154]);
 	writel(DDRMC_CR155_AXI0_AWCACHE | DDRMC_CR155_PAD_ODT_BYTE1(2),
 		&ddrmr->cr[155]);
 	writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]);
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1.9.2
#1 lore raw

PATCH 1/1 arm: vf610: add DDR_SEL_PAD_CONTR register

Hi stefan at agner.ch,

Quoted 29 lines · stefan at agner.ch

From: Stefan Agner <[email protected]>

Set DDR_SEL_PAD_CONTR register explicitly to DDR3 which solves RAM issues with newer silicon (1.1). This register was added in revision 4 of the Vybrid Reference Manual.

Signed-off-by Stefan Agner <[email protected]>
---
 arch/arm/include/asm/arch-vf610/imx-regs.h | 1 +
 board/freescale/vf610twr/vf610twr.c        | 3 ++-
 2 files changed, 3 insertions(+), 1 deletion(-)
arch/arm/include/asm/arch-vf610/imx-regs.h +1 -0
index c2f9761..0c28e1b 100644
@@ -215,6 +215,7 @@
 #define DDRMC_CR139_PHY_WRLV_EN(v)			((v) & 0xff)
 #define DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(v)	(((v) & 0x1f) << 27)
 #define DDRMC_CR154_PAD_ZQ_MODE(v)			(((v) & 0x3) << 21)
+#define DDRMC_CR154_DDR_SEL_PAD_CONTR(v)		(((v) & 0x3) << 18)
 #define DDRMC_CR155_AXI0_AWCACHE			(1 << 10)
 #define DDRMC_CR155_PAD_ODT_BYTE1(v)			((v) & 0x7)
 #define DDRMC_CR158_TWR(v)				((v) & 0x3f)
board/freescale/vf610twr/vf610twr.c +0 -0
index 4ee74c0..d64d3aa 100644

board/freescale/vf610twr/vf610twr.c void ddr_ctrl_init(void) · line 224

Quoted 9 lines
board/freescale/vf610twr/vf610twr.c +2 -1
@@ -217,7 +217,8 @@ void ddr_ctrl_init(void)
 		&ddrmr->cr[139]);
 
 	writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
-		DDRMC_CR154_PAD_ZQ_MODE(1), &ddrmr->cr[154]);
+		DDRMC_CR154_PAD_ZQ_MODE(1) |
+		DDRMC_CR154_DDR_SEL_PAD_CONTR(3), &ddrmr->cr[154]);
 	writel(DDRMC_CR155_AXI0_AWCACHE | DDRMC_CR155_PAD_ODT_BYTE1(2),
 		&ddrmr->cr[155]);
 	writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]);

Applied to u-boot-arm/master, thanks!

Amicalement,

Signature · 1 line
Albert.