arm: ls102xa: Add Freescale LS102xA SoC and LS1021AQDS/TWR board support
Subsystems (8)
v2 cover arm: ls102xa: Add Freescale LS102xA SoC and LS1021AQDS/TWR board support
This series contain the support for Freescale LS102xA SoC and LS1021AQDS/TWR board.
PATCH v2 1/10 arm: ls102xa: Add Freescale LS102xA SoC support
The QorIQ LS1 family is built on Layerscape architecture, the industry's first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale.
Freescale LS102xA is a set of SoCs combines two ARM Cortex-A7 cores that have been optimized for high reliability and pack the highest level of integration available for sub-3 W embedded communications processors with Layerscape architecture and with a comprehensive enablement model focused on ease of programmability.
---
Change log:
v2: Add serdes support.
Update DDR frequency and data rate information. Fix overflow condition error for the timer.
arch/arm/cpu/armv7/ls102xa/Makefile | 12 + arch/arm/cpu/armv7/ls102xa/clock.c | 131 ++++++ arch/arm/cpu/armv7/ls102xa/cpu.c | 103 +++++ arch/arm/cpu/armv7/ls102xa/fdt.c | 73 ++++ arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c | 119 ++++++ arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.h | 12 + arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c | 41 ++ arch/arm/cpu/armv7/ls102xa/timer.c | 127 ++++++ arch/arm/include/asm/arch-ls102xa/clock.h | 23 ++ arch/arm/include/asm/arch-ls102xa/config.h | 69 ++++ arch/arm/include/asm/arch-ls102xa/fsl_serdes.h | 33 ++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 461 ++++++++++++++++++++++ arch/arm/include/asm/arch-ls102xa/imx-regs.h | 53 +++ arch/arm/include/asm/config.h | 4 + arch/arm/include/asm/io.h | 8 +- drivers/watchdog/Makefile | 2 +- 16 files changed, 1269 insertions(+), 2 deletions(-) create mode 100644 arch/arm/cpu/armv7/ls102xa/Makefile create mode 100644 arch/arm/cpu/armv7/ls102xa/clock.c create mode 100644 arch/arm/cpu/armv7/ls102xa/cpu.c create mode 100644 arch/arm/cpu/armv7/ls102xa/fdt.c create mode 100644 arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c create mode 100644 arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.h create mode 100644 arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c create mode 100644 arch/arm/cpu/armv7/ls102xa/timer.c create mode 100644 arch/arm/include/asm/arch-ls102xa/clock.h create mode 100644 arch/arm/include/asm/arch-ls102xa/config.h create mode 100644 arch/arm/include/asm/arch-ls102xa/fsl_serdes.h create mode 100644 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h create mode 100644 arch/arm/include/asm/arch-ls102xa/imx-regs.h
arch/arm/cpu/armv7/ls102xa/Makefile new file +12 -0
@@ -0,0 +1,12 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += cpu.o +obj-y += clock.o +obj-y += timer.o + +obj-$(CONFIG_OF_LIBFDT) += fdt.o +obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
arch/arm/cpu/armv7/ls102xa/clock.c new file +131 -0
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arch/arm/cpu/armv7/ls102xa/cpu.c new file +103 -0
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arch/arm/cpu/armv7/ls102xa/fdt.c new file +73 -0
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arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c new file +119 -0
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arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.h new file +12 -0
@@ -0,0 +1,12 @@ +/* +* Copyright 2014 Freescale Semiconductor, Inc. +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef __FSL_LS1_SERDES_H +#define __FSL_LS1_SERDES_H + +int is_serdes_prtcl_valid (int serdes,u32 prtcl); +int serdes_lane_enabled (int lane); +#endif /* __FSL_LS1_SERDES_H */
arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c new file +41 -0
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arch/arm/cpu/armv7/ls102xa/timer.c new file +127 -0
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arch/arm/include/asm/arch-ls102xa/clock.h new file +23 -0
@@ -0,0 +1,23 @@ +/* +* Copyright 2014 Freescale Semiconductor, Inc. +* +* SPDX-License-Identifier: GPL-2.0+ +* +*/ + +#ifndef __ASM_ARCH_LS102XA_CLOCK_H_ +#define __ASM_ARCH_LS102XA_CLOCK_H_ + +#include <common.h> + +enum mxc_clock { +MXC_ARM_CLK =0 , +MXC_UART_CLK , +MXC_ESDHC_CLK , +MXC_I2C_CLK , +MXC_DSPI_CLK , +}; + +unsigned int mxc_get_clock (enum mxc_clock clk); + +#endif /* __ASM_ARCH_LS102XA_CLOCK_H_ */
arch/arm/include/asm/arch-ls102xa/config.h new file +69 -0
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arch/arm/include/asm/arch-ls102xa/fsl_serdes.h new file +33 -0
@@ -0,0 +1,33 @@ +/* +* Copyright 2014 Freescale Semiconductor, Inc. +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef __FSL_SERDES_H +#define __FSL_SERDES_H + +#include <config.h> + +enum srds_prtcl { +NONE =0 , +PCIE1 , +PCIE2 , +SATA1 , +SGMII_TSEC1 , +SGMII_TSEC2 , +}; + +enum srds { +FSL_SRDS_1 =0 , +FSL_SRDS_2 =1 , +}; + +int is_serdes_configured (enum srds_prtcl device); +void fsl_serdes_init (void ); +const char *serdes_clock_to_string (u32 clock); + +int serdes_get_first_lane (u32 sd,enum srds_prtcl device); +enum srds_prtcl serdes_get_prtcl (int serdes,int cfg,int lane); + +#endif /* __FSL_SERDES_H */
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h new file +461 -0
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arch/arm/include/asm/arch-ls102xa/imx-regs.h new file +53 -0
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arch/arm/include/asm/config.h +4 -0
@@ -17,4 +17,8 @@#define CONFIG_STATIC_RELA #endif +#ifdef CONFIG_LS102xA +#include <asm/arch/config.h> +#endif +#endif
arch/arm/include/asm/io.h +7 -1
@@ -367,7 +367,12 @@ out: return retval; } -#elif !defined(readb) +#else +#define memset_io (a, b, c) memset((void *)(a), (b), (c)) +#define memcpy_fromio (a, b, c) memcpy((a), (void *)(b), (c)) +#define memcpy_toio (a, b, c) memcpy((void *)(a), (b), (c)) + +#if !defined(readb)#define readb (addr) (__readwrite_bug("readb"),0)#define readw (addr) (__readwrite_bug("readw"),0)
@@ -380,6 +385,7 @@ out:#define check_signature (io,sig,len) (0) +#endif #endif /* __mem_pci */ /*
drivers/watchdog/Makefile +1 -1
@@ -7,7 +7,7 @@ obj-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o -ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 vf610)) +ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 vf610 ls102xa)) obj-y += imx_watchdog.o endif obj-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o
Signature · 1 line
1.8.0
PATCH v2 1/10 arm: ls102xa: Add Freescale LS102xA SoC support
Quoted 15 lines · Alison Wang
The QorIQ LS1 family is built on Layerscape architecture, the industry's first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale.
Freescale LS102xA is a set of SoCs combines two ARM Cortex-A7 cores that have been optimized for high reliability and pack the highest level of integration available for sub-3 W embedded communications processors with Layerscape architecture and with a comprehensive enablement model focused on ease of programmability.
Signed-off-by Alison Wang <[email protected]>Signed-off-by Jason Jin <[email protected]>Signed-off-by Jingchang Lu <[email protected]>Signed-off-by Prabhakar Kushwaha <[email protected]>
Quoted 6 lines
---
Change log:
v2: Add serdes support.
Update DDR frequency and data rate information. Fix overflow condition error for the timer.
Albert,
As you can see, Freescale starts to make ARM core SoCs on QorIQ product line. As previously discussed, I will maintain fsl-qoriq repository to host these patches. Beside ARMv8, I am new to ARM cores. To start, I would like to solicit your comments/ack for this series.
It will be helpful if you can share how ARM maintainers do the daily jobs like sending notice, pull requests, etc.
York
PATCH v2 2/10 arm: ls102xa: Add i2c support for LS102xA
In reply to Alison Wang---
Change log:
v2: no change.
drivers/i2c/mxc_i2c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/i2c/mxc_i2c.c +1 -1
@@ -423,7 +423,7 @@ static void * const i2c_bases[] = { (void *)IMX_I2C2_BASE#elif defined(CONFIG_MX31 ) || defined(CONFIG_MX35 ) || \ defined(CONFIG_MX51 ) || defined(CONFIG_MX53 ) || \ - defined(CONFIG_MX6 ) + defined(CONFIG_MX6 ) || defined(CONFIG_LS102xA) (void *)I2C1_BASE_ADDR , (void *)I2C2_BASE_ADDR , (void *)I2C3_BASE_ADDR
Signature · 1 line
1.8.0
PATCH v2 3/10 net: Merge asm/fsl_enet.h into fsl_mdio.h
In reply to Alison WangFrom: Claudiu Manoil <[email protected]>
fsl_enet.h defines the mapping of the usual MII management registers, which are included in the MDIO register block common to Freescale ethernet controllers. So it shouldn't depend on the CPU architecture but it should be actually part of the arch independent fsl_mdio.h.
To remove the arch dependency, merge the content of asm/fsl_enet.h into fsl_mdio.h.
Some files (like fm_eth.h) were simply including fsl_enet.h only for phy.h. These were updated to include phy.h instead.
---
Change log:
v2: no change.
arch/powerpc/include/asm/fsl_enet.h | 24 ------------------------ board/freescale/mpc8360emds/mpc8360emds.c | 2 +- board/freescale/mpc837xemds/mpc837xemds.c | 1 - drivers/net/fm/dtsec.c | 1 - drivers/net/fm/fm.h | 2 +- drivers/net/fm/init.c | 1 + drivers/net/fm/memac.c | 1 - drivers/net/fm/tgec.c | 1 - drivers/net/fsl_mdio.c | 1 - drivers/qe/uec.h | 1 - include/fm_eth.h | 2 +- include/fsl_mdio.h | 13 ++++++++++++- include/tsec.h | 2 +- 13 files changed, 17 insertions(+), 35 deletions(-) delete mode 100644 arch/powerpc/include/asm/fsl_enet.h
arch/powerpc/include/asm/fsl_enet.h deleted +0 -24
@@ -1,24 +0,0 @@ -/* -* Copyright 2010 Freescale Semiconductor, Inc. -* -* SPDX-License-Identifier: GPL-2.0+ -*/ - -#ifndef __ASM_PPC_FSL_ENET_H -#define __ASM_PPC_FSL_ENET_H - -#include <phy.h> - -struct tsec_mii_mng { -u32 miimcfg;/* MII management configuration reg */ -u32 miimcom;/* MII management command reg */ -u32 miimadd;/* MII management address reg */ -u32 miimcon;/* MII management control reg */ -u32 miimstat;/* MII management status reg */ -u32 miimind;/* MII management indication reg */ -u32 ifstat;/* Interface Status Register */ -} __attribute__ ((packed)); - -int fdt_fixup_phy_connection (void *blob,int offset,phy_interface_t phyc); - -#endif /* __ASM_PPC_FSL_ENET_H */
board/freescale/mpc8360emds/mpc8360emds.c +1 -1
@@ -11,13 +11,13 @@#include <i2c.h> #include <miiphy.h> #include <phy.h> +#include <fsl_mdio.h> #if defined(CONFIG_PCI )#include <pci.h> #endif #include <spd_sdram.h> #include <asm/mmu.h> #include <asm/io.h> -#include <asm/fsl_enet.h> #include <asm/mmu.h> #if defined(CONFIG_OF_LIBFDT )#include <libfdt.h>
board/freescale/mpc837xemds/mpc837xemds.c +0 -1
@@ -10,7 +10,6 @@#include <i2c.h> #include <asm/io.h> #include <asm/fsl_mpc83xx_serdes.h> -#include <asm/fsl_enet.h> #include <spd_sdram.h> #include <tsec.h> #include <libfdt.h>
drivers/net/fm/dtsec.c +0 -1
@@ -7,7 +7,6 @@#include <common.h> #include <asm/types.h> #include <asm/io.h> -#include <asm/fsl_enet.h> #include <asm/fsl_dtsec.h> #include <fsl_mdio.h> #include <phy.h>
drivers/net/fm/fm.h +1 -1
@@ -8,8 +8,8 @@#define __FM_H__#include <common.h> +#include <phy.h> #include <fm_eth.h> -#include <asm/fsl_enet.h> #include <asm/fsl_fman.h> /* Port ID */
drivers/net/fm/init.c +1 -0
@@ -6,6 +6,7 @@#include <common.h> #include <asm/io.h> #include <asm/fsl_serdes.h> +#include <fsl_mdio.h> #include "fm.h"
drivers/net/fm/memac.c +0 -1
@@ -12,7 +12,6 @@#include <phy.h> #include <asm/types.h> #include <asm/io.h> -#include <asm/fsl_enet.h> #include <asm/fsl_memac.h> #include "fm.h"
drivers/net/fm/tgec.c +0 -1
@@ -12,7 +12,6 @@#include <phy.h> #include <asm/types.h> #include <asm/io.h> -#include <asm/fsl_enet.h> #include <asm/fsl_tgec.h> #include "fm.h"
drivers/net/fsl_mdio.c +0 -1
@@ -11,7 +11,6 @@#include <fsl_mdio.h> #include <asm/io.h> #include <asm/errno.h> -#include <asm/fsl_enet.h> void tsec_local_mdio_write (struct tsec_mii_mng __iomem *phyregs,int port_addr,int dev_addr,int regnum,int value)
drivers/qe/uec.h +0 -1
@@ -13,7 +13,6 @@#include "qe.h" #include "uccf.h" #include <phy.h> -#include <asm/fsl_enet.h> #define MAX_TX_THREADS 8#define MAX_RX_THREADS 8
include/fm_eth.h +1 -1
@@ -8,8 +8,8 @@#define __FM_ETH_H__#include <common.h> +#include <phy.h> #include <asm/types.h> -#include <asm/fsl_enet.h> enum fm_port {FM1_DTSEC1 ,
include/fsl_mdio.h +12 -1
@@ -10,7 +10,18 @@#include <net.h> #include <miiphy.h> -#include <asm/fsl_enet.h> + +struct tsec_mii_mng { +u32 miimcfg;/* MII management configuration reg */ +u32 miimcom;/* MII management command reg */ +u32 miimadd;/* MII management address reg */ +u32 miimcon;/* MII management control reg */ +u32 miimstat;/* MII management status reg */ +u32 miimind;/* MII management indication reg */ +u32 ifstat;/* Interface Status Register */ +} __packed; + +int fdt_fixup_phy_connection (void *blob,int offset,phy_interface_t phyc);/* PHY register offsets */ #define PHY_EXT_PAGE_ACCESS 0x1f
include/tsec.h +1 -1
@@ -20,7 +20,7 @@#include <net.h> #include <config.h> #include <phy.h> -#include <asm/fsl_enet.h> +#include <fsl_mdio.h> #define TSEC_SIZE 0x01000#define TSEC_MDIO_OFFSET 0x01000
Signature · 1 line
1.8.0
PATCH v2 4/10 arm: ls102xa: Add etsec support for LS102xA
In reply to Alison Wang---
Change log:
v2: Add private mdio read and write support.
drivers/net/fsl_mdio.c | 24 +++++++++++++++++++----- drivers/net/tsec.c | 7 +++++++ include/fsl_mdio.h | 3 +++ include/tsec.h | 7 ++++++- 4 files changed, 35 insertions(+), 6 deletions(-)
drivers/net/fsl_mdio.c +19 -5
@@ -12,6 +12,15 @@#include <asm/io.h> #include <asm/errno.h> +void tsec_mdio_sync (void ) +{ +#if defined(CONFIG_PPC ) + asm("sync" ); +#elif defined(CONFIG_ARM ) + asm("dsb" ); +#endif +} +void tsec_local_mdio_write (struct tsec_mii_mng __iomem *phyregs,int port_addr,int dev_addr,int regnum,int value) {
@@ -19,7 +28,7 @@ void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr,out_be32 (&phyregs->miimadd, (port_addr <<8 ) | (regnum &0x1f ));out_be32 (&phyregs->miimcon, value); - asm("sync" ); +tsec_mdio_sync ();while ((in_be32 (&phyregs->miimind) &MIIMIND_BUSY ) && timeout--) ;
@@ -37,11 +46,11 @@ int tsec_local_mdio_read(struct tsec_mii_mng __iomem *phyregs, int port_addr,/* Clear the command register, and wait */ out_be32 (&phyregs->miimcom,0 ); - asm("sync" ); +tsec_mdio_sync ();/* Initiate a read command, and wait */ out_be32 (&phyregs->miimcom,MIIMCOM_READ_CYCLE ); - asm("sync" ); +tsec_mdio_sync ();/* Wait for the the indication that the read is done */ while ((in_be32(&phyregs->miimind) & (MIIMIND_NOTVALID | MIIMIND_BUSY))
@@ -98,8 +107,13 @@ int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info)return -1 ; } - bus->read = tsec_phy_read; - bus->write = tsec_phy_write; +if (info->priv_mdio_read) { + bus->read = info->priv_mdio_read; + bus->write = info->priv_mdio_write; + }else { + bus->read = tsec_phy_read; + bus->write = tsec_phy_write; + } bus->reset = fsl_pq_mdio_reset;sprintf (bus->name, info->name);
drivers/net/tsec.c +7 -0
@@ -20,6 +20,7 @@#include <fsl_mdio.h> #include <asm/errno.h> #include <asm/processor.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR ;
@@ -270,6 +271,9 @@ void redundant_init(struct eth_device *dev)out_be32 (®s->tstat,TSTAT_CLEAR_THALT );out_be32 (®s->rstat,RSTAT_CLEAR_RHALT );clrbits_be32 (®s->dmactrl,DMACTRL_GRS |DMACTRL_GTS ); +#ifdef CONFIG_LS102xA +setbits_be32 (®s->dmactrl,DMACTRL_LE ); +#endif do { uint16_t status;
@@ -366,6 +370,9 @@ static void startup_tsec(struct eth_device *dev)out_be32 (®s->tstat,TSTAT_CLEAR_THALT );out_be32 (®s->rstat,RSTAT_CLEAR_RHALT );clrbits_be32 (®s->dmactrl,DMACTRL_GRS |DMACTRL_GTS ); +#ifdef CONFIG_LS102xA +setbits_be32 (®s->dmactrl,DMACTRL_LE ); +#endif }/* This returns the status bits of the device. The return value
include/fsl_mdio.h +3 -0
@@ -57,6 +57,9 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,struct fsl_pq_mdio_info {struct tsec_mii_mng __iomem *regs;char *name; +int (*priv_mdio_read)(struct mii_dev *bus,int addr,int devad,int reg); +int (*priv_mdio_write)(struct mii_dev *bus,int addr,int devad,int reg, +u16 val); };int fsl_pq_mdio_init (bd_t *bis,struct fsl_pq_mdio_info *info);
include/tsec.h +6 -1
@@ -20,10 +20,14 @@#include <net.h> #include <config.h> #include <phy.h> -#include <fsl_mdio.h> +#ifdef CONFIG_LS102xA +#define TSEC_SIZE 0x40000 +#define TSEC_MDIO_OFFSET 0x40000 +#else #define TSEC_SIZE 0x01000#define TSEC_MDIO_OFFSET 0x01000 +#endif #define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520)
@@ -128,6 +132,7 @@#define DMACTRL_INIT_SETTINGS 0x000000c3#define DMACTRL_GRS 0x00000010#define DMACTRL_GTS 0x00000008 +#define DMACTRL_LE 0x00008000#define TSTAT_CLEAR_THALT 0x80000000#define RSTAT_CLEAR_RHALT 0x00800000
Signature · 1 line
1.8.0
PATCH v2 4/10 arm: ls102xa: Add etsec support for LS102xA
On 07/03/2014 12:24 AM, Alison Wang wrote:
Missing commit message here.
Quoted 32 lines
Signed-off-by Alison Wang <[email protected]>---
Change log:
v2: Add private mdio read and write support.drivers/net/fsl_mdio.c | 24 +++++++++++++++++++----- drivers/net/tsec.c | 7 +++++++ include/fsl_mdio.h | 3 +++ include/tsec.h | 7 ++++++- 4 files changed, 35 insertions(+), 6 deletions(-)drivers/net/fsl_mdio.c +9
-0@@ -12,6 +12,15 @@#include <asm/io.h> #include <asm/errno.h> +void tsec_mdio_sync (void ) +{ +#if defined(CONFIG_PPC ) + asm("sync" ); +#elif defined(CONFIG_ARM ) + asm("dsb" ); +#endif +} +void tsec_local_mdio_write (struct tsec_mii_mng __iomem *phyregs,int port_addr,int dev_addr,int regnum,int value) {
drivers/net/fsl_mdio.c void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr, · line 32
Quoted 6 lines
drivers/net/fsl_mdio.c +1
-1@@ -19,7 +28,7 @@ void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr,out_be32 (&phyregs->miimadd, (port_addr <<8 ) | (regnum &0x1f ));out_be32 (&phyregs->miimcon, value); - asm("sync" ); +tsec_mdio_sync ();
Don't reinvent the wheel. You can use mb() where you use tsec_mdio_sync();
York
PATCH v2 4/10 arm: ls102xa: Add etsec support for LS102xA
On 07/03/2014 12:24 AM, Alison Wang wrote:
Missing commit message here.
[Alison Wang] Yes, I will add in v3.
Quoted 33 lines
Signed-off-by: Alison Wang <[hidden email]>
---
Change log:
v2: Add private mdio read and write support.drivers/net/fsl_mdio.c | 24 +++++++++++++++++++----- drivers/net/tsec.c | 7 +++++++ include/fsl_mdio.h | 3 +++ include/tsec.h | 7 ++++++- 4 files changed, 35 insertions(+), 6 deletions(-)drivers/net/fsl_mdio.c +9
-0@@ -12,6 +12,15 @@#include <asm/io.h> #include <asm/errno.h> +void tsec_mdio_sync (void ) +{ +#if defined(CONFIG_PPC ) + asm("sync" ); +#elif defined(CONFIG_ARM ) + asm("dsb" ); +#endif +} +void tsec_local_mdio_write (struct tsec_mii_mng __iomem *phyregs,int port_addr,int dev_addr,int regnum,int value){
drivers/net/fsl_mdio.c void tsec_local_mdio_write(struct tsec_mii_mng __iomem · line 33
Quoted 7 lines
drivers/net/fsl_mdio.c +1
-1@@ -19,7 +28,7 @@ void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr,out_be32 (&phyregs->miimadd, (port_addr <<8 ) | (regnum &0x1f ));out_be32 (&phyregs->miimcon, value); - asm("sync" ); +tsec_mdio_sync ();
Don't reinvent the wheel. You can use mb() where you use tsec_mdio_sync();
[Alison Wang] Yes, I will change in v3. Thanks.
Best Regards,
Alison Wang
--
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PATCH v2 5/10 arm: ls102xa: Add esdhc support for LS102xA
In reply to Alison Wang---
Change log:
v2: no change.
drivers/mmc/fsl_esdhc.c | 4 ++-- include/fsl_esdhc.h | 14 +++++++++++++- 2 files changed, 15 insertions(+), 3 deletions(-)
drivers/mmc/fsl_esdhc.c +2 -2
@@ -96,7 +96,7 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)else if (cmd->resp_type &MMC_RSP_PRESENT ) xfertyp |=XFERTYP_RSPTYP_48 ; -#if defined(CONFIG_MX53 ) || defined(CONFIG_PPC_T4240 ) +#if defined(CONFIG_MX53 ) || defined(CONFIG_PPC_T4240 ) || defined(CONFIG_LS102xA)if (cmd->cmdidx ==MMC_CMD_STOP_TRANSMISSION ) xfertyp |=XFERTYP_CMDTYP_ABORT ;#endif
@@ -561,7 +561,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)memset (&cfg->cfg,0 ,sizeof (cfg->cfg)); voltage_caps =0 ; - caps = regs->hostcapblt; + caps =esdhc_read32 (®s->hostcapblt);#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
include/fsl_esdhc.h +13 -1
@@ -162,7 +162,19 @@ struct fsl_esdhc_cfg { };/* Select the correct accessors depending on endianess */ -#if __BYTE_ORDER == __LITTLE_ENDIAN +#if definedCONFIG_SYS_FSL_ESDHC_LE +#define esdhc_read32 in_le32 +#define esdhc_write32 out_le32 +#define esdhc_clrsetbits32 clrsetbits_le32 +#define esdhc_clrbits32 clrbits_le32 +#define esdhc_setbits32 setbits_le32 +#elif defined(CONFIG_SYS_FSL_ESDHC_BE ) +#define esdhc_read32 in_be32 +#define esdhc_write32 out_be32 +#define esdhc_clrsetbits32 clrsetbits_be32 +#define esdhc_clrbits32 clrbits_be32 +#define esdhc_setbits32 setbits_be32 +#elif __BYTE_ORDER == __LITTLE_ENDIAN#define esdhc_read32 in_le32#define esdhc_write32 out_le32#define esdhc_clrsetbits32 clrsetbits_le32
Signature · 1 line
1.8.0
PATCH v2 5/10 arm: ls102xa: Add esdhc support for LS102xA
On 07/03/2014 12:24 AM, Alison Wang wrote:
Missing commit message here. You should explain why we need this change. It will help us search the log later.
Quoted 2 lines
Signed-off-by Alison Wang <[email protected]>---
York
PATCH v2 5/10 arm: ls102xa: Add esdhc support for LS102xA
On 07/03/2014 12:24 AM, Alison Wang wrote:
Missing commit message here. You should explain why we need this change. It will
help us search the log later.
[Alison Wang] I will add commit message in v3.
Quoted 2 lines
Signed-off-by Alison Wang <[hidden email]>---
Best Regards,
Alison Wang
--
View this message in context: http://u-boot.10912.n7.nabble.com/PATCH-v2-0-9-arm-ls102xa-Add-Freescale-LS102xA-SoC-and-LS1021AQDS-TWR-board-support-tp183468p186447.html
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PATCH v2 6/10 driver/ddr/freescale: Add support of accumulate ECC
In reply to Alison WangFrom: York Sun <[email protected]>
If less than 8 ECC pins are used for DDR data bus width smaller than 64 bits, the 8-bit ECC code will be transmitted/received across several beats, and it will be used to check 64-bits of data once 8-bits of ECC are accumulated.
---
Change log:
v2: no change.
drivers/ddr/fsl/ctrl_regs.c | 5 +++++ 1 file changed, 5 insertions(+)
drivers/ddr/fsl/ctrl_regs.c +5 -0
@@ -693,6 +693,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,unsigned int x32_en =0 ;/* x32 enable */ unsigned int pchb8 =0 ;/* precharge bit 8 enable */ unsigned int hse;/* Global half strength override */ +unsigned int acc_ecc_en =0 ;/* Accumulated ECC enable */ unsigned int mem_halt =0 ;/* memory controller halt */ unsigned int bi =0 ;/* Bypass initialization */
@@ -736,6 +737,9 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, ba_intlv_ctl = popts->ba_intlv_ctl; hse = popts->half_strength_driver_enable; +/* set when ddr bus width < 64 */ + acc_ecc_en = (dbw !=0 && ecc_en ==1 ) ?1 :0 ; + ddr->ddr_sdram_cfg = (0 | ((mem_en &0x1 ) <<31 ) | ((sren & 0x1) << 30)
@@ -752,6 +756,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, | ((x32_en & 0x1) << 5) | ((pchb8 &0x1 ) <<4 ) | ((hse &0x1 ) <<3 ) + | ((acc_ecc_en &0x1 ) <<2 ) | ((mem_halt &0x1 ) <<1 ) | ((bi &0x1 ) <<0 ) );
Signature · 1 line
1.8.0
PATCH v2 7/10 driver/ddr/freescale: Fix DDR3 driver for ARM
In reply to Alison WangFrom: York Sun <[email protected]>
Reading DDR register should use ddr_in32() for proper endianess. This patch fixes incorrect waiting time for ARM platforms.
---
Change log:
v2: no change.
drivers/ddr/fsl/arm_ddr_gen3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/ddr/fsl/arm_ddr_gen3.c +1 -1
@@ -194,7 +194,7 @@ step2:* For example, 2GB on 666MT/s 64-bit bus takes about 402ms * Let's wait for 800ms */ - bus_width =3 - ((ddr->sdram_cfg &SDRAM_CFG_DBW_MASK ) + bus_width =3 - ((ddr_in32 (&ddr->sdram_cfg) &SDRAM_CFG_DBW_MASK ) >>SDRAM_CFG_DBW_SHIFT ); timeout = ((total_gb_size_per_controller << (6 - bus_width)) *100 / (get_ddr_freq (0 ) >>20 )) <<1 ;
Signature · 1 line
1.8.0
PATCH v2 8/10 driver/ddr/fsl: Add support of overriding chip select write leveling
In reply to Alison WangFrom: York Sun <[email protected]>
JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This is not an issue unless some DQ pins are not connected. If a platform uses regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on those floating pins for the second rank. The workaround is to use a known good chip select for this purpose.
---
Change log:
v2: no change.
drivers/ddr/fsl/ctrl_regs.c | 3 +++ drivers/ddr/fsl/interactive.c | 2 ++ include/fsl_ddr_sdram.h | 2 ++ 3 files changed, 7 insertions(+)
drivers/ddr/fsl/ctrl_regs.c +3 -0
@@ -2273,6 +2273,9 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,if (ip_rev >0x40400 ) unq_mrs_en =1 ; +if (ip_rev >0x40700 ) + ddr->debug[18 ] = popts->cswl_override; +set_ddr_sdram_cfg_2 (ddr, popts, unq_mrs_en);set_ddr_sdram_mode (ddr, popts, common_dimm, cas_latency, additive_latency, unq_mrs_en);
drivers/ddr/fsl/interactive.c +2 -0
@@ -511,6 +511,7 @@ static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,CTRL_OPTIONS (wrlvl_override),CTRL_OPTIONS (wrlvl_sample),CTRL_OPTIONS (wrlvl_start), +CTRL_OPTIONS (cswl_override),CTRL_OPTIONS (rcw_override),CTRL_OPTIONS (rcw_1), CTRL_OPTIONS(rcw_2),
@@ -801,6 +802,7 @@ static void print_memctl_options(const memctl_options_t *popts)CTRL_OPTIONS (wrlvl_override),CTRL_OPTIONS (wrlvl_sample),CTRL_OPTIONS (wrlvl_start), +CTRL_OPTIONS_HEX (cswl_override),CTRL_OPTIONS (rcw_override),CTRL_OPTIONS (rcw_1), CTRL_OPTIONS(rcw_2),
include/fsl_ddr_sdram.h +2 -0
@@ -281,6 +281,7 @@ typedef struct memctl_options_partial_s {#define DDR_DATA_BUS_WIDTH_64 0#define DDR_DATA_BUS_WIDTH_32 1#define DDR_DATA_BUS_WIDTH_16 2 +#define DDR_CSWL_CS0 0x04000001/* * Generalized parameters for memory controller configuration, * might be a little specific to the FSL memory controller
@@ -340,6 +341,7 @@ typedef struct memctl_options_s {unsigned int cpo_override;unsigned int write_data_delay;/* DQS adjust */ +unsigned int cswl_override;unsigned int wrlvl_override;unsigned int wrlvl_sample;/* Write leveling */ unsigned int wrlvl_start;
Signature · 1 line
1.8.0
PATCH v2 9/10 arm: ls102xa: Add basic support for LS1021AQDS board
In reply to Alison Wang---
Change log:
v2: Remove ethaddr/ipaddr setting.
Add board maintainer.
Add serdes and multiple ethernet controllers support.
board/freescale/ls1021aqds/Makefile | 9 + board/freescale/ls1021aqds/README | 112 +++++++ board/freescale/ls1021aqds/ddr.c | 169 +++++++++++ board/freescale/ls1021aqds/ddr.h | 64 ++++ board/freescale/ls1021aqds/eth.c | 129 ++++++++ board/freescale/ls1021aqds/ls1021aqds.c | 244 +++++++++++++++ board/freescale/ls1021aqds/ls1021aqds_qixis.h | 35 +++ boards.cfg | 1 + include/common.h | 5 +- include/configs/ls1021aqds.h | 419 ++++++++++++++++++++++++++ lib/lmb.c | 2 +- 11 files changed, 1185 insertions(+), 4 deletions(-) create mode 100644 board/freescale/ls1021aqds/Makefile create mode 100644 board/freescale/ls1021aqds/README create mode 100644 board/freescale/ls1021aqds/ddr.c create mode 100644 board/freescale/ls1021aqds/ddr.h create mode 100644 board/freescale/ls1021aqds/eth.c create mode 100644 board/freescale/ls1021aqds/ls1021aqds.c create mode 100644 board/freescale/ls1021aqds/ls1021aqds_qixis.h create mode 100644 include/configs/ls1021aqds.h
board/freescale/ls1021aqds/Makefile new file +9 -0
@@ -0,0 +1,9 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1021aqds.o +obj-y += ddr.o +obj-y += eth.o
board/freescale/ls1021aqds/README new file +112 -0
112 lines not on this page · raw message
board/freescale/ls1021aqds/ddr.c new file +169 -0
169 lines not on this page · raw message
board/freescale/ls1021aqds/ddr.h new file +64 -0
64 lines not on this page · raw message
board/freescale/ls1021aqds/eth.c new file +129 -0
129 lines not on this page · raw message
board/freescale/ls1021aqds/ls1021aqds.c new file +244 -0
244 lines not on this page · raw message
board/freescale/ls1021aqds/ls1021aqds_qixis.h new file +35 -0
@@ -0,0 +1,35 @@ +/* +* Copyright 2014 Freescale Semiconductor, Inc. +* +* SPDX-License-Identifier: GPL-2.0+ +*/ + +#ifndef __LS1021AQDS_QIXIS_H__ +#define __LS1021AQDS_QIXIS_H__ + +/* Definitions of QIXIS Registers for LS1021AQDS */ + +/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ +#define BRDCFG4_EMISEL_MASK 0xe0 +#define BRDCFG4_EMISEL_SHIFT 5 + +/* SYSCLK */ +#define QIXIS_SYSCLK_66 0x0 +#define QIXIS_SYSCLK_83 0x1 +#define QIXIS_SYSCLK_100 0x2 +#define QIXIS_SYSCLK_125 0x3 +#define QIXIS_SYSCLK_133 0x4 +#define QIXIS_SYSCLK_150 0x5 +#define QIXIS_SYSCLK_160 0x6 +#define QIXIS_SYSCLK_166 0x7 +#define QIXIS_SYSCLK_64 0x8 + +/* DDRCLK */ +#define QIXIS_DDRCLK_66 0x0 +#define QIXIS_DDRCLK_100 0x1 +#define QIXIS_DDRCLK_125 0x2 +#define QIXIS_DDRCLK_133 0x3 + +#define QIXIS_SRDS1CLK_100 0x0 + +#endif
boards.cfg +1 -0
@@ -296,6 +296,7 @@ Active arm armv7 exynos samsung trats2 Active arm armv7 exynos samsung universal_c210 s5pc210_universal - Przemyslaw Marczak <[email protected]> Active arm armv7 highbank - highbank highbank - Rob Herring <[email protected]> Active arm armv7 keystone ti k2hk_evm k2hk_evm - Vitaly Andrianov <[email protected]> +Active arm armv7 ls102xa freescale ls1021aqds ls1021aqds_nor ls1021aqds Alison Wang <[email protected]> Active arm armv7 mx5 denx m53evk m53evk m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg Marek Vasut <[email protected]> Active arm armv7 mx5 esg ima3-mx53 ima3-mx53 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg - Active arm armv7 mx5 freescale mx51evk mx51evk mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg Stefano Babic <[email protected]>
include/common.h +2 -3
@@ -687,9 +687,6 @@ ulong get_PERCLK3(void);ulong get_bus_freq (ulong );int get_serial_clock (void ); -#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) -ulong get_ddr_freq (ulong ); -#endif #if defined(CONFIG_MPC85xx)typedef MPC85xx_SYS_INFO sys_info_t ;void get_sys_info (sys_info_t * );
@@ -705,6 +702,8 @@ static inline ulong get_ddr_freq(ulong dummy) {return get_bus_freq (dummy); } +#else +ulong get_ddr_freq (ulong );#endif #if defined(CONFIG_4xx)
include/configs/ls1021aqds.h new file +419 -0
419 lines not on this page · raw message
lib/lmb.c +1 -1
@@ -295,7 +295,7 @@ phys_addr_t __lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align, phyif (max_addr ==LMB_ALLOC_ANYWHERE ) base =lmb_align_down (lmbbase + lmbsize - size, align);else if (lmbbase < max_addr) { - base =min (lmbbase + lmbsize, max_addr); + base =min (lmbbase + lmbsize -1 , max_addr); base =lmb_align_down (base - size, align); }else continue ;
Signature · 1 line
1.8.0
PATCH v2 9/10 arm: ls102xa: Add basic support for LS1021AQDS board
Quoted 6 lines · Alison Wang
lib/lmb.c +0
-0
lib/lmb.c phys_addr_t __lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align, phy · line 301
Quoted 8 lines
lib/lmb.c +1
-1@@ -295,7 +295,7 @@ phys_addr_t __lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align, phyif (max_addr ==LMB_ALLOC_ANYWHERE ) base =lmb_align_down (lmbbase + lmbsize - size, align);else if (lmbbase < max_addr) { - base =min (lmbbase + lmbsize, max_addr); + base =min (lmbbase + lmbsize -1 , max_addr); base =lmb_align_down (base - size, align); }else continue ;
Alison,
You didn't mention the change to lmb.c. It looks like a bug fix.
York
PATCH v2 9/10 arm: ls102xa: Add basic support for LS1021AQDS board
Hi, York,
Quoted 11 lines · Alison Wang
lib/lmb.c +0
-0@@ -295,7 +295,7 @@ phys_addr_t __lmb_alloc_base(struct lmb *lmb,
phys_size_tsize, ulong align, phy
if (max_addr==LMB_ALLOC_ANYWHERE)
base = lmb_align_down(lmbbase + lmbsize - size,align); else if (lmbbase < max_addr) {
lib/lmb.c phys_addr_t __lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align, phy · line 301
Quoted 5 lines
lib/lmb.c +1
-1- base =min (lmbbase + lmbsize, max_addr); + base =min (lmbbase + lmbsize -1 , max_addr); base =lmb_align_down (base - size, align); }else continue ;
Alison,
You didn't mention the change to lmb.c. It looks like a bug fix.
[Alison Wang] Yes, I will prepare a separate patch for it and add the commit message. Thanks.
Best Regards,
Alison Wang
--
View this message in context: http://u-boot.10912.n7.nabble.com/PATCH-v2-0-9-arm-ls102xa-Add-Freescale-LS102xA-SoC-and-LS1021AQDS-TWR-board-support-tp183468p186445.html
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PATCH v2 10/10 arm: ls102xa: Add basic support for LS1021ATWR board
In reply to Alison Wang---
Change log:
v2: New file.
board/freescale/ls1021atwr/Makefile | 7 + board/freescale/ls1021atwr/README | 109 +++++++ board/freescale/ls1021atwr/ls1021atwr.c | 499 ++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/ls1021atwr.h | 285 ++++++++++++++++++ 5 files changed, 901 insertions(+) create mode 100644 board/freescale/ls1021atwr/Makefile create mode 100644 board/freescale/ls1021atwr/README create mode 100644 board/freescale/ls1021atwr/ls1021atwr.c create mode 100644 include/configs/ls1021atwr.h
board/freescale/ls1021atwr/Makefile new file +7 -0
@@ -0,0 +1,7 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1021atwr.o
board/freescale/ls1021atwr/README new file +109 -0
109 lines not on this page · raw message
board/freescale/ls1021atwr/ls1021atwr.c new file +499 -0
499 lines not on this page · raw message
boards.cfg +1 -0
@@ -297,6 +297,7 @@ Active arm armv7 exynos samsung universal_c210 Active arm armv7 highbank - highbank highbank - Rob Herring <[email protected]> Active arm armv7 keystone ti k2hk_evm k2hk_evm - Vitaly Andrianov <[email protected]> Active arm armv7 ls102xa freescale ls1021aqds ls1021aqds_nor ls1021aqds Alison Wang <[email protected]> +Active arm armv7 ls102xa freescale ls1021atwr ls1021atwr_nor ls1021atwr Alison Wang <[email protected]> Active arm armv7 mx5 denx m53evk m53evk m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg Marek Vasut <[email protected]> Active arm armv7 mx5 esg ima3-mx53 ima3-mx53 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg - Active arm armv7 mx5 freescale mx51evk mx51evk mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg Stefano Babic <[email protected]>
include/configs/ls1021atwr.h new file +285 -0
285 lines not on this page · raw message
Signature · 1 line
1.8.0
v2 cover arm: ls102xa: Add Freescale LS102xA SoC and LS1021AQDS/TWR board support
In reply to Alison WangHi Alison,
Quoted 1 line · Alison Wang
This series contain the support for Freescale LS102xA SoC and LS1021AQDS/TWR board.
The numbering in the cover letter (0/9) does not match that in the individual patches (n/10). Is this normal?
Amicalement,
Signature · 1 line
Albert.
v2 cover arm: ls102xa: Add Freescale LS102xA SoC and LS1021AQDS/TWR board support
Hi, Albert,
Quoted 2 lines · Alison Wang
This series contain the support for Freescale LS102xA SoC and LS1021AQDS/TWR board.
The numbering in the cover letter (0/9) does not match that in the individual patches (n/10). Is this normal?
Sorry, it's my mistake. It should be 0/10 in the cover letter, not 0/9.
Best Regards,
Alison Wang
--
View this message in context: http://u-boot.10912.n7.nabble.com/PATCH-v2-0-9-arm-ls102xa-Add-Freescale-LS102xA-SoC-and-LS1021AQDS-TWR-board-support-tp183468p183492.html
Sent from the U-Boot mailing list archive at Nabble.com.
v2 cover arm: ls102xa: Add Freescale LS102xA SoC and LS1021AQDS/TWR board support
In reply to Alison WangQuoted 2 lines · Alison Wang
This series contain the support for Freescale LS102xA SoC and LS1021AQDS/TWR board.
Alison,
Please respin your patches. It has been a while since you submitted them. For your convenience, I have rebased your patches to v2014.10-rc1 and converted to the latest Kconfig. They can be compiled but I didn't verify on boards. Please verify and address the review comments.
http://git.denx.de/?p=u-boot/u-boot-fsl-qoriq.git;a=shortlog;h=refs/heads/test
Please submit your new patches based on u-boot-fsl-qoriq/master.
York
v2 cover arm: ls102xa: Add Freescale LS102xA SoC and LS1021AQDS/TWR board support
Hi, York,
Quoted 3 lines · Alison Wang
This series contain the support for Freescale LS102xA SoC and LS1021AQDS/TWR board.
Alison,
Please respin your patches. It has been a while since you submitted them. For
your convenience, I have rebased your patches to v2014.10-rc1 and converted to
the latest Kconfig. They can be compiled but I didn't verify on boards. Please
verify and address the review comments.
http://git.denx.de/?p=u-boot/u-boot-fsl-qoriq.git;a=shortlog;h=refs/heads/test
Please submit your new patches based on u-boot-fsl-qoriq/master.
[Alison Wang] Thanks for your help. I will respin the patches and send out v3.
Best Regards,
Alison Wang
--
View this message in context: http://u-boot.10912.n7.nabble.com/PATCH-v2-0-9-arm-ls102xa-Add-Freescale-LS102xA-SoC-and-LS1021AQDS-TWR-board-support-tp183468p186448.html
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