ARM: cache_v7: use __weak
PATCH 1/1 ARM: cache_v7: use __weak
This is not only more readable but also prevents a warning about a missing prototype. The prototypes which are actually missing are added.
cc Albert Aribaud <[email protected]>
Signed-off-by Jeroen Hofstee <[email protected]>
--- arch/arm/cpu/armv7/cache_v7.c | 45 +++++++------------------------------------ arch/arm/include/asm/cache.h | 3 +++ arch/arm/lib/cache-cp15.c | 9 ++------- arch/arm/lib/cache.c | 13 +++---------- 4 files changed, 15 insertions(+), 55 deletions(-)
arch/arm/cpu/armv7/cache_v7.c +7 -38
@@ -354,41 +354,10 @@ void invalidate_icache_all(void) }#endif -/* -* Stub implementations for outer cache operations -*/ -void __v7_outer_cache_enable (void ) -{ -} -void v7_outer_cache_enable (void ) - __attribute__((weak,alias ("__v7_outer_cache_enable" ))); - -void __v7_outer_cache_disable (void ) -{ -} -void v7_outer_cache_disable (void ) - __attribute__((weak,alias ("__v7_outer_cache_disable" ))); - -void __v7_outer_cache_flush_all (void ) -{ -} -void v7_outer_cache_flush_all (void ) - __attribute__((weak,alias ("__v7_outer_cache_flush_all" ))); - -void __v7_outer_cache_inval_all (void ) -{ -} -void v7_outer_cache_inval_all (void ) - __attribute__((weak,alias ("__v7_outer_cache_inval_all" ))); - -void __v7_outer_cache_flush_range (u32 start,u32 end) -{ -} -void v7_outer_cache_flush_range (u32 start,u32 end) - __attribute__((weak,alias ("__v7_outer_cache_flush_range" ))); - -void __v7_outer_cache_inval_range (u32 start,u32 end) -{ -} -void v7_outer_cache_inval_range (u32 start,u32 end) - __attribute__((weak,alias ("__v7_outer_cache_inval_range" ))); +/* Stub implementations for outer cache operations */ +__weak void v7_outer_cache_enable (void ) {} +__weak void v7_outer_cache_disable (void ) {} +__weak void v7_outer_cache_flush_all (void ) {} +__weak void v7_outer_cache_inval_all (void ) {} +__weak void v7_outer_cache_flush_range (u32 start,u32 end) {} +__weak void v7_outer_cache_inval_range (u32 start,u32 end) {}
arch/arm/include/asm/cache.h +3 -0
@@ -29,6 +29,9 @@ void l2_cache_enable(void);void l2_cache_disable (void );void set_section_dcache (int section,enum dcache_option option); +void arm_init_before_mmu (void ); +void arm_init_domains (void ); +void cpu_cache_initialization (void );void dram_bank_mmu_setup (int bank);#endif
arch/arm/lib/cache-cp15.c +2 -7
@@ -14,11 +14,9 @@DECLARE_GLOBAL_DATA_PTR ; -void __arm_init_before_mmu (void ) +__weak void arm_init_before_mmu (void ) { } -void arm_init_before_mmu (void ) - __attribute__((weak,alias ("__arm_init_before_mmu" )));__weak void arm_init_domains (void ) {
@@ -44,14 +42,11 @@ void set_section_dcache(int section, enum dcache_option option) page_table[section] = value; } -void __mmu_page_table_flush (unsigned long start,unsigned long stop) +__weak void mmu_page_table_flush (unsigned long start,unsigned long stop) {debug ("%s: Warning: not implemented\n" , __func__); } -void mmu_page_table_flush (unsigned long start,unsigned long stop) - __attribute__((weak,alias ("__mmu_page_table_flush" ))); -void mmu_set_region_dcache_behaviour (u32 start,int size,enum dcache_option option) {
arch/arm/lib/cache.c +3 -10
@@ -9,7 +9,7 @@#include <common.h> -void __flush_cache (unsigned long start,unsigned long size) +__weak void flush_cache (unsigned long start,unsigned long size) {#if defined(CONFIG_ARM1136 )
@@ -31,28 +31,21 @@ void __flush_cache(unsigned long start, unsigned long size)#endif /* CONFIG_ARM926EJS */ return ; } -void flush_cache (unsigned long start,unsigned long size) - __attribute__((weak,alias ("__flush_cache" )));/* * Default implementation: * do a range flush for the entire range */ -void __flush_dcache_all (void ) +__weak void flush_dcache_all (void ) {flush_cache (0 , ~0 ); } -void flush_dcache_all (void ) - __attribute__((weak,alias ("__flush_dcache_all" ))); -/* * Default implementation of enable_caches() * Real implementation should be in platform code */ -void __enable_caches (void ) +__weak void enable_caches (void ) {puts ("WARNING: Caches not enabled\n" ); } -void enable_caches (void ) - __attribute__((weak,alias ("__enable_caches" )));
Signature · 1 line
1.8.3.2
PATCH 1/1 ARM: cache_v7: use __weak
Quoted 6 lines · Jeroen Hofstee
This is not only more readable but also prevents a warning about a missing prototype. The prototypes which are actually missing are added.
cc Albert Aribaud <[email protected]>Signed-off-by Jeroen Hofstee <[email protected]>
Been on my TODO list for a long time, thanks!
Reviewed-by Tom Rini <[email protected]>
Quoted 1 line
+/* Stub implementations for outer cache operations */
Extra space. Albert assuming you're OK can you just fix it up when you take it?
Signature · 8 lines
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PATCH 1/1 ARM: cache_v7: use __weak
Hi Tom,
Quoted 9 lines · Tom Rini
Quoted 6 lines · Jeroen Hofstee
This is not only more readable but also prevents a warning about a missing prototype. The prototypes which are actually missing are added.
cc Albert Aribaud <[email protected]>Signed-off-by Jeroen Hofstee <[email protected]>
Quoted 8 lines
Been on my TODO list for a long time, thanks!
Reviewed-by Tom Rini <[email protected]>Quoted 1 line
+/* Stub implementations for outer cache operations */
Extra space. Albert assuming you're OK can you just fix it up when you take it?
Ok -- pulling this one in as a bugfix (though I don't see the warning with the toolchain I am using).
Amicalement,
Signature · 1 line
Albert.
PATCH 1/1 ARM: cache_v7: use __weak
In reply to Jeroen HofsteeHi Jeroen,
Quoted 147 lines · Jeroen Hofstee
This is not only more readable but also prevents a warning about a missing prototype. The prototypes which are actually missing are added.
cc Albert Aribaud <[email protected]>Signed-off-by Jeroen Hofstee <[email protected]>--- arch/arm/cpu/armv7/cache_v7.c | 45 +++++++------------------------------------ arch/arm/include/asm/cache.h | 3 +++ arch/arm/lib/cache-cp15.c | 9 ++------- arch/arm/lib/cache.c | 13 +++---------- 4 files changed, 15 insertions(+), 55 deletions(-)arch/arm/cpu/armv7/cache_v7.c +7
-38@@ -354,41 +354,10 @@ void invalidate_icache_all(void) }#endif -/* -* Stub implementations for outer cache operations -*/ -void __v7_outer_cache_enable (void ) -{ -} -void v7_outer_cache_enable (void ) - __attribute__((weak,alias ("__v7_outer_cache_enable" ))); - -void __v7_outer_cache_disable (void ) -{ -} -void v7_outer_cache_disable (void ) - __attribute__((weak,alias ("__v7_outer_cache_disable" ))); - -void __v7_outer_cache_flush_all (void ) -{ -} -void v7_outer_cache_flush_all (void ) - __attribute__((weak,alias ("__v7_outer_cache_flush_all" ))); - -void __v7_outer_cache_inval_all (void ) -{ -} -void v7_outer_cache_inval_all (void ) - __attribute__((weak,alias ("__v7_outer_cache_inval_all" ))); - -void __v7_outer_cache_flush_range (u32 start,u32 end) -{ -} -void v7_outer_cache_flush_range (u32 start,u32 end) - __attribute__((weak,alias ("__v7_outer_cache_flush_range" ))); - -void __v7_outer_cache_inval_range (u32 start,u32 end) -{ -} -void v7_outer_cache_inval_range (u32 start,u32 end) - __attribute__((weak,alias ("__v7_outer_cache_inval_range" ))); +/* Stub implementations for outer cache operations */ +__weak void v7_outer_cache_enable (void ) {} +__weak void v7_outer_cache_disable (void ) {} +__weak void v7_outer_cache_flush_all (void ) {} +__weak void v7_outer_cache_inval_all (void ) {} +__weak void v7_outer_cache_flush_range (u32 start,u32 end) {} +__weak void v7_outer_cache_inval_range (u32 start,u32 end) {}arch/arm/include/asm/cache.h +3
-0@@ -29,6 +29,9 @@ void l2_cache_enable(void);void l2_cache_disable (void );void set_section_dcache (int section,enum dcache_option option); +void arm_init_before_mmu (void ); +void arm_init_domains (void ); +void cpu_cache_initialization (void );void dram_bank_mmu_setup (int bank);#endif arch/arm/lib/cache-cp15.c +2
-7@@ -14,11 +14,9 @@DECLARE_GLOBAL_DATA_PTR ; -void __arm_init_before_mmu (void ) +__weak void arm_init_before_mmu (void ) { } -void arm_init_before_mmu (void ) - __attribute__((weak,alias ("__arm_init_before_mmu" )));__weak void arm_init_domains (void ) {@@ -44,14 +42,11 @@ void set_section_dcache(int section, enum dcache_option option) page_table[section] = value; } -void __mmu_page_table_flush (unsigned long start,unsigned long stop) +__weak void mmu_page_table_flush (unsigned long start,unsigned long stop) {debug ("%s: Warning: not implemented\n" , __func__); } -void mmu_page_table_flush (unsigned long start,unsigned long stop) - __attribute__((weak,alias ("__mmu_page_table_flush" ))); -void mmu_set_region_dcache_behaviour (u32 start,int size,enum dcache_option option) {arch/arm/lib/cache.c +2
-7@@ -9,7 +9,7 @@#include <common.h> -void __flush_cache (unsigned long start,unsigned long size) +__weak void flush_cache (unsigned long start,unsigned long size) {#if defined(CONFIG_ARM1136 )@@ -31,28 +31,21 @@ void __flush_cache(unsigned long start, unsigned long size)#endif /* CONFIG_ARM926EJS */ return ; } -void flush_cache (unsigned long start,unsigned long size) - __attribute__((weak,alias ("__flush_cache" )));/* * Default implementation: * do a range flush for the entire range */ -void __flush_dcache_all (void ) +__weak void flush_dcache_all (void ) {flush_cache (0 , ~0 ); } -void flush_dcache_all (void ) - __attribute__((weak,alias ("__flush_dcache_all" ))); -/*
arch/arm/lib/cache.c void __flush_cache(unsigned long start, unsigned long size) · line 58
Quoted 10 lines
arch/arm/lib/cache.c +1
-3* Default implementation of enable_caches() * Real implementation should be in platform code */ -void __enable_caches (void ) +__weak void enable_caches (void ) {puts ("WARNING: Caches not enabled\n" ); } -void enable_caches (void ) - __attribute__((weak,alias ("__enable_caches" )));
Applied to u-boot-arm/master, thanks!
Amicalement,
Signature · 1 line
Albert.