socfpga: Adding DesignWare watchdog support

PATCH New Chin Liang See 2 participants 2 messages Jun 10, 2014 – Jul 4, 2014 Arm (32-bit)

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Chin Liang See

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2014-06-10 06:11 UTC #0 lore raw

PATCH v5 2/2 socfpga: Adding DesignWare watchdog support

To enable the DesignWare watchdog support at SOCFPGA Cyclone V dev kit.

Signed-off-by Chin Liang See <[email protected]>

Cc Anatolij Gustschin <[email protected]>

Cc Albert Aribaud <[email protected]>

Cc Heiko Schocher <[email protected]>

Cc Tom Rini <[email protected]>

---
Changes for v5
- Updated to latest code branch
Changes for v4
- Updated to latest code branch
Changes for v3
- Split to 2 series patch
Changes for v2
- Enable this driver at socfpga_cyclone5 board

---
 .../include/asm/arch-socfpga/socfpga_base_addrs.h  |    1 +
 include/configs/socfpga_cyclone5.h                 |   14 ++++++++++++++
 2 files changed, 15 insertions(+)

arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +1 -0

index f564046..f2ecbbd 100644
@@ -11,6 +11,7 @@
 #define SOCFPGA_UART0_ADDRESS 0xffc02000
 #define SOCFPGA_UART1_ADDRESS 0xffc03000
 #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
+#define SOCFPGA_L4WD0_ADDRESS 0xffd02000
 #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
 #define SOCFPGA_SYSMGR_ADDRESS 0xffd08000

include/configs/socfpga_cyclone5.h +14 -0

index 0254249..34291c7 100644
@@ -206,6 +206,17 @@
 #define CONFIG_ENV_IS_NOWHERE
 
 /*
+ * L4 Watchdog
+ */
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_HW_WATCHDOG_TIMEOUT_MS	2000
+#define CONFIG_DESIGNWARE_WATCHDOG
+#define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRESS
+/* Clocks source frequency to watchdog timer */
+#define CONFIG_DW_WDT_CLOCK_KHZ		25000
+
+
+/*
  * SPL "Second Program Loader" aka Initial Software
  */

@@ -237,4 +248,7 @@
 /* Support for lib/libgeneric.o in SPL binary */
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 
+/* Support for watchdog */
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+
 #endif	/* __CONFIG_H */

Signature · 1 line

1.7.9.5

Albert ARIBAUD

2014-07-04 22:26 UTC #1 lore raw

PATCH v5 2/2 socfpga: Adding DesignWare watchdog support

Hi Chin,

Quoted 57 lines · Chin Liang See

To enable the DesignWare watchdog support at SOCFPGA Cyclone V dev kit.
Signed-off-by Chin Liang See <[email protected]>
Cc Anatolij Gustschin <[email protected]>
Cc Albert Aribaud <[email protected]>
Cc Heiko Schocher <[email protected]>
Cc Tom Rini <[email protected]>
---
Changes for v5
- Updated to latest code branch
Changes for v4
- Updated to latest code branch
Changes for v3
- Split to 2 series patch
Changes for v2
- Enable this driver at socfpga_cyclone5 board
---
 .../include/asm/arch-socfpga/socfpga_base_addrs.h  |    1 +
 include/configs/socfpga_cyclone5.h                 |   14 ++++++++++++++
 2 files changed, 15 insertions(+)
arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +1 -0
index f564046..f2ecbbd 100644
@@ -11,6 +11,7 @@
 #define SOCFPGA_UART0_ADDRESS 0xffc02000
 #define SOCFPGA_UART1_ADDRESS 0xffc03000
 #define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
+#define SOCFPGA_L4WD0_ADDRESS 0xffd02000
 #define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
 #define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
 #define SOCFPGA_SYSMGR_ADDRESS 0xffd08000
include/configs/socfpga_cyclone5.h +11 -0
index 0254249..34291c7 100644
@@ -206,6 +206,17 @@
 #define CONFIG_ENV_IS_NOWHERE
 
 /*
+ * L4 Watchdog
+ */
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_HW_WATCHDOG_TIMEOUT_MS	2000
+#define CONFIG_DESIGNWARE_WATCHDOG
+#define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRESS
+/* Clocks source frequency to watchdog timer */
+#define CONFIG_DW_WDT_CLOCK_KHZ		25000
+
+
+/*
  * SPL "Second Program Loader" aka Initial Software
  */
 

include/configs/socfpga_cyclone5.h line 254

Quoted 7 lines

include/configs/socfpga_cyclone5.h +3 -0

@@ -237,4 +248,7 @@
 /* Support for lib/libgeneric.o in SPL binary */
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 
+/* Support for watchdog */
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+
 #endif	/* __CONFIG_H */

Applied to u-boot-arm/master, thanks!

Amicalement,

Signature · 1 line

Albert.