dt-bindings: add Marvell core PLL and clock divider PMU documentation
Subsystems (2)
PATCH v3 1/3 dt-bindings: add Marvell core PLL and clock divider PMU documentation
Add documentation for the Marvell clock divider driver, which is used to source clocks for the AXI bus, video decoder, GPU and LCD blocks.
Acked-by Andrew Lunn <[email protected]>
Acked-by Rob Herring <[email protected]>
Signed-off-by Russell King <[email protected]>
--- .../bindings/clock/dove-divider-clock.txt | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/dove-divider-clock.txt
Documentation/devicetree/bindings/clock/dove-divider-clock.txt new file +28 -0
@@ -0,0 +1,28 @@ +PLL divider based Dove clocks + +Marvell Dove has a 2GHz PLL, which feeds into a set of dividers to provide +high speed clocks for a number of peripherals. These dividers are part of +the PMU, and thus this node should be a child of the PMU node. + +The following clocks are provided: + +ID Clock +------------- +0 AXI bus clock +1 GPU clock +2 VMeta clock +3 LCD clock + +Required properties: +- compatible : shall be "marvell,dove-divider-clock" +- reg : shall be the register address of the Core PLL and Clock Divider + Control 0 register. This will cover that register, as well as the + Core PLL and Clock Divider Control 1 register. Thus, it will have + a size of 8. +- #clock-cells : from common clock binding; shall be set to 1 + +divider_clk: core-clock at 0064 { + compatible = "marvell,dove-divider-clock"; + reg = <0x0064 0x8>; + #clock-cells = <1>; +};
Signature · 1 line
2.1.0