usb: dwc3: of-simple: Add compatible for rk3328

Add a compatible to be hooked into by the Rockchip rk3328 device tree.

The rk3399 compatible cannot be reused because the rk3328 SoCs may require a specialized driver in the future, and old device trees must remain commpatible with newer kernels.

---
drivers/usb/dwc3/dwc3-of-simple.c | 4 +++-

1 file changed, 3 insertions(+), 1 deletion(-)

index 7df115012935..54f38e434028 100644
@@ -49,7 +49,8 @@ static int dwc3_of_simple_probe(struct platform_device *pdev)

* Some controllers need to toggle the usb3-otg reset before trying to
* initialize the PHY, otherwise the PHY times out.
*/
- if (of_device_is_compatible(np, "rockchip,rk3399-dwc3"))
+ if (of_device_is_compatible(np, "rockchip,rk3399-dwc3") ||
+     of_device_is_compatible(np, "rockchip,rk3328-dwc3"))
simple->need_reset = true;

simple->resets = of_reset_control_array_get(np, false, true,
@@ -171,6 +172,7 @@ static const struct dev_pm_ops dwc3_of_simple_dev_pm_ops = { };

static const struct of_device_id of_dwc3_simple_match[] = {
+ { .compatible = "rockchip,rk3328-dwc3" },
{ .compatible = "rockchip,rk3399-dwc3" },
{ .compatible = "xlnx,zynqmp-dwc3" },
{ .compatible = "cavium,octeon-7130-usb-uctl" }, --
2.28.0

RK3328 SoCs have one USB 3.0 OTG controller which uses DWC_USB3 core's general architecture. It can act as static xHCI host controller, static device controller, USB 3.0/2.0 OTG basing on ID of USB3.0 PHY.

---
arch/arm64/boot/dts/rockchip/rk3328.dtsi | 27 ++++++++++++++++++++++++

1 file changed, 27 insertions(+)

index bbdb19a3e85d..27e86bf06d3e 100644
@@ -983,6 +983,33 @@ usb_host0_ohci: usb@ff5d0000 {

status = "disabled";
};

+ usbdrd3: usb@ff600000 {
+ compatible = "rockchip,rk3328-dwc3";
+ clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
+ <&cru ACLK_USB3OTG>;
+ clock-names = "ref_clk", "suspend_clk",
+       "bus_clk";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ usbdrd_dwc3: dwc3@ff600000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0xff600000 0x0 0x100000>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "otg";
+ phy_type = "utmi_wide";
+ snps,dis_enblslpm_quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis-tx-ipgap-linecheck-quirk;
+ status = "disabled";
+ };
+ };
+
gic: interrupt-controller@ff811000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.28.0

---
arch/arm64/boot/dts/rockchip/rk3328-rock64.dts | 9 +++++++++

1 file changed, 9 insertions(+)

index 86cfb5c50a94..ae27f449f4a3 100644
@@ -392,6 +392,15 @@ &usb_host0_ohci {

status = "okay";
};

+&usbdrd3 {
+ status = "okay";
+};
+
+&usbdrd_dwc3 {
+ dr_mode = "host";
+ status = "okay";
+};
+
&vop {
status = "okay";
};
--
2.28.0

Unfortunately I had not noticed that these patches were malformed when I sent them. I will fix my email setup then resend.
--
Cameron Nemo

Hi Cameron,

Use plain text mode for patches.

Before you introduce a new compatible string, your patch serie must change the documents first in version 2.
See:

dwc3.txt
rockchip,dwc3.txt

(TODO but not now) Both documents are in need for a conversion to yaml.

Also sort nodes without reg alphabetically in rk3328-rock64.dts.

&u2phy {}
&uart2 {}
&usb20_otg {}
&usbdrd3 {}
&usbdrd_dwc3 {}
&usb_host0_ehci {}
&usb_host0_ohci {}