Platform Changes for UCC TDM driver for MPC8323ERDB. Also includes related QE changes.
Subsystems (4)
PATCH 1/1 Platform Changes for UCC TDM driver for MPC8323ERDB. Also includes related QE changes.
From: Poonam Aggrwal <[email protected]>
This patch makes necessary changes in the QE and UCC framework to support TDM. It also adds support to configure the BRG properly through device tree entries. Includes the device tree changes for UCC TDM driver as well. It also includes device tree entries for UCC TDM driver.
Tested on MPC8323ERDB platform.
Signed-off-by Poonam Aggrwal <[email protected]>
Signed-off-by Ashish Kalra <[email protected]>
Signed-off-by Kim Phillips <[email protected]>
Signed-off-by Michael Barkowski <[email protected]>
---
Incorporated comments of Stephen and Tabi. Please review if they look fine.
arch/powerpc/boot/dts/mpc832x_rdb.dts | 58 +++++++ arch/powerpc/sysdev/qe_lib/qe.c | 205 ++++++++++++++++++++++++-- arch/powerpc/sysdev/qe_lib/ucc.c | 265 +++++++++++++++++++++++++++++++++ arch/powerpc/sysdev/qe_lib/ucc_fast.c | 37 +++++ include/asm-powerpc/qe.h | 8 + include/asm-powerpc/ucc.h | 4 + include/asm-powerpc/ucc_fast.h | 4 + 7 files changed, 568 insertions(+), 13 deletions(-)
arch/powerpc/boot/dts/mpc832x_rdb.dts +58 -0
@@ -105,6 +105,17 @@ device_type = "par_io"; num-ports = <7>; + ucc1pio:ucc_pin@01 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0 e 2 0 1 0 /* CLK11 */ + 3 16 1 0 2 0 /* BRG9 */ + 3 1b 1 0 2 0 /* BRG3 */ + 0 0 3 0 2 0 /* TDMATxD0 */ + 0 4 3 0 2 0 /* TDMARxD0 */ + 3 1b 2 0 1 0>; /* CLK1 */ + }; + ucc2pio:ucc_pin@02 { pio-map = < /* port pin dir open_drain assignment has_irq */
@@ -169,6 +180,36 @@ }; }; + clocks { + compatible = "fsl,cpm-clocks"; + /* clock freqs in Hz(for CLK1~CLK24). + * CLK11 is 1024KHz, + * all other clocks unused + * #clock-cells define number of cells + * used by the clock-frequency. + * right now only #clock cells=1 is + * implemented. Provision is there to + * handle frequencies >4Gig + */ + #clock-cells = <1>; + clock-frequency = <0 0 0 0 0 0 + 0 0 0 0 d#1024000 0 + 0 0 0 0 0 0 + 0 0 0 0 0 0>; + }; + + brg@640 { + compatible = "fsl,cpm-brg"; + /* input clock sources for all the 16 BRGs. + * 1-24 for CLK1 to CLK24. + * BRG9 uses CLK11,BRG1 and BRG2-8 use + * the QE clock. + */ + fsl,brg-sources = <0 0 0 0 0 0 0 0 + b 0 0 0 0 0 0 0>; + reg = <640 7f>; + }; + spi@4c0 { device_type = "spi"; compatible = "fsl_spi";
@@ -187,6 +228,23 @@ mode = "cpu"; }; + ucc@2000 { + device_type = "tdm"; + compatible = "fsl,ucc-tdm"; + model = "UCC"; + device-id = <1>; + fsl,tdm-num = <1>; + fsl,si-num = <1>; + fsl,tdm-tx-clk = "CLK1"; + fsl,tdm-rx-clk = "CLK1"; + fsl,tdm-tx-sync = "BRG9"; + fsl,tdm-rx-sync = "BRG9"; + reg = <2000 200>; + interrupts = <20>; + interrupt-parent = <&qeic>; + pio-handle = <&ucc1pio>; + }; + ucc@3000 { device_type = "network"; compatible = "ucc_geth";
arch/powerpc/sysdev/qe_lib/qe.c +192 -13
231 lines not on this page · raw message
arch/powerpc/sysdev/qe_lib/ucc.c +265 -0
268 lines not on this page · raw message
arch/powerpc/sysdev/qe_lib/ucc_fast.c +37 -0
@@ -327,6 +327,43 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** uccucc_fast_free (uccf);return -EINVAL ; } + }else { +/* TDM Rx clock routing */ +if ((uf_info->tdm_rx_clk !=NULL ) && +ucc_set_tdm_rxtx_clk (uf_info->ucc_num, + uf_info->tdm_rx_clk,COMM_DIR_RX )) { +printk (KERN_ERR "%s: illegal value for TDM RX clock" , + __FUNCTION__); +ucc_fast_free (uccf); +return -EINVAL ; + } +/* TDM Tx clock routing */ +if ((uf_info->tdm_tx_clk !=NULL ) && +ucc_set_tdm_rxtx_clk (uf_info->ucc_num, + uf_info->tdm_tx_clk,COMM_DIR_TX )) { +printk (KERN_ERR "%s: illegal value for TDM TX clock" , + __FUNCTION__); +ucc_fast_free (uccf); +return -EINVAL ; + } +/* TDM Rx sync routing */ +if ((uf_info->tdm_rx_sync !=NULL ) && +ucc_set_tdm_rxtx_sync (uf_info->ucc_num, + uf_info->tdm_rx_sync,COMM_DIR_RX )) { +printk (KERN_ERR "%s: illegal value for TDM RX" +"Frame sync" , __FUNCTION__); +ucc_fast_free (uccf); +return -EINVAL ; + } +/* TDM Tx sync routing */ +if ((uf_info->tdm_tx_sync !=NULL ) && +ucc_set_tdm_rxtx_sync (uf_info->ucc_num, + uf_info->tdm_tx_sync,COMM_DIR_TX )) { +printk (KERN_ERR "%s: illegal value for TDM TX" +"Frame sync" , __FUNCTION__); +ucc_fast_free (uccf); +return -EINVAL ; + } }/* Set interrupt mask register at UCC level. */
include/asm-powerpc/qe.h +8 -0
@@ -497,6 +497,14 @@ struct ucc_slow_pram {#define UCC_GETH_UCCE_RXF1 0x00000002#define UCC_GETH_UCCE_RXF0 0x00000001 +/* Transparent UCC Event Register (UCCE) */ +#define UCC_TRANS_UCCE_GRA 0x0080 +#define UCC_TRANS_UCCE_TXE 0x0010 +#define UCC_TRANS_UCCE_RXF 0x0008 +#define UCC_TRANS_UCCE_BSY 0x0004 +#define UCC_TRANS_UCCE_TXB 0x0002 +#define UCC_TRANS_UCCE_RXB 0x0001 +/* UPSMR, when used as a UART */ #define UCC_UART_UPSMR_FLC 0x8000#define UCC_UART_UPSMR_SL 0x4000
include/asm-powerpc/ucc.h +4 -0
@@ -42,6 +42,10 @@ int ucc_set_qe_mux_mii_mng(unsigned int ucc_num);int ucc_set_qe_mux_rxtx (unsigned int ucc_num,enum qe_clock clock,enum comm_dir mode); +int ucc_set_tdm_rxtx_clk (int tdm_num,char *clk_src,enum comm_dir mode); + +int ucc_set_tdm_rxtx_sync (int tdm_num,char *clk_src,enum comm_dir mode); +int ucc_mux_set_grant_tsa_bkpt (unsigned int ucc_num,int set,u32 mask);/* QE MUX clock routing for UCC
include/asm-powerpc/ucc_fast.h +4 -0
@@ -152,6 +152,10 @@ struct ucc_fast_info {enum ucc_fast_rx_decoding_method renc;enum ucc_fast_transparent_tcrc tcrc;enum ucc_fast_sync_len synl; +char *tdm_rx_clk; +char *tdm_tx_clk; +char *tdm_rx_sync; +char *tdm_tx_sync; };struct ucc_fast_private {
Signature · 1 line
1.5.3.3