usb: dwc3: 5.15 backports

From: Johan Hovold <[email protected]>

commit d2ac7bef95c9ead307801ccb6cb6dfbeb14247bf upstream.

Generic PHYs must be powered-off before they can be tore down.

Similarly, suspending legacy PHYs after having powered them off makes no sense.

Fix the dwc3_core_exit() (e.g. called during suspend) and open-coded dwc3_probe() error-path sequences that got this wrong.

Note that this makes dwc3_core_exit() match the dwc3_core_init() error path with respect to powering off the PHYs.

Fixes 03c1fd622f72 ("usb: dwc3: core: add phy cleanup for probe error handling")

Fixes c499ff71ff2a ("usb: dwc3: core: re-factor init and exit paths")

Cc [email protected] # 4.8

Reviewed-by Andrew Halaney <[email protected]>

Reviewed-by Matthias Kaehlcke <[email protected]>

Reviewed-by Manivannan Sadhasivam <[email protected]>

Signed-off-by Johan Hovold <[email protected]>

Link https://lore.kernel.org/r/[email protected] open here

Signed-off-by Greg Kroah-Hartman <[email protected]>

[ johan: adjust context to 5.15 ]

Signed-off-by Johan Hovold <[email protected]>

---
 drivers/usb/dwc3/core.c | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

Quoted 26 lines · Johan Hovold

From: Johan Hovold <[email protected]>

commit d2ac7bef95c9ead307801ccb6cb6dfbeb14247bf upstream.

Generic PHYs must be powered-off before they can be tore down.

Similarly, suspending legacy PHYs after having powered them off makes no sense.

Fix the dwc3_core_exit() (e.g. called during suspend) and open-coded dwc3_probe() error-path sequences that got this wrong.

Note that this makes dwc3_core_exit() match the dwc3_core_init() error path with respect to powering off the PHYs.

Fixes 03c1fd622f72 ("usb: dwc3: core: add phy cleanup for probe error handling")

Fixes c499ff71ff2a ("usb: dwc3: core: re-factor init and exit paths")

Cc [email protected] # 4.8

Reviewed-by Andrew Halaney <[email protected]>

Reviewed-by Matthias Kaehlcke <[email protected]>

Reviewed-by Manivannan Sadhasivam <[email protected]>

Signed-off-by Johan Hovold <[email protected]>

Link https://lore.kernel.org/r/[email protected] open here

Signed-off-by Greg Kroah-Hartman <[email protected]>

[ johan: adjust context to 5.15 ]

Signed-off-by Johan Hovold <[email protected]>

Quoted 3 lines

---
 drivers/usb/dwc3/core.c | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

This one did not apply to 4.9.y, 4.14.y, or 4.19.y :(

Quoted 31 lines · Greg Kroah-Hartman

Quoted 29 lines · Johan Hovold

From: Johan Hovold <[email protected]>

commit d2ac7bef95c9ead307801ccb6cb6dfbeb14247bf upstream.

Generic PHYs must be powered-off before they can be tore down.

Similarly, suspending legacy PHYs after having powered them off makes no sense.

Fix the dwc3_core_exit() (e.g. called during suspend) and open-coded dwc3_probe() error-path sequences that got this wrong.

Note that this makes dwc3_core_exit() match the dwc3_core_init() error path with respect to powering off the PHYs.

Fixes 03c1fd622f72 ("usb: dwc3: core: add phy cleanup for probe error handling")

Fixes c499ff71ff2a ("usb: dwc3: core: re-factor init and exit paths")

Cc [email protected] # 4.8

Reviewed-by Andrew Halaney <[email protected]>

Reviewed-by Matthias Kaehlcke <[email protected]>

Reviewed-by Manivannan Sadhasivam <[email protected]>

Signed-off-by Johan Hovold <[email protected]>

Link https://lore.kernel.org/r/[email protected] open here

Signed-off-by Greg Kroah-Hartman <[email protected]>

[ johan: adjust context to 5.15 ]

Signed-off-by Johan Hovold <[email protected]>

---
 drivers/usb/dwc3/core.c | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

Quoted 1 line

This one did not apply to 4.9.y, 4.14.y, or 4.19.y :(

Perhaps someone who cares about these old trees can do the backports. Should be as trivial. Can't be the patch submitters responsibility to maintain 8 stable trees.

From: Johan Hovold <[email protected]>

commit a872ab303d5ddd4c965f9cd868677781a33ce35a upstream.

The Qualcomm dwc3 runtime-PM implementation checks the xhci platform-device pointer in the wakeup-interrupt handler to determine whether the controller is in host mode and if so triggers a resume.

After a role switch in OTG mode the xhci platform-device would have been freed and the next wakeup from runtime suspend would access the freed memory.

Note that role switching is executed from a freezable workqueue, which guarantees that the pointer is stable during suspend.

Also note that runtime PM has been broken since commit 2664deb09306 ("usb: dwc3: qcom: Honor wakeup enabled/disabled state"), which incidentally also prevents this issue from being triggered.

Fixes a4333c3a6ba9 ("usb: dwc3: Add Qualcomm DWC3 glue driver")

Cc [email protected] # 4.18

Reviewed-by Matthias Kaehlcke <[email protected]>

Reviewed-by Manivannan Sadhasivam <[email protected]>

Signed-off-by Johan Hovold <[email protected]>

Link https://lore.kernel.org/r/[email protected] open here

Signed-off-by Greg Kroah-Hartman <[email protected]>

[ johan: adjust context for 5.15 ]

Signed-off-by Johan Hovold <[email protected]>

---
 drivers/usb/dwc3/dwc3-qcom.c | 14 +++++++++++++-
 drivers/usb/dwc3/host.c      |  1 +
 2 files changed, 14 insertions(+), 1 deletion(-)

From: Johan Hovold <[email protected]>

commit 6000b8d900cd5f52fbcd0776d0cc396e88c8c2ea upstream.

The dwc3 driver manages its PHYs itself so the USB core PHY management needs to be disabled.

Use the struct xhci_plat_priv hack added by commits 46034a999c07 ("usb:
host: xhci-plat: add platform data support") and f768e718911e ("usb:
host: xhci-plat: add priv quirk for skip PHY initialization") to propagate the setting for now.

Fixes 4e88d4c08301 ("usb: add a flag to skip PHY initialization to struct usb_hcd")

Fixes 178a0bce05cb ("usb: core: hcd: integrate the PHY wrapper into the HCD core")

Tested-by Matthias Kaehlcke <[email protected]>

Cc stable <[email protected]>

Reviewed-by Matthias Kaehlcke <[email protected]>

Signed-off-by Johan Hovold <[email protected]>

Link https://lore.kernel.org/r/[email protected] open here

Signed-off-by Greg Kroah-Hartman <[email protected]>

[ johan: adjust context to 5.15 ]

Signed-off-by Johan Hovold <[email protected]>

Signed-off-by Greg Kroah-Hartman <[email protected]>

---
 drivers/usb/dwc3/host.c |   10 ++++++++++
 1 file changed, 10 insertions(+)

Quoted 23 lines · Johan Hovold

From: Johan Hovold <[email protected]>

commit 6000b8d900cd5f52fbcd0776d0cc396e88c8c2ea upstream.

The dwc3 driver manages its PHYs itself so the USB core PHY management needs to be disabled.

Use the struct xhci_plat_priv hack added by commits 46034a999c07 ("usb:
host: xhci-plat: add platform data support") and f768e718911e ("usb:
host: xhci-plat: add priv quirk for skip PHY initialization") to propagate the setting for now.

Fixes 4e88d4c08301 ("usb: add a flag to skip PHY initialization to struct usb_hcd")

Fixes 178a0bce05cb ("usb: core: hcd: integrate the PHY wrapper into the HCD core")

Tested-by Matthias Kaehlcke <[email protected]>

Cc stable <[email protected]>

Reviewed-by Matthias Kaehlcke <[email protected]>

Signed-off-by Johan Hovold <[email protected]>

Link https://lore.kernel.org/r/[email protected] open here

Signed-off-by Greg Kroah-Hartman <[email protected]>

[ johan: adjust context to 5.15 ]

Signed-off-by Johan Hovold <[email protected]>

Signed-off-by Greg Kroah-Hartman <[email protected]>

Quoted 3 lines

---
 drivers/usb/dwc3/host.c |   10 ++++++++++
 1 file changed, 10 insertions(+)

Breaks the build on 4.19.y :(

From: Johan Hovold <[email protected]>

commit 6000b8d900cd5f52fbcd0776d0cc396e88c8c2ea upstream.

The dwc3 driver manages its PHYs itself so the USB core PHY management needs to be disabled.

Use the struct xhci_plat_priv hack added by commits 46034a999c07 ("usb:
host: xhci-plat: add platform data support") and f768e718911e ("usb:
host: xhci-plat: add priv quirk for skip PHY initialization") to propagate the setting for now.

Fixes 4e88d4c08301 ("usb: add a flag to skip PHY initialization to

struct usb_hcd")

Fixes 178a0bce05cb ("usb: core: hcd: integrate the PHY wrapper into

the HCD core")

Tested-by Matthias Kaehlcke <[email protected]>

Cc stable <[email protected]>

Reviewed-by Matthias Kaehlcke <[email protected]>

Signed-off-by Johan Hovold <[email protected]>

Link https://lore.kernel.org/r/[email protected] open here

Signed-off-by Greg Kroah-Hartman <[email protected]>

[ johan: adjust context to 5.15 ]

Signed-off-by Johan Hovold <[email protected]>

---
 drivers/usb/dwc3/host.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

drivers/usb/dwc3/host.c +10 -0

index 2078e9d70292..85165a972076 100644
@@ -10,8 +10,13 @@
 #include <linux/acpi.h>
 #include <linux/platform_device.h>
 
+#include "../host/xhci-plat.h"
 #include "core.h"
 
+static const struct xhci_plat_priv dwc3_xhci_plat_priv = {
+	.quirks = XHCI_SKIP_PHY_INIT,
+};
+
 static int dwc3_host_get_irq(struct dwc3 *dwc)
 {
 	struct platform_device	*dwc3_pdev = to_platform_device(dwc->dev);

@@ -87,6 +92,11 @@ int dwc3_host_init(struct dwc3 *dwc)
 		goto err;
 	}
 
+	ret = platform_device_add_data(xhci, &dwc3_xhci_plat_priv,
+					sizeof(dwc3_xhci_plat_priv));
+	if (ret)
+		goto err;
+
 	memset(props, 0, sizeof(struct property_entry) * ARRAY_SIZE(props));
 
 	if (dwc->usb3_lpm_capable)

Hi Johan,

Quoted 11 lines · Johan Hovold

From: Johan Hovold <[email protected]>

commit 6000b8d900cd5f52fbcd0776d0cc396e88c8c2ea upstream.

The dwc3 driver manages its PHYs itself so the USB core PHY management needs to be disabled.

Use the struct xhci_plat_priv hack added by commits 46034a999c07 ("usb:
host: xhci-plat: add platform data support") and f768e718911e ("usb:
host: xhci-plat: add priv quirk for skip PHY initialization") to propagate the setting for now.

[adding also Samsung/ODROID device tree authors Krzysztof and Marek]

For some reason, this commit seems to break detection of the USB to S-ATA controller on ODROID-HC1 devices (Exynos 5422).

We have a known to work OS release of v5.15.60, and known to not be working of v5.15.67. By reverting suspicious commits, I was able to pinpoint the problem to this particular commit.

From what I understand, on that particular hardware the S-ATA controller power is controlled via the V-BUS signal VBUSCTRL_U2 (Schematic [1]). Presumably this signal is no longer controlled with this change.

This came up in our HAOS issue #2153 [2].

Quoted 24 lines · Stefan Agner

Hi Johan,

Quoted 11 lines · Johan Hovold

From: Johan Hovold <[email protected]>

commit 6000b8d900cd5f52fbcd0776d0cc396e88c8c2ea upstream.

The dwc3 driver manages its PHYs itself so the USB core PHY management needs to be disabled.

Use the struct xhci_plat_priv hack added by commits 46034a999c07 ("usb:
host: xhci-plat: add platform data support") and f768e718911e ("usb:
host: xhci-plat: add priv quirk for skip PHY initialization") to propagate the setting for now.

[adding also Samsung/ODROID device tree authors Krzysztof and Marek]

For some reason, this commit seems to break detection of the USB to S-ATA controller on ODROID-HC1 devices (Exynos 5422).

We have a known to work OS release of v5.15.60, and known to not be working of v5.15.67. By reverting suspicious commits, I was able to pinpoint the problem to this particular commit.

Quoted 5 lines

From what I understand, on that particular hardware the S-ATA controller power is controlled via the V-BUS signal VBUSCTRL_U2 (Schematic [1]). Presumably this signal is no longer controlled with this change.

This came up in our HAOS issue #2153 [2].

Thanks for the report and sorry about the breakage. This wasn't supposed to go to stable but Greg thought otherwise (and I helped with the backporting to prevent autosel from pulling in even more changes).

But at least this way we found out sooner that this platform depends on having both USB core and dwc3 managing the same PHY.

I think this may be related to the calibration calls added to dwc3 and later removed again by commits:

	d8c80bb3b55b ("phy: exynos5-usbdrd: Calibrate LOS levels for exynos5420/5800")
	a0a465569b45 ("usb: dwc3: remove generic PHY calibrate() calls")

The removal explicitly mentions that the expectation is that USB core will do the PHY calibration.

There could be other changes in the sequencing of events that this platform has been implicitly relying on, but as a start, could try adding the missing calibration calls (patch below) and see if that makes a difference?

Quoted 26 lines · Johan Hovold

Quoted 8 lines · Stefan Agner

Quoted 7 lines · Johan Hovold

From: Johan Hovold <[email protected]>

commit 6000b8d900cd5f52fbcd0776d0cc396e88c8c2ea upstream.

The dwc3 driver manages its PHYs itself so the USB core PHY management needs to be disabled.

Quoted 7 lines

Quoted 4 lines

Use the struct xhci_plat_priv hack added by commits 46034a999c07 ("usb:
host: xhci-plat: add platform data support") and f768e718911e ("usb:
host: xhci-plat: add priv quirk for skip PHY initialization") to propagate the setting for now.

For some reason, this commit seems to break detection of the USB to S-ATA controller on ODROID-HC1 devices (Exynos 5422).

I think this may be related to the calibration calls added to dwc3 and later removed again by commits:

	d8c80bb3b55b ("phy: exynos5-usbdrd: Calibrate LOS levels for exynos5420/5800")
	a0a465569b45 ("usb: dwc3: remove generic PHY calibrate() calls")

The removal explicitly mentions that the expectation is that USB core will do the PHY calibration.

Quoted 4 lines

There could be other changes in the sequencing of events that this platform has been implicitly relying on, but as a start, could try adding the missing calibration calls (patch below) and see if that makes a difference?

The patch below did not apply to 5.15.74 directly, but I think I was able to get the corrected patch applied (see below)

That said, I do not have direct access to that hardware, but I created a build and asked the user test it.

Quoted 27 lines · Stefan Agner

Quoted 26 lines · Johan Hovold

Quoted 8 lines · Stefan Agner

Quoted 7 lines · Johan Hovold

From: Johan Hovold <[email protected]>

commit 6000b8d900cd5f52fbcd0776d0cc396e88c8c2ea upstream.

The dwc3 driver manages its PHYs itself so the USB core PHY management needs to be disabled.

Quoted 7 lines

Quoted 4 lines

Use the struct xhci_plat_priv hack added by commits 46034a999c07 ("usb:
host: xhci-plat: add platform data support") and f768e718911e ("usb:
host: xhci-plat: add priv quirk for skip PHY initialization") to propagate the setting for now.

For some reason, this commit seems to break detection of the USB to S-ATA controller on ODROID-HC1 devices (Exynos 5422).

I think this may be related to the calibration calls added to dwc3 and later removed again by commits:

	d8c80bb3b55b ("phy: exynos5-usbdrd: Calibrate LOS levels for exynos5420/5800")
	a0a465569b45 ("usb: dwc3: remove generic PHY calibrate() calls")

The removal explicitly mentions that the expectation is that USB core will do the PHY calibration.

Quoted 7 lines

Quoted 4 lines

There could be other changes in the sequencing of events that this platform has been implicitly relying on, but as a start, could try adding the missing calibration calls (patch below) and see if that makes a difference?

The patch below did not apply to 5.15.74 directly, but I think I was able to get the corrected patch applied (see below)

Looks good to me.

Quoted 2 lines

That said, I do not have direct access to that hardware, but I created a build and asked the user test it.

Thanks, let me know how it goes.

Quoted 33 lines · Johan Hovold

Quoted 32 lines · Stefan Agner

Quoted 30 lines · Johan Hovold

Quoted 8 lines · Stefan Agner

Quoted 7 lines · Johan Hovold

From: Johan Hovold <[email protected]>

commit 6000b8d900cd5f52fbcd0776d0cc396e88c8c2ea upstream.

The dwc3 driver manages its PHYs itself so the USB core PHY management needs to be disabled.

Quoted 7 lines

Quoted 4 lines

Use the struct xhci_plat_priv hack added by commits 46034a999c07 ("usb:
host: xhci-plat: add platform data support") and f768e718911e ("usb:
host: xhci-plat: add priv quirk for skip PHY initialization") to propagate the setting for now.

For some reason, this commit seems to break detection of the USB to S-ATA controller on ODROID-HC1 devices (Exynos 5422).

I think this may be related to the calibration calls added to dwc3 and later removed again by commits:

	d8c80bb3b55b ("phy: exynos5-usbdrd: Calibrate LOS levels for exynos5420/5800")
	a0a465569b45 ("usb: dwc3: remove generic PHY calibrate() calls")

The removal explicitly mentions that the expectation is that USB core will do the PHY calibration.

There could be other changes in the sequencing of events that this platform has been implicitly relying on, but as a start, could try adding the missing calibration calls (patch below) and see if that makes a difference?

Quoted 2 lines

Quoted 2 lines

The patch below did not apply to 5.15.74 directly, but I think I was able to get the corrected patch applied (see below)

The user reports the S-ATA disk is *not* recognized with that patch applied.

Quoted 2 lines · Stefan Agner

The user reports the S-ATA disk is *not* recognized with that patch applied.

I just noticed a mistake in the instrumentation patch I sent you. Could you try moving the calibrations calls after dwc3_host_init() (e.g. as in the second chunk in the diff below)?

As mentioned in the commit message for a0a465569b45 ("usb: dwc3: remove generic PHY calibrate() calls"), this may not work if the xhci-plat driver is built as a module and there are some corner cases that it does not cover.

It seems we should revert the offending commit and then try to find some time to untangle this mess, but please check if the below addresses the issue first so we know what the problem is.

I'll prepare a revert in the meantime.

drivers/usb/dwc3/core.c +5 -0

index 31156d4dec9f..37d49a394912 100644
@@ -197,6 +197,8 @@ static void __dwc3_set_mode(struct work_struct *work)
                                otg_set_vbus(dwc->usb2_phy->otg, true);
                        phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
                        phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
+                       phy_calibrate(dwc->usb2_generic_phy);
+                       phy_calibrate(dwc->usb3_generic_phy);
                        if (dwc->dis_split_quirk) {
                                reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
                                reg |= DWC3_GUCTL3_SPLITDISABLE;

@@ -1391,6 +1393,9 @@ static int dwc3_core_init_mode(struct dwc3 *dwc)
                ret = dwc3_host_init(dwc);
                if (ret)
                        return dev_err_probe(dev, ret, "failed to initialize host\n");
+
+               phy_calibrate(dwc->usb2_generic_phy);
+               phy_calibrate(dwc->usb3_generic_phy);
                break;
        case USB_DR_MODE_OTG:
                INIT_WORK(&dwc->drd_work, __dwc3_set_mode);

Quoted 12 lines · Johan Hovold

Quoted 2 lines · Stefan Agner

The user reports the S-ATA disk is *not* recognized with that patch applied.

I just noticed a mistake in the instrumentation patch I sent you. Could you try moving the calibrations calls after dwc3_host_init() (e.g. as in the second chunk in the diff below)?

As mentioned in the commit message for a0a465569b45 ("usb: dwc3: remove generic PHY calibrate() calls"), this may not work if the xhci-plat driver is built as a module and there are some corner cases that it does not cover.

Quoted 5 lines

It seems we should revert the offending commit and then try to find some time to untangle this mess, but please check if the below addresses the issue first so we know what the problem is.

I'll prepare a revert in the meantime.

I've now posted the revert, but please do check if the below patch was enough to resolve the immediate issue.

Johan

Quoted 15 lines

drivers/usb/dwc3/core.c +2 -0

index 31156d4dec9f..37d49a394912 100644
@@ -197,6 +197,8 @@ static void __dwc3_set_mode(struct work_struct *work)
                                 otg_set_vbus(dwc->usb2_phy->otg, true);
                         phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
                         phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
+                       phy_calibrate(dwc->usb2_generic_phy);
+                       phy_calibrate(dwc->usb3_generic_phy);
                         if (dwc->dis_split_quirk) {
                                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
                                 reg |= DWC3_GUCTL3_SPLITDISABLE;

@@ -1391,6 +1393,9 @@ static int dwc3_core_init_mode(struct dwc3 *dwc)
                 ret = dwc3_host_init(dwc);

drivers/usb/dwc3/core.c static int dwc3_core_init_mode(struct dwc3 *dwc) · line 1401

Quoted 8 lines

drivers/usb/dwc3/core.c +3 -0

                 if (ret)
                         return dev_err_probe(dev, ret, "failed to initialize host\n");
+
+               phy_calibrate(dwc->usb2_generic_phy);
+               phy_calibrate(dwc->usb3_generic_phy);
                 break;
         case USB_DR_MODE_OTG:
                 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);

Hi Johan,

Quoted 17 lines · Johan Hovold

Quoted 16 lines · Johan Hovold

Quoted 2 lines · Stefan Agner

The user reports the S-ATA disk is *not* recognized with that patch applied.

I just noticed a mistake in the instrumentation patch I sent you. Could you try moving the calibrations calls after dwc3_host_init() (e.g. as in the second chunk in the diff below)?

As mentioned in the commit message for a0a465569b45 ("usb: dwc3: remove generic PHY calibrate() calls"), this may not work if the xhci-plat driver is built as a module and there are some corner cases that it does not cover.

It seems we should revert the offending commit and then try to find some time to untangle this mess, but please check if the below addresses the issue first so we know what the problem is.

Quoted 3 lines

Quoted 1 line

I'll prepare a revert in the meantime.

I've now posted the revert, but please do check if the below patch was enough to resolve the immediate issue.

The below patch was a half-fix. It worked only if both dwc3 and xhci_plat_hcd were compiled into the kernel. Afair Debian-based distros used xhci compiled as a module, so this didn't work for that case due to timing issues.

Hi Johan,

Quoted 11 lines · Johan Hovold

From: Johan Hovold <[email protected]>

commit 6000b8d900cd5f52fbcd0776d0cc396e88c8c2ea upstream.

The dwc3 driver manages its PHYs itself so the USB core PHY management needs to be disabled.

Use the struct xhci_plat_priv hack added by commits 46034a999c07 ("usb:
host: xhci-plat: add platform data support") and f768e718911e ("usb:
host: xhci-plat: add priv quirk for skip PHY initialization") to propagate the setting for now.

[adding also Samsung/ODROID device tree authors Krzysztof and Marek]

For some reason, this commit seems to break detection of the USB to S-ATA controller on ODROID-HC1 devices (Exynos 5422).

We have a known to work OS release of v5.15.60, and known to not be working of v5.15.67. By reverting suspicious commits, I was able to pinpoint the problem to this particular commit.

Quoted 1 line

From what I understand, on that particular hardware the S-ATA controller

power is controlled via the V-BUS signal VBUSCTRL_U2 (Schematic [1]). Presumably this signal is no longer controlled with this change.

This came up in our HAOS issue #2153 [2].