arm64: dts: qcom: sc8280xp: fix UFS reference clocks and PHY nodes

There are three UFS reference clocks on SC8280XP which are used as follows:

- The GCC_UFS_REF_CLKREF_CLK clock is fed to any UFS device connected to either controller.

- The GCC_UFS_1_CARD_CLKREF_CLK and GCC_UFS_CARD_CLKREF_CLK clocks provide reference clocks to the two PHYs.

Note that this depends on first updating the clock driver to reflect that all three clocks are sourced from CXO. Specifically, the UFS controller driver expects the device reference clock to have a valid frequency:

ufshcd-qcom 1d84000.ufs: invalid ref_clk setting = 0

Fixes 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")

Fixes 8d6b458ce6e9 ("arm64: dts: qcom: sc8280xp: fix ufs_card_phy ref clock")

Fixes f3aa975e230e ("arm64: dts: qcom: sc8280xp: correct ref clock for ufs_mem_phy")

Link https://lore.kernel.org/lkml/[email protected]/ open here

Cc [email protected] # 5.20

Signed-off-by Johan Hovold <[email protected]>

---

  arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 8 ++++----
  1 file changed, 4 insertions(+), 4 deletions(-)

arch/arm64/boot/dts/qcom/sc8280xp.dtsi +4 -4

index 21ac119e0382..e0d0fb6994b5 100644
@@ -912,7 +912,7 @@ ufs_mem_hc: ufs@1d84000 {
  				 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
  				 <&gcc GCC_UFS_PHY_AHB_CLK>,
  				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
-				 <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_UFS_REF_CLKREF_CLK>,
  				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
  				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
  				 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;

@@ -943,7 +943,7 @@ ufs_mem_phy: phy@1d87000 {
  			ranges;
  			clock-names = "ref",
  				      "ref_aux";
-			clocks = <&gcc GCC_UFS_REF_CLKREF_CLK>,
+			clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>,
  				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
 
  			resets = <&ufs_mem_hc 0>;

@@ -980,7 +980,7 @@ ufs_card_hc: ufs@1da4000 {
  				 <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
  				 <&gcc GCC_UFS_CARD_AHB_CLK>,
  				 <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>,
-				 <&rpmhcc RPMH_CXO_CLK>,
+				 <&gcc GCC_UFS_REF_CLKREF_CLK>,
  				 <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>,
  				 <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>,
  				 <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>;

@@ -1011,7 +1011,7 @@ ufs_card_phy: phy@1da7000 {
  			ranges;
  			clock-names = "ref",
  				      "ref_aux";
-			clocks = <&gcc GCC_UFS_REF_CLKREF_CLK>,
+			clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>,
  				 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>;
 
  			resets = <&ufs_card_hc 0>;

There are three UFS reference clocks on SC8280XP which are used as follows:

- The GCC_UFS_REF_CLKREF_CLK clock is fed to any UFS device connected to either controller.

- The GCC_UFS_1_CARD_CLKREF_CLK and GCC_UFS_CARD_CLKREF_CLK clocks provide reference clocks to the two PHYs.

Note that this depends on first updating the clock driver to reflect that all three clocks are sourced from CXO. Specifically, the UFS controller driver expects the device reference clock to have a valid frequency:

ufshcd-qcom 1d84000.ufs: invalid ref_clk setting = 0

Fixes 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")

Fixes 8d6b458ce6e9 ("arm64: dts: qcom: sc8280xp: fix ufs_card_phy ref clock")

Fixes f3aa975e230e ("arm64: dts: qcom: sc8280xp: correct ref clock for ufs_mem_phy")

Link https://lore.kernel.org/lkml/[email protected]/ open here

Cc [email protected] # 5.20

Signed-off-by Johan Hovold <[email protected]>

Quoted 14 lines · Johan Hovold

There are three UFS reference clocks on SC8280XP which are used as follows:

- The GCC_UFS_REF_CLKREF_CLK clock is fed to any UFS device connected to either controller.

- The GCC_UFS_1_CARD_CLKREF_CLK and GCC_UFS_CARD_CLKREF_CLK clocks provide reference clocks to the two PHYs.

Note that this depends on first updating the clock driver to reflect that all three clocks are sourced from CXO. Specifically, the UFS controller driver expects the device reference clock to have a valid frequency:

Quoted 8 lines

ufshcd-qcom 1d84000.ufs: invalid ref_clk setting = 0

Fixes 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")

Fixes 8d6b458ce6e9 ("arm64: dts: qcom: sc8280xp: fix ufs_card_phy ref clock")

Fixes f3aa975e230e ("arm64: dts: qcom: sc8280xp: correct ref clock for ufs_mem_phy")

Link https://lore.kernel.org/lkml/[email protected]/ open here

Cc [email protected] # 5.20

Signed-off-by Johan Hovold <[email protected]>

Reviewed-by Brian Masney <[email protected]>

Note that there was no 5.20 kernel; that should be 6.0. Bjorn should be able to fix this up during merge.

Update the UFS PHY nodes to match the new binding.

Signed-off-by Johan Hovold <[email protected]>

---

  arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 49 +++++++++-----------------
  1 file changed, 17 insertions(+), 32 deletions(-)

arch/arm64/boot/dts/qcom/sc8280xp.dtsi +17 -32

index e0d0fb6994b5..1b309fa93484 100644
@@ -896,7 +896,7 @@ ufs_mem_hc: ufs@1d84000 {
  				     "jedec,ufs-2.0";
  			reg = <0 0x01d84000 0 0x3000>;
  			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
-			phys = <&ufs_mem_phy_lanes>;
+			phys = <&ufs_mem_phy>;
  			phy-names = "ufsphy";
  			lanes-per-direction = <2>;
  			#reset-cells = <1>;

@@ -937,27 +937,20 @@ ufs_mem_hc: ufs@1d84000 {
 
  		ufs_mem_phy: phy@1d87000 {
  			compatible = "qcom,sc8280xp-qmp-ufs-phy";
-			reg = <0 0x01d87000 0 0x1c8>;
-			#address-cells = <2>;
-			#size-cells = <2>;
-			ranges;
-			clock-names = "ref",
-				      "ref_aux";
+			reg = <0 0x01d87000 0 0x1000>;
+
  			clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>,
  				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+			clock-names = "ref", "ref_aux";
+
+			power-domains = <&gcc UFS_PHY_GDSC>;
 
  			resets = <&ufs_mem_hc 0>;
  			reset-names = "ufsphy";
-			status = "disabled";
 
-			ufs_mem_phy_lanes: phy@1d87400 {
-				reg = <0 0x01d87400 0 0x108>,
-				      <0 0x01d87600 0 0x1e0>,
-				      <0 0x01d87c00 0 0x1dc>,
-				      <0 0x01d87800 0 0x108>,
-				      <0 0x01d87a00 0 0x1e0>;
-				#phy-cells = <0>;
-			};
+			#phy-cells = <0>;
+
+			status = "disabled";
  		};
 
  		ufs_card_hc: ufs@1da4000 {

@@ -965,7 +958,7 @@ ufs_card_hc: ufs@1da4000 {
  				     "jedec,ufs-2.0";
  			reg = <0 0x01da4000 0 0x3000>;
  			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
-			phys = <&ufs_card_phy_lanes>;
+			phys = <&ufs_card_phy>;
  			phy-names = "ufsphy";
  			lanes-per-direction = <2>;
  			#reset-cells = <1>;

@@ -1005,28 +998,20 @@ ufs_card_hc: ufs@1da4000 {
 
  		ufs_card_phy: phy@1da7000 {
  			compatible = "qcom,sc8280xp-qmp-ufs-phy";
-			reg = <0 0x01da7000 0 0x1c8>;
-			#address-cells = <2>;
-			#size-cells = <2>;
-			ranges;
-			clock-names = "ref",
-				      "ref_aux";
+			reg = <0 0x01da7000 0 0x1000>;
+
  			clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>,
  				 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>;
+			clock-names = "ref", "ref_aux";
+
+			power-domains = <&gcc UFS_CARD_GDSC>;
 
  			resets = <&ufs_card_hc 0>;
  			reset-names = "ufsphy";
 
-			status = "disabled";
+			#phy-cells = <0>;
 
-			ufs_card_phy_lanes: phy@1da7400 {
-				reg = <0 0x01da7400 0 0x108>,
-				      <0 0x01da7600 0 0x1e0>,
-				      <0 0x01da7c00 0 0x1dc>,
-				      <0 0x01da7800 0 0x108>,
-				      <0 0x01da7a00 0 0x1e0>;
-				#phy-cells = <0>;
-			};
+			status = "disabled";
  		};
 
  		tcsr_mutex: hwlock@1f40000 {

Update the UFS PHY nodes to match the new binding.

Signed-off-by Johan Hovold <[email protected]>

Quoted 3 lines · Johan Hovold

Update the UFS PHY nodes to match the new binding.

Signed-off-by Johan Hovold <[email protected]>

This is needed in order to boot the sa8540p on linux-next-20221110.

After some initial confusion, we've finally settled how the UFS ref clocks are used.

The first patch fixes the UFS controller and PHY nodes so that they reflect the hardware. This one should go in 6.1-rc where the two previous attempts to address this are heading.

[...]

After some initial confusion, we've finally settled how the UFS ref clocks are used.

The first patch fixes the UFS controller and PHY nodes so that they reflect the hardware. This one should go in 6.1-rc where the two previous attempts to address this are heading.

[...]