iommu/arm-smmu-qcom: Add SC7280 support

Adreno(GPU) SMMU and APSS(Application Processor SubSystem) SMMU both implement "arm,mmu-500" in some QTI SoCs and to run through adreno smmu specific implementation such as enabling split pagetables support, we need to match the "qcom,adreno-smmu" compatible first before apss smmu or else we will be running apps smmu implementation for adreno smmu and the additional features for adreno smmu is never set. For ex: we have "qcom,sc7280-smmu-500" compatible for both apps and adreno smmu implementing "arm,mmu-500", so the adreno smmu implementation is never reached because the current sequence checks for apps smmu compatible(qcom,sc7280-smmu-500) first and runs that specific impl and we never reach adreno smmu specific implementation.

Suggested-by Akhil P Oommen <[email protected]>

Signed-off-by Sai Prakash Ranjan <[email protected]>

---
 drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +9 -3

index bea3ee0dabc2..03f048aebb80 100644
@@ -345,11 +345,17 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)
 {
 	const struct device_node *np = smmu->dev->of_node;
 
-	if (of_match_node(qcom_smmu_impl_of_match, np))
-		return qcom_smmu_create(smmu, &qcom_smmu_impl);
-
+	/*
+	 * Do not change this order of implementation, i.e., first adreno
+	 * smmu impl and then apss smmu since we can have both implementing
+	 * arm,mmu-500 in which case we will miss setting adreno smmu specific
+	 * features if the order is changed.
+	 */
 	if (of_device_is_compatible(np, "qcom,adreno-smmu"))
 		return qcom_smmu_create(smmu, &qcom_adreno_smmu_impl);
 
+	if (of_match_node(qcom_smmu_impl_of_match, np))
+		return qcom_smmu_create(smmu, &qcom_smmu_impl);
+
 	return smmu;
 }

Signature · 7 lines

QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

_______________________________________________
iommu mailing list
[email protected]
https://lists.linuxfoundation.org/mailman/listinfo/iommu

Adreno(GPU) SMMU and APSS(Application Processor SubSystem) SMMU both implement "arm,mmu-500" in some QTI SoCs and to run through adreno smmu specific implementation such as enabling split pagetables support, we need to match the "qcom,adreno-smmu" compatible first before apss smmu or else we will be running apps smmu implementation for adreno smmu and the additional features for adreno smmu is never set. For ex: we have "qcom,sc7280-smmu-500" compatible for both apps and adreno smmu implementing "arm,mmu-500", so the adreno smmu implementation is never reached because the current sequence checks for apps smmu compatible(qcom,sc7280-smmu-500) first and runs that specific impl and we never reach adreno smmu specific implementation.

Suggested-by Akhil P Oommen <[email protected]>

Signed-off-by Sai Prakash Ranjan <[email protected]>

---
 drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +9 -3

index bea3ee0dabc2..03f048aebb80 100644
@@ -345,11 +345,17 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)
 {
 	const struct device_node *np = smmu->dev->of_node;
 
-	if (of_match_node(qcom_smmu_impl_of_match, np))
-		return qcom_smmu_create(smmu, &qcom_smmu_impl);
-
+	/*
+	 * Do not change this order of implementation, i.e., first adreno
+	 * smmu impl and then apss smmu since we can have both implementing
+	 * arm,mmu-500 in which case we will miss setting adreno smmu specific
+	 * features if the order is changed.
+	 */
 	if (of_device_is_compatible(np, "qcom,adreno-smmu"))
 		return qcom_smmu_create(smmu, &qcom_adreno_smmu_impl);
 
+	if (of_match_node(qcom_smmu_impl_of_match, np))
+		return qcom_smmu_create(smmu, &qcom_smmu_impl);
+
 	return smmu;
 }

Signature · 2 lines

QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

Quoted 12 lines · Sai Prakash Ranjan

Adreno(GPU) SMMU and APSS(Application Processor SubSystem) SMMU both implement "arm,mmu-500" in some QTI SoCs and to run through adreno smmu specific implementation such as enabling split pagetables support, we need to match the "qcom,adreno-smmu" compatible first before apss smmu or else we will be running apps smmu implementation for adreno smmu and the additional features for adreno smmu is never set. For ex: we have "qcom,sc7280-smmu-500" compatible for both apps and adreno smmu implementing "arm,mmu-500", so the adreno smmu implementation is never reached because the current sequence checks for apps smmu compatible(qcom,sc7280-smmu-500) first and runs that specific impl and we never reach adreno smmu specific implementation.

So you're saying that you have a single SMMU instance that's compatible with both an entry in qcom_smmu_impl_of_match[] and "qcom,adreno-smmu"?

Per your proposed change we will pick the adreno ops _only_ for this component, essentially disabling the non-Adreno quirks selected by the qcom impl. As such keeping the non-adreno compatible in the qcom_smmu_impl_init[] seems to only serve to obfuscate the situation.

Don't we somehow need the combined set of quirks? (At least if we're running this with a standard UEFI based boot flow?)

Quoted 24 lines · Bjorn Andersson

Quoted 12 lines · Sai Prakash Ranjan

Adreno(GPU) SMMU and APSS(Application Processor SubSystem) SMMU both implement "arm,mmu-500" in some QTI SoCs and to run through adreno smmu specific implementation such as enabling split pagetables support, we need to match the "qcom,adreno-smmu" compatible first before apss smmu or else we will be running apps smmu implementation for adreno smmu and the additional features for adreno smmu is never set. For ex: we have "qcom,sc7280-smmu-500" compatible for both apps and adreno smmu implementing "arm,mmu-500", so the adreno smmu implementation is never reached because the current sequence checks for apps smmu compatible(qcom,sc7280-smmu-500) first and runs that specific impl and we never reach adreno smmu specific implementation.

So you're saying that you have a single SMMU instance that's compatible with both an entry in qcom_smmu_impl_of_match[] and "qcom,adreno-smmu"?

Per your proposed change we will pick the adreno ops _only_ for this component, essentially disabling the non-Adreno quirks selected by the qcom impl. As such keeping the non-adreno compatible in the qcom_smmu_impl_init[] seems to only serve to obfuscate the situation.

Quoted 3 lines

Don't we somehow need the combined set of quirks? (At least if we're running this with a standard UEFI based boot flow?)

are you thinking of the apps-smmu handover of display context bank? That shouldn't change, the only thing that changes is that gpu-smmu becomes an mmu-500, whereas previously only apps-smmu was..

On Fri 26 Feb 12:23 CST 2021, Rob Clark wrote:

The current logic picks one of:
1) is the compatible mentioned in qcom_smmu_impl_of_match[]
2) is the compatible an adreno
3) no quirks needed

The change flips the order of these, so the only way I can see this change affecting things is if we expected a match on #2, but we got one on #1.

Which implies that the instance that we want to act according to the adreno impl was listed in qcom_smmu_impl_of_match[] - which either is wrong, or there's a single instance that needs both behaviors.

(And I believe Jordan's answer confirms the latter - there's a single SMMU instance that needs all them quirks at once)

Hi Bjorn,

Quoted 12 lines · Bjorn Andersson

On Fri 26 Feb 12:23 CST 2021, Rob Clark wrote:

The current logic picks one of:
1) is the compatible mentioned in qcom_smmu_impl_of_match[]
2) is the compatible an adreno
3) no quirks needed

The change flips the order of these, so the only way I can see this change affecting things is if we expected a match on #2, but we got one on #1.

Quoted 7 lines

Which implies that the instance that we want to act according to the adreno impl was listed in qcom_smmu_impl_of_match[] - which either is wrong, or there's a single instance that needs both behaviors.

(And I believe Jordan's answer confirms the latter - there's a single SMMU instance that needs all them quirks at once)

Let me go through the problem statement in case my commit message wasn't clear. There are two SMMUs (APSS and GPU) on SC7280 and both are SMMU500 (ARM SMMU IP).

APSS SMMU compatible - ("qcom,sc7280-smmu-500", "arm,mmu-500")
GPU SMMU compatible - ("qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500")

Now if we take SC7180 as an example, GPU SMMU was QSMMU(QCOM SMMU IP) and APSS SMMU was SMMU500(ARM SMMU IP).

APSS SMMU compatible - ("qcom,sc7180-smmu-500", "arm,mmu-500")
GPU SMMU compatible - ("qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2")

Current code sequence without this patch,

if (of_match_node(qcom_smmu_impl_of_match, np))

                 return qcom_smmu_create(smmu, &qcom_smmu_impl);

if (of_device_is_compatible(np, "qcom,adreno-smmu"))

        return qcom_smmu_create(smmu, &qcom_adreno_smmu_impl);

Now if we look at the compatible for SC7180, there is no problem because the APSS SMMU will match the one in qcom_smmu_impl_of_match[] and GPU SMMU will match "qcom,adreno-smmu" because the compatible strings are different. But for SC7280, both the APSS SMMU and GPU SMMU compatible("qcom,sc7280-smmu-500") are same. So GPU SMMU will match with the one in qcom_smmu_impl_of_match[] i.e.., "qcom,sc7280-smmu-500" which functionally doesn't cause any problem but we will miss settings for split pagetables which are part of GPU SMMU specific implementation.

We can avoid this with yet another new compatible for GPU SMMU something like "qcom,sc7280-adreno-smmu-500" but since we can handle this easily in the driver and since the IPs are same, meaning if there was a hardware quirk required, then we would need to apply to both of them and would this additional compatible be of any help?

Coming to the part of quirks now, you are right saying both SMMUs will need to have the same quirks in SC7280 and similar others where both are based on same IPs but those should probably be *hardware quirks* and if they are software based like the S2CR quirk depending on the firmware, then it might not be applicable to both. In case if it is applicable, then as Jordan mentioned, we can add the same quirks in GPU SMMU implementation.

Quoted 53 lines · Sai Prakash Ranjan

Hi Bjorn,

Quoted 12 lines · Bjorn Andersson

On Fri 26 Feb 12:23 CST 2021, Rob Clark wrote:

The current logic picks one of:
1) is the compatible mentioned in qcom_smmu_impl_of_match[]
2) is the compatible an adreno
3) no quirks needed

The change flips the order of these, so the only way I can see this change affecting things is if we expected a match on #2, but we got one on #1.

Quoted 7 lines

Which implies that the instance that we want to act according to the adreno impl was listed in qcom_smmu_impl_of_match[] - which either is wrong, or there's a single instance that needs both behaviors.

(And I believe Jordan's answer confirms the latter - there's a single SMMU instance that needs all them quirks at once)

Let me go through the problem statement in case my commit message wasn't clear. There are two SMMUs (APSS and GPU) on SC7280 and both are SMMU500 (ARM SMMU IP).

APSS SMMU compatible - ("qcom,sc7280-smmu-500", "arm,mmu-500")
GPU SMMU compatible - ("qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500")

Now if we take SC7180 as an example, GPU SMMU was QSMMU(QCOM SMMU IP) and APSS SMMU was SMMU500(ARM SMMU IP).

APSS SMMU compatible - ("qcom,sc7180-smmu-500", "arm,mmu-500")
GPU SMMU compatible - ("qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2")

Current code sequence without this patch,

if (of_match_node(qcom_smmu_impl_of_match, np))

                 return qcom_smmu_create(smmu, &qcom_smmu_impl);

if (of_device_is_compatible(np, "qcom,adreno-smmu"))

        return qcom_smmu_create(smmu, &qcom_adreno_smmu_impl);

Now if we look at the compatible for SC7180, there is no problem because the APSS SMMU will match the one in qcom_smmu_impl_of_match[] and GPU SMMU will match "qcom,adreno-smmu" because the compatible strings are different. But for SC7280, both the APSS SMMU and GPU SMMU compatible("qcom,sc7280-smmu-500") are same. So GPU SMMU will match with the one in qcom_smmu_impl_of_match[] i.e.., "qcom,sc7280-smmu-500" which functionally doesn't cause any problem but we will miss settings for split pagetables which are part of GPU SMMU specific implementation.

Quoted 6 lines

We can avoid this with yet another new compatible for GPU SMMU something like "qcom,sc7280-adreno-smmu-500" but since we can handle this easily in the driver and since the IPs are same, meaning if there was a hardware quirk required, then we would need to apply to both of them and would this additional compatible be of any help?

No, I think you're doing the right thing of having them both. I just didn't remember us doing that.

Quoted 7 lines

Coming to the part of quirks now, you are right saying both SMMUs will need to have the same quirks in SC7280 and similar others where both are based on same IPs but those should probably be *hardware quirks* and if they are software based like the S2CR quirk depending on the firmware, then it might not be applicable to both. In case if it is applicable, then as Jordan mentioned, we can add the same quirks in GPU SMMU implementation.

I do suspect that at some point (probably sooner than later) we'd have to support both inheriting of stream from the bootloader and the Adreno "quirks" in the same instance.

But for now this is okay to me.

Quoted 77 lines · Bjorn Andersson

Quoted 53 lines · Sai Prakash Ranjan

Hi Bjorn,

Quoted 12 lines · Bjorn Andersson

On Fri 26 Feb 12:23 CST 2021, Rob Clark wrote:

The current logic picks one of:
1) is the compatible mentioned in qcom_smmu_impl_of_match[]
2) is the compatible an adreno
3) no quirks needed

The change flips the order of these, so the only way I can see this change affecting things is if we expected a match on #2, but we got one on #1.

Quoted 7 lines

Which implies that the instance that we want to act according to the adreno impl was listed in qcom_smmu_impl_of_match[] - which either is wrong, or there's a single instance that needs both behaviors.

(And I believe Jordan's answer confirms the latter - there's a single SMMU instance that needs all them quirks at once)

Let me go through the problem statement in case my commit message wasn't clear. There are two SMMUs (APSS and GPU) on SC7280 and both are SMMU500 (ARM SMMU IP).

APSS SMMU compatible - ("qcom,sc7280-smmu-500", "arm,mmu-500")
GPU SMMU compatible - ("qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500")

Now if we take SC7180 as an example, GPU SMMU was QSMMU(QCOM SMMU IP) and APSS SMMU was SMMU500(ARM SMMU IP).

APSS SMMU compatible - ("qcom,sc7180-smmu-500", "arm,mmu-500")
GPU SMMU compatible - ("qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2")

Current code sequence without this patch,

if (of_match_node(qcom_smmu_impl_of_match, np))

                 return qcom_smmu_create(smmu, &qcom_smmu_impl);

if (of_device_is_compatible(np, "qcom,adreno-smmu"))

        return qcom_smmu_create(smmu, &qcom_adreno_smmu_impl);

Now if we look at the compatible for SC7180, there is no problem because the APSS SMMU will match the one in qcom_smmu_impl_of_match[] and GPU SMMU will match "qcom,adreno-smmu" because the compatible strings are different. But for SC7280, both the APSS SMMU and GPU SMMU compatible("qcom,sc7280-smmu-500") are same. So GPU SMMU will match with the one in qcom_smmu_impl_of_match[] i.e.., "qcom,sc7280-smmu-500" which functionally doesn't cause any problem but we will miss settings for split pagetables which are part of GPU SMMU specific implementation.

Quoted 6 lines

We can avoid this with yet another new compatible for GPU SMMU something like "qcom,sc7280-adreno-smmu-500" but since we can handle this easily in the driver and since the IPs are same, meaning if there was a hardware quirk required, then we would need to apply to both of them and would this additional compatible be of any help?

No, I think you're doing the right thing of having them both. I just didn't remember us doing that.

Quoted 7 lines

Coming to the part of quirks now, you are right saying both SMMUs will need to have the same quirks in SC7280 and similar others where both are based on same IPs but those should probably be *hardware quirks* and if they are software based like the S2CR quirk depending on the firmware, then it might not be applicable to both. In case if it is applicable, then as Jordan mentioned, we can add the same quirks in GPU SMMU implementation.

I do suspect that at some point (probably sooner than later) we'd have to support both inheriting of stream from the bootloader and the Adreno "quirks" in the same instance.

Quoted 2 lines

But for now this is okay to me.

Sure, let me know if you or anyone face any issues without it and I will add it. I will resend this series with the dt-bindings patch for sc7280 smmu which wasn't cc'd to smmu folks by mistake.

Quoted 99 lines · Sai Prakash Ranjan

Quoted 97 lines · Bjorn Andersson

Quoted 62 lines · Sai Prakash Ranjan

Quoted 12 lines · Bjorn Andersson

On Fri 26 Feb 12:23 CST 2021, Rob Clark wrote:

The current logic picks one of:
1) is the compatible mentioned in qcom_smmu_impl_of_match[]
2) is the compatible an adreno
3) no quirks needed

The change flips the order of these, so the only way I can see this change affecting things is if we expected a match on #2, but we got one on #1.

Quoted 7 lines

Which implies that the instance that we want to act according to the adreno impl was listed in qcom_smmu_impl_of_match[] - which either is wrong, or there's a single instance that needs both behaviors.

(And I believe Jordan's answer confirms the latter - there's a single SMMU instance that needs all them quirks at once)

Let me go through the problem statement in case my commit message wasn't
clear. There are two SMMUs (APSS and GPU) on SC7280 and both are SMMU500
(ARM SMMU IP).

APSS SMMU compatible - ("qcom,sc7280-smmu-500", "arm,mmu-500") GPU SMMU compatible - ("qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500")

Now if we take SC7180 as an example, GPU SMMU was QSMMU(QCOM SMMU IP) and APSS SMMU was SMMU500(ARM SMMU IP).

APSS SMMU compatible - ("qcom,sc7180-smmu-500", "arm,mmu-500") GPU SMMU compatible - ("qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2")

Current code sequence without this patch,

if (of_match_node(qcom_smmu_impl_of_match, np))

                 return qcom_smmu_create(smmu, &qcom_smmu_impl);

if (of_device_is_compatible(np, "qcom,adreno-smmu"))

        return qcom_smmu_create(smmu, &qcom_adreno_smmu_impl);

Now if we look at the compatible for SC7180, there is no problem because
the APSS SMMU will match the one in qcom_smmu_impl_of_match[] and GPU SMMU
will match "qcom,adreno-smmu" because the compatible strings are different.
But for SC7280, both the APSS SMMU and GPU SMMU compatible("qcom,sc7280-smmu-500")
are same. So GPU SMMU will match with the one in qcom_smmu_impl_of_match[]
i.e.., "qcom,sc7280-smmu-500" which functionally doesn't cause any problem
but we will miss settings for split pagetables which are part of GPU SMMU
specific implementation.

Quoted 10 lines

We can avoid this with yet another new compatible for GPU SMMU something like
"qcom,sc7280-adreno-smmu-500" but since we can handle this easily in the
driver and since the IPs are same, meaning if there was a hardware quirk
required, then we would need to apply to both of them and would this additional
compatible be of any help?

No, I think you're doing the right thing of having them both. I just didn't remember us doing that.

Quoted 12 lines

Coming to the part of quirks now, you are right saying both SMMUs will need
to have the same quirks in SC7280 and similar others where both are based on
same IPs but those should probably be *hardware quirks* and if they are
software based like the S2CR quirk depending on the firmware, then it might
not be applicable to both. In case if it is applicable, then as Jordan mentioned,
we can add the same quirks in GPU SMMU implementation.

I do suspect that at some point (probably sooner than later) we'd have to support both inheriting of stream from the bootloader and the Adreno
"quirks" in the same instance.

But for now this is okay to me.

Quoted 5 lines

Sure, let me know if you or anyone face any issues without it and I will add it. I will resend this series with the dt-bindings patch for sc7280 smmu
which wasn't cc'd to smmu folks by mistake.

I think there is consensus on this series. I can resend if required but it still applies cleanly, let me know if you have any comments?

On Thu, Mar 25, 2021 at 01:10:12PM +0530, Sai Prakash Ranjan wrote:

Quoted 3 lines

I think there is consensus on this series. I can resend if required but it still applies cleanly, let me know if you have any comments?

Please resend with the bindings patch, and I'd like Bjorn's Ack as well.

Hi Bjorn,

Quoted 1 line · Will Deacon

On Thu, Mar 25, 2021 at 01:10:12PM +0530, Sai Prakash Ranjan wrote:

<snip>...

Quoted 1 line

Quoted 1 line

Quoted 5 lines

Quoted 2 lines

I think there is consensus on this series. I can resend if required but it still applies cleanly, let me know if you have any comments?

Please resend with the bindings patch, and I'd like Bjorn's Ack as well.

Can we have your review/ack in case there is nothing pending here?

Quoted 12 lines · Sai Prakash Ranjan

Adreno(GPU) SMMU and APSS(Application Processor SubSystem) SMMU both implement "arm,mmu-500" in some QTI SoCs and to run through adreno smmu specific implementation such as enabling split pagetables support, we need to match the "qcom,adreno-smmu" compatible first before apss smmu or else we will be running apps smmu implementation for adreno smmu and the additional features for adreno smmu is never set. For ex: we have "qcom,sc7280-smmu-500" compatible for both apps and adreno smmu implementing "arm,mmu-500", so the adreno smmu implementation is never reached because the current sequence checks for apps smmu compatible(qcom,sc7280-smmu-500) first and runs that specific impl and we never reach adreno smmu specific implementation.

So you're saying that you have a single SMMU instance that's compatible with both an entry in qcom_smmu_impl_of_match[] and "qcom,adreno-smmu"?

Per your proposed change we will pick the adreno ops _only_ for this component, essentially disabling the non-Adreno quirks selected by the qcom impl. As such keeping the non-adreno compatible in the qcom_smmu_impl_init[] seems to only serve to obfuscate the situation.

Don't we somehow need the combined set of quirks? (At least if we're running this with a standard UEFI based boot flow?)

Quoted 26 lines

Suggested-by Akhil P Oommen <[email protected]>

Signed-off-by Sai Prakash Ranjan <[email protected]>

---
 drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +6 -3

index bea3ee0dabc2..03f048aebb80 100644
@@ -345,11 +345,17 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)
 {
 	const struct device_node *np = smmu->dev->of_node;
 
-	if (of_match_node(qcom_smmu_impl_of_match, np))
-		return qcom_smmu_create(smmu, &qcom_smmu_impl);
-
+	/*
+	 * Do not change this order of implementation, i.e., first adreno
+	 * smmu impl and then apss smmu since we can have both implementing
+	 * arm,mmu-500 in which case we will miss setting adreno smmu specific
+	 * features if the order is changed.
+	 */
 	if (of_device_is_compatible(np, "qcom,adreno-smmu"))
 		return qcom_smmu_create(smmu, &qcom_adreno_smmu_impl);
 

Quoted 9 lines

drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +3 -0

+	if (of_match_node(qcom_smmu_impl_of_match, np))
+		return qcom_smmu_create(smmu, &qcom_smmu_impl);
+
 	return smmu;
 }

Signature · 2 lines

QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

_______________________________________________
iommu mailing list
[email protected]
https://lists.linuxfoundation.org/mailman/listinfo/iommu

Quoted 18 lines · Bjorn Andersson

Quoted 12 lines · Sai Prakash Ranjan

Adreno(GPU) SMMU and APSS(Application Processor SubSystem) SMMU both implement "arm,mmu-500" in some QTI SoCs and to run through adreno smmu specific implementation such as enabling split pagetables support, we need to match the "qcom,adreno-smmu" compatible first before apss smmu or else we will be running apps smmu implementation for adreno smmu and the additional features for adreno smmu is never set. For ex: we have "qcom,sc7280-smmu-500" compatible for both apps and adreno smmu implementing "arm,mmu-500", so the adreno smmu implementation is never reached because the current sequence checks for apps smmu compatible(qcom,sc7280-smmu-500) first and runs that specific impl and we never reach adreno smmu specific implementation.

So you're saying that you have a single SMMU instance that's compatible with both an entry in qcom_smmu_impl_of_match[] and "qcom,adreno-smmu"?

Quoted 7 lines

Per your proposed change we will pick the adreno ops _only_ for this component, essentially disabling the non-Adreno quirks selected by the qcom impl. As such keeping the non-adreno compatible in the qcom_smmu_impl_init[] seems to only serve to obfuscate the situation.

Don't we somehow need the combined set of quirks? (At least if we're running this with a standard UEFI based boot flow?)

We *do* need the combined set of quirks, so there has to be an adreno-smmu impelmentation that matches the "generic" implementation with a few extra function hooks added on. I'm not sure if there is a clever way to figure out how to meld the implementation hooks at runtime but the alternative is to just make sure that the adreno-smmu static struct calls the same quirks as its generic partner.

Quoted 26 lines

Quoted 26 lines

Suggested-by Akhil P Oommen <[email protected]>

Signed-off-by Sai Prakash Ranjan <[email protected]>

---
 drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +6 -3

index bea3ee0dabc2..03f048aebb80 100644
@@ -345,11 +345,17 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)
 {
 	const struct device_node *np = smmu->dev->of_node;
 
-	if (of_match_node(qcom_smmu_impl_of_match, np))
-		return qcom_smmu_create(smmu, &qcom_smmu_impl);
-
+	/*
+	 * Do not change this order of implementation, i.e., first adreno
+	 * smmu impl and then apss smmu since we can have both implementing
+	 * arm,mmu-500 in which case we will miss setting adreno smmu specific
+	 * features if the order is changed.
+	 */
 	if (of_device_is_compatible(np, "qcom,adreno-smmu"))
 		return qcom_smmu_create(smmu, &qcom_adreno_smmu_impl);
 

Quoted 5 lines

Quoted 5 lines

drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +3 -0

+	if (of_match_node(qcom_smmu_impl_of_match, np))
+		return qcom_smmu_create(smmu, &qcom_smmu_impl);
+
 	return smmu;
 }

Quoted 8 lines

Quoted 4 lines

Signature · 2 lines

QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

_______________________________________________
iommu mailing list
[email protected]
https://lists.linuxfoundation.org/mailman/listinfo/iommu

Adreno(GPU) SMMU and APSS(Application Processor SubSystem) SMMU both implement "arm,mmu-500" in some QTI SoCs and to run through adreno smmu specific implementation such as enabling split pagetables support, we need to match the "qcom,adreno-smmu" compatible first before apss smmu or else we will be running apps smmu implementation for adreno smmu and the additional features for adreno smmu is never set. For ex: we have "qcom,sc7280-smmu-500" compatible for both apps and adreno smmu implementing "arm,mmu-500", so the adreno smmu implementation is never reached because the current sequence checks for apps smmu compatible(qcom,sc7280-smmu-500) first and runs that specific impl and we never reach adreno smmu specific implementation.

Suggested-by Akhil P Oommen <[email protected]>

Signed-off-by Sai Prakash Ranjan <[email protected]>

---
 drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +9 -3

index bea3ee0dabc2..03f048aebb80 100644
@@ -345,11 +345,17 @@ struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu)
 {
 	const struct device_node *np = smmu->dev->of_node;
 
-	if (of_match_node(qcom_smmu_impl_of_match, np))
-		return qcom_smmu_create(smmu, &qcom_smmu_impl);
-
+	/*
+	 * Do not change this order of implementation, i.e., first adreno
+	 * smmu impl and then apss smmu since we can have both implementing
+	 * arm,mmu-500 in which case we will miss setting adreno smmu specific
+	 * features if the order is changed.
+	 */
 	if (of_device_is_compatible(np, "qcom,adreno-smmu"))
 		return qcom_smmu_create(smmu, &qcom_adreno_smmu_impl);
 
+	if (of_match_node(qcom_smmu_impl_of_match, np))
+		return qcom_smmu_create(smmu, &qcom_smmu_impl);
+
 	return smmu;
 }

Signature · 2 lines

QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

Quoted 12 lines · Sai Prakash Ranjan

Adreno(GPU) SMMU and APSS(Application Processor SubSystem) SMMU both implement "arm,mmu-500" in some QTI SoCs and to run through adreno smmu specific implementation such as enabling split pagetables support, we need to match the "qcom,adreno-smmu" compatible first before apss smmu or else we will be running apps smmu implementation for adreno smmu and the additional features for adreno smmu is never set. For ex: we have "qcom,sc7280-smmu-500" compatible for both apps and adreno smmu implementing "arm,mmu-500", so the adreno smmu implementation is never reached because the current sequence checks for apps smmu compatible(qcom,sc7280-smmu-500) first and runs that specific impl and we never reach adreno smmu specific implementation.

Quoted 2 lines

Suggested-by Akhil P Oommen <[email protected]>

Signed-off-by Sai Prakash Ranjan <[email protected]>

Sorry for taking my time thinking about this.

Reviewed-by Bjorn Andersson <[email protected]>