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arm64: dts: qcom: sc7180: Add xo clock for eMMC and Sd card

PATCH Superseded Shaik Sajida Bhanu 3 participants 3 messages Jun 16, 2021 – Jun 18, 2021

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Device tree bindings Arm Qualcomm mailing list MMC, SD and SDIO Arm Qualcomm support +1 more subsystems
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Shaik Sajida Bhanu

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#0 lore raw

PATCH v2 1/1 arm64: dts: qcom: sc7180: Add xo clock for eMMC and Sd card

Add XO clock for eMMC and SDCard as it would help in calculating dll register values.

Signed-off-by Shaik Sajida Bhanu <[email protected]>
Reviewed-by Konrad Dybcio <[email protected]>

---

Changes since V1:
- Updated commit message as suggested by Bjorn Andersson.
- Added space after before xo clock name as suggested by Konrad Dybcio.

---
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)
arch/arm64/boot/dts/qcom/sc7180.dtsi +6 -4
index 52115e0..fb1d9ad 100644
@@ -701,8 +701,9 @@
 			interrupt-names = "hc_irq", "pwr_irq";
 
 			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
-					<&gcc GCC_SDCC1_AHB_CLK>;
-			clock-names = "core", "iface";
+				 <&gcc GCC_SDCC1_AHB_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "core", "iface", "xo";
 			interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
 					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
 			interconnect-names = "sdhc-ddr","cpu-sdhc";

@@ -2564,8 +2565,9 @@
 			interrupt-names = "hc_irq", "pwr_irq";
 
 			clocks = <&gcc GCC_SDCC2_APPS_CLK>,
-					<&gcc GCC_SDCC2_AHB_CLK>;
-			clock-names = "core", "iface";
+				 <&gcc GCC_SDCC2_AHB_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "core", "iface", "xo";
 
 			interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
 					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member 
of Code Aurora Forum, hosted by The Linux Foundation
#2 lore raw
In reply to Shaik Sajida Bhanu
Quoted 11 lines · Shaik Sajida Bhanu

Add XO clock for eMMC and SDCard as it would help in calculating dll register values.

Signed-off-by Shaik Sajida Bhanu <[email protected]>
Reviewed-by Konrad Dybcio <[email protected]>

---

Changes since V1:
- Updated commit message as suggested by Bjorn Andersson.
- Added space after before xo clock name as suggested by Konrad Dybcio.

Thank you Shaik. Sorry if I wasn't clear when I tried to say that I fixed these things and applied your previous patch.

Regards,
Bjorn

Quoted 36 lines
---
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)
arch/arm64/boot/dts/qcom/sc7180.dtsi +6 -4
index 52115e0..fb1d9ad 100644
@@ -701,8 +701,9 @@
 			interrupt-names = "hc_irq", "pwr_irq";
 
 			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
-					<&gcc GCC_SDCC1_AHB_CLK>;
-			clock-names = "core", "iface";
+				 <&gcc GCC_SDCC1_AHB_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "core", "iface", "xo";
 			interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
 					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
 			interconnect-names = "sdhc-ddr","cpu-sdhc";

@@ -2564,8 +2565,9 @@
 			interrupt-names = "hc_irq", "pwr_irq";
 
 			clocks = <&gcc GCC_SDCC2_APPS_CLK>,
-					<&gcc GCC_SDCC2_AHB_CLK>;
-			clock-names = "core", "iface";
+				 <&gcc GCC_SDCC2_AHB_CLK>,
+				 <&rpmhcc RPMH_CXO_CLK>;
+			clock-names = "core", "iface", "xo";
 
 			interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
 					<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member 
of Code Aurora Forum, hosted by The Linux Foundation