imx8q video decoder/encoder driver
Subsystems (3)
v5 cover imx8q video decoder/encoder driver
Hi all,
This patch series adds support for
the imx8q video encoder and decoder
via the VPU block present in imx8q platforms. Currently, support for IMX8QXP and IMX8QM is included.
It features decoding for the following formats:
- H.264
- HEVC
- MPEG4
- MPEG2
- VC1
- VP8
It features encoding for the following formats:
- H.264
The driver creates a separate device node for the encoder and decoder.
Changelog:
v5:
- move some definition from imx_vph.h to videodev2.h
- remove some unnecessary content
- add some documentation descriptions
- pass the lateset v4l2-compliance test
v4:
- redefine the memory-region in devicetree bindings documentation
- use v4l2's mechanism to implement synchronize queuing ioctl
- remove the unnecessary mutex ioctl_sync
- don't notify source change event if the parameters are same as previously established
- add flag V4L2_FMT_FLAG_DYN_RESOLUTION to decoder's capture format
v3:
- don't make vpu device node a simple-bus
- trigger probing vpu core in the driver
- remove unnecessary vpu core index property
v2:
- fix dt bindings build error
- split driver patch into several parts to avoid exceeding bytes limit
Compliance
==========
# v4l2-compliance -d /dev/video0 v4l2-compliance 1.21.0-4831, 64 bits, 64-bit time_t v4l2-compliance SHA: a4f2e3a6f306 2021-07-13 08:04:15
Compliance test for vpu B0 device /dev/video0:
Driver Info:
Driver name : vpu B0 Card type : imx vpu decoder Bus info : platform: imx8q-vpu Driver version : 5.10.46 Capabilities : 0x84204000
Video Memory-to-Memory Multiplanar Streaming
Extended Pix Format
Device Capabilities
Device Caps : 0x04204000
Video Memory-to-Memory Multiplanar Streaming
Extended Pix Format
Detected Stateful Decoder
Required ioctls:
test VIDIOC_QUERYCAP: OK
test invalid ioctls: OK
Allow for multiple opens:
test second /dev/video0 open: OK test VIDIOC_QUERYCAP: OK
test VIDIOC_G/S_PRIORITY: OK
test for unlimited opens: OK
Debug ioctls:
test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported) test VIDIOC_LOG_STATUS: OK (Not Supported)
Input ioctls:
test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported) test VIDIOC_G/S_FREQUENCY: OK (Not Supported) test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported) test VIDIOC_ENUMAUDIO: OK (Not Supported)
test VIDIOC_G/S/ENUMINPUT: OK (Not Supported) test VIDIOC_G/S_AUDIO: OK (Not Supported)
Inputs: 0 Audio Inputs: 0 Tuners: 0
Output ioctls:
test VIDIOC_G/S_MODULATOR: OK (Not Supported) test VIDIOC_G/S_FREQUENCY: OK (Not Supported) test VIDIOC_ENUMAUDOUT: OK (Not Supported) test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported) test VIDIOC_G/S_AUDOUT: OK (Not Supported)
Outputs: 0 Audio Outputs: 0 Modulators: 0
Input/Output configuration ioctls:
test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported) test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported) test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported) test VIDIOC_G/S_EDID: OK (Not Supported)
Control ioctls:
test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK test VIDIOC_QUERYCTRL: OK
test VIDIOC_G/S_CTRL: OK
test VIDIOC_G/S/TRY_EXT_CTRLS: OK test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK test VIDIOC_G/S_JPEGCOMP: OK (Not Supported) Standard Controls: 3 Private Controls: 2
Format ioctls:
test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK test VIDIOC_G/S_PARM: OK (Not Supported) test VIDIOC_G_FBUF: OK (Not Supported) test VIDIOC_G_FMT: OK
test VIDIOC_TRY_FMT: OK
test VIDIOC_S_FMT: OK
test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported) test Cropping: OK (Not Supported)
test Composing: OK
test Scaling: OK (Not Supported)
Codec ioctls:
test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported) test VIDIOC_G_ENC_INDEX: OK (Not Supported) test VIDIOC_(TRY_)DECODER_CMD: OK
Buffer ioctls:
test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK test VIDIOC_EXPBUF: OK
test Requests: OK (Not Supported)
Total for vpu B0 device /dev/video0: 45, Succeeded: 45, Failed: 0, Warnings: 0
# v4l2-compliance -d /dev/video1 v4l2-compliance 1.21.0-4831, 64 bits, 64-bit time_t v4l2-compliance SHA: a4f2e3a6f306 2021-07-13 08:04:15
Compliance test for imx vpu encoder device /dev/video1:
Driver Info:
Driver name : imx vpu encoder Card type : imx vpu encoder Bus info : platform: imx8q-vpu Driver version : 5.10.46 Capabilities : 0x84204000
Video Memory-to-Memory Multiplanar Streaming
Extended Pix Format
Device Capabilities
Device Caps : 0x04204000
Video Memory-to-Memory Multiplanar Streaming
Extended Pix Format
Detected Stateful Encoder
Required ioctls:
test VIDIOC_QUERYCAP: OK
test invalid ioctls: OK
Allow for multiple opens:
test second /dev/video1 open: OK test VIDIOC_QUERYCAP: OK
test VIDIOC_G/S_PRIORITY: OK
test for unlimited opens: OK
Debug ioctls:
test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported) test VIDIOC_LOG_STATUS: OK (Not Supported)
Input ioctls:
test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported) test VIDIOC_G/S_FREQUENCY: OK (Not Supported) test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported) test VIDIOC_ENUMAUDIO: OK (Not Supported)
test VIDIOC_G/S/ENUMINPUT: OK (Not Supported) test VIDIOC_G/S_AUDIO: OK (Not Supported)
Inputs: 0 Audio Inputs: 0 Tuners: 0
Output ioctls:
test VIDIOC_G/S_MODULATOR: OK (Not Supported) test VIDIOC_G/S_FREQUENCY: OK (Not Supported) test VIDIOC_ENUMAUDOUT: OK (Not Supported) test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported) test VIDIOC_G/S_AUDOUT: OK (Not Supported)
Outputs: 0 Audio Outputs: 0 Modulators: 0
Input/Output configuration ioctls:
test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported) test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported) test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported) test VIDIOC_G/S_EDID: OK (Not Supported)
Control ioctls:
test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK test VIDIOC_QUERYCTRL: OK
test VIDIOC_G/S_CTRL: OK
test VIDIOC_G/S/TRY_EXT_CTRLS: OK test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK test VIDIOC_G/S_JPEGCOMP: OK (Not Supported) Standard Controls: 20 Private Controls: 0
Format ioctls:
test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK test VIDIOC_G/S_PARM: OK
test VIDIOC_G_FBUF: OK (Not Supported) test VIDIOC_G_FMT: OK
test VIDIOC_TRY_FMT: OK
test VIDIOC_S_FMT: OK
test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported) test Cropping: OK
test Composing: OK (Not Supported)
test Scaling: OK (Not Supported)
Codec ioctls:
test VIDIOC_(TRY_)ENCODER_CMD: OK
test VIDIOC_G_ENC_INDEX: OK (Not Supported) test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
Buffer ioctls:
test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK test VIDIOC_EXPBUF: OK
test Requests: OK (Not Supported)
Total for imx vpu encoder device /dev/video1: 45, Succeeded: 45, Failed: 0, Warnings: 0
Ming Qian (14):
dt-bindings: media: imx8q: add imx video codec bindings media:Add nt8 and nt10 video format.
media:Add v4l2 buf flag codec data.
media: imx: imx8q: add imx8q vpu device driver
media: imx: imx8q: add vpu core driver
media: imx: imx8q: implement vpu core communication based on mailbox
media: imx: imx8q: add vpu v4l2 m2m support
media: imx: imx8q: add v4l2 m2m vpu encoder stateful driver
media: imx: imx8q: add v4l2 m2m vpu decoder stateful driver
media: imx: imx8q: implement windsor encoder rpc interface
media: imx: imx8q: implement malone decoder rpc interface
ARM64: dts: freescale: imx8q: add imx vpu codec entries
firmware: imx: scu-pd: imx8q: add vpu mu resources
MAINTAINERS: add NXP IMX8Q VPU CODEC V4L2 driver entry
.../bindings/media/nxp,imx8q-vpu.yaml | 178 ++ .../userspace-api/media/v4l/buffer.rst | 8 + .../media/v4l/pixfmt-reserved.rst | 15 + .../media/v4l/vidioc-dqevent.rst | 12 + MAINTAINERS | 10 + .../arm64/boot/dts/freescale/imx8-ss-vpu.dtsi | 72 + arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 17 + arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 26 + drivers/firmware/imx/scu-pd.c | 4 + drivers/media/platform/Kconfig | 2 + drivers/media/platform/Makefile | 2 + drivers/media/platform/imx/Kconfig | 19 + drivers/media/platform/imx/Makefile | 1 + drivers/media/platform/imx/vpu-8q/Makefile | 23 + drivers/media/platform/imx/vpu-8q/vdec.c | 1687 ++++++++++++++++ drivers/media/platform/imx/vpu-8q/venc.c | 1383 ++++++++++++++ drivers/media/platform/imx/vpu-8q/vpu.h | 333 ++++ drivers/media/platform/imx/vpu-8q/vpu_cmds.c | 438 +++++ drivers/media/platform/imx/vpu-8q/vpu_cmds.h | 25 + drivers/media/platform/imx/vpu-8q/vpu_codec.h | 68 + drivers/media/platform/imx/vpu-8q/vpu_color.c | 192 ++ drivers/media/platform/imx/vpu-8q/vpu_core.c | 910 +++++++++ drivers/media/platform/imx/vpu-8q/vpu_core.h | 16 + drivers/media/platform/imx/vpu-8q/vpu_dbg.c | 496 +++++ drivers/media/platform/imx/vpu-8q/vpu_defs.h | 185 ++ .../media/platform/imx/vpu-8q/vpu_dev_imx8q.c | 73 + drivers/media/platform/imx/vpu-8q/vpu_drv.c | 217 +++ .../media/platform/imx/vpu-8q/vpu_helpers.c | 396 ++++ .../media/platform/imx/vpu-8q/vpu_helpers.h | 71 + drivers/media/platform/imx/vpu-8q/vpu_imx8q.c | 218 +++ drivers/media/platform/imx/vpu-8q/vpu_imx8q.h | 116 ++ drivers/media/platform/imx/vpu-8q/vpu_log.h | 44 + .../media/platform/imx/vpu-8q/vpu_malone.c | 1696 +++++++++++++++++ .../media/platform/imx/vpu-8q/vpu_malone.h | 42 + drivers/media/platform/imx/vpu-8q/vpu_mbox.c | 126 ++ drivers/media/platform/imx/vpu-8q/vpu_mbox.h | 16 + drivers/media/platform/imx/vpu-8q/vpu_msgs.c | 411 ++++ drivers/media/platform/imx/vpu-8q/vpu_msgs.h | 14 + drivers/media/platform/imx/vpu-8q/vpu_rpc.c | 257 +++ drivers/media/platform/imx/vpu-8q/vpu_rpc.h | 463 +++++ drivers/media/platform/imx/vpu-8q/vpu_v4l2.c | 653 +++++++ drivers/media/platform/imx/vpu-8q/vpu_v4l2.h | 44 + .../media/platform/imx/vpu-8q/vpu_windsor.c | 1244 ++++++++++++ .../media/platform/imx/vpu-8q/vpu_windsor.h | 39 + drivers/media/v4l2-core/v4l2-ioctl.c | 2 + include/linux/imx_vpu.h | 11 + include/uapi/linux/imx_vpu.h | 17 + include/uapi/linux/videodev2.h | 3 + 48 files changed, 12295 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi create mode 100644 drivers/media/platform/imx/Kconfig create mode 100644 drivers/media/platform/imx/Makefile create mode 100644 drivers/media/platform/imx/vpu-8q/Makefile create mode 100644 drivers/media/platform/imx/vpu-8q/vdec.c create mode 100644 drivers/media/platform/imx/vpu-8q/venc.c create mode 100644 drivers/media/platform/imx/vpu-8q/vpu.h create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_cmds.c create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_cmds.h create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_codec.h create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_color.c create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_core.c create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_core.h create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_dbg.c create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_defs.h create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_dev_imx8q.c create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_drv.c create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_helpers.c create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_helpers.h create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_imx8q.c create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_imx8q.h create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_log.h create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_malone.c create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_malone.h create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_mbox.c create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_mbox.h create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_msgs.c create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_msgs.h create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_rpc.c create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_rpc.h create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_v4l2.c create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_v4l2.h create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_windsor.c create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_windsor.h create mode 100644 include/linux/imx_vpu.h create mode 100644 include/uapi/linux/imx_vpu.h
Signature · 1 line
2.32.0
PATCH v5 1/14 dt-bindings: media: imx8q: add imx video codec bindings
Add devicetree binding documentation for IMX8Q Video Processing Unit IP
--- .../bindings/media/nxp,imx8q-vpu.yaml | 178 ++++++++++++++++++ 1 file changed, 178 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml
Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml new file +178 -0
@@ -0,0 +1,178 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/nxp,imx8q-vpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8Q video encode and decode accelerators + +maintainers: + - Ming Qian <[email protected]> + - Shijie Qin <[email protected]> + +description: |- + The Amphion MXC video encoder(Windsor) and decoder(Malone) accelerators present + on NXP i.MX8Q SoCs. + +properties: + $nodename: + pattern: "^vpu@[0-9a-f]+$" + + compatible: + oneOf: + - const: nxp,imx8qm-vpu + - const: nxp,imx8qxp-vpu + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + +patternProperties: + "^mailbox@[0-9a-f]+$": + description: + Each vpu encoder or decoder correspond a MU, which used for communication + between driver and firmware. Implement via mailbox on driver. + $ref: ../mailbox/fsl,mu.yaml# + + + "^vpu_core@[0-9a-f]+$": + description: + Each core correspond a decoder or encoder, need to configure them + separately. NXP i.MX8QM SoC has one decoder and two encoder, i.MX8QXP SoC + has one decoder and one encoder. + type: object + + properties: + compatible: + oneOf: + - const: nxp,imx8q-vpu-decoder + - const: nxp,imx8q-vpu-encoder + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + mbox-names: + items: + - const: tx0 + - const: tx1 + - const: rx + + mboxes: + description: + List of phandle of 2 MU channels for tx, 1 MU channel for rx. + maxItems: 3 + + memory-region: + description: + Phandle to the reserved memory nodes to be associated with the + remoteproc device. The reserved memory nodes should be carveout nodes, + and should be defined as per the bindings in + Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt + items: + - description: region reserved for firmware image sections. + - description: region used for RPC shared memory between firmware and + driver. + + required: + - compatible + - reg + - power-domains + - mbox-names + - mboxes + - memory-region + + additionalProperties: false + +required: + - compatible + - reg + - power-domains + +additionalProperties: false + +examples: + # Device node example for i.MX8QM platform: + - | + #include <dt-bindings/firmware/imx/rsrc.h> + + vpu: vpu@2c000000 { + compatible = "nxp,imx8qm-vpu"; + ranges = <0x2c000000 0x2c000000 0x2000000>; + reg = <0x2c000000 0x1000000>; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&pd IMX_SC_R_VPU>; + + mu_m0: mailbox@2d000000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d000000 0x20000>; + interrupts = <0 472 4>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_0>; + }; + + mu1_m0: mailbox@2d020000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d020000 0x20000>; + interrupts = <0 473 4>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_1>; + }; + + mu2_m0: mailbox@2d040000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d040000 0x20000>; + interrupts = <0 474 4>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_2>; + }; + + vpu_core0: vpu_core@2d080000 { + compatible = "nxp,imx8q-vpu-decoder"; + reg = <0x2d080000 0x10000>; + power-domains = <&pd IMX_SC_R_VPU_DEC_0>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu_m0 0 0>, + <&mu_m0 0 1>, + <&mu_m0 1 0>; + memory-region = <&decoder_boot>, <&decoder_rpc>; + }; + + vpu_core1: vpu_core@2d090000 { + compatible = "nxp,imx8q-vpu-encoder"; + reg = <0x2d090000 0x10000>; + power-domains = <&pd IMX_SC_R_VPU_ENC_0>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu1_m0 0 0>, + <&mu1_m0 0 1>, + <&mu1_m0 1 0>; + memory-region = <&encoder1_boot>, <&encoder1_rpc>; + }; + + vpu_core2: vpu_core@2d0a0000 { + reg = <0x2d0a0000 0x10000>; + compatible = "nxp,imx8q-vpu-encoder"; + power-domains = <&pd IMX_SC_R_VPU_ENC_1>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu2_m0 0 0>, + <&mu2_m0 0 1>, + <&mu2_m0 1 0>; + memory-region = <&encoder2_boot>, <&encoder2_rpc>; + }; + }; + +...
Signature · 1 line
2.32.0
Re: [PATCH v5 01/14] dt-bindings: media: imx8q: add imx video codec bindings
Quoted 10 lines · Ming Qian
Add devicetree binding documentation for IMX8Q Video Processing Unit IP
Signed-off-by Ming Qian <[email protected]>Signed-off-by Shijie Qin <[email protected]>Signed-off-by Zhou Peng <[email protected]>--- .../bindings/media/nxp,imx8q-vpu.yaml | 178 ++++++++++++++++++ 1 file changed, 178 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml
PATCH v5 2/14 media:Add nt8 and nt10 video format.
In reply to Ming QianNT8 is 8-bit tiled nv12 format used by amphion decoder. NT10 is 10-bit tiled format used by amphion decoder. The tile size is 8x128
--- .../userspace-api/media/v4l/pixfmt-reserved.rst | 15 +++++++++++++++ drivers/media/v4l2-core/v4l2-ioctl.c | 2 ++ include/uapi/linux/videodev2.h | 2 ++ 3 files changed, 19 insertions(+)
Documentation/userspace-api/media/v4l/pixfmt-reserved.rst +15 -0
@@ -256,3 +256,18 @@ please make a proposal on the linux-media mailing list. of tiles, resulting in 32-aligned resolutions for the luminance plane and 16-aligned resolutions for the chrominance plane (with 2x2 subsampling). + * .. _V4L2-PIX-FMT-NT8: + + - ``V4L2_PIX_FMT_NT8`` + - 'NA12' + - Two-planar NV12-based format used by the video engine found on Amphion decoder, + with 8x128 tiles for the luminance plane and chrominance plane. + The number of bytes in one luminance or chrominance row must be divisible by 256. + * .. _V4L2-PIX-FMT-NT10: + + - ``V4L2_PIX_FMT_NT10`` + - 'NT12' + - NT10 is a tiled YUV format with 10-bits per pixel with interleaved UV. + It's used by the video engine found on Amphion decoder, + with 8x128 tiles for the luminance plane and chrominance plane. + The number of bytes in one luminance or chrominance row must be divisible by 256.
drivers/media/v4l2-core/v4l2-ioctl.c +2 -0
@@ -1402,6 +1402,8 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt)case V4L2_META_FMT_UVC : descr ="UVC Payload Header Metadata" ;break ;case V4L2_META_FMT_D4XX : descr ="Intel D4xx UVC Metadata" ;break ;case V4L2_META_FMT_VIVID : descr ="Vivid Metadata" ;break ; +case V4L2_PIX_FMT_NT8 : descr ="Amphion Tiled 8x128 NV12" ;break ; +case V4L2_PIX_FMT_NT10 : descr ="Amphion Tiled 8x128 10-bit" ;break ;default :/* Compressed formats */
include/uapi/linux/videodev2.h +2 -0
@@ -740,6 +740,8 @@ struct v4l2_pix_format {#define V4L2_PIX_FMT_INZI v4l2_fourcc('I', 'N', 'Z', 'I')/* Intel Planar Greyscale 10-bit and Depth 16-bit */ #define V4L2_PIX_FMT_SUNXI_TILED_NV12 v4l2_fourcc('S', 'T', '1', '2')/* Sunxi Tiled NV12 Format */ #define V4L2_PIX_FMT_CNF4 v4l2_fourcc('C', 'N', 'F', '4')/* Intel 4-bit packed depth confidence information */ +#define V4L2_PIX_FMT_NT8 v4l2_fourcc('N', 'A', '1', '2')/* Amphion Tiled 8x128 NV12 Format */ +#define V4L2_PIX_FMT_NT10 v4l2_fourcc('N', 'T', '1', '2')/* Amphion Tiled 8x128 10 bit Format */ /* 10bit raw bayer packed, 32 bytes for every 25 pixels, last LSB 6 bits unused */ #define V4L2_PIX_FMT_IPU3_SBGGR10 v4l2_fourcc('i', 'p', '3', 'b')/* IPU3 packed 10-bit BGGR bayer */
Signature · 1 line
2.32.0
Re: [PATCH v5 02/14] media:Add nt8 and nt10 video format.
Le mardi 27 juillet 2021 à 11:20 +0800, Ming Qian a écrit :
Quoted 19 lines
NT8 is 8-bit tiled nv12 format used by amphion decoder. NT10 is 10-bit tiled format used by amphion decoder. The tile size is 8x128
Signed-off-by Ming Qian <[email protected]>Signed-off-by Shijie Qin <[email protected]>Signed-off-by Zhou Peng <[email protected]>--- .../userspace-api/media/v4l/pixfmt-reserved.rst | 15 +++++++++++++++ drivers/media/v4l2-core/v4l2-ioctl.c | 2 ++ include/uapi/linux/videodev2.h | 2 ++ 3 files changed, 19 insertions(+)Documentation/userspace-api/media/v4l/pixfmt-reserved.rst +0
-0@@ -256,3 +256,18 @@ please make a proposal on the linux-media mailing list. of tiles, resulting in 32-aligned resolutions for the luminance plane
Documentation/userspace-api/media/v4l/pixfmt-reserved.rst please make a proposal on the linux-media mailing list. · line 266
Quoted 10 lines
Documentation/userspace-api/media/v4l/pixfmt-reserved.rst +8
-0and 16-aligned resolutions for the chrominance plane (with 2x2 subsampling). + * .. _V4L2-PIX-FMT-NT8: + + - ``V4L2_PIX_FMT_NT8`` + - 'NA12' + - Two-planar NV12-based format used by the video engine found on Amphion decoder, + with 8x128 tiles for the luminance plane and chrominance plane. + The number of bytes in one luminance or chrominance row must be divisible by 256. + * .. _V4L2-PIX-FMT-NT10:
There is a large spread of "vendor specific" format that aren't really specific, or complex enough to be worth being marked as vendor format. As per my reading of this description, this is linearly layout 8x128 tiled format, with no compression or anything (well unless you forgot to mention). As a side effect, we should give that format an explicit name (NT8 is cryptic). What about V4L2_PIX_FMT_NV12_8L128, my colleague is about to send a proposal in that direction. That would be NV12 with plane tiled 8x128 bytes and layout linearly, row by row, left to right. We already have cryptic formats like SUNXI, HM12 that are literally just that, simple tiling, and we endup having to use obscure vendor name whenever other HW uses the same.
(this comment extends to the other formats here)
Quoted 33 lines
Documentation/userspace-api/media/v4l/pixfmt-reserved.rst +7
-0+ + - ``V4L2_PIX_FMT_NT10`` + - 'NT12' + - NT10 is a tiled YUV format with 10-bits per pixel with interleaved UV. + It's used by the video engine found on Amphion decoder, + with 8x128 tiles for the luminance plane and chrominance plane. + The number of bytes in one luminance or chrominance row must be divisible by 256.drivers/media/v4l2-core/v4l2-ioctl.c +2
-0@@ -1402,6 +1402,8 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt)case V4L2_META_FMT_UVC : descr ="UVC Payload Header Metadata" ;break ;case V4L2_META_FMT_D4XX : descr ="Intel D4xx UVC Metadata" ;break ;case V4L2_META_FMT_VIVID : descr ="Vivid Metadata" ;break ; +case V4L2_PIX_FMT_NT8 : descr ="Amphion Tiled 8x128 NV12" ;break ; +case V4L2_PIX_FMT_NT10 : descr ="Amphion Tiled 8x128 10-bit" ;break ;default :/* Compressed formats */ include/uapi/linux/videodev2.h +2
-0@@ -740,6 +740,8 @@ struct v4l2_pix_format {#define V4L2_PIX_FMT_INZI v4l2_fourcc('I', 'N', 'Z', 'I')/* Intel Planar Greyscale 10-bit and Depth 16-bit */ #define V4L2_PIX_FMT_SUNXI_TILED_NV12 v4l2_fourcc('S', 'T', '1', '2')/* Sunxi Tiled NV12 Format */ #define V4L2_PIX_FMT_CNF4 v4l2_fourcc('C', 'N', 'F', '4')/* Intel 4-bit packed depth confidence information */ +#define V4L2_PIX_FMT_NT8 v4l2_fourcc('N', 'A', '1', '2')/* Amphion Tiled 8x128 NV12 Format */ +#define V4L2_PIX_FMT_NT10 v4l2_fourcc('N', 'T', '1', '2')/* Amphion Tiled 8x128 10 bit Format */ /* 10bit raw bayer packed, 32 bytes for every 25 pixels, last LSB 6 bits unused */ #define V4L2_PIX_FMT_IPU3_SBGGR10 v4l2_fourcc('i', 'p', '3', 'b')/* IPU3 packed 10-bit BGGR bayer */
Re: [PATCH v5 02/14] media:Add nt8 and nt10 video format.
Quoted 43 lines · Nicolas Dufresne
Quoted 19 lines · Ming Qian
NT8 is 8-bit tiled nv12 format used by amphion decoder. NT10 is 10-bit tiled format used by amphion decoder. The tile size is 8x128
Signed-off-by Ming Qian <[email protected]>Signed-off-by Shijie Qin <[email protected]>Signed-off-by Zhou Peng <[email protected]>--- .../userspace-api/media/v4l/pixfmt-reserved.rst | 15 +++++++++++++++ drivers/media/v4l2-core/v4l2-ioctl.c | 2 ++ include/uapi/linux/videodev2.h | 2 ++ 3 files changed, 19 insertions(+)Documentation/userspace-api/media/v4l/pixfmt-reserved.rst +0
-0@@ -256,3 +256,18 @@ please make a proposal on the linux-media mailing list. of tiles, resulting in 32-aligned resolutions for the luminance planeDocumentation/userspace-api/media/v4l/pixfmt-reserved.rst please make a proposal on the linux-media mailing list. · line 266
Quoted 10 lines
Documentation/userspace-api/media/v4l/pixfmt-reserved.rst +8
-0and 16-aligned resolutions for the chrominance plane (with 2x2 subsampling). + * .. _V4L2-PIX-FMT-NT8: + + - ``V4L2_PIX_FMT_NT8`` + - 'NA12' + - Two-planar NV12-based format used by the video engine found on Amphion decoder, + with 8x128 tiles for the luminance plane and chrominance plane. + The number of bytes in one luminance or chrominance row must be divisible by 256. + * .. _V4L2-PIX-FMT-NT10:There is a large spread of "vendor specific" format that aren't really specific, or complex enough to be worth being marked as vendor format. As per my reading of this description, this is linearly layout 8x128 tiled format, with no compression or anything (well unless you forgot to mention). As a side effect, we should give that format an explicit name (NT8 is cryptic). What about
V4L2_PIX_FMT_NV12_8L128, my colleague is about to send a proposal in that direction. That would be NV12 with plane tiled 8x128 bytes and layout linearly, row by row, left to right. We already have cryptic formats like SUNXI, HM12 that are literally just that, simple tiling, and we endup having to use obscure vendor name whenever other HW uses the same.
Quoted 2 lines
(this comment extends to the other formats here)
Here's the proposal Nicolas is talking about:
https://lore.kernel.org/linux-media/[email protected]/T/#t
V4L2_PIX_FMT_NV12_8L128 makes sense, please also add support for this format in GStreamer. I think that makes it easier to confirm the layout of the format.
Thanks!
Ezequiel
RE: [EXT] Re: [PATCH v5 02/14] media:Add nt8 and nt10 video format.
In reply to Nicolas DufresneQuoted 61 lines
-----Original Message-----
From: Nicolas Dufresne [mailto:[email protected]]
Sent: Wednesday, July 28, 2021 1:58 AM
To: Ming Qian <[email protected]>; [email protected]; [email protected]; [email protected]; [email protected]
Cc: [email protected]; [email protected]; [email protected]; dl-linux-imx <[email protected]>; Aisheng Dong <[email protected]>; [email protected]; [email protected]; [email protected]; [email protected]
Subject: [EXT] Re: [PATCH v5 02/14] media:Add nt8 and nt10 video format.Caution: EXT Email
Documentation/userspace-api/media/v4l/pixfmt-reserved.rst please make a proposal on the linux-media mailing
Quoted 19 lines · Ming Qian
NT8 is 8-bit tiled nv12 format used by amphion decoder. NT10 is 10-bit tiled format used by amphion decoder. The tile size is 8x128
Signed-off-by Ming Qian <[email protected]>Signed-off-by Shijie Qin <[email protected]>Signed-off-by Zhou Peng <[email protected]>--- .../userspace-api/media/v4l/pixfmt-reserved.rst | 15 +++++++++++++++ drivers/media/v4l2-core/v4l2-ioctl.c | 2 ++ include/uapi/linux/videodev2.h | 2 ++ 3 files changed, 19 insertions(+)Documentation/userspace-api/media/v4l/pixfmt-reserved.rst +0
-0@@ -256,3 +256,18 @@ please make a proposal on the linux-media mailinglist.
Documentation/userspace-api/media/v4l/pixfmt-reserved.rst please make a proposal on the linux-media mailing list.
Quoted 8 lines
Documentation/userspace-api/media/v4l/pixfmt-reserved.rst +5
-0of tiles, resulting in 32-aligned resolutions for the luminance plane and 16-aligned resolutions for the chrominance plane (with 2x2 subsampling). + * .. _V4L2-PIX-FMT-NT8: + + - ``V4L2_PIX_FMT_NT8`` + - 'NA12' + - Two-planar NV12-based format used by the video engine found onAmphion decoder,
Documentation/userspace-api/media/v4l/pixfmt-reserved.rst please make a proposal on the linux-media mailing · line 265
Quoted 2 lines
Documentation/userspace-api/media/v4l/pixfmt-reserved.rst +2
-0+ with 8x128 tiles for the luminance plane and chrominance plane. + The number of bytes in one luminance or chrominance row must bedivisible by 256.
Documentation/userspace-api/media/v4l/pixfmt-reserved.rst please make a proposal on the linux-media mailing list. · line 266
Quoted 1 line
Documentation/userspace-api/media/v4l/pixfmt-reserved.rst +1
-0+ * .. _V4L2-PIX-FMT-NT10:There is a large spread of "vendor specific" format that aren't really specific, or complex enough to be worth being marked as vendor format. As per my reading of this description, this is linearly layout 8x128 tiled format, with no compression or anything (well unless you forgot to mention). As a side effect, we should give that format an explicit name (NT8 is cryptic). What about
V4L2_PIX_FMT_NV12_8L128, my colleague is about to send a proposal in that direction. That would be NV12 with plane tiled 8x128 bytes and layout linearly, row by row, left to right. We already have cryptic formats like SUNXI, HM12 that are literally just that, simple tiling, and we endup having to use obscure vendor name whenever other HW uses the same.
Quoted 1 line
(this comment extends to the other formats here)
Hi Nicolas,
Thanks for your advice, I'll change the format name from NT8 to NV12_8L128
Quoted 51 lines
Documentation/userspace-api/media/v4l/pixfmt-reserved.rst please make a proposal on the linux-media mailing list.
Quoted 5 lines
Documentation/userspace-api/media/v4l/pixfmt-reserved.rst +4
-0+ + - ``V4L2_PIX_FMT_NT10`` + - 'NT12' + - NT10 is a tiled YUV format with 10-bits per pixel with interleavedUV.
Documentation/userspace-api/media/v4l/pixfmt-reserved.rst please make a proposal on the linux-media mailing list.
Quoted 3 lines
Documentation/userspace-api/media/v4l/pixfmt-reserved.rst +3
-0+ It's used by the video engine found on Amphion decoder, + with 8x128 tiles for the luminance plane and chrominance plane. + The number of bytes in one luminance or chrominance row must bedivisible by 256.
drivers/media/v4l2-core/v4l2-ioctl.c static void v4l_fill_fmtdesc(struct v4l2_fmtdesc
Quoted 6 lines
drivers/media/v4l2-core/v4l2-ioctl.c +0
-0@@ -1402,6 +1402,8 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc*fmt)
drivers/media/v4l2-core/v4l2-ioctl.c static void v4l_fill_fmtdesc(struct v4l2_fmtdesc · line 1402
Quoted 1 line
drivers/media/v4l2-core/v4l2-ioctl.c +0
-0case V4L2_META_FMT_UVC: descr = "UVC Payload HeaderMetadata"; break;
drivers/media/v4l2-core/v4l2-ioctl.c static void v4l_fill_fmtdesc(struct v4l2_fmtdesc · line 1403
Quoted 1 line
drivers/media/v4l2-core/v4l2-ioctl.c +0
-0case V4L2_META_FMT_D4XX: descr = "Intel D4xx UVCMetadata"; break;
drivers/media/v4l2-core/v4l2-ioctl.c static void v4l_fill_fmtdesc(struct v4l2_fmtdesc · line 1404
Quoted 1 line
drivers/media/v4l2-core/v4l2-ioctl.c +0
-0case V4L2_META_FMT_VIVID : descr ="Vivid Metadata" ;break;
drivers/media/v4l2-core/v4l2-ioctl.c static void v4l_fill_fmtdesc(struct v4l2_fmtdesc · line 1405
Quoted 1 line
drivers/media/v4l2-core/v4l2-ioctl.c +1
-0+ case V4L2_PIX_FMT_NT8: descr = "Amphion Tiled 8x128NV12"; break;
drivers/media/v4l2-core/v4l2-ioctl.c static void v4l_fill_fmtdesc(struct v4l2_fmtdesc · line 1406
Quoted 1 line
drivers/media/v4l2-core/v4l2-ioctl.c +1
-0+ case V4L2_PIX_FMT_NT10: descr = "Amphion Tiled 8x12810-bit"; break;
include/uapi/linux/videodev2.h struct v4l2_pix_format { · line 740
Quoted 9 lines
drivers/media/v4l2-core/v4l2-ioctl.c +0
-0default : /* Compressed formats */ diff --git
a/include/uapi/linux/videodev2.hb/include/uapi/linux/videodev2.hindex534eaa4d39bc..4836590a690c100644include/uapi/linux/videodev2.h +0
-0@@ -740,6 +740,8 @@ struct v4l2_pix_format {#define V4L2_PIX_FMT_INZI v4l2_fourcc('I', 'N', 'Z', 'I')/* Intel Planar Greyscale 10-bit and Depth 16-bit */
include/uapi/linux/videodev2.h struct v4l2_pix_format { · line 741
Quoted 1 line
include/uapi/linux/videodev2.h +0
-0#define V4L2_PIX_FMT_SUNXI_TILED_NV12 v4l2_fourcc('S', 'T', '1', '2')/* Sunxi Tiled NV12 Format */
include/uapi/linux/videodev2.h struct v4l2_pix_format { · line 742
Quoted 1 line
include/uapi/linux/videodev2.h +0
-0#define V4L2_PIX_FMT_CNF4 v4l2_fourcc('C', 'N', 'F', '4')/* Intel 4-bit packed depth confidence information */
include/uapi/linux/videodev2.h struct v4l2_pix_format { · line 743
Quoted 1 line
include/uapi/linux/videodev2.h +1
-0+#define V4L2_PIX_FMT_NT8 v4l2_fourcc('N', 'A', '1', '2')/* Amphion Tiled 8x128 NV12 Format */
include/uapi/linux/videodev2.h struct v4l2_pix_format { · line 744
Quoted 1 line
include/uapi/linux/videodev2.h +1
-0+#define V4L2_PIX_FMT_NT10 v4l2_fourcc('N', 'T', '1', '2')/* Amphion Tiled 8x128 10 bit Format */
include/uapi/linux/videodev2.h struct v4l2_pix_format { · line 745
Quoted 2 lines
include/uapi/linux/videodev2.h +0
-0/* 10bit raw bayer packed, 32 bytes for every 25 pixels, last LSB 6 bits unused */
include/uapi/linux/videodev2.h struct v4l2_pix_format { · line 746
Quoted 1 line
include/uapi/linux/videodev2.h +0
-0#define V4L2_PIX_FMT_IPU3_SBGGR10 v4l2_fourcc('i', 'p', '3', 'b')/* IPU3 packed 10-bit BGGR bayer */
PATCH v5 3/14 media:Add v4l2 buf flag codec data.
In reply to Ming QianIn some decoing scenarios, application may queue a buffer that only contains codec config data, and the driver needs to know whether is it a frame or not.
So we add a buf flag to tell this case.
--- Documentation/userspace-api/media/v4l/buffer.rst | 8 ++++++++ include/uapi/linux/videodev2.h | 1 + 2 files changed, 9 insertions(+)
Documentation/userspace-api/media/v4l/buffer.rst +8 -0
@@ -611,6 +611,14 @@ Buffer Flags the format. Any Any subsequent call to the :ref:`VIDIOC_DQBUF <VIDIOC_QBUF>` ioctl will not block anymore, but return an ``EPIPE`` error code. + * .. _`V4L2-BUF-FLAG-CODECCONFIG`: + + - ``V4L2_BUF_FLAG_CODECCONFIG`` + - 0x00200000 + - The buffer only contains codec config data, eg. sps and pps. + Applications can set this bit when ``type`` refers to an output + stream, this flag is usually used by v4l2 decoder. + * .. _`V4L2-BUF-FLAG-REQUEST-FD`: - ``V4L2_BUF_FLAG_REQUEST_FD``
include/uapi/linux/videodev2.h +1 -0
@@ -1110,6 +1110,7 @@ static inline __u64 v4l2_timeval_to_ns(const struct timeval *tv)#define V4L2_BUF_FLAG_TSTAMP_SRC_SOE 0x00010000/* mem2mem encoder/decoder */ #define V4L2_BUF_FLAG_LAST 0x00100000 +#define V4L2_BUF_FLAG_CODECCONFIG 0x00200000/* request_fd is valid */ #define V4L2_BUF_FLAG_REQUEST_FD 0x00800000
Signature · 1 line
2.32.0
PATCH v5 4/14 media: imx: imx8q: add imx8q vpu device driver
In reply to Ming QianIMX8Q SoCs feature a powerful video processing unit able to decode many foramts and encode H.264.
The vpu IP is amphion malone decoder and windsor encoder. This Driver is for this IP that is based on the v4l2 mem2mem framework.
Supported SoCs are: IMX8QXP, IMX8QM
--- .../media/v4l/vidioc-dqevent.rst | 12 + drivers/media/platform/Kconfig | 2 + drivers/media/platform/Makefile | 2 + drivers/media/platform/imx/Kconfig | 19 + drivers/media/platform/imx/Makefile | 1 + drivers/media/platform/imx/vpu-8q/Makefile | 23 ++ drivers/media/platform/imx/vpu-8q/vpu.h | 333 ++++++++++++++++++ drivers/media/platform/imx/vpu-8q/vpu_defs.h | 185 ++++++++++ .../media/platform/imx/vpu-8q/vpu_dev_imx8q.c | 73 ++++ drivers/media/platform/imx/vpu-8q/vpu_drv.c | 217 ++++++++++++ include/linux/imx_vpu.h | 11 + include/uapi/linux/imx_vpu.h | 17 + 12 files changed, 895 insertions(+) create mode 100644 drivers/media/platform/imx/Kconfig create mode 100644 drivers/media/platform/imx/Makefile create mode 100644 drivers/media/platform/imx/vpu-8q/Makefile create mode 100644 drivers/media/platform/imx/vpu-8q/vpu.h create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_defs.h create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_dev_imx8q.c create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_drv.c create mode 100644 include/linux/imx_vpu.h create mode 100644 include/uapi/linux/imx_vpu.h
Documentation/userspace-api/media/v4l/vidioc-dqevent.rst +12 -0
@@ -189,6 +189,18 @@ call. * - ``V4L2_EVENT_PRIVATE_START`` - 0x08000000 - Base event number for driver-private events. + * - ``V4L2_EVENT_CODEC_ERROR`` + - 0x08000001 + - This event is triggered when some error error occurs inside the codec engine, + usually it can be replaced by a POLLERR event, but in some cases, the POLLERR + may cause the application to exit, but this event can allow the application to + handle the codec error without exiting. + * - ``V4L2_EVENT_SKIP`` + - 0x08000002 + - This event is triggered when one frame is decoded, but it won't be outputed + to the display. So the application can't get this frame, and the input frame count + is dismatch with the output frame count. And this evevt is telling the client to + handle this case.
drivers/media/platform/Kconfig +2 -0
@@ -168,6 +168,8 @@ config VIDEO_TI_CAL In TI Technical Reference Manual this module is referred as Camera Interface Subsystem (CAMSS). +source "drivers/media/platform/imx/Kconfig" + endif # V4L_PLATFORM_DRIVERS menuconfig V4L_MEM2MEM_DRIVERS
drivers/media/platform/Makefile +2 -0
@@ -80,3 +80,5 @@ obj-$(CONFIG_VIDEO_QCOM_CAMSS) += qcom/camss/ obj-$(CONFIG_VIDEO_QCOM_VENUS) += qcom/venus/ obj-y += sunxi/ + +obj-y += imx/
drivers/media/platform/imx/Kconfig new file +19 -0
@@ -0,0 +1,19 @@ +# +# Codec configuration +# + +config MXC_VPU_8Q + tristate "Support for MXC 8Q VPU(Video Processing Unit) Codec" + depends on ARCH_MXC + depends on MEDIA_SUPPORT + depends on VIDEO_DEV + depends on VIDEO_V4L2 + select V4L2_MEM2MEM_DEV + select VIDEOBUF2_DMA_CONTIG + select VIDEOBUF2_VMALLOC + default y + help + This is a V4L2 driver for NXP MXC 8Q video accelerator hardware. + It accelerates encoding and decoding operations on + various NXP SoCs. + To compile this driver as a module choose m here.
drivers/media/platform/imx/Makefile new file +1 -0
@@ -0,0 +1 @@ +obj-$(CONFIG_MXC_VPU_8Q) += vpu-8q/
drivers/media/platform/imx/vpu-8q/Makefile new file +23 -0
@@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0 +# Makefile for NXP VPU driver + +vpu-8q-dev-objs += vpu_drv.o \ + vpu_dev_imx8q.o + +vpu-8q-core-objs += vpu_core.o \ + vpu_mbox.o \ + vpu_v4l2.o \ + vpu_helpers.o \ + vpu_cmds.o \ + vpu_msgs.o \ + vpu_rpc.o \ + vpu_imx8q.o \ + vpu_windsor.o \ + vpu_malone.o \ + vpu_color.o \ + vdec.o \ + venc.o \ + vpu_dbg.o + +obj-$(CONFIG_MXC_VPU_8Q) += vpu-8q-dev.o +obj-$(CONFIG_MXC_VPU_8Q) += vpu-8q-core.o
drivers/media/platform/imx/vpu-8q/vpu.h new file +333 -0
333 lines not on this page · raw message
drivers/media/platform/imx/vpu-8q/vpu_defs.h new file +185 -0
185 lines not on this page · raw message
drivers/media/platform/imx/vpu-8q/vpu_dev_imx8q.c new file +73 -0
73 lines not on this page · raw message
drivers/media/platform/imx/vpu-8q/vpu_drv.c new file +217 -0
217 lines not on this page · raw message
include/linux/imx_vpu.h new file +11 -0
@@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* +* Copyright 2020-2021 NXP +*/ + +#ifndef __LINUX_IMX_VPU_H +#define __LINUX_IMX_VPU_H + +#include <uapi/linux/imx_vpu.h> + +#endif
include/uapi/linux/imx_vpu.h new file +17 -0
@@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* +* Copyright 2020-2021 NXP +*/ + +#ifndef _UAPI__LINUX_IMX_VPU_H +#define _UAPI__LINUX_IMX_VPU_H + +#include <linux/videodev2.h> + +/*imx v4l2 event*/ +//error happened in dec/enc +#define V4L2_EVENT_CODEC_ERROR (V4L2_EVENT_PRIVATE_START + 1) +//frame loss in dec/enc +#define V4L2_EVENT_SKIP (V4L2_EVENT_PRIVATE_START + 2) + +#endif //#ifndef _UAPI__LINUX_IMX_VPU_H
Signature · 1 line
2.32.0
PATCH v5 5/14 media: imx: imx8q: add vpu core driver
In reply to Ming QianThe vpu support encoder and decoder.
And it need mu core to handle it.
Each core will run either encoder or decoder firmware.
This driver is for support the vpu core.
--- drivers/media/platform/imx/vpu-8q/vpu_codec.h | 68 ++ drivers/media/platform/imx/vpu-8q/vpu_core.c | 910 ++++++++++++++++++ drivers/media/platform/imx/vpu-8q/vpu_core.h | 16 + drivers/media/platform/imx/vpu-8q/vpu_dbg.c | 496 ++++++++++ drivers/media/platform/imx/vpu-8q/vpu_log.h | 44 + drivers/media/platform/imx/vpu-8q/vpu_rpc.c | 257 +++++ drivers/media/platform/imx/vpu-8q/vpu_rpc.h | 463 +++++++++ 7 files changed, 2254 insertions(+) create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_codec.h create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_core.c create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_core.h create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_dbg.c create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_log.h create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_rpc.c create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_rpc.h
drivers/media/platform/imx/vpu-8q/vpu_codec.h new file +68 -0
@@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* +* Copyright 2020-2021 NXP +*/ + +#ifndef _IMX_VPU_CODEC_H +#define _IMX_VPU_CODEC_H + +struct vpu_encode_params { +u32 input_format; +u32 codec_format; +u32 profile; +u32 tier; +u32 level; +u32 frame_rate_num; +u32 frame_rate_den; +u32 src_stride; +u32 src_width; +u32 src_height; +struct v4l2_rect crop; +u32 out_width; +u32 out_height; + +u32 gop_length; +u32 bframes; + +u32 rc_mode; +u32 bitrate; +u32 bitrate_min; +u32 bitrate_max; + +u32 i_frame_qp; +u32 p_frame_qp; +u32 b_frame_qp; +u32 qp_min; +u32 qp_max; +u32 qp_min_i; +u32 qp_max_i; + +struct { +u32 enable; +u32 idc; +u32 width; +u32 height; + } sar; + +struct { +u32 primaries; +u32 transfer; +u32 matrix; +u32 full_range; + } color; +}; + +struct vpu_decode_params { +u32 codec_format; +u32 output_format; +u32 b_dis_reorder; +u32 b_non_frame; +u32 frame_count; +u32 end_flag; +struct { +u32 base; +u32 size; + } udata; +}; + +#endif
drivers/media/platform/imx/vpu-8q/vpu_core.c new file +910 -0
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drivers/media/platform/imx/vpu-8q/vpu_core.h new file +16 -0
@@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* +* Copyright 2020-2021 NXP +*/ + +#ifndef _IMX_VPU_CORE_H +#define _IMX_VPU_CORE_H + +void csr_writel (struct vpu_core *core,u32 reg,u32 val); +u32 csr_readl (struct vpu_core *core,u32 reg); +int vpu_alloc_dma (struct vpu_core *core,struct vpu_buffer *buf); +void vpu_free_dma (struct vpu_buffer *buf); +struct vpu_inst *vpu_core_find_instance (struct vpu_core *core,u32 index); +int vpu_core_check_fmt (struct vpu_core *core,u32 pixelfmt); + +#endif
drivers/media/platform/imx/vpu-8q/vpu_dbg.c new file +496 -0
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drivers/media/platform/imx/vpu-8q/vpu_log.h new file +44 -0
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drivers/media/platform/imx/vpu-8q/vpu_rpc.c new file +257 -0
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drivers/media/platform/imx/vpu-8q/vpu_rpc.h new file +463 -0
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Signature · 1 line
2.32.0
PATCH v5 6/14 media: imx: imx8q: implement vpu core communication based on mailbox
In reply to Ming Qiandriver use mailbox to communicate with vpu core. and there are a command buffer and a message buffer. driver will write commands to the command buffer, then trigger a vpu core interrupt
vpu core will write messages to the message buffer, then trigger a cpu interrupt.
--- drivers/media/platform/imx/vpu-8q/vpu_cmds.c | 438 +++++++++++++++++++ drivers/media/platform/imx/vpu-8q/vpu_cmds.h | 25 ++ drivers/media/platform/imx/vpu-8q/vpu_mbox.c | 126 ++++++ drivers/media/platform/imx/vpu-8q/vpu_mbox.h | 16 + drivers/media/platform/imx/vpu-8q/vpu_msgs.c | 411 +++++++++++++++++ drivers/media/platform/imx/vpu-8q/vpu_msgs.h | 14 + 6 files changed, 1030 insertions(+) create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_cmds.c create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_cmds.h create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_mbox.c create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_mbox.h create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_msgs.c create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_msgs.h
drivers/media/platform/imx/vpu-8q/vpu_cmds.c new file +438 -0
@@ -0,0 +1,438 @@ +// SPDX-License-Identifier: GPL-2.0 +/* +* Copyright 2020-2021 NXP +*/ + +#define TAG "CMD" + +#include <linux/init.h> +#include <linux/interconnect.h> +#include <linux/ioctl.h> +#include <linux/list.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/types.h> +#include <linux/delay.h> +#include <linux/vmalloc.h> +#include "vpu.h" +#include "vpu_defs.h" +#include "vpu_cmds.h" +#include "vpu_rpc.h" +#include "vpu_mbox.h" +#include "vpu_log.h" + +struct vpu_cmd_request { +u32 request; +u32 response; +u32 handled; +}; + +struct vpu_cmd_t { +struct list_head list; +u32 id; +struct vpu_cmd_request *request; +struct vpu_rpc_event *pkt; +unsigned long key; +}; + +static struct vpu_cmd_request vpu_cmd_requests[] = { + { + .request =VPU_CMD_ID_CONFIGURE_CODEC , + .response =VPU_MSG_ID_MEM_REQUEST , + .handled =1 , + }, + { + .request =VPU_CMD_ID_START , + .response =VPU_MSG_ID_START_DONE , + .handled =0 , + }, + { + .request =VPU_CMD_ID_STOP , + .response =VPU_MSG_ID_STOP_DONE , + .handled =0 , + }, + { + .request =VPU_CMD_ID_ABORT , + .response =VPU_MSG_ID_ABORT_DONE , + .handled =0 , + }, + { + .request =VPU_CMD_ID_RST_BUF , + .response =VPU_MSG_ID_BUF_RST , + .handled =1 , + }, +}; + +int vpu_cmd_send (struct vpu_core *core,struct vpu_rpc_event *pkt) +{ +int ret =0 ; + +WARN_ON (!core || !pkt); + + ret =vpu_iface_send_cmd (core, pkt); +if (ret) +return ret; + +/*write cmd data to cmd buffer before trigger a cmd interrupt*/ +mb (); +vpu_mbox_send_type (core,COMMAND ); + +return ret; +} + +struct vpu_cmd_t *vpu_alloc_cmd (struct vpu_inst *inst,u32 id,void *data) +{ +struct vpu_cmd_t *cmd; +int i; +int ret; + + cmd =vzalloc (sizeof (*cmd)); +if (!cmd) +return NULL ; + + cmd->pkt =vzalloc (sizeof (*cmd->pkt)); +if (!cmd->pkt) { +vfree (cmd); +return NULL ; + } + + cmd->id = id; + ret =vpu_iface_pack_cmd (inst->core, cmd->pkt, inst->id, id, data); +if (ret) { +inst_err (inst,"iface pack cmd(%d) fail\n" , id); +vfree (cmd->pkt); +vfree (cmd); +return NULL ; + } +for (i =0 ; i <ARRAY_SIZE (vpu_cmd_requests); i++) { +if (vpu_cmd_requests[i].request == id) { + cmd->request = &vpu_cmd_requests[i]; +break ; + } + } + +return cmd; +} + +void vpu_free_cmd (struct vpu_cmd_t *cmd) +{ +if (!cmd) +return ; +if (cmd->pkt) +vfree (cmd->pkt); +vfree (cmd); +} + +int vpu_session_process_cmd (struct vpu_inst *inst,struct vpu_cmd_t *cmd) +{ +int ret; + +if (!inst || !cmd || !cmd->pkt) +return -EINVAL ; + +inst_dbg (inst,LVL_CMD ,"send cmd(%d)\n" , cmd->id); +vpu_iface_pre_send_cmd (inst); + ret =vpu_cmd_send (inst->core, cmd->pkt); +if (!ret) { +vpu_iface_post_send_cmd (inst); +vpu_inst_record_flow (inst, cmd->id); + }else { +inst_err (inst,"iface send cmd(%d) fail\n" , cmd->id); + } + +return ret; +} + +void vpu_process_cmd_request (struct vpu_inst *inst) +{ +struct vpu_cmd_t *cmd; +struct vpu_cmd_t *tmp; + +if (!inst || inst->pending) +return ; + +list_for_each_entry_safe (cmd, tmp, &inst->cmd_q, list) { +list_del_init (&cmd->list); +if (vpu_session_process_cmd (inst, cmd)) +inst_err (inst,"process cmd(%d) fail\n" , cmd->id); +if (cmd->request) { + inst->pending = (void *)cmd; +break ; + } +vpu_free_cmd (cmd); + } +} + +int vpu_request_cmd (struct vpu_inst *inst,u32 id,void *data, +unsigned long *key,int *sync) +{ +struct vpu_core *core; +struct vpu_cmd_t *cmd; + +if (!inst || !inst->core) +return -EINVAL ; + + core = inst->core; + cmd =vpu_alloc_cmd (inst, id, data); +if (!cmd) +return -ENOMEM ; + +mutex_lock (&core->cmd_lock); + cmd->key = core->cmd_seq++; +if (key) + *key = cmd->key; +if (sync) + *sync = cmd->request ? true : false; +list_add_tail (&cmd->list, &inst->cmd_q); +vpu_process_cmd_request (inst); +mutex_unlock (&core->cmd_lock); + +return 0 ; +} + +void vpu_clear_pending (struct vpu_inst *inst) +{ +if (!inst || !inst->pending) +return ; + +vpu_free_cmd (inst->pending); +wake_up_all (&inst->core->ack_wq); + inst->pending =NULL ; +} + +bool vpu_check_response (struct vpu_cmd_t *cmd,u32 response,u32 handled) +{ +struct vpu_cmd_request *request; + +if (!cmd || !cmd->request) +return false; + + request = cmd->request; +if (request->response != response) +return false; +if (request->handled != handled) +return false; + +return true; +} + +int vpu_response_cmd (struct vpu_inst *inst,u32 response,u32 handled) +{ +struct vpu_core *core; + +if (!inst || !inst->core) +return -EINVAL ; + + core = inst->core; +mutex_lock (&core->cmd_lock); +if (vpu_check_response (inst->pending, response, handled)) +vpu_clear_pending (inst); + +vpu_process_cmd_request (inst); +mutex_unlock (&core->cmd_lock); + +return 0 ; +} + +void vpu_clear_request (struct vpu_inst *inst) +{ +struct vpu_cmd_t *cmd; +struct vpu_cmd_t *tmp; + +mutex_lock (&inst->core->cmd_lock); +if (inst->pending) +vpu_clear_pending (inst); + +list_for_each_entry_safe (cmd, tmp, &inst->cmd_q, list) { +list_del_init (&cmd->list); +vpu_free_cmd (cmd); + } +mutex_unlock (&inst->core->cmd_lock); +} + +static bool check_is_responsed (struct vpu_inst *inst,unsigned long key) +{ +struct vpu_core *core = inst->core; +struct vpu_cmd_t *cmd; +bool flag = true; + +mutex_lock (&core->cmd_lock); + cmd = inst->pending; +if (cmd && key == cmd->key) { + flag = false; + goto exit; + } +list_for_each_entry (cmd, &inst->cmd_q, list) { +if (key == cmd->key) { + flag = false; +break ; + } + } +exit: +mutex_unlock (&core->cmd_lock); + +return flag; +} + +static int sync_session_response (struct vpu_inst *inst,unsigned long key) +{ +struct vpu_core *core; +long ret; + +if (!inst || !inst->core) +return -EINVAL ; + + core = inst->core; + +call_vop (inst, wait_prepare); + ret =wait_event_timeout (core->ack_wq, +check_is_responsed (inst, key), +VPU_TIMEOUT ); +call_vop (inst, wait_finish); + +if (!check_is_responsed (inst, key)) { +inst_err (inst,"sync session timeout\n" ); +set_bit (inst->id, &core->hang_mask); +mutex_lock (&inst->core->cmd_lock); +vpu_clear_pending (inst); +mutex_unlock (&inst->core->cmd_lock); +return -EINVAL ; + } + +return 0 ; +} + +int vpu_session_send_cmd (struct vpu_inst *inst,u32 id,void *data) +{ +struct vpu_core *core; +unsigned long key; +int sync = false; +int ret = -EINVAL ; + +WARN_ON (!inst || !inst->core || inst->id <0 ); + core = inst->core; + + ret =vpu_request_cmd (inst, id, data, &key, &sync); +if (!ret && sync) + ret =sync_session_response (inst, key); + +if (ret) +inst_err (inst,"send cmd(%d) fail\n" , id); + +return ret; +} + +int vpu_session_configure_codec (struct vpu_inst *inst) +{ +return vpu_session_send_cmd (inst,VPU_CMD_ID_CONFIGURE_CODEC ,NULL ); +} + +int vpu_session_start (struct vpu_inst *inst) +{ +inst_dbg (inst,LVL_FLOW ,"send start cmd\n" ); + +return vpu_session_send_cmd (inst,VPU_CMD_ID_START ,NULL ); +} + +int vpu_session_stop (struct vpu_inst *inst) +{ +inst_dbg (inst,LVL_FLOW ,"send stop cmd\n" ); + +return vpu_session_send_cmd (inst,VPU_CMD_ID_STOP ,NULL ); +} + +int vpu_session_encode_frame (struct vpu_inst *inst,s64 timestamp) +{ +return vpu_session_send_cmd (inst,VPU_CMD_ID_FRAME_ENCODE , ×tamp); +} + +int vpu_session_alloc_fs (struct vpu_inst *inst,struct vpu_fs_info *fs) +{ +return vpu_session_send_cmd (inst,VPU_CMD_ID_FS_ALLOC , fs); +} + +int vpu_session_release_fs (struct vpu_inst *inst,struct vpu_fs_info *fs) +{ +return vpu_session_send_cmd (inst,VPU_CMD_ID_FS_RELEASE , fs); +} + +int vpu_session_abort (struct vpu_inst *inst) +{ +return vpu_session_send_cmd (inst,VPU_CMD_ID_ABORT ,NULL ); +} + +int vpu_session_rst_buf (struct vpu_inst *inst) +{ +return vpu_session_send_cmd (inst,VPU_CMD_ID_RST_BUF ,NULL ); +} + +int vpu_session_fill_timestamp (struct vpu_inst *inst,struct vpu_ts_info *info) +{ +return vpu_session_send_cmd (inst,VPU_CMD_ID_TIMESTAMP , info); +} + +int vpu_session_update_parameters (struct vpu_inst *inst,void *arg) +{ +if (inst->type &VPU_CORE_TYPE_DEC ) +vpu_iface_set_decode_params (inst, arg,1 ); +else +vpu_iface_set_encode_params (inst, arg,1 ); + +return vpu_session_send_cmd (inst,VPU_CMD_ID_UPDATE_PARAMETER , arg); +} + +int vpu_session_debug (struct vpu_inst *inst) +{ +return vpu_session_send_cmd (inst,VPU_CMD_ID_DEBUG ,NULL ); +} + +int vpu_core_snapshot (struct vpu_core *core) +{ +struct vpu_inst *inst; +int ret; + +WARN_ON (!core ||list_empty (&core->instances)); + + inst = list_first_entry(&core->instances, struct vpu_inst, list); + +reinit_completion (&core->cmp); + ret =vpu_session_send_cmd (inst,VPU_CMD_ID_SNAPSHOT ,NULL ); +if (ret) +return ret; + ret =wait_for_completion_timeout (&core->cmp,VPU_TIMEOUT ); +if (!ret) { +vpu_err ("core[%d] snapshot timeout\n" , core->id); +return -EINVAL ; + } + +return 0 ; +} + +int vpu_core_sw_reset (struct vpu_core *core) +{ +struct vpu_rpc_event pkt; +int ret; + +WARN_ON (!core); + +memset (&pkt,0 ,sizeof (pkt)); +vpu_iface_pack_cmd (core, &pkt,0 ,VPU_CMD_ID_FIRM_RESET ,NULL ); + +reinit_completion (&core->cmp); +mutex_lock (&core->cmd_lock); + ret =vpu_cmd_send (core, &pkt); +mutex_unlock (&core->cmd_lock); +if (ret) +return ret; + ret =wait_for_completion_timeout (&core->cmp,VPU_TIMEOUT ); +if (!ret) { +vpu_err ("core[%d] sw reset timeout\n" , core->id); +return -EINVAL ; + } + +return 0 ; +}
drivers/media/platform/imx/vpu-8q/vpu_cmds.h new file +25 -0
@@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* +* Copyright 2020-2021 NXP +*/ + +#ifndef _IMX_VPU_CMDS_H +#define _IMX_VPU_CMDS_H + +int vpu_session_configure_codec (struct vpu_inst *inst); +int vpu_session_start (struct vpu_inst *inst); +int vpu_session_stop (struct vpu_inst *inst); +int vpu_session_abort (struct vpu_inst *inst); +int vpu_session_rst_buf (struct vpu_inst *inst); +int vpu_session_encode_frame (struct vpu_inst *inst,s64 timestamp); +int vpu_session_alloc_fs (struct vpu_inst *inst,struct vpu_fs_info *fs); +int vpu_session_release_fs (struct vpu_inst *inst,struct vpu_fs_info *fs); +int vpu_session_fill_timestamp (struct vpu_inst *inst,struct vpu_ts_info *info); +int vpu_session_update_parameters (struct vpu_inst *inst,void *arg); +int vpu_core_snapshot (struct vpu_core *core); +int vpu_core_sw_reset (struct vpu_core *core); +int vpu_response_cmd (struct vpu_inst *inst,u32 response,u32 handled); +void vpu_clear_request (struct vpu_inst *inst); +int vpu_session_debug (struct vpu_inst *inst); + +#endif
drivers/media/platform/imx/vpu-8q/vpu_mbox.c new file +126 -0
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drivers/media/platform/imx/vpu-8q/vpu_mbox.h new file +16 -0
@@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* +* Copyright 2020-2021 NXP +*/ + +#ifndef _IMX_VPU_MBOX_H +#define _IMX_VPU_MBOX_H + +int vpu_mbox_init (struct vpu_core *core); +int vpu_mbox_request (struct vpu_core *core); +void vpu_mbox_free (struct vpu_core *core); +void vpu_mbox_send_msg (struct vpu_core *core,u32 type,u32 data); +void vpu_mbox_send_type (struct vpu_core *core,u32 type); +void vpu_mbox_enable_rx (struct vpu_dev *dev); + +#endif
drivers/media/platform/imx/vpu-8q/vpu_msgs.c new file +411 -0
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drivers/media/platform/imx/vpu-8q/vpu_msgs.h new file +14 -0
@@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* +* Copyright 2020-2021 NXP +*/ + +#ifndef _IMX_VPU_MSGS_H +#define _IMX_VPU_MSGS_H + +int vpu_isr (struct vpu_core *core,u32 irq); +void vpu_inst_run_work (struct work_struct *work); +void vpu_msg_run_work (struct work_struct *work); +void vpu_msg_delayed_work (struct work_struct *work); + +#endif
Signature · 1 line
2.32.0
PATCH v5 7/14 media: imx: imx8q: add vpu v4l2 m2m support
In reply to Ming Qianvpu_v4l2.c implements the v4l2 m2m driver methods. vpu_helpers.c implements the common helper functions vpu_color.c converts the v4l2 colorspace with iso
--- drivers/media/platform/imx/vpu-8q/vpu_color.c | 192 +++++ .../media/platform/imx/vpu-8q/vpu_helpers.c | 396 +++++++++++ .../media/platform/imx/vpu-8q/vpu_helpers.h | 71 ++ drivers/media/platform/imx/vpu-8q/vpu_v4l2.c | 653 ++++++++++++++++++ drivers/media/platform/imx/vpu-8q/vpu_v4l2.h | 44 ++ 5 files changed, 1356 insertions(+) create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_color.c create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_helpers.c create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_helpers.h create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_v4l2.c create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_v4l2.h
drivers/media/platform/imx/vpu-8q/vpu_color.c new file +192 -0
@@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0 +/* +* Copyright 2020-2021 NXP +*/ + +#define TAG "COLOR" + +#include <linux/init.h> +#include <linux/device.h> +#include <linux/ioctl.h> +#include <linux/list.h> +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/slab.h> +#include <linux/delay.h> +#include <linux/types.h> +#include <media/v4l2-device.h> +#include "vpu.h" +#include "vpu_helpers.h" + +static const u8 colorprimaries[] = { +0 , +V4L2_COLORSPACE_REC709 ,/*Rec. ITU-R BT.709-6*/ +0 , +0 , +V4L2_COLORSPACE_470_SYSTEM_M ,/*Rec. ITU-R BT.470-6 System M*/ +V4L2_COLORSPACE_470_SYSTEM_BG ,/*Rec. ITU-R BT.470-6 System B, G*/ +V4L2_COLORSPACE_SMPTE170M ,/*SMPTE170M*/ +V4L2_COLORSPACE_SMPTE240M ,/*SMPTE240M*/ +0 ,/*Generic film*/ +V4L2_COLORSPACE_BT2020 ,/*Rec. ITU-R BT.2020-2*/ +0 ,/*SMPTE ST 428-1*/ +}; + +static const u8 colortransfers[] = { +0 , +V4L2_XFER_FUNC_709 ,/*Rec. ITU-R BT.709-6*/ +0 , +0 , +0 ,/*Rec. ITU-R BT.470-6 System M*/ +0 ,/*Rec. ITU-R BT.470-6 System B, G*/ +V4L2_XFER_FUNC_709 ,/*SMPTE170M*/ +V4L2_XFER_FUNC_SMPTE240M ,/*SMPTE240M*/ +V4L2_XFER_FUNC_NONE ,/*Linear transfer characteristics*/ +0 , +0 , +0 ,/*IEC 61966-2-4*/ +0 ,/*Rec. ITU-R BT.1361-0 extended colour gamut*/ +V4L2_XFER_FUNC_SRGB ,/*IEC 61966-2-1 sRGB or sYCC*/ +V4L2_XFER_FUNC_709 ,/*Rec. ITU-R BT.2020-2 (10 bit system)*/ +V4L2_XFER_FUNC_709 ,/*Rec. ITU-R BT.2020-2 (12 bit system)*/ +V4L2_XFER_FUNC_SMPTE2084 ,/*SMPTE ST 2084*/ +0 ,/*SMPTE ST 428-1*/ +0 /*Rec. ITU-R BT.2100-0 hybrid log-gamma (HLG)*/ +}; + +static const u8 colormatrixcoefs[] = { +0 , +V4L2_YCBCR_ENC_709 ,/*Rec. ITU-R BT.709-6*/ +0 , +0 , +0 ,/*Title 47 Code of Federal Regulations*/ +V4L2_YCBCR_ENC_601 ,/*Rec. ITU-R BT.601-7 625*/ +V4L2_YCBCR_ENC_601 ,/*Rec. ITU-R BT.601-7 525*/ +V4L2_YCBCR_ENC_SMPTE240M ,/*SMPTE240M*/ +0 , +V4L2_YCBCR_ENC_BT2020 ,/*Rec. ITU-R BT.2020-2*/ +V4L2_YCBCR_ENC_BT2020_CONST_LUM /*Rec. ITU-R BT.2020-2 constant*/ +}; + +u32 vpu_color_cvrt_primaries_v2i (u32 primaries) +{ +return VPU_ARRAY_FIND (colorprimaries, primaries); +} + +u32 vpu_color_cvrt_primaries_i2v (u32 primaries) +{ +return VPU_ARRAY_AT (colorprimaries, primaries); +} + +u32 vpu_color_cvrt_transfers_v2i (u32 transfers) +{ +return VPU_ARRAY_FIND (colortransfers, transfers); +} + +u32 vpu_color_cvrt_transfers_i2v (u32 transfers) +{ +return VPU_ARRAY_AT (colortransfers, transfers); +} + +u32 vpu_color_cvrt_matrix_v2i (u32 matrix) +{ +return VPU_ARRAY_FIND (colormatrixcoefs, matrix); +} + +u32 vpu_color_cvrt_matrix_i2v (u32 matrix) +{ +return VPU_ARRAY_AT (colormatrixcoefs, matrix); +} + +u32 vpu_color_cvrt_full_range_v2i (u32 full_range) +{ +return (full_range ==V4L2_QUANTIZATION_FULL_RANGE ); +} + +u32 vpu_color_cvrt_full_range_i2v (u32 full_range) +{ +if (full_range) +return V4L2_QUANTIZATION_FULL_RANGE ; + +return V4L2_QUANTIZATION_LIM_RANGE ; +} + +int vpu_color_check_primaries (u32 primaries) +{ +return vpu_color_cvrt_primaries_v2i (primaries) ?0 : -EINVAL ; +} + +int vpu_color_check_transfers (u32 transfers) +{ +return vpu_color_cvrt_transfers_v2i (transfers) ?0 : -EINVAL ; +} + +int vpu_color_check_matrix (u32 matrix) +{ +return vpu_color_cvrt_matrix_v2i (matrix) ?0 : -EINVAL ; +} + +int vpu_color_check_full_range (u32 full_range) +{ +int ret = -EINVAL ; + +switch (full_range) { +case V4L2_QUANTIZATION_FULL_RANGE : +case V4L2_QUANTIZATION_LIM_RANGE : + ret =0 ; +break ; +default : +break ; + + } + +return ret; +} + +int vpu_color_get_default (u32 primaries, +u32 *ptransfers,u32 *pmatrix,u32 *pfull_range) +{ +u32 transfers; +u32 matrix; +u32 full_range; + +switch (primaries) { +case V4L2_COLORSPACE_REC709 : + transfers =V4L2_XFER_FUNC_709 ; + matrix =V4L2_YCBCR_ENC_709 ; + full_range =V4L2_QUANTIZATION_LIM_RANGE ; +break ; +case V4L2_COLORSPACE_470_SYSTEM_M : +case V4L2_COLORSPACE_470_SYSTEM_BG : +case V4L2_COLORSPACE_SMPTE170M : + transfers =V4L2_XFER_FUNC_709 ; + matrix =V4L2_YCBCR_ENC_601 ; + full_range =V4L2_QUANTIZATION_LIM_RANGE ; +break ; +case V4L2_COLORSPACE_SMPTE240M : + transfers =V4L2_XFER_FUNC_SMPTE240M ; + matrix =V4L2_YCBCR_ENC_SMPTE240M ; + full_range =V4L2_QUANTIZATION_LIM_RANGE ; +break ; +case V4L2_COLORSPACE_BT2020 : + transfers =V4L2_XFER_FUNC_709 ; + matrix =V4L2_YCBCR_ENC_BT2020 ; + full_range =V4L2_QUANTIZATION_LIM_RANGE ; +break ; +default : + transfers =V4L2_XFER_FUNC_709 ; + matrix =V4L2_YCBCR_ENC_709 ; + full_range =V4L2_QUANTIZATION_LIM_RANGE ; +break ; + } + +if (ptransfers) + *ptransfers = transfers; +if (pmatrix) + *pmatrix = matrix; +if (pfull_range) + *pfull_range = full_range; + + +return 0 ; +}
drivers/media/platform/imx/vpu-8q/vpu_helpers.c new file +396 -0
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drivers/media/platform/imx/vpu-8q/vpu_helpers.h new file +71 -0
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drivers/media/platform/imx/vpu-8q/vpu_v4l2.c new file +653 -0
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drivers/media/platform/imx/vpu-8q/vpu_v4l2.h new file +44 -0
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Signature · 1 line
2.32.0
PATCH v5 8/14 media: imx: imx8q: add v4l2 m2m vpu encoder stateful driver
In reply to Ming QianThis consists of video encoder implementation plus encoder controls.
--- drivers/media/platform/imx/vpu-8q/venc.c | 1383 ++++++++++++++++++++++ 1 file changed, 1383 insertions(+) create mode 100644 drivers/media/platform/imx/vpu-8q/venc.c
drivers/media/platform/imx/vpu-8q/venc.c new file +1383 -0
@@ -0,0 +1,1383 @@ +// SPDX-License-Identifier: GPL-2.0 +/* +* Copyright 2020-2021 NXP +*/ + +#define TAG "ENC" + +#include <linux/init.h> +#include <linux/interconnect.h> +#include <linux/ioctl.h> +#include <linux/list.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/delay.h> +#include <linux/videodev2.h> +#include <linux/ktime.h> +#include <media/v4l2-device.h> +#include <media/v4l2-event.h> +#include <media/v4l2-mem2mem.h> +#include <media/v4l2-ioctl.h> +#include <media/videobuf2-v4l2.h> +#include <media/videobuf2-dma-contig.h> +#include <media/videobuf2-vmalloc.h> +#include <linux/imx_vpu.h> +#include "vpu.h" +#include "vpu_defs.h" +#include "vpu_core.h" +#include "vpu_helpers.h" +#include "vpu_v4l2.h" +#include "vpu_cmds.h" +#include "vpu_rpc.h" +#include "vpu_log.h" + +#define VENC_OUTPUT_ENABLE (1 << 0) +#define VENC_CAPTURE_ENABLE (1 << 1) +#define VENC_ENABLE_MASK (VENC_OUTPUT_ENABLE | VENC_CAPTURE_ENABLE) +#define VENC_MAX_BUF_CNT 8 + +struct venc_t { +struct vpu_encode_params params; +u32 request_key_frame; +u32 input_ready; +u32 cpb_size; +bool bitrate_change; + +struct vpu_buffer enc[VENC_MAX_BUF_CNT ]; +struct vpu_buffer ref[VENC_MAX_BUF_CNT ]; +struct vpu_buffer act[VENC_MAX_BUF_CNT ]; +struct list_head frames; +u32 frame_count; +u32 encode_count; +u32 ready_count; +u32 enable; +u32 stopped; + +u32 skipped_count; +u32 skipped_bytes; + +wait_queue_head_t wq; +}; + +struct venc_frame_t { +struct list_head list; +struct vpu_enc_pic_info info; +u32 bytesused; +s64 timestamp; +}; + +static const struct vpu_format venc_formats[] = { + { + .pixfmt =V4L2_PIX_FMT_NV12 , + .num_planes =2 , + .type =V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE , + }, + { + .pixfmt =V4L2_PIX_FMT_H264 , + .num_planes =1 , + .type =V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE , + }, + {0 ,0 ,0 ,0 }, +}; + +static int venc_querycap (struct file *file,void *fh,struct v4l2_capability *cap) +{ +strscpy (cap->driver,"imx vpu encoder" ,sizeof (cap->driver)); +strscpy (cap->card,"imx vpu encoder" ,sizeof (cap->card)); +strscpy (cap->bus_info,"platform: imx8q-vpu" ,sizeof (cap->bus_info)); + +return 0 ; +} + +static int venc_enum_fmt (struct file *file,void *fh,struct v4l2_fmtdesc *f) +{ +struct vpu_inst *inst =to_inst (file); +const struct vpu_format *fmt; + +memset (f->reserved,0 ,sizeof (f->reserved)); + fmt =vpu_helper_enum_format (inst, f->type, f->index); +if (!fmt) +return -EINVAL ; + + f->pixelformat = fmt->pixfmt; + f->flags = fmt->flags; + +return 0 ; +} + +static int venc_enum_framesizes (struct file *file,void *fh,struct v4l2_frmsizeenum *fsize) +{ +struct vpu_inst *inst =to_inst (file); + +if (!fsize || fsize->index) +return -EINVAL ; + +if (!vpu_helper_find_format (inst,0 , fsize->pixel_format)) +return -EINVAL ; + + fsize->type =V4L2_FRMSIZE_TYPE_STEPWISE ; + fsize->stepwise.max_width = inst->core->res->max_width; + fsize->stepwise.max_height = inst->core->res->max_height; + fsize->stepwise.min_width = inst->core->res->min_width; + fsize->stepwise.min_height = inst->core->res->min_height; + fsize->stepwise.step_width = inst->core->res->step_width; + fsize->stepwise.step_height = inst->core->res->step_height; + +return 0 ; +} + +static int venc_enum_frameintervals (struct file *file,void *fh,struct v4l2_frmivalenum *fival) +{ +struct vpu_inst *inst =to_inst (file); + +if (!fival || fival->index) +return -EINVAL ; + +if (!vpu_helper_find_format (inst,0 , fival->pixel_format)) +return -EINVAL ; + +if (!fival->width || !fival->height) +return -EINVAL ; + +if (fival->width < inst->core->res->min_width || + fival->width > inst->core->res->max_width || + fival->height < inst->core->res->min_height || + fival->height > inst->core->res->max_height) +return -EINVAL ; + + fival->type =V4L2_FRMIVAL_TYPE_CONTINUOUS ; + fival->stepwise.min.numerator =1 ; + fival->stepwise.min.denominator =USHRT_MAX ; + fival->stepwise.max.numerator =USHRT_MAX ; + fival->stepwise.max.denominator =1 ; + fival->stepwise.step.numerator =1 ; + fival->stepwise.step.denominator =1 ; + +return 0 ; +} + +static int venc_g_fmt (struct file *file,void *fh,struct v4l2_format *f) +{ +struct vpu_inst *inst =to_inst (file); +struct venc_t *venc = inst->priv; +struct v4l2_pix_format_mplane *pixmp = &f->fmt.pix_mp; +struct vpu_format *cur_fmt; +int i; + + cur_fmt =vpu_get_format (inst, f->type); + + pixmp->pixelformat = cur_fmt->pixfmt; + pixmp->num_planes = cur_fmt->num_planes; + pixmp->width = cur_fmt->width; + pixmp->height = cur_fmt->height; + pixmp->field = cur_fmt->field; + pixmp->flags = cur_fmt->flags; +for (i =0 ; i < pixmp->num_planes; i++) { + pixmp->plane_fmt[i].bytesperline = cur_fmt->bytesperline[i]; + pixmp->plane_fmt[i].sizeimage = cur_fmt->sizeimage[i]; + } + + f->fmt.pix_mp.colorspace = venc->params.color.primaries; + f->fmt.pix_mp.xfer_func = venc->params.color.transfer; + f->fmt.pix_mp.ycbcr_enc = venc->params.color.matrix; + f->fmt.pix_mp.quantization = venc->params.color.full_range; + +return 0 ; +} + +static int venc_try_fmt (struct file *file,void *fh,struct v4l2_format *f) +{ +struct vpu_inst *inst =to_inst (file); + +vpu_try_fmt_common (inst, f); + +return 0 ; +} + +static int venc_s_fmt (struct file *file,void *fh,struct v4l2_format *f) +{ +struct vpu_inst *inst =to_inst (file); +const struct vpu_format *fmt; +struct vpu_format *cur_fmt; +struct vb2_queue *q; +struct venc_t *venc = inst->priv; +struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp; +int i; + + q =v4l2_m2m_get_vq (inst->m2m_ctx, f->type); +if (!q) +return -EINVAL ; +if (vb2_is_streaming (q)) +return -EBUSY ; + + fmt =vpu_try_fmt_common (inst, f); +if (!fmt) +return -EINVAL ; + + cur_fmt =vpu_get_format (inst, f->type); + + cur_fmt->pixfmt = fmt->pixfmt; + cur_fmt->num_planes = fmt->num_planes; + cur_fmt->type = fmt->type; + cur_fmt->flags = fmt->flags; + cur_fmt->width = pix_mp->width; + cur_fmt->height = pix_mp->height; +for (i =0 ; i < fmt->num_planes; i++) { + cur_fmt->sizeimage[i] = pix_mp->plane_fmt[i].sizeimage; + cur_fmt->bytesperline[i] = pix_mp->plane_fmt[i].bytesperline; + } + +if (pix_mp->field !=V4L2_FIELD_ANY ) + cur_fmt->field = pix_mp->field; + +if (V4L2_TYPE_IS_OUTPUT (f->type)) { + venc->params.input_format = cur_fmt->pixfmt; + venc->params.src_stride = cur_fmt->bytesperline[0 ]; + venc->params.src_width = cur_fmt->width; + venc->params.src_height = cur_fmt->height; + venc->params.crop.left =0 ; + venc->params.crop.top =0 ; + venc->params.crop.width = cur_fmt->width; + venc->params.crop.height = cur_fmt->height; + }else { + venc->params.codec_format = cur_fmt->pixfmt; + venc->params.out_width = cur_fmt->width; + venc->params.out_height = cur_fmt->height; + } + +if (V4L2_TYPE_IS_OUTPUT (f->type)) { +if (!vpu_color_check_primaries (pix_mp->colorspace)) { + venc->params.color.primaries = pix_mp->colorspace; +vpu_color_get_default (venc->params.color.primaries, + &venc->params.color.transfer, + &venc->params.color.matrix, + &venc->params.color.full_range); + } +if (!vpu_color_check_transfers (pix_mp->xfer_func)) + venc->params.color.transfer = pix_mp->xfer_func; +if (!vpu_color_check_matrix (pix_mp->ycbcr_enc)) + venc->params.color.matrix = pix_mp->ycbcr_enc; +if (!vpu_color_check_full_range (pix_mp->quantization)) + venc->params.color.full_range = pix_mp->quantization; + } + + pix_mp->colorspace = venc->params.color.primaries; + pix_mp->xfer_func = venc->params.color.transfer; + pix_mp->ycbcr_enc = venc->params.color.matrix; + pix_mp->quantization = venc->params.color.full_range; + +return 0 ; +} + +static int venc_g_parm (struct file *file,void *fh,struct v4l2_streamparm *parm) +{ +struct vpu_inst *inst =to_inst (file); +struct venc_t *venc = inst->priv; +struct v4l2_fract *timeperframe = &parm->parm.capture.timeperframe; + +if (!parm) +return -EINVAL ; + +if (!vpu_helper_check_type (inst, parm->type)) +return -EINVAL ; + + parm->parm.capture.capability =V4L2_CAP_TIMEPERFRAME ; + parm->parm.capture.readbuffers =0 ; + timeperframe->numerator = venc->params.frame_rate_num; + timeperframe->denominator = venc->params.frame_rate_den; + +return 0 ; +} + +static int venc_s_parm (struct file *file,void *fh,struct v4l2_streamparm *parm) +{ +struct vpu_inst *inst =to_inst (file); +struct venc_t *venc = inst->priv; +struct v4l2_fract *timeperframe = &parm->parm.capture.timeperframe; + +if (!parm) +return -EINVAL ; + +if (!vpu_helper_check_type (inst, parm->type)) +return -EINVAL ; + +if (!timeperframe->numerator) + timeperframe->numerator = venc->params.frame_rate_num; +if (!timeperframe->denominator) + timeperframe->denominator = venc->params.frame_rate_den; + + venc->params.frame_rate_num = timeperframe->numerator; + venc->params.frame_rate_den = timeperframe->denominator; + +vpu_helper_calc_coprime (&venc->params.frame_rate_num, + &venc->params.frame_rate_den); + + parm->parm.capture.capability =V4L2_CAP_TIMEPERFRAME ; +memset (parm->parm.capture.reserved, +0 ,sizeof (parm->parm.capture.reserved)); + +return 0 ; +} + +static int venc_g_selection (struct file *file,void *fh,struct v4l2_selection *s) +{ +struct vpu_inst *inst =to_inst (file); +struct venc_t *venc = inst->priv; + +if (s->type !=V4L2_BUF_TYPE_VIDEO_OUTPUT && s->type !=V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE ) +return -EINVAL ; + +switch (s->target) { +case V4L2_SEL_TGT_CROP_DEFAULT : +case V4L2_SEL_TGT_CROP_BOUNDS : + s->r.left =0 ; + s->r.top =0 ; + s->r.width = inst->out_format.width; + s->r.height = inst->out_format.height; +break ; +case V4L2_SEL_TGT_CROP : + s->r = venc->params.crop; +break ; +default : +return -EINVAL ; + } + +return 0 ; +} + +static int venc_valid_crop (struct venc_t *venc,struct vpu_core *core) +{ +struct v4l2_rect *rect =NULL ; +u32 min_width; +u32 min_height; +u32 src_width; +u32 src_height; + + rect = &venc->params.crop; + min_width = core->res->min_width; + min_height = core->res->min_height; + src_width = venc->params.src_width; + src_height = venc->params.src_height; + +if (rect->width ==0 || rect->height ==0 ) +return -EINVAL ; +if (rect->left > src_width - min_width || + rect->top > src_height - min_height) +return -EINVAL ; + + rect->width =min (rect->width, src_width - rect->left); + rect->width =max_t (u32, rect->width, min_width); + + rect->height =min (rect->height, src_height - rect->top); + rect->height =max_t (u32, rect->height, min_height); + +return 0 ; +} + +static int venc_s_selection (struct file *file,void *fh,struct v4l2_selection *s) +{ +struct vpu_inst *inst =to_inst (file); +const struct vpu_core_resources *res = inst->core->res; +struct venc_t *venc = inst->priv; + +if (s->type !=V4L2_BUF_TYPE_VIDEO_OUTPUT && s->type !=V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE ) +return -EINVAL ; +if (s->target !=V4L2_SEL_TGT_CROP ) +return -EINVAL ; + + venc->params.crop.left =ALIGN (s->r.left, res->step_width); + venc->params.crop.top =ALIGN (s->r.top, res->step_height); + venc->params.crop.width =ALIGN (s->r.width, res->step_width); + venc->params.crop.height =ALIGN (s->r.height, res->step_height); +if (venc_valid_crop (venc, inst->core)) { + venc->params.crop.left =0 ; + venc->params.crop.top =0 ; + venc->params.crop.width = venc->params.src_width; + venc->params.crop.height = venc->params.src_height; + } + + inst->crop = venc->params.crop; + +return 0 ; +} + +static int venc_response_eos (struct vpu_inst *inst) +{ +struct venc_t *venc = inst->priv; +int ret; + +if (inst->state !=VPU_CODEC_STATE_DRAIN ) +return 0 ; + +if (v4l2_m2m_num_src_bufs_ready (inst->m2m_ctx)) +return 0 ; + +if (!venc->input_ready) +return 0 ; + + venc->input_ready = false; +inst_dbg (inst,LVL_FLOW ,"stop\n" ); + ret =vpu_session_stop (inst); +if (ret) +return ret; + inst->state =VPU_CODEC_STATE_STOP ; +wake_up_all (&venc->wq); + +return 0 ; +} + +static int venc_request_eos (struct vpu_inst *inst) +{ + inst->state =VPU_CODEC_STATE_DRAIN ; +venc_response_eos (inst); + +return 0 ; +} + +static int venc_encoder_cmd (struct file *file,void *fh,struct v4l2_encoder_cmd *cmd) +{ +struct vpu_inst *inst =to_inst (file); +int ret; + + ret =v4l2_m2m_ioctl_try_encoder_cmd (file, fh, cmd); +if (ret) +return ret; + +vpu_inst_lock (inst); +if (cmd->cmd ==V4L2_ENC_CMD_STOP ) { +if (inst->state ==VPU_CODEC_STATE_DEINIT ) +vpu_notify_eos (inst); +else +venc_request_eos (inst); + } +vpu_inst_unlock (inst); + +return 0 ; +} + +static int venc_subscribe_event (struct v4l2_fh *fh,const struct v4l2_event_subscription *sub) +{ +switch (sub->type) { +case V4L2_EVENT_EOS : +return v4l2_event_subscribe (fh, sub,0 ,NULL ); +case V4L2_EVENT_CTRL : +return v4l2_ctrl_subscribe_event (fh, sub); +default : +return -EINVAL ; + } +} + +static const struct v4l2_ioctl_ops venc_ioctl_ops = { + .vidioc_querycap = venc_querycap, + .vidioc_enum_fmt_vid_cap = venc_enum_fmt, + .vidioc_enum_fmt_vid_out = venc_enum_fmt, + .vidioc_enum_framesizes = venc_enum_framesizes, + .vidioc_enum_frameintervals = venc_enum_frameintervals, + .vidioc_g_fmt_vid_cap_mplane = venc_g_fmt, + .vidioc_g_fmt_vid_out_mplane = venc_g_fmt, + .vidioc_try_fmt_vid_cap_mplane = venc_try_fmt, + .vidioc_try_fmt_vid_out_mplane = venc_try_fmt, + .vidioc_s_fmt_vid_cap_mplane = venc_s_fmt, + .vidioc_s_fmt_vid_out_mplane = venc_s_fmt, + .vidioc_g_parm = venc_g_parm, + .vidioc_s_parm = venc_s_parm, + .vidioc_g_selection = venc_g_selection, + .vidioc_s_selection = venc_s_selection, + .vidioc_try_encoder_cmd = v4l2_m2m_ioctl_try_encoder_cmd, + .vidioc_encoder_cmd = venc_encoder_cmd, + .vidioc_subscribe_event = venc_subscribe_event, + .vidioc_unsubscribe_event = v4l2_event_unsubscribe, + .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs, + .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, + .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs, + .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf, + .vidioc_qbuf = v4l2_m2m_ioctl_qbuf, + .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, + .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf, + .vidioc_streamon = v4l2_m2m_ioctl_streamon, + .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, +}; + +static int venc_op_s_ctrl (struct v4l2_ctrl *ctrl) +{ +struct vpu_inst *inst =ctrl_to_inst (ctrl); +struct venc_t *venc = inst->priv; +int ret =0 ; + +vpu_inst_lock (inst); +switch (ctrl->id) { +case V4L2_CID_MPEG_VIDEO_H264_PROFILE : + venc->params.profile = ctrl->val; +break ; +case V4L2_CID_MPEG_VIDEO_H264_LEVEL : + venc->params.level = ctrl->val; +break ; +case V4L2_CID_MPEG_VIDEO_BITRATE_MODE : + venc->params.rc_mode = ctrl->val; +break ; +case V4L2_CID_MPEG_VIDEO_BITRATE : +if (ctrl->val != venc->params.bitrate) + venc->bitrate_change = true; + venc->params.bitrate = ctrl->val; +break ; +case V4L2_CID_MPEG_VIDEO_GOP_SIZE : + venc->params.gop_length = ctrl->val; +break ; +case V4L2_CID_MPEG_VIDEO_B_FRAMES : + venc->params.bframes = ctrl->val; +break ; +case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP : + venc->params.i_frame_qp = ctrl->val; +break ; +case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP : + venc->params.p_frame_qp = ctrl->val; +break ; +case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP : + venc->params.b_frame_qp = ctrl->val; +break ; +case V4L2_CID_MPEG_VIDEO_FORCE_KEY_FRAME : + venc->request_key_frame =1 ; +break ; +case V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE : + venc->cpb_size = ctrl->val *1024 ; +break ; +case V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_ENABLE : + venc->params.sar.enable = ctrl->val; +break ; +case V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_IDC : + venc->params.sar.idc = ctrl->val; +break ; +case V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_WIDTH : + venc->params.sar.width = ctrl->val; +break ; +case V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_HEIGHT : + venc->params.sar.height = ctrl->val; +break ; +case V4L2_CID_MPEG_VIDEO_HEADER_MODE : +break ; +default : + ret = -EINVAL ; +break ; + } +vpu_inst_unlock (inst); + +return ret; +} + +static const struct v4l2_ctrl_ops venc_ctrl_ops = { + .s_ctrl = venc_op_s_ctrl, + .g_volatile_ctrl = vpu_helper_g_volatile_ctrl, +}; + +static int venc_ctrl_init (struct vpu_inst *inst) +{ +struct v4l2_ctrl *ctrl; +int ret; + + ret =v4l2_ctrl_handler_init (&inst->ctrl_handler,20 ); +if (ret) +return ret; + +v4l2_ctrl_new_std_menu (&inst->ctrl_handler, &venc_ctrl_ops, +V4L2_CID_MPEG_VIDEO_H264_PROFILE , +V4L2_MPEG_VIDEO_H264_PROFILE_HIGH , + ~((1 <<V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE ) | + (1 <<V4L2_MPEG_VIDEO_H264_PROFILE_MAIN ) | + (1 <<V4L2_MPEG_VIDEO_H264_PROFILE_HIGH )), +V4L2_MPEG_VIDEO_H264_PROFILE_HIGH ); + +v4l2_ctrl_new_std_menu (&inst->ctrl_handler, &venc_ctrl_ops, +V4L2_CID_MPEG_VIDEO_H264_LEVEL , +V4L2_MPEG_VIDEO_H264_LEVEL_5_1 , +0x0 , +V4L2_MPEG_VIDEO_H264_LEVEL_4_0 ); + +v4l2_ctrl_new_std_menu (&inst->ctrl_handler, &venc_ctrl_ops, +V4L2_CID_MPEG_VIDEO_BITRATE_MODE , +V4L2_MPEG_VIDEO_BITRATE_MODE_CBR , +0x0 , +V4L2_MPEG_VIDEO_BITRATE_MODE_CBR ); + +v4l2_ctrl_new_std (&inst->ctrl_handler, &venc_ctrl_ops, +V4L2_CID_MPEG_VIDEO_BITRATE , +BITRATE_MIN , +BITRATE_MAX , +BITRATE_STEP , +BITRATE_DEFAULT ); + +v4l2_ctrl_new_std (&inst->ctrl_handler, &venc_ctrl_ops, +V4L2_CID_MPEG_VIDEO_GOP_SIZE ,0 , (1 <<16 ) -1 ,1 ,30 ); + +v4l2_ctrl_new_std (&inst->ctrl_handler, &venc_ctrl_ops, +V4L2_CID_MPEG_VIDEO_B_FRAMES ,0 ,4 ,1 ,0 ); + +v4l2_ctrl_new_std (&inst->ctrl_handler, &venc_ctrl_ops, +V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP ,1 ,51 ,1 ,26 ); +v4l2_ctrl_new_std (&inst->ctrl_handler, &venc_ctrl_ops, +V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP ,1 ,51 ,1 ,28 ); +v4l2_ctrl_new_std (&inst->ctrl_handler, &venc_ctrl_ops, +V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP ,1 ,51 ,1 ,30 ); +v4l2_ctrl_new_std (&inst->ctrl_handler, &venc_ctrl_ops, +V4L2_CID_MPEG_VIDEO_FORCE_KEY_FRAME ,0 ,0 ,0 ,0 ); + ctrl =v4l2_ctrl_new_std (&inst->ctrl_handler, &venc_ctrl_ops, +V4L2_CID_MIN_BUFFERS_FOR_CAPTURE ,1 ,32 ,1 ,2 ); +if (ctrl) + ctrl->flags |=V4L2_CTRL_FLAG_VOLATILE ; + ctrl =v4l2_ctrl_new_std (&inst->ctrl_handler, &venc_ctrl_ops, +V4L2_CID_MIN_BUFFERS_FOR_OUTPUT ,1 ,32 ,1 ,2 ); +if (ctrl) + ctrl->flags |=V4L2_CTRL_FLAG_VOLATILE ; + +v4l2_ctrl_new_std (&inst->ctrl_handler, &venc_ctrl_ops, +V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE ,64 ,10240 ,1 ,1024 ); + +v4l2_ctrl_new_std (&inst->ctrl_handler, &venc_ctrl_ops, +V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_ENABLE ,0 ,1 ,1 ,1 ); +v4l2_ctrl_new_std_menu (&inst->ctrl_handler, &venc_ctrl_ops, +V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_IDC , +V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_EXTENDED , +0x0 , + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_1x1); +v4l2_ctrl_new_std (&inst->ctrl_handler, &venc_ctrl_ops, +V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_WIDTH , +0 ,USHRT_MAX ,1 ,1 ); +v4l2_ctrl_new_std (&inst->ctrl_handler, &venc_ctrl_ops, +V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_HEIGHT , +0 ,USHRT_MAX ,1 ,1 ); +v4l2_ctrl_new_std_menu (&inst->ctrl_handler, &venc_ctrl_ops, +V4L2_CID_MPEG_VIDEO_HEADER_MODE , +V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME , + ~(1 <<V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME ), +V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME ); + + ret =v4l2_ctrl_handler_setup (&inst->ctrl_handler); +if (ret) { +inst_err (inst,"setup ctrls fail, ret = %d\n" , ret); +v4l2_ctrl_handler_free (&inst->ctrl_handler); +return ret; + } + +return 0 ; +} + +static bool venc_check_ready (struct vpu_inst *inst,unsigned int type) +{ +struct venc_t *venc = inst->priv; + +if (V4L2_TYPE_IS_OUTPUT (type)) { +if (vpu_helper_get_free_space (inst) < venc->cpb_size) +return false; +return venc->input_ready; + } + +return true; +} + +static u32 venc_get_enable_mask (u32 type) +{ +if (V4L2_TYPE_IS_OUTPUT (type)) +return VENC_OUTPUT_ENABLE ; +else +return VENC_CAPTURE_ENABLE ; +} + +static void venc_set_enable (struct venc_t *venc,u32 type,int enable) +{ +u32 mask =venc_get_enable_mask (type); + +if (enable) + venc->enable |= mask; +else + venc->enable &= ~mask; +} + +static u32 venc_get_enable (struct venc_t *venc,u32 type) +{ +return venc->enable &venc_get_enable_mask (type); +} + +static void venc_input_done (struct vpu_inst *inst) +{ +struct venc_t *venc = inst->priv; + +vpu_inst_lock (inst); + venc->input_ready = true; +vpu_process_output_buffer (inst); +venc_response_eos (inst); +vpu_inst_unlock (inst); +} + +/* +* It's hardware limitation, that there may be several bytes +* redundant data at the beginning of frame. +* For android platform, the redundant data may cause cts test fail +* So driver will strip them +*/ +static int venc_precheck_encoded_frame (struct vpu_inst *inst,struct venc_frame_t *frame) +{ +struct venc_t *venc; +int skipped; + +if (!inst || !frame || !frame->bytesused) +return -EINVAL ; + + venc = inst->priv; + skipped =vpu_helper_find_startcode (&inst->stream_buffer, + inst->cap_format.pixfmt, + frame->info.wptr - inst->stream_buffer.phys, + frame->bytesused); +if (skipped >0 ) { + frame->bytesused -= skipped; + frame->info.wptr =vpu_helper_step_walk (&inst->stream_buffer, + frame->info.wptr, skipped); + venc->skipped_bytes += skipped; + venc->skipped_count++; + } + +return 0 ; +} + +static int venc_get_one_encoded_frame (struct vpu_inst *inst, +struct venc_frame_t *frame, +struct vb2_v4l2_buffer *vbuf) +{ +struct venc_t *venc = inst->priv; +struct vpu_vb2_buffer *vpu_buf; + +if (!vbuf) +return -EAGAIN ; + +if (!venc_get_enable (inst->priv, vbuf->vb2_buf.type)) { +inst_dbg (inst,LVL_DEBUG , +"type %d is disabled, frame sequence %d\n" , + vbuf->vb2_buf.type, frame->info.frame_id); +v4l2_m2m_buf_done (vbuf,VB2_BUF_STATE_ERROR ); +return 0 ; + } + vpu_buf =to_vpu_vb2_buffer (vbuf); +if (frame->bytesused > vbuf->vb2_buf.planes[0 ].length) { +v4l2_m2m_buf_done (vbuf,VB2_BUF_STATE_ERROR ); +return -ENOMEM ; + } + +venc_precheck_encoded_frame (inst, frame); + +if (frame->bytesused) { +u32 rptr = frame->info.wptr; +void *dst =vb2_plane_vaddr (&vbuf->vb2_buf,0 ); + +vpu_helper_copy_from_stream_buffer (&inst->stream_buffer, + &rptr, frame->bytesused, dst); +vpu_iface_update_stream_buffer (inst, rptr,0 ); + } +vb2_set_plane_payload (&vbuf->vb2_buf,0 , frame->bytesused); + vbuf->sequence = frame->info.frame_id; + vbuf->vb2_buf.timestamp = frame->info.timestamp; + vbuf->flags |= frame->info.pic_type; + vpu_buf->state =VPU_BUF_STATE_IDLE ; +inst_dbg (inst,LVL_TS ,"[OUTPUT TS]%32lld\n" , frame->info.timestamp); +v4l2_m2m_buf_done (vbuf,VB2_BUF_STATE_DONE ); + venc->ready_count++; + +if (vbuf->flags &V4L2_BUF_FLAG_KEYFRAME ) +inst_dbg (inst,LVL_DEBUG ,"[%d]Iframe\n" , frame->info.frame_id); + +return 0 ; +} + +static int venc_get_encoded_frames (struct vpu_inst *inst) +{ +struct venc_t *venc; +struct venc_frame_t *frame; +struct venc_frame_t *tmp; + +if (!inst || !inst->priv) +return -EINVAL ; + + venc = inst->priv; +list_for_each_entry_safe (frame, tmp, &venc->frames, list) { +if (venc_get_one_encoded_frame (inst, frame, +v4l2_m2m_dst_buf_remove (inst->m2m_ctx))) +break ; +list_del_init (&frame->list); +vfree (frame); + } + +return 0 ; +} + +static int venc_frame_encoded (struct vpu_inst *inst,void *arg) +{ +struct vpu_enc_pic_info *info = arg; +struct venc_frame_t *frame; +struct venc_t *venc; +int ret =0 ; + +if (!inst || !info) +return -EINVAL ; + venc = inst->priv; + frame =vzalloc (sizeof (*frame)); +if (!frame) +return -ENOMEM ; + +memcpy (&frame->info, info,sizeof (frame->info)); + frame->bytesused = info->frame_size; + +vpu_inst_lock (inst); +list_add_tail (&frame->list, &venc->frames); + venc->encode_count++; +venc_get_encoded_frames (inst); +vpu_inst_unlock (inst); + +return ret; +} + +static void venc_buf_done (struct vpu_inst *inst,struct vpu_frame_info *frame) +{ +struct vb2_v4l2_buffer *vbuf; +struct vpu_vb2_buffer *vpu_buf; + +if (!inst || !frame) +return ; + +inst_dbg (inst,LVL_DEBUG ,"buf done : type = %d, sequence = %d\n" , + frame->type, frame->sequence); + +vpu_inst_lock (inst); +if (!venc_get_enable (inst->priv, frame->type)) { +inst_dbg (inst,LVL_DEBUG , +"type %d is disabled, frame sequence %d\n" , + frame->type, frame->sequence); + goto exit; + } + vbuf =vpu_find_buf_by_sequence (inst, frame->type, frame->sequence); +if (!vbuf) { +inst_err (inst,"can't find buf: type %d, sequence %d\n" , + frame->type, frame->sequence); + goto exit; + } + + vpu_buf =to_vpu_vb2_buffer (vbuf); + vpu_buf->state =VPU_BUF_STATE_IDLE ; +if (V4L2_TYPE_IS_OUTPUT (frame->type)) +v4l2_m2m_src_buf_remove_by_buf (inst->m2m_ctx, vbuf); +else +v4l2_m2m_dst_buf_remove_by_buf (inst->m2m_ctx, vbuf); +v4l2_m2m_buf_done (vbuf,VB2_BUF_STATE_DONE ); +exit: +vpu_inst_unlock (inst); +} + +static int venc_append_empty_frame (struct vpu_inst *inst) +{ +struct venc_frame_t *frame; +struct venc_t *venc; + +if (!inst || !inst->priv) +return -EINVAL ; + + venc = inst->priv; + frame =vzalloc (sizeof (*frame)); +if (!frame) +return -ENOMEM ; + + frame->bytesused =0 ; + frame->info.pic_type =V4L2_BUF_FLAG_LAST ; + frame->info.frame_id = inst->sequence; + +list_add_tail (&frame->list, &venc->frames); +venc_get_encoded_frames (inst); + +return 0 ; +} + +static void venc_stop_done (struct vpu_inst *inst) +{ +struct venc_t *venc = inst->priv; + +inst_dbg (inst,LVL_FLOW ,"append empty frame\n" ); + +vpu_inst_lock (inst); +venc_append_empty_frame (inst); + venc->stopped = true; +vpu_inst_unlock (inst); + +wake_up_all (&venc->wq); +} + +static void venc_event_notify (struct vpu_inst *inst,u32 event,void *data) +{ +} + +static void venc_release (struct vpu_inst *inst) +{ +} + +static void venc_cleanup (struct vpu_inst *inst) +{ +struct venc_t *venc; + +if (!inst) +return ; + + venc = inst->priv; +if (venc) +vfree (venc); + inst->priv =NULL ; +vfree (inst); +} + +static int venc_start_session (struct vpu_inst *inst,u32 type) +{ +struct venc_t *venc = inst->priv; +int stream_buffer_size; +int ret; + +venc_set_enable (venc, type,1 ); +if ((venc->enable &VENC_ENABLE_MASK ) !=VENC_ENABLE_MASK ) +return 0 ; + +vpu_iface_init_instance (inst); + stream_buffer_size =vpu_iface_get_stream_buffer_size (inst->core); +if (stream_buffer_size >0 ) { + inst->stream_buffer.length =max_t (u32, stream_buffer_size, venc->cpb_size *3 ); + ret =vpu_alloc_dma (inst->core, &inst->stream_buffer); +if (ret) + goto error; + + inst->use_stream_buffer = true; +vpu_iface_config_stream_buffer (inst, &inst->stream_buffer); + } + + ret =vpu_iface_set_encode_params (inst, &venc->params,0 ); +if (ret) + goto error; + ret =vpu_session_configure_codec (inst); +if (ret) + goto error; + + inst->state =VPU_CODEC_STATE_CONFIGURED ; +/*vpu_iface_config_memory_resource*/ + +/*config enc expert mode parameter*/ + ret =vpu_iface_set_encode_params (inst, &venc->params,1 ); +if (ret) + goto error; + + ret =vpu_session_start (inst); +if (ret) + goto error; + inst->state =VPU_CODEC_STATE_STARTED ; + + venc->bitrate_change = false; + venc->input_ready = true; + venc->frame_count =0 ; + venc->encode_count =0 ; + venc->ready_count =0 ; + venc->stopped = false; +vpu_process_output_buffer (inst); +if (venc->frame_count ==0 ) +inst_err (inst,"there is no input when starting\n" ); + +return 0 ; +error: +venc_set_enable (venc, type,0 ); + inst->state =VPU_CODEC_STATE_DEINIT ; + +vpu_free_dma (&inst->stream_buffer); +return ret; +} + +static void venc_cleanup_mem_resource (struct vpu_inst *inst) +{ +struct venc_t *venc; +u32 i; + +WARN_ON (!inst || !inst->priv || !inst->core); + + venc = inst->priv; + +for (i =0 ; i <ARRAY_SIZE (venc->enc); i++) +vpu_free_dma (&venc->enc[i]); +for (i =0 ; i <ARRAY_SIZE (venc->ref); i++) +vpu_free_dma (&venc->ref[i]); +for (i =0 ; i <ARRAY_SIZE (venc->act); i++) +vpu_free_dma (&venc->act[i]); +} + +static void venc_request_mem_resource (struct vpu_inst *inst, +u32 enc_frame_size, +u32 enc_frame_num, +u32 ref_frame_size, +u32 ref_frame_num, +u32 act_frame_size, +u32 act_frame_num) +{ +struct venc_t *venc; +u32 i; +int ret; + +WARN_ON (!inst || !inst->priv || !inst->core); + + venc = inst->priv; + +if (enc_frame_num >ARRAY_SIZE (venc->enc)) { +inst_err (inst,"enc num(%d) is out of range\n" , enc_frame_num); +return ; + } +if (ref_frame_num >ARRAY_SIZE (venc->ref)) { +inst_err (inst,"ref num(%d) is out of range\n" , ref_frame_num); +return ; + } +if (act_frame_num >ARRAY_SIZE (venc->act)) { +inst_err (inst,"act num(%d) is out of range\n" , act_frame_num); +return ; + } + +for (i =0 ; i < enc_frame_num; i++) { + venc->enc[i].length = enc_frame_size; + ret =vpu_alloc_dma (inst->core, &venc->enc[i]); +if (ret) { +venc_cleanup_mem_resource (inst); +return ; + } + } +for (i =0 ; i < ref_frame_num; i++) { + venc->ref[i].length = ref_frame_size; + ret =vpu_alloc_dma (inst->core, &venc->ref[i]); +if (ret) { +venc_cleanup_mem_resource (inst); +return ; + } + } +if (act_frame_num !=1 || act_frame_size > inst->act.length) { +venc_cleanup_mem_resource (inst); +return ; + } + venc->act[0 ].length = act_frame_size; + venc->act[0 ].phys = inst->act.phys; + venc->act[0 ].virt = inst->act.virt; + +for (i =0 ; i < enc_frame_num; i++) +vpu_iface_config_memory_resource (inst,MEM_RES_ENC , i, &venc->enc[i]); +for (i =0 ; i < ref_frame_num; i++) +vpu_iface_config_memory_resource (inst,MEM_RES_REF , i, &venc->ref[i]); +for (i =0 ; i < act_frame_num; i++) +vpu_iface_config_memory_resource (inst,MEM_RES_ACT , i, &venc->act[i]); +} + +static void venc_cleanup_frames (struct venc_t *venc) +{ +struct venc_frame_t *frame; +struct venc_frame_t *tmp; + +if (!list_empty (&venc->frames)) +vpu_dbg (LVL_DEBUG ,"Warning some encoded frames are dropped\n" ); + +list_for_each_entry_safe (frame, tmp, &venc->frames, list) { +list_del_init (&frame->list); +vfree (frame); + } +} + +static int venc_stop_session (struct vpu_inst *inst,u32 type) +{ +struct venc_t *venc = inst->priv; + +venc_set_enable (venc, type,0 ); +if (venc->enable &VENC_ENABLE_MASK ) +return 0 ; + +if (inst->state ==VPU_CODEC_STATE_DEINIT ) +return 0 ; + +if (inst->state !=VPU_CODEC_STATE_STOP ) +venc_request_eos (inst); + +call_vop (inst, wait_prepare); +if (!wait_event_timeout (venc->wq, venc->stopped,VPU_TIMEOUT )) { +set_bit (inst->id, &inst->core->hang_mask); +vpu_session_debug (inst); + } +call_vop (inst, wait_finish); + + inst->state =VPU_CODEC_STATE_DEINIT ; +venc_cleanup_frames (inst->priv); +vpu_free_dma (&inst->stream_buffer); +venc_cleanup_mem_resource (inst); + +return 0 ; +} + +static int venc_process_output (struct vpu_inst *inst,struct vb2_buffer *vb) +{ +struct venc_t *venc = inst->priv; +struct vb2_v4l2_buffer *vbuf; +struct vpu_vb2_buffer *vpu_buf =NULL ; +u32 flags; + +if (inst->state ==VPU_CODEC_STATE_DEINIT ) +return -EINVAL ; + + vbuf =to_vb2_v4l2_buffer (vb); + vpu_buf =to_vpu_vb2_buffer (vbuf); +if (inst->state ==VPU_CODEC_STATE_STARTED ) + inst->state =VPU_CODEC_STATE_ACTIVE ; + + flags = vbuf->flags; +if (venc->request_key_frame) { + vbuf->flags |=V4L2_BUF_FLAG_KEYFRAME ; + venc->request_key_frame =0 ; + } +if (venc->bitrate_change) { +vpu_session_update_parameters (inst, &venc->params); + venc->bitrate_change = false; + } +inst_dbg (inst,LVL_TS ,"[INPUT TS]%32lld\n" , vb->timestamp); +vpu_iface_input_frame (inst, vb); + vbuf->flags = flags; + venc->input_ready = false; + venc->frame_count++; + vpu_buf->state =VPU_BUF_STATE_INUSE ; + +return 0 ; +} + +static int venc_process_capture (struct vpu_inst *inst,struct vb2_buffer *vb) +{ +struct venc_t *venc; +struct venc_frame_t *frame =NULL ; +struct vb2_v4l2_buffer *vbuf; +int ret; + + venc = inst->priv; +if (list_empty (&venc->frames)) +return -EINVAL ; + + frame = list_first_entry(&venc->frames, struct venc_frame_t, list); + vbuf =to_vb2_v4l2_buffer (vb); +v4l2_m2m_dst_buf_remove_by_buf (inst->m2m_ctx, vbuf); + ret =venc_get_one_encoded_frame (inst, frame, vbuf); +if (ret) +return ret; + +list_del_init (&frame->list); +vfree (frame); +return 0 ; +} + +static int venc_get_debug_info (struct vpu_inst *inst,char *str,u32 size,u32 i) +{ +struct venc_t *venc = inst->priv; +int num =-1 ; + +switch (i) { +case 0 : + num =scnprintf (str, size,"profile = %d\n" , venc->params.profile); +break ; +case 1 : + num =scnprintf (str, size,"level = %d\n" , venc->params.level); +break ; +case 2 : + num =scnprintf (str, size,"fps = %d/%d\n" , + venc->params.frame_rate_num, + venc->params.frame_rate_den); +break ; +case 3 : + num =scnprintf (str, size,"%d x %d -> %d x %d\n" , + venc->params.src_width, + venc->params.src_height, + venc->params.out_width, + venc->params.out_height); +break ; +case 4 : + num =scnprintf (str, size,"(%d, %d) %d x %d\n" , + venc->params.crop.left, + venc->params.crop.top, + venc->params.crop.width, + venc->params.crop.height); +break ; +case 5 : + num =scnprintf (str, size, +"enable = 0x%x, input = %d, encode = %d, ready = %d, stopped = %d\n" , + venc->enable, + venc->frame_count, venc->encode_count, + venc->ready_count, + venc->stopped); +break ; +case 6 : + num =scnprintf (str, size,"gop = %d\n" , venc->params.gop_length); +break ; +case 7 : + num =scnprintf (str, size,"bframes = %d\n" , venc->params.bframes); +break ; +case 8 : + num =scnprintf (str, size,"rc: mode = %d, bitrate = %d, qp = %d\n" , + venc->params.rc_mode, + venc->params.bitrate, + venc->params.i_frame_qp); +break ; +case 9 : + num =scnprintf (str, size,"sar: enable = %d, idc = %d, %d x %d\n" , + venc->params.sar.enable, + venc->params.sar.idc, + venc->params.sar.width, + venc->params.sar.height); + +break ; +case 10 : + num =scnprintf (str, size, +"colorspace: primaries = %d, transfer = %d, matrix = %d, full_range = %d\n" , + venc->params.color.primaries, + venc->params.color.transfer, + venc->params.color.matrix, + venc->params.color.full_range); +break ; +case 11 : + num =scnprintf (str, size,"skipped: count = %d, bytes = %d\n" , + venc->skipped_count, venc->skipped_bytes); +break ; +default : +break ; + } + +return num; +} + +static struct vpu_inst_ops venc_inst_ops = { + .ctrl_init = venc_ctrl_init, + .check_ready = venc_check_ready, + .input_done = venc_input_done, + .get_one_frame = venc_frame_encoded, + .buf_done = venc_buf_done, + .stop_done = venc_stop_done, + .event_notify = venc_event_notify, + .release = venc_release, + .cleanup = venc_cleanup, + .start = venc_start_session, + .mem_request = venc_request_mem_resource, + .stop = venc_stop_session, + .process_output = venc_process_output, + .process_capture = venc_process_capture, + .get_debug_info = venc_get_debug_info, + .wait_prepare = vpu_inst_unlock, + .wait_finish = vpu_inst_lock, +}; + +static void venc_init (struct file *file) +{ +struct vpu_inst *inst =to_inst (file); +struct venc_t *venc; +struct v4l2_format f; +struct v4l2_streamparm parm; + + venc = inst->priv; + venc->params.qp_min =1 ; + venc->params.qp_max =51 ; + venc->params.qp_min_i =1 ; + venc->params.qp_max_i =51 ; + venc->params.bitrate_max =BITRATE_MAX ; + venc->params.bitrate_min =BITRATE_MIN ; + +memset (&f,0 ,sizeof (f)); + f.type =V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE ; + f.fmt.pix_mp.pixelformat =V4L2_PIX_FMT_NV12 ; + f.fmt.pix_mp.width =1280 ; + f.fmt.pix_mp.height =720 ; + f.fmt.pix_mp.field =V4L2_FIELD_NONE ; + f.fmt.pix_mp.colorspace =V4L2_COLORSPACE_REC709 ; +venc_s_fmt (file, &inst->fh, &f); + +memset (&f,0 ,sizeof (f)); + f.type =V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE ; + f.fmt.pix_mp.pixelformat =V4L2_PIX_FMT_H264 ; + f.fmt.pix_mp.width =1280 ; + f.fmt.pix_mp.height =720 ; + f.fmt.pix_mp.field =V4L2_FIELD_NONE ; +venc_s_fmt (file, &inst->fh, &f); + +memset (&parm,0 ,sizeof (parm)); + parm.type =V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE ; + parm.parm.capture.timeperframe.numerator =1 ; + parm.parm.capture.timeperframe.denominator =30 ; +venc_s_parm (file, &inst->fh, &parm); +} + +int venc_open (struct file *file) +{ +struct vpu_inst *inst; +struct venc_t *venc; +int ret; + + inst =vzalloc (sizeof (*inst)); +if (!inst) +return -ENOMEM ; + + venc =vzalloc (sizeof (*venc)); +if (!venc) { +vfree (inst); +return -ENOMEM ; + } + + inst->ops = &venc_inst_ops; + inst->formats = venc_formats; + inst->type =VPU_CORE_TYPE_ENC ; + inst->priv = venc; +INIT_LIST_HEAD (&venc->frames); +init_waitqueue_head (&venc->wq); + + ret =vpu_v4l2_open (file, inst); +if (ret) { +vfree (venc); +vfree (inst); +return ret; + } + +venc_init (file); + +return 0 ; +} + +static const struct v4l2_file_operations venc_fops = { + .owner =THIS_MODULE , + .open = venc_open, + .release = vpu_v4l2_close, + .unlocked_ioctl = video_ioctl2, + .poll = v4l2_m2m_fop_poll, + .mmap = v4l2_m2m_fop_mmap, +}; + +int venc_create_video_device (struct vpu_dev *vpu) +{ +struct video_device *venc; +int ret; + +if (!vpu) +return -EINVAL ; + +if (vpu->vdev_enc) +return 0 ; + + venc =video_device_alloc (); +if (!venc) { +vpu_err ("alloc vpu encoder video device fail\n" ); +return -ENOMEM ; + } +strscpy (venc->name,"imx-vpu-encoder" ,sizeof (venc->name)); + venc->release = video_device_release; + venc->fops = &venc_fops; + venc->ioctl_ops = &venc_ioctl_ops; + venc->vfl_dir =VFL_DIR_M2M ; + venc->v4l2_dev = &vpu->v4l2_dev; + venc->device_caps =V4L2_CAP_VIDEO_M2M_MPLANE |V4L2_CAP_STREAMING ; + + ret =video_register_device (venc,VFL_TYPE_VIDEO ,-1 ); +if (ret) { +video_device_release (venc); +return ret; + } +video_set_drvdata (venc, vpu); + vpu->vdev_enc = venc; + +return 0 ; +}
Signature · 1 line
2.32.0
PATCH v5 9/14 media: imx: imx8q: add v4l2 m2m vpu decoder stateful driver
In reply to Ming QianThis consists of video decoder implementation plus decoder controls.
--- drivers/media/platform/imx/vpu-8q/vdec.c | 1687 ++++++++++++++++++++++ 1 file changed, 1687 insertions(+) create mode 100644 drivers/media/platform/imx/vpu-8q/vdec.c
drivers/media/platform/imx/vpu-8q/vdec.c new file +1687 -0
@@ -0,0 +1,1687 @@ +// SPDX-License-Identifier: GPL-2.0 +/* +* Copyright 2020-2021 NXP +*/ + +#define TAG "DEC" +#include <linux/init.h> +#include <linux/interconnect.h> +#include <linux/ioctl.h> +#include <linux/list.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/videodev2.h> +#include <media/v4l2-device.h> +#include <media/v4l2-event.h> +#include <media/v4l2-mem2mem.h> +#include <media/v4l2-ioctl.h> +#include <media/videobuf2-v4l2.h> +#include <media/videobuf2-dma-contig.h> +#include <media/videobuf2-vmalloc.h> +#include <linux/imx_vpu.h> +#include "vpu.h" +#include "vpu_defs.h" +#include "vpu_core.h" +#include "vpu_helpers.h" +#include "vpu_v4l2.h" +#include "vpu_cmds.h" +#include "vpu_rpc.h" +#include "vpu_log.h" + +#define VDEC_FRAME_DEPTH 256 + +struct vdec_fs_info { +char name[8 ]; +u32 type; +u32 max_count; +u32 req_count; +u32 count; +u32 index; +u32 size; +struct vpu_buffer buffer[32 ]; +u32 tag; +}; + +struct vdec_t { +u32 seq_hdr_found; +struct vpu_buffer udata; +struct vpu_decode_params params; +struct vpu_dec_codec_info codec_info; +enum vpu_codec_state state; + +struct vpu_vb2_buffer *slots[VB2_MAX_FRAME ]; +u32 req_frame_count; +struct vdec_fs_info mbi; +struct vdec_fs_info dcp; +u32 seq_tag; + +u32 decoded_frame_count; +u32 display_frame_count; +u32 eos_received; +u32 eos_subscribed; +bool is_source_changed; +u32 source_change; +u32 drain; +u32 ts_pre_count; +u32 frame_depth; +s64 ts_start; +s64 ts_input; +s64 timestamp; +}; + +static const struct vpu_format vdec_formats[] = { + { + .pixfmt =V4L2_PIX_FMT_NV12 , + .num_planes =2 , + .type =V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE , + }, + { + .pixfmt =V4L2_PIX_FMT_NT8 , + .num_planes =2 , + .type =V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE , + }, + { + .pixfmt =V4L2_PIX_FMT_NT10 , + .num_planes =2 , + .type =V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE , + }, + { + .pixfmt =V4L2_PIX_FMT_H264 , + .num_planes =1 , + .type =V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE , + .flags =V4L2_FMT_FLAG_DYN_RESOLUTION + }, + { + .pixfmt =V4L2_PIX_FMT_H264_MVC , + .num_planes =1 , + .type =V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE , + .flags =V4L2_FMT_FLAG_DYN_RESOLUTION + }, + { + .pixfmt =V4L2_PIX_FMT_HEVC , + .num_planes =1 , + .type =V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE , + .flags =V4L2_FMT_FLAG_DYN_RESOLUTION + }, + { + .pixfmt =V4L2_PIX_FMT_VC1_ANNEX_G , + .num_planes =1 , + .type =V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE , + .flags =V4L2_FMT_FLAG_DYN_RESOLUTION + }, + { + .pixfmt =V4L2_PIX_FMT_VC1_ANNEX_L , + .num_planes =1 , + .type =V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE , + .flags =V4L2_FMT_FLAG_DYN_RESOLUTION + }, + { + .pixfmt =V4L2_PIX_FMT_MPEG2 , + .num_planes =1 , + .type =V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE , + .flags =V4L2_FMT_FLAG_DYN_RESOLUTION + }, + { + .pixfmt =V4L2_PIX_FMT_MPEG4 , + .num_planes =1 , + .type =V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE , + .flags =V4L2_FMT_FLAG_DYN_RESOLUTION + }, + { + .pixfmt =V4L2_PIX_FMT_XVID , + .num_planes =1 , + .type =V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE , + .flags =V4L2_FMT_FLAG_DYN_RESOLUTION + }, + { + .pixfmt =V4L2_PIX_FMT_VP8 , + .num_planes =1 , + .type =V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE , + .flags =V4L2_FMT_FLAG_DYN_RESOLUTION + }, + { + .pixfmt =V4L2_PIX_FMT_H263 , + .num_planes =1 , + .type =V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE , + .flags =V4L2_FMT_FLAG_DYN_RESOLUTION + }, + {0 ,0 ,0 ,0 }, +}; + +static const struct v4l2_ctrl_ops vdec_ctrl_ops = { + .g_volatile_ctrl = vpu_helper_g_volatile_ctrl, +}; + +static int vdec_ctrl_init (struct vpu_inst *inst) +{ +struct v4l2_ctrl *ctrl; +int ret; + + ret =v4l2_ctrl_handler_init (&inst->ctrl_handler,20 ); +if (ret) +return ret; + + ctrl =v4l2_ctrl_new_std (&inst->ctrl_handler, &vdec_ctrl_ops, +V4L2_CID_MIN_BUFFERS_FOR_CAPTURE ,1 ,32 ,1 ,2 ); +if (ctrl) + ctrl->flags |=V4L2_CTRL_FLAG_VOLATILE ; + + ctrl =v4l2_ctrl_new_std (&inst->ctrl_handler, &vdec_ctrl_ops, +V4L2_CID_MIN_BUFFERS_FOR_OUTPUT ,1 ,32 ,1 ,2 ); +if (ctrl) + ctrl->flags |=V4L2_CTRL_FLAG_VOLATILE ; + + ret =v4l2_ctrl_handler_setup (&inst->ctrl_handler); +if (ret) { +inst_err (inst,"setup ctrls fail, ret = %d\n" , ret); +v4l2_ctrl_handler_free (&inst->ctrl_handler); +return ret; + } + +return 0 ; +} + +static int vdec_handle_eos (struct vpu_inst *inst) +{ +struct vdec_t *vdec = inst->priv; +struct vb2_queue *dst_q =v4l2_m2m_get_dst_vq (inst->m2m_ctx); + +if (!vdec->eos_received) +return 0 ; + +if (!vdec->eos_subscribed) +return 0 ; + +if (!list_empty (&dst_q->done_list)) +return 0 ; + + dst_q->last_buffer_dequeued = true; +vpu_notify_eos (inst); + vdec->eos_received--; + +return 0 ; +} + +static void vdec_handle_resolution_change (struct vpu_inst *inst) +{ +struct vdec_t *vdec = inst->priv; +struct vb2_queue *q; + +if (inst->state !=VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE ) +return ; +if (!vdec->source_change) +return ; + + q =v4l2_m2m_get_dst_vq (inst->m2m_ctx); +if (!list_empty (&q->done_list)) +return ; + + vdec->source_change--; +vpu_notify_source_change (inst); +} + +static int vdec_update_state (struct vpu_inst *inst, +enum vpu_codec_state state,u32 force) +{ +struct vdec_t *vdec = inst->priv; +enum vpu_codec_state pre_state = inst->state; + +if (state ==VPU_CODEC_STATE_SEEK ) { +if (inst->state ==VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE ) + vdec->state = inst->state; +else + vdec->state =VPU_CODEC_STATE_ACTIVE ; + } +if (inst->state !=VPU_CODEC_STATE_SEEK || force) + inst->state = state; +else if (state ==VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE ) + vdec->state =VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE ; + +inst_dbg (inst,LVL_FLOW ,"state : %d -> %d\n" , pre_state, inst->state); + +if (inst->state ==VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE ) +vdec_handle_resolution_change (inst); + +return 0 ; +} + +static int vdec_querycap (struct file *file,void *fh,struct v4l2_capability *cap) +{ +strscpy (cap->driver,"vpu B0" ,sizeof (cap->driver)); +strscpy (cap->card,"imx vpu decoder" ,sizeof (cap->card)); +strscpy (cap->bus_info,"platform: imx8q-vpu" ,sizeof (cap->bus_info)); + +return 0 ; +} + +static int vdec_enum_fmt (struct file *file,void *fh,struct v4l2_fmtdesc *f) +{ +struct vpu_inst *inst =to_inst (file); +struct vdec_t *vdec = inst->priv; +const struct vpu_format *fmt; +int ret = -EINVAL ; + +vpu_inst_lock (inst); +if (!V4L2_TYPE_IS_OUTPUT (f->type) && vdec->seq_hdr_found) { +if (f->index ==0 ) { + f->pixelformat = inst->cap_format.pixfmt; + f->flags = inst->cap_format.flags; + ret =0 ; + } + }else { + fmt =vpu_helper_enum_format (inst, f->type, f->index); +memset (f->reserved,0 ,sizeof (f->reserved)); +if (!fmt) + goto exit; + + f->pixelformat = fmt->pixfmt; + f->flags = fmt->flags; + ret =0 ; + } + +exit: +vpu_inst_unlock (inst); +return ret; +} + +static int vdec_g_fmt (struct file *file,void *fh,struct v4l2_format *f) +{ +struct vpu_inst *inst =to_inst (file); +struct vdec_t *vdec = inst->priv; +struct v4l2_pix_format_mplane *pixmp = &f->fmt.pix_mp; +struct vpu_format *cur_fmt; +int i; + + cur_fmt =vpu_get_format (inst, f->type); + + pixmp->pixelformat = cur_fmt->pixfmt; + pixmp->num_planes = cur_fmt->num_planes; + pixmp->width = cur_fmt->width; + pixmp->height = cur_fmt->height; + pixmp->field = cur_fmt->field; + pixmp->flags = cur_fmt->flags; +for (i =0 ; i < pixmp->num_planes; i++) { + pixmp->plane_fmt[i].bytesperline = cur_fmt->bytesperline[i]; + pixmp->plane_fmt[i].sizeimage = cur_fmt->sizeimage[i]; + } + + f->fmt.pix_mp.colorspace = vdec->codec_info.color_primaries; + f->fmt.pix_mp.xfer_func = vdec->codec_info.transfer_chars; + f->fmt.pix_mp.ycbcr_enc = vdec->codec_info.matrix_coeffs; + f->fmt.pix_mp.quantization = vdec->codec_info.full_range; + +inst_dbg (inst,LVL_DEBUG ,"%s g_fmt: %c%c%c%c %dx%d %d,%d, %d,%d\n" , +vpu_type_name (f->type), + f->fmt.pix_mp.pixelformat, + f->fmt.pix_mp.pixelformat >>8 , + f->fmt.pix_mp.pixelformat >>16 , + f->fmt.pix_mp.pixelformat >>24 , + f->fmt.pix_mp.width, + f->fmt.pix_mp.height, + pixmp->plane_fmt[0 ].sizeimage, + pixmp->plane_fmt[1 ].sizeimage, + pixmp->plane_fmt[0 ].bytesperline, + pixmp->plane_fmt[1 ].bytesperline); + +return 0 ; +} + +static int vdec_try_fmt (struct file *file,void *fh,struct v4l2_format *f) +{ +struct vpu_inst *inst =to_inst (file); +struct vdec_t *vdec = inst->priv; + +vpu_try_fmt_common (inst, f); + +vpu_inst_lock (inst); +if (vdec->seq_hdr_found) { + f->fmt.pix_mp.colorspace = vdec->codec_info.color_primaries; + f->fmt.pix_mp.xfer_func = vdec->codec_info.transfer_chars; + f->fmt.pix_mp.ycbcr_enc = vdec->codec_info.matrix_coeffs; + f->fmt.pix_mp.quantization = vdec->codec_info.full_range; + }else { + f->fmt.pix_mp.colorspace =V4L2_COLORSPACE_DEFAULT ; + f->fmt.pix_mp.xfer_func =V4L2_XFER_FUNC_DEFAULT ; + f->fmt.pix_mp.ycbcr_enc =V4L2_YCBCR_ENC_DEFAULT ; + f->fmt.pix_mp.quantization =V4L2_QUANTIZATION_DEFAULT ; + } +vpu_inst_unlock (inst); + +return 0 ; +} + +static int vdec_s_fmt (struct file *file,void *fh,struct v4l2_format *f) +{ +struct vpu_inst *inst =to_inst (file); +struct v4l2_pix_format_mplane *pixmp = &f->fmt.pix_mp; +const struct vpu_format *fmt; +struct vpu_format *cur_fmt; +struct vb2_queue *q; +struct vdec_t *vdec; +int i; + + vdec = inst->priv; + q =v4l2_m2m_get_vq (inst->m2m_ctx, f->type); +if (!q) +return -EINVAL ; +if (vb2_is_streaming (q)) +return -EBUSY ; + + fmt =vpu_try_fmt_common (inst, f); +if (!fmt) +return -EINVAL ; + + cur_fmt =vpu_get_format (inst, f->type); + +vpu_inst_lock (inst); + cur_fmt->pixfmt = fmt->pixfmt; + cur_fmt->type = fmt->type; +if (V4L2_TYPE_IS_OUTPUT (f->type) || vdec->seq_hdr_found <=0 ) { + cur_fmt->num_planes = fmt->num_planes; + cur_fmt->flags = fmt->flags; + cur_fmt->width = pixmp->width; + cur_fmt->height = pixmp->height; +for (i =0 ; i < fmt->num_planes; i++) { + cur_fmt->sizeimage[i] = pixmp->plane_fmt[i].sizeimage; + cur_fmt->bytesperline[i] = pixmp->plane_fmt[i].bytesperline; + } +if (pixmp->field !=V4L2_FIELD_ANY ) + cur_fmt->field = pixmp->field; + }else { + pixmp->num_planes = cur_fmt->num_planes; + pixmp->width = cur_fmt->width; + pixmp->height = cur_fmt->height; +for (i =0 ; i < pixmp->num_planes; i++) { + pixmp->plane_fmt[i].bytesperline = cur_fmt->bytesperline[i]; + pixmp->plane_fmt[i].sizeimage = cur_fmt->sizeimage[i]; + } + pixmp->field = cur_fmt->field; + } +if (V4L2_TYPE_IS_OUTPUT (f->type)) + vdec->params.codec_format = cur_fmt->pixfmt; +else + vdec->params.output_format = cur_fmt->pixfmt; + +if (!vdec->seq_hdr_found) { + vdec->codec_info.color_primaries = f->fmt.pix_mp.colorspace; + vdec->codec_info.transfer_chars = f->fmt.pix_mp.xfer_func; + vdec->codec_info.matrix_coeffs = f->fmt.pix_mp.ycbcr_enc; + vdec->codec_info.full_range = f->fmt.pix_mp.quantization; + + inst->crop.left =0 ; + inst->crop.top =0 ; + inst->crop.width = cur_fmt->width; + inst->crop.height = cur_fmt->height; + }else { + f->fmt.pix_mp.colorspace = vdec->codec_info.color_primaries; + f->fmt.pix_mp.xfer_func = vdec->codec_info.transfer_chars; + f->fmt.pix_mp.ycbcr_enc = vdec->codec_info.matrix_coeffs; + f->fmt.pix_mp.quantization = vdec->codec_info.full_range; + } + +vpu_inst_unlock (inst); + +inst_dbg (inst,LVL_FLOW ,"%s s_fmt: %c%c%c%c %dx%d %u,%u, %u,%u\n" , +vpu_type_name (f->type), + f->fmt.pix_mp.pixelformat, + f->fmt.pix_mp.pixelformat >>8 , + f->fmt.pix_mp.pixelformat >>16 , + f->fmt.pix_mp.pixelformat >>24 , + f->fmt.pix_mp.width, + f->fmt.pix_mp.height, + pixmp->plane_fmt[0 ].sizeimage, + pixmp->plane_fmt[1 ].sizeimage, + pixmp->plane_fmt[0 ].bytesperline, + pixmp->plane_fmt[1 ].bytesperline); + +return 0 ; +} + +static int vdec_g_selection (struct file *file,void *fh, +struct v4l2_selection *s) +{ +struct vpu_inst *inst =to_inst (file); + +if (s->type !=V4L2_BUF_TYPE_VIDEO_CAPTURE && + s->type !=V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE ) +return -EINVAL ; + +switch (s->target) { +case V4L2_SEL_TGT_COMPOSE : +case V4L2_SEL_TGT_COMPOSE_DEFAULT : +case V4L2_SEL_TGT_COMPOSE_PADDED : + s->r = inst->crop; +break ; +case V4L2_SEL_TGT_COMPOSE_BOUNDS : + s->r.left =0 ; + s->r.top =0 ; + s->r.width = inst->cap_format.width; + s->r.height = inst->cap_format.height; +break ; +default : +return -EINVAL ; + } + +return 0 ; +} + +static int vdec_drain (struct vpu_inst *inst) +{ +struct vdec_t *vdec = inst->priv; + +if (!vdec->drain) +return 0 ; + +if (v4l2_m2m_num_src_bufs_ready (inst->m2m_ctx)) +return 0 ; + +if (!vdec->params.frame_count) { +vpu_notify_eos (inst); +return 0 ; + } + +vpu_iface_add_scode (inst,SCODE_PADDING_EOS ); + vdec->params.end_flag =1 ; +vpu_iface_set_decode_params (inst, &vdec->params,1 ); + vdec->drain =0 ; +inst_dbg (inst,LVL_FLOW ,"append eos\n" ); + +return 0 ; +} + +static int vdec_cmd_stop (struct vpu_inst *inst) +{ +struct vdec_t *vdec = inst->priv; + +inst_dbg (inst,LVL_FLOW ,"stop cmd\n" ); + +if (inst->state ==VPU_CODEC_STATE_DEINIT ) { +vpu_notify_eos (inst); + }else { + vdec->drain =1 ; +vdec_drain (inst); + } + +return 0 ; +} + +static int vdec_decoder_cmd (struct file *file, +void *fh, +struct v4l2_decoder_cmd *cmd) +{ +struct vpu_inst *inst =to_inst (file); +int ret; + + ret =v4l2_m2m_ioctl_try_decoder_cmd (file, fh, cmd); +if (ret) +return ret; + +vpu_inst_lock (inst); +switch (cmd->cmd) { +case V4L2_DEC_CMD_STOP : +vdec_cmd_stop (inst); +break ; +default : +break ; + } +vpu_inst_unlock (inst); + +return 0 ; +} + +static int vdec_subscribe_event (struct v4l2_fh *fh, +const struct v4l2_event_subscription *sub) +{ + struct vpu_inst *inst = container_of(fh, struct vpu_inst, fh); +struct vdec_t *vdec = inst->priv; + +switch (sub->type) { +case V4L2_EVENT_EOS : + vdec->eos_subscribed = true; +return v4l2_event_subscribe (fh, sub,0 ,NULL ); +case V4L2_EVENT_SOURCE_CHANGE : +return v4l2_src_change_event_subscribe (fh, sub); +case V4L2_EVENT_CTRL : +return v4l2_ctrl_subscribe_event (fh, sub); +case V4L2_EVENT_SKIP : +case V4L2_EVENT_CODEC_ERROR : +return v4l2_event_subscribe (fh, sub,0 ,NULL ); +default : +return -EINVAL ; + } + +return 0 ; +} + +static int vdec_unsubscribe_event (struct v4l2_fh *fh, +const struct v4l2_event_subscription *sub) +{ + struct vpu_inst *inst = container_of(fh, struct vpu_inst, fh); +struct vdec_t *vdec = inst->priv; +int ret; + + ret =v4l2_event_unsubscribe (fh, sub); +if (ret) +return ret; + +if (sub->type ==V4L2_EVENT_EOS ) + vdec->eos_subscribed = false; + +return 0 ; +} + +static const struct v4l2_ioctl_ops vdec_ioctl_ops = { + .vidioc_querycap = vdec_querycap, + .vidioc_enum_fmt_vid_cap = vdec_enum_fmt, + .vidioc_enum_fmt_vid_out = vdec_enum_fmt, + .vidioc_g_fmt_vid_cap_mplane = vdec_g_fmt, + .vidioc_g_fmt_vid_out_mplane = vdec_g_fmt, + .vidioc_try_fmt_vid_cap_mplane = vdec_try_fmt, + .vidioc_try_fmt_vid_out_mplane = vdec_try_fmt, + .vidioc_s_fmt_vid_cap_mplane = vdec_s_fmt, + .vidioc_s_fmt_vid_out_mplane = vdec_s_fmt, + .vidioc_g_selection = vdec_g_selection, + .vidioc_try_decoder_cmd = v4l2_m2m_ioctl_try_decoder_cmd, + .vidioc_decoder_cmd = vdec_decoder_cmd, + .vidioc_subscribe_event = vdec_subscribe_event, + .vidioc_unsubscribe_event = vdec_unsubscribe_event, + .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs, + .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs, + .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf, + .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, + .vidioc_qbuf = v4l2_m2m_ioctl_qbuf, + .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, + .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf, + .vidioc_streamon = v4l2_m2m_ioctl_streamon, + .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, +}; + +static bool vdec_check_ready (struct vpu_inst *inst,unsigned int type) +{ +struct vdec_t *vdec = inst->priv; + +if (V4L2_TYPE_IS_OUTPUT (type)) { +if (vdec->ts_pre_count >= vdec->frame_depth) +return false; +return true; + } + +if (vdec->req_frame_count || vdec->eos_received) +return true; + +return false; +} + +static int vdec_frame_decoded (struct vpu_inst *inst,void *arg) +{ +struct vdec_t *vdec = inst->priv; +struct vpu_dec_pic_info *info = arg; +struct vpu_vb2_buffer *vpu_buf; +int ret =0 ; + +if (!info || info->id >=ARRAY_SIZE (vdec->slots)) +return -EINVAL ; + +vpu_inst_lock (inst); + vpu_buf = vdec->slots[info->id]; +if (!vpu_buf) { +inst_err (inst,"decoded invalid frame[%d]\n" , info->id); + ret = -EINVAL ; + goto exit; + } +if (vpu_buf->state ==VPU_BUF_STATE_DECODED ) +inst_dbg (inst,LVL_INFO ,"buf[%d] has been decoded\n" , info->id); + vpu_buf->state =VPU_BUF_STATE_DECODED ; + vdec->decoded_frame_count++; +if (vdec->ts_pre_count >= info->consumed_count) + vdec->ts_pre_count -= info->consumed_count; +else + vdec->ts_pre_count =0 ; +exit: +vpu_inst_unlock (inst); + +return ret; +} + +static struct vpu_vb2_buffer *vdec_find_buffer (struct vpu_inst *inst,u32 luma) +{ +struct vdec_t *vdec = inst->priv; +int i; + +for (i =0 ; i <ARRAY_SIZE (vdec->slots); i++) { +if (!vdec->slots[i]) +continue ; +if (luma == vdec->slots[i]->luma) +return vdec->slots[i]; + } + +return NULL ; +} + +static void vdec_buf_done (struct vpu_inst *inst,struct vpu_frame_info *frame) +{ +struct vdec_t *vdec = inst->priv; +struct vpu_vb2_buffer *vpu_buf; +struct vb2_v4l2_buffer *vbuf; + +if (!frame) +return ; + +vpu_inst_lock (inst); + vpu_buf =vdec_find_buffer (inst, frame->luma); +vpu_inst_unlock (inst); +if (!vpu_buf) { +inst_err (inst,"can't find buffer, id = %d, addr = 0x%x\n" , + frame->id, frame->luma); +return ; + } +if (frame->skipped) { +inst_dbg (inst,LVL_DEBUG ,"frame skip\n" ); +vpu_notify_skip (inst); +return ; + } + + vbuf = &vpu_buf->m2m_buf.vb; +if (vbuf->vb2_buf.index != frame->id) +inst_err (inst,"buffer id(%d, %d) dismatch\n" , + vbuf->vb2_buf.index, frame->id); + +if (vpu_buf->state !=VPU_BUF_STATE_DECODED ) +inst_err (inst,"buffer(%d) ready without decoded\n" , frame->id); + vpu_buf->state =VPU_BUF_STATE_READY ; +vb2_set_plane_payload (&vbuf->vb2_buf,0 , inst->cap_format.sizeimage[0 ]); +vb2_set_plane_payload (&vbuf->vb2_buf,1 , inst->cap_format.sizeimage[1 ]); + vbuf->vb2_buf.timestamp = frame->timestamp; + vbuf->field = inst->cap_format.field; +inst_dbg (inst,LVL_TS ,"[OUTPUT TS]%32lld\n" , frame->timestamp); + +v4l2_m2m_buf_done (vbuf,VB2_BUF_STATE_DONE ); +vpu_inst_lock (inst); + vdec->timestamp = frame->timestamp; + vdec->display_frame_count++; +vpu_inst_unlock (inst); +inst_dbg (inst,LVL_DEBUG ,"decoded : %d, display : %d\n" , + vdec->decoded_frame_count, vdec->display_frame_count); +} + +static void vdec_stop_done (struct vpu_inst *inst) +{ +struct vdec_t *vdec = inst->priv; + +vpu_inst_lock (inst); +vdec_update_state (inst,VPU_CODEC_STATE_DEINIT ,0 ); + vdec->seq_hdr_found =0 ; +vpu_inst_unlock (inst); +} + +static bool vdec_check_source_change (struct vpu_inst *inst) +{ +struct vdec_t *vdec = inst->priv; +const struct vpu_format *fmt; +int i; + + fmt =vpu_helper_find_format (inst, inst->cap_format.type, vdec->codec_info.pixfmt); +if (inst->cap_format.pixfmt != vdec->codec_info.pixfmt) +return true; +if (inst->cap_format.width != vdec->codec_info.decoded_width) +return true; +if (inst->cap_format.height != vdec->codec_info.decoded_height) +return true; +if (vpu_get_num_buffers (inst, inst->cap_format.type) < inst->min_buffer_cap) +return true; +if (inst->crop.left != vdec->codec_info.offset_x) +return true; +if (inst->crop.top != vdec->codec_info.offset_y) +return true; +if (inst->crop.width != vdec->codec_info.width) +return true; +if (inst->crop.height != vdec->codec_info.height) +return true; +if (fmt && inst->cap_format.num_planes != fmt->num_planes) +return true; +for (i =0 ; i < inst->cap_format.num_planes; i++) { +if (inst->cap_format.bytesperline[i] != vdec->codec_info.bytesperline[i]) +return true; +if (inst->cap_format.sizeimage[i] != vdec->codec_info.sizeimage[i]) +return true; + } + +return false; +} + +static void vdec_init_fmt (struct vpu_inst *inst) +{ +struct vdec_t *vdec = inst->priv; +const struct vpu_format *fmt; +int i; + + fmt =vpu_helper_find_format (inst, inst->cap_format.type, vdec->codec_info.pixfmt); + inst->out_format.width = vdec->codec_info.width; + inst->out_format.height = vdec->codec_info.height; + inst->cap_format.width = vdec->codec_info.decoded_width; + inst->cap_format.height = vdec->codec_info.decoded_height; + inst->cap_format.pixfmt = vdec->codec_info.pixfmt; +if (fmt) { + inst->cap_format.num_planes = fmt->num_planes; + inst->cap_format.flags = fmt->flags; + } +for (i =0 ; i < inst->cap_format.num_planes; i++) { + inst->cap_format.bytesperline[i] = vdec->codec_info.bytesperline[i]; + inst->cap_format.sizeimage[i] = vdec->codec_info.sizeimage[i]; + } +if (vdec->codec_info.progressive) + inst->cap_format.field =V4L2_FIELD_NONE ; +else + inst->cap_format.field =V4L2_FIELD_INTERLACED ; +if (vdec->codec_info.color_primaries ==V4L2_COLORSPACE_DEFAULT ) + vdec->codec_info.color_primaries =V4L2_COLORSPACE_REC709 ; +if (vdec->codec_info.transfer_chars ==V4L2_XFER_FUNC_DEFAULT ) + vdec->codec_info.transfer_chars =V4L2_XFER_FUNC_709 ; +if (vdec->codec_info.matrix_coeffs ==V4L2_YCBCR_ENC_DEFAULT ) + vdec->codec_info.matrix_coeffs =V4L2_YCBCR_ENC_709 ; +if (vdec->codec_info.full_range ==V4L2_QUANTIZATION_DEFAULT ) + vdec->codec_info.full_range =V4L2_QUANTIZATION_LIM_RANGE ; +} + +static void vdec_init_crop (struct vpu_inst *inst) +{ +struct vdec_t *vdec = inst->priv; + + inst->crop.left = vdec->codec_info.offset_x; + inst->crop.top = vdec->codec_info.offset_y; + inst->crop.width = vdec->codec_info.width; + inst->crop.height = vdec->codec_info.height; +} + +static void vdec_init_mbi (struct vpu_inst *inst) +{ +struct vdec_t *vdec = inst->priv; + + vdec->mbi.size = vdec->codec_info.mbi_size; + vdec->mbi.max_count =ARRAY_SIZE (vdec->mbi.buffer); +scnprintf (vdec->mbi.name,sizeof (vdec->mbi.name),"mbi" ); + vdec->mbi.type =MEM_RES_MBI ; + vdec->mbi.tag = vdec->seq_tag; +} + +static void vdec_init_dcp (struct vpu_inst *inst) +{ +struct vdec_t *vdec = inst->priv; + + vdec->dcp.size = vdec->codec_info.dcp_size; + vdec->dcp.max_count =ARRAY_SIZE (vdec->dcp.buffer); +scnprintf (vdec->dcp.name,sizeof (vdec->dcp.name),"dcp" ); + vdec->dcp.type =MEM_RES_DCP ; + vdec->dcp.tag = vdec->seq_tag; +} + +static void vdec_request_one_fs (struct vdec_fs_info *fs) +{ +WARN_ON (!fs); + + fs->req_count++; +if (fs->req_count > fs->max_count) { +vpu_err ("error:request %s over %d\n" , fs->name, fs->max_count); + fs->req_count = fs->max_count; + } +} + +static int vdec_alloc_fs_buffer (struct vpu_inst *inst,struct vdec_fs_info *fs) +{ +struct vpu_buffer *buffer; + +if (!inst || !fs || !fs->size) +return -EINVAL ; + +if (fs->count >= fs->req_count) +return -EINVAL ; + + buffer = &fs->buffer[fs->count]; +if (buffer->virt && buffer->length >= fs->size) +return 0 ; + +vpu_free_dma (buffer); + buffer->length = fs->size; +return vpu_alloc_dma (inst->core, buffer); +} + +static void vdec_alloc_fs (struct vpu_inst *inst,struct vdec_fs_info *fs) +{ +int ret; + +while (fs->count < fs->req_count) { + ret =vdec_alloc_fs_buffer (inst, fs); +if (ret) +break ; + fs->count++; + } +} + +static void vdec_clear_fs (struct vdec_fs_info *fs) +{ +u32 i; + +if (!fs) +return ; + +for (i =0 ; i <ARRAY_SIZE (fs->buffer); i++) +vpu_free_dma (&fs->buffer[i]); +memset (fs,0 ,sizeof (*fs)); +} + +static int vdec_response_fs (struct vpu_inst *inst,struct vdec_fs_info *fs) +{ +struct vpu_fs_info info; +int ret; + +if (fs->index >= fs->count) +return 0 ; + +memset (&info,0 ,sizeof (info)); + info.id = fs->index; + info.type = fs->type; + info.tag = fs->tag; + info.luma_addr = fs->buffer[fs->index].phys; + info.luma_size = fs->buffer[fs->index].length; + ret =vpu_session_alloc_fs (inst, &info); +if (ret) +return ret; + + fs->index++; +return 0 ; +} + +static int vdec_response_frame_abnormal (struct vpu_inst *inst) +{ +struct vdec_t *vdec = inst->priv; +struct vpu_fs_info info; + +if (!vdec->req_frame_count) +return 0 ; + +memset (&info,0 ,sizeof (info)); + info.type =MEM_RES_FRAME ; + info.tag = vdec->seq_tag +0xf0 ; +vpu_session_alloc_fs (inst, &info); + vdec->req_frame_count--; + +return 0 ; +} + +static int vdec_response_frame (struct vpu_inst *inst,struct vb2_v4l2_buffer *vbuf) +{ +struct vdec_t *vdec = inst->priv; +struct vpu_vb2_buffer *vpu_buf; +struct vpu_fs_info info; +int ret; + +if (inst->state !=VPU_CODEC_STATE_ACTIVE ) +return -EINVAL ; + +if (!vdec->req_frame_count) +return -EINVAL ; + +if (!vbuf) +return -EINVAL ; + +if (vdec->slots[vbuf->vb2_buf.index]) { +inst_err (inst,"repeat alloc fs %d\n" , vbuf->vb2_buf.index); +return -EINVAL ; + } + +inst_dbg (inst,LVL_DEBUG ,"inst->state = %d, alloc fs %d, tag = 0x%x\n" , + inst->state, vbuf->vb2_buf.index, vdec->seq_tag); + vpu_buf =to_vpu_vb2_buffer (vbuf); + +memset (&info,0 ,sizeof (info)); + info.id = vbuf->vb2_buf.index; + info.type =MEM_RES_FRAME ; + info.tag = vdec->seq_tag; + info.luma_addr =vpu_get_vb_phy_addr (&vbuf->vb2_buf,0 ); + info.luma_size = inst->cap_format.sizeimage[0 ]; + info.chroma_addr =vpu_get_vb_phy_addr (&vbuf->vb2_buf,1 ); + info.chromau_size = inst->cap_format.sizeimage[1 ]; + info.bytesperline = inst->cap_format.bytesperline[0 ]; + ret =vpu_session_alloc_fs (inst, &info); +if (ret) +return ret; + + vpu_buf->tag = info.tag; + vpu_buf->luma = info.luma_addr; + vpu_buf->chroma_u = info.chromau_size; + vpu_buf->chroma_v =0 ; + vpu_buf->state =VPU_BUF_STATE_INUSE ; + vdec->slots[info.id] = vpu_buf; + vdec->req_frame_count--; + +return 0 ; +} + +static void vdec_response_fs_request (struct vpu_inst *inst,bool force) +{ +struct vdec_t *vdec = inst->priv; +int i; +int ret; + +if (force) { +for (i = vdec->req_frame_count; i >0 ; i--) +vdec_response_frame_abnormal (inst); +return ; + } + +for (i = vdec->req_frame_count; i >0 ; i--) { + ret =vpu_process_capture_buffer (inst); +if (ret) +break ; +if (vdec->eos_received) +break ; + } + +for (i = vdec->mbi.index; i < vdec->mbi.count; i++) { +if (vdec_response_fs (inst, &vdec->mbi)) +break ; +if (vdec->eos_received) +break ; + } +for (i = vdec->dcp.index; i < vdec->dcp.count; i++) { +if (vdec_response_fs (inst, &vdec->dcp)) +break ; +if (vdec->eos_received) +break ; + } +} + +static void vdec_response_fs_release (struct vpu_inst *inst,u32 id,u32 tag) +{ +struct vpu_fs_info info; + +memset (&info,0 ,sizeof (info)); + info.id = id; + info.tag = tag; +vpu_session_release_fs (inst, &info); +} + +static void vdec_recycle_buffer (struct vpu_inst *inst,struct vb2_v4l2_buffer *vbuf) +{ +if (!inst || !vbuf) +return ; + +if (vbuf->vb2_buf.state !=VB2_BUF_STATE_ACTIVE ) +return ; +if (vpu_find_buf_by_idx (inst, vbuf->vb2_buf.type, vbuf->vb2_buf.index)) +return ; +v4l2_m2m_buf_queue (inst->m2m_ctx, vbuf); +} + +static void vdec_clear_slots (struct vpu_inst *inst) +{ +struct vdec_t *vdec = inst->priv; +struct vpu_vb2_buffer *vpu_buf; +struct vb2_v4l2_buffer *vbuf; +int i; + +for (i =0 ; i <ARRAY_SIZE (vdec->slots); i++) { +if (!vdec->slots[i]) +continue ; + + vpu_buf = vdec->slots[i]; + vbuf = &vpu_buf->m2m_buf.vb; +if (vpu_buf->tag == vdec->seq_tag) +inst_dbg (inst,LVL_WARN ,"clear slot[%d], %d, %d\n" , + i, + vdec->slots[i]->state, + vbuf->vb2_buf.state); + +vdec_response_fs_release (inst, i, vpu_buf->tag); +vdec_recycle_buffer (inst, vbuf); + vdec->slots[i]->state =VPU_BUF_STATE_IDLE ; + vdec->slots[i] =NULL ; + } +} + +static void vdec_event_seq_hdr (struct vpu_inst *inst, +struct vpu_dec_codec_info *hdr) +{ +struct vdec_t *vdec = inst->priv; + +vpu_inst_lock (inst); +memcpy (&vdec->codec_info, hdr,sizeof (vdec->codec_info)); + +inst_dbg (inst,LVL_FLOW ,"%d x %d, crop : (%d, %d) %d x %d\n" , + vdec->codec_info.decoded_width, + vdec->codec_info.decoded_height, + vdec->codec_info.offset_x, + vdec->codec_info.offset_y, + vdec->codec_info.width, + vdec->codec_info.height); + inst->min_buffer_cap = hdr->num_ref_frms + hdr->num_dpb_frms; + vdec->is_source_changed =vdec_check_source_change (inst); +vdec_init_fmt (inst); +vdec_init_crop (inst); +vdec_init_mbi (inst); +vdec_init_dcp (inst); +if (!vdec->seq_hdr_found) { + vdec->seq_tag = vdec->codec_info.tag; +if (vdec->is_source_changed) { +vdec_update_state (inst,VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE ,0 ); +vpu_notify_source_change (inst); + vdec->is_source_changed = false; + } + } +if (vdec->seq_tag != vdec->codec_info.tag) { +vdec_response_fs_request (inst, true); +inst_dbg (inst,LVL_DEBUG ,"seq tag change: %d -> %d\n" , + vdec->seq_tag, vdec->codec_info.tag); + } + vdec->seq_hdr_found++; +vpu_inst_unlock (inst); +} + +static void vdec_event_resolution_change (struct vpu_inst *inst) +{ +struct vdec_t *vdec = inst->priv; + +inst_dbg (inst,LVL_FLOW ,"resolution change\n" ); +vpu_inst_lock (inst); + vdec->seq_tag = vdec->codec_info.tag; +vdec_clear_fs (&vdec->mbi); +vdec_clear_fs (&vdec->dcp); +vdec_clear_slots (inst); +vdec_init_mbi (inst); +vdec_init_dcp (inst); +if (vdec->is_source_changed) { +vdec_update_state (inst,VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE ,0 ); + vdec->source_change++; +vdec_handle_resolution_change (inst); + vdec->is_source_changed = false; + } +vpu_inst_unlock (inst); +} + +static void vdec_event_req_fs (struct vpu_inst *inst,struct vpu_fs_info *fs) +{ +struct vdec_t *vdec = inst->priv; + +if (!fs) +return ; + +vpu_inst_lock (inst); + +switch (fs->type) { +case MEM_RES_FRAME : + vdec->req_frame_count++; +break ; +case MEM_RES_MBI : +vdec_request_one_fs (&vdec->mbi); +break ; +case MEM_RES_DCP : +vdec_request_one_fs (&vdec->dcp); +break ; +default : +break ; + } + +vdec_alloc_fs (inst, &vdec->mbi); +vdec_alloc_fs (inst, &vdec->dcp); + +vdec_response_fs_request (inst, false); + +vpu_inst_unlock (inst); +} + +static void vdec_evnet_rel_fs (struct vpu_inst *inst,struct vpu_fs_info *fs) +{ +struct vdec_t *vdec = inst->priv; +struct vpu_vb2_buffer *vpu_buf; +struct vb2_v4l2_buffer *vbuf; + +if (!fs || fs->id >=ARRAY_SIZE (vdec->slots)) +return ; +if (fs->type !=MEM_RES_FRAME ) +return ; + +if (fs->id >=vpu_get_num_buffers (inst, inst->cap_format.type)) { +inst_err (inst,"invalid fs(%d) to release\n" , fs->id); +return ; + } + +vpu_inst_lock (inst); + vpu_buf = vdec->slots[fs->id]; + vdec->slots[fs->id] =NULL ; + +if (!vpu_buf) { +inst_dbg (inst,LVL_DEBUG ,"fs[%d] has bee released\n" , fs->id); + goto exit; + } + +if (vpu_buf->state ==VPU_BUF_STATE_DECODED ) { +inst_dbg (inst,LVL_DEBUG ,"this frame is skipped\n" ); +vpu_notify_skip (inst); + } + +vdec_response_fs_release (inst, fs->id, vpu_buf->tag); + vbuf = &vpu_buf->m2m_buf.vb; +if (vpu_buf->state !=VPU_BUF_STATE_READY ) +vdec_recycle_buffer (inst, vbuf); + + vpu_buf->state =VPU_BUF_STATE_IDLE ; +vpu_process_capture_buffer (inst); + +exit: +vpu_inst_unlock (inst); +} + +static void vdec_event_eos (struct vpu_inst *inst) +{ +struct vdec_t *vdec = inst->priv; + +inst_dbg (inst,LVL_FLOW ,"eos\n" ); +vpu_inst_lock (inst); + vdec->eos_received++; +vdec_update_state (inst,VPU_CODEC_STATE_DRAIN ,0 ); +vpu_process_capture_buffer (inst); +vdec_handle_eos (inst); +vpu_inst_unlock (inst); +} + +static void vdec_event_notify (struct vpu_inst *inst,u32 event,void *data) +{ +switch (event) { +case VPU_MSG_ID_SEQ_HDR_FOUND : +vdec_event_seq_hdr (inst, data); +break ; +case VPU_MSG_ID_RES_CHANGE : +vdec_event_resolution_change (inst); +break ; +case VPU_MSG_ID_FRAME_REQ : +vdec_event_req_fs (inst, data); +break ; +case VPU_MSG_ID_FRAME_RELEASE : +vdec_evnet_rel_fs (inst, data); +break ; +case VPU_MSG_ID_PIC_EOS : +vdec_event_eos (inst); +break ; +default : +break ; + } +} + +static int vdec_process_output (struct vpu_inst *inst,struct vb2_buffer *vb) +{ +struct vdec_t *vdec = inst->priv; +struct vb2_v4l2_buffer *vbuf; +struct vpu_vb2_buffer *vpu_buf; +struct vpu_rpc_buffer_desc desc; +s64 timestamp; +u32 free_space; +int ret; + + vbuf =to_vb2_v4l2_buffer (vb); + vpu_buf =to_vpu_vb2_buffer (vbuf); +inst_dbg (inst,LVL_DEBUG ,"dec output [%d] %d : %ld\n" , + vbuf->sequence, vb->index,vb2_get_plane_payload (vb,0 )); + +if (inst->state ==VPU_CODEC_STATE_DEINIT ) +return -EINVAL ; + +if (inst->state ==VPU_CODEC_STATE_STARTED ) +vdec_update_state (inst,VPU_CODEC_STATE_ACTIVE ,0 ); + + ret =vpu_iface_get_stream_buffer_desc (inst, &desc); +if (ret) +return ret; + + free_space =vpu_helper_get_free_space (inst); +if (free_space <vb2_get_plane_payload (vb,0 ) +0x40000 ) +return -ENOMEM ; + + timestamp = vb->timestamp; +if (timestamp >=0 && vdec->ts_start <0 ) + vdec->ts_start = timestamp; +if (vdec->ts_input < timestamp) + vdec->ts_input = timestamp; + + ret =vpu_iface_input_frame (inst, vb); +if (ret <0 ) +return -ENOMEM ; + +inst_dbg (inst,LVL_TS ,"[INPUT TS]%32lld\n" , vb->timestamp); + vdec->ts_pre_count++; + vdec->params.frame_count++; + +v4l2_m2m_src_buf_remove_by_buf (inst->m2m_ctx, vbuf); + vpu_buf->state =VPU_BUF_STATE_IDLE ; +v4l2_m2m_buf_done (vbuf,VB2_BUF_STATE_DONE ); + +if (vdec->drain) +vdec_drain (inst); + +return 0 ; +} + +static int vdec_process_capture (struct vpu_inst *inst,struct vb2_buffer *vb) +{ +struct vdec_t *vdec = inst->priv; +struct vb2_v4l2_buffer *vbuf; +int ret; + +if (inst->state ==VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE ) +return -EINVAL ; + + vbuf =to_vb2_v4l2_buffer (vb); + +if (vdec->eos_received) { +if (vdec->eos_subscribed) { +vdec_handle_eos (inst); + }else { +vb2_set_plane_payload (vb,0 ,0 ); +vb2_set_plane_payload (vb,1 ,0 ); + vbuf->flags |=V4L2_BUF_FLAG_LAST ; +v4l2_m2m_dst_buf_remove_by_buf (inst->m2m_ctx, vbuf); +v4l2_m2m_buf_done (vbuf,VB2_BUF_STATE_DONE ); + vdec->eos_received--; + } +return 0 ; + } + + ret =vdec_response_frame (inst, vbuf); +if (ret) +return ret; +v4l2_m2m_dst_buf_remove_by_buf (inst->m2m_ctx, vbuf); +return 0 ; +} + +static void vdec_on_queue_emtpy (struct vpu_inst *inst,u32 type) +{ +if (V4L2_TYPE_IS_OUTPUT (type)) +return ; + +vdec_handle_resolution_change (inst); +vdec_handle_eos (inst); +} + +static void vdec_abort (struct vpu_inst *inst) +{ +struct vdec_t *vdec = inst->priv; +struct vpu_rpc_buffer_desc desc; +int ret; + +inst_dbg (inst,LVL_FLOW ,"abort, inst->state = %d\n" , inst->state); +vpu_iface_add_scode (inst,SCODE_PADDING_ABORT ); + vdec->params.end_flag =1 ; +vpu_iface_set_decode_params (inst, &vdec->params,1 ); + +vpu_session_abort (inst); + + ret =vpu_iface_get_stream_buffer_desc (inst, &desc); +if (!ret) +vpu_iface_update_stream_buffer (inst, desc.rptr,1 ); + +vpu_session_rst_buf (inst); +inst_dbg (inst,LVL_FLOW ,"input : %d, decoded : %d, display : %d\n" , + vdec->params.frame_count, + vdec->decoded_frame_count, + vdec->display_frame_count); + vdec->params.end_flag =0 ; + vdec->drain =0 ; + vdec->ts_pre_count =0 ; + vdec->timestamp =VPU_INVALID_TIMESTAMP ; + vdec->ts_start =VPU_INVALID_TIMESTAMP ; + vdec->ts_input =VPU_INVALID_TIMESTAMP ; + vdec->params.frame_count =0 ; + vdec->decoded_frame_count =0 ; + vdec->display_frame_count =0 ; +} + +static void vdec_release (struct vpu_inst *inst) +{ +struct vdec_t *vdec = inst->priv; + +inst_dbg (inst,LVL_FLOW ,"release\n" ); +vpu_inst_lock (inst); +vdec_clear_slots (inst); +if (inst->state !=VPU_CODEC_STATE_DEINIT ) +vpu_session_stop (inst); +vdec_clear_fs (&vdec->mbi); +vdec_clear_fs (&vdec->dcp); +vpu_free_dma (&vdec->udata); +vpu_free_dma (&inst->stream_buffer); +vdec_update_state (inst,VPU_CODEC_STATE_DEINIT ,1 ); +vpu_inst_unlock (inst); +} + +static void vdec_cleanup (struct vpu_inst *inst) +{ +struct vdec_t *vdec; + +if (!inst) +return ; + + vdec = inst->priv; +if (vdec) +vfree (vdec); + inst->priv =NULL ; +vfree (inst); +} + +static void vdec_init_params (struct vdec_t *vdec) +{ + vdec->params.frame_count =0 ; + vdec->params.end_flag =0 ; +} + +static int vdec_start (struct vpu_inst *inst) +{ +struct vdec_t *vdec = inst->priv; +int stream_buffer_size; +int ret; + +if (inst->state !=VPU_CODEC_STATE_DEINIT ) +return 0 ; + +inst_dbg (inst,LVL_FLOW ,"start\n" ); + vdec->udata.length =0x1000 ; + ret =vpu_alloc_dma (inst->core, &vdec->udata); +if (ret) { +inst_err (inst,"alloc udata fail\n" ); + goto error; + } + +vpu_iface_init_instance (inst); + stream_buffer_size =vpu_iface_get_stream_buffer_size (inst->core); +if (stream_buffer_size >0 ) { + inst->stream_buffer.length = stream_buffer_size; + ret =vpu_alloc_dma (inst->core, &inst->stream_buffer); +if (ret) { +inst_err (inst,"alloc stream buffer fail\n" ); + goto error; + } + inst->use_stream_buffer = true; +vpu_iface_config_stream_buffer (inst, &inst->stream_buffer); + } + + vdec->params.udata.base = vdec->udata.phys; + vdec->params.udata.size = vdec->udata.length; + ret =vpu_iface_set_decode_params (inst, &vdec->params,0 ); +if (ret) { +inst_err (inst,"set decode params fail\n" ); + goto error; + } + +vdec_init_params (vdec); + ret =vpu_session_start (inst); +if (ret) { +inst_err (inst,"start fail\n" ); + goto error; + } + +vdec_update_state (inst,VPU_CODEC_STATE_STARTED ,0 ); + +return 0 ; +error: +vpu_free_dma (&vdec->udata); +vpu_free_dma (&inst->stream_buffer); +return ret; +} + +static int vdec_start_session (struct vpu_inst *inst,u32 type) +{ +struct vdec_t *vdec = inst->priv; +int ret =0 ; + +if (inst->state ==VPU_CODEC_STATE_DEINIT ) { +if (V4L2_TYPE_IS_OUTPUT (type)) { + ret =vdec_start (inst); +if (ret) +return ret; + } + } + +if (V4L2_TYPE_IS_OUTPUT (type)) { +if (inst->state ==VPU_CODEC_STATE_SEEK ) +vdec_update_state (inst, vdec->state,1 ); + vdec->eos_received =0 ; +vpu_process_output_buffer (inst); + }else { +if (inst->state ==VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE ) +vdec_update_state (inst,VPU_CODEC_STATE_ACTIVE ,0 ); +vpu_process_capture_buffer (inst); + } +if (inst->state ==VPU_CODEC_STATE_ACTIVE ) +vdec_response_fs_request (inst, false); + +return ret; +} + +static int vdec_stop_session (struct vpu_inst *inst,u32 type) +{ +struct vdec_t *vdec = inst->priv; + +if (inst->state ==VPU_CODEC_STATE_DEINIT ) +return 0 ; + +if (V4L2_TYPE_IS_OUTPUT (type)) { +vdec_update_state (inst,VPU_CODEC_STATE_SEEK ,0 ); + vdec->drain =0 ; + }else { +if (inst->state !=VPU_CODEC_STATE_DYAMIC_RESOLUTION_CHANGE ) +vdec_abort (inst); + + vdec->eos_received =0 ; +vdec_clear_slots (inst); + } + +return 0 ; +} + +static int vdec_get_debug_info (struct vpu_inst *inst,char *str,u32 size,u32 i) +{ +struct vdec_t *vdec = inst->priv; +int num =-1 ; + +switch (i) { +case 0 : + num =scnprintf (str, size, +"req_frame_count = %d\ninterlaced = %d\n" , + vdec->req_frame_count, + vdec->codec_info.progressive ?0 :1 ); +break ; +case 1 : + num =scnprintf (str, size, +"mbi: size = 0x%x request = %d, alloc = %d, response = %d\n" , + vdec->mbi.size, + vdec->mbi.req_count, + vdec->mbi.count, + vdec->mbi.index); +break ; +case 2 : + num =scnprintf (str, size, +"dcp: size = 0x%x request = %d, alloc = %d, response = %d\n" , + vdec->dcp.size, + vdec->dcp.req_count, + vdec->dcp.count, + vdec->dcp.index); +break ; +case 3 : + num =scnprintf (str, size,"input_frame_count = %d\n" , vdec->params.frame_count); +break ; +case 4 : + num =scnprintf (str, size,"decoded_frame_count = %d\n" , vdec->decoded_frame_count); +break ; +case 5 : + num =scnprintf (str, size,"display_frame_count = %d\n" , vdec->display_frame_count); +break ; +case 6 : + num =scnprintf (str, size,"drain = %d, eos = %d, source_change = %d\n" , + vdec->drain, vdec->eos_received, vdec->source_change); +break ; +case 7 : + num =scnprintf (str, size,"ts_pre_count = %d, frame_depth = %d\n" , + vdec->ts_pre_count, vdec->frame_depth); +break ; +case 8 : + num =scnprintf (str, size,"b_dis_reorder = %d, b_non_frame = %d\n" , + vdec->params.b_dis_reorder, + vdec->params.b_non_frame); +break ; +case 9 : + { +s64 timestamp = vdec->timestamp; +s64 ts_start = vdec->ts_start; +s64 ts_input = vdec->ts_input; + + num =scnprintf (str, size,"timestamp = %9lld.%09lld(%9lld.%09lld, %9lld.%09lld)\n" , + timestamp /NSEC_PER_SEC , + timestamp %NSEC_PER_SEC , + ts_start /NSEC_PER_SEC , + ts_start %NSEC_PER_SEC , + ts_input /NSEC_PER_SEC , + ts_input %NSEC_PER_SEC ); + } +break ; +default : +break ; + } + +return num; +} + +static struct vpu_inst_ops vdec_inst_ops = { + .ctrl_init = vdec_ctrl_init, + .check_ready = vdec_check_ready, + .buf_done = vdec_buf_done, + .get_one_frame = vdec_frame_decoded, + .stop_done = vdec_stop_done, + .event_notify = vdec_event_notify, + .release = vdec_release, + .cleanup = vdec_cleanup, + .start = vdec_start_session, + .stop = vdec_stop_session, + .process_output = vdec_process_output, + .process_capture = vdec_process_capture, + .on_queue_empty = vdec_on_queue_emtpy, + .get_debug_info = vdec_get_debug_info, + .wait_prepare = vpu_inst_unlock, + .wait_finish = vpu_inst_lock, +}; + +static void vdec_init (struct file *file) +{ +struct vpu_inst *inst =to_inst (file); +struct vdec_t *vdec; +struct v4l2_format f; + + vdec = inst->priv; + vdec->frame_depth =VDEC_FRAME_DEPTH ; + vdec->timestamp =VPU_INVALID_TIMESTAMP ; + vdec->ts_start =VPU_INVALID_TIMESTAMP ; + vdec->ts_input =VPU_INVALID_TIMESTAMP ; + +memset (&f,0 ,sizeof (f)); + f.type =V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE ; + f.fmt.pix_mp.pixelformat =V4L2_PIX_FMT_H264 ; + f.fmt.pix_mp.width =1280 ; + f.fmt.pix_mp.height =720 ; + f.fmt.pix_mp.field =V4L2_FIELD_NONE ; +vdec_s_fmt (file, &inst->fh, &f); + +memset (&f,0 ,sizeof (f)); + f.type =V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE ; + f.fmt.pix_mp.pixelformat =V4L2_PIX_FMT_NV12 ; + f.fmt.pix_mp.width =1280 ; + f.fmt.pix_mp.height =720 ; + f.fmt.pix_mp.field =V4L2_FIELD_NONE ; +vdec_s_fmt (file, &inst->fh, &f); +} + +int vdec_open (struct file *file) +{ +struct vpu_inst *inst; +struct vdec_t *vdec; +int ret; + + inst =vzalloc (sizeof (*inst)); +if (!inst) +return -ENOMEM ; + + vdec =vzalloc (sizeof (*vdec)); +if (!vdec) { +vfree (inst); +return -ENOMEM ; + } + + inst->ops = &vdec_inst_ops; + inst->formats = vdec_formats; + inst->type =VPU_CORE_TYPE_DEC ; + inst->priv = vdec; + + ret =vpu_v4l2_open (file, inst); +if (ret) { +vdec_cleanup (inst); +return ret; + } + +vdec_init (file); + +return 0 ; +} + +__poll_t vdec_poll (struct file *file,poll_table *wait) +{ +struct vpu_inst *inst =to_inst (file); +struct vb2_queue *src_q, *dst_q; +__poll_t ret; + + ret =v4l2_m2m_fop_poll (file, wait); + src_q =v4l2_m2m_get_src_vq (inst->m2m_ctx); + dst_q =v4l2_m2m_get_dst_vq (inst->m2m_ctx); +if (vb2_is_streaming (src_q) && !vb2_is_streaming (dst_q)) + ret &= (~EPOLLERR ); + +return ret; +} + +static const struct v4l2_file_operations vdec_fops = { + .owner =THIS_MODULE , + .open = vdec_open, + .release = vpu_v4l2_close, + .unlocked_ioctl = video_ioctl2, + .poll = vdec_poll, + .mmap = v4l2_m2m_fop_mmap, +}; + +int vdec_create_video_device (struct vpu_dev *vpu) +{ +struct video_device *vdec; +int ret; + +if (!vpu) +return -EINVAL ; + +if (vpu->vdev_dec) +return 0 ; + + vdec =video_device_alloc (); +if (!vdec) { +vpu_err ("alloc vpu decoder video device fail\n" ); +return -ENOMEM ; + } +strscpy (vdec->name,"imx-vpu-decoder" ,sizeof (vdec->name)); + vdec->release = video_device_release; + vdec->fops = &vdec_fops; + vdec->ioctl_ops = &vdec_ioctl_ops; + vdec->vfl_dir =VFL_DIR_M2M ; + vdec->v4l2_dev = &vpu->v4l2_dev; + vdec->device_caps =V4L2_CAP_VIDEO_M2M_MPLANE |V4L2_CAP_STREAMING ; + + ret =video_register_device (vdec,VFL_TYPE_VIDEO ,-1 ); +if (ret) { +video_device_release (vdec); +return ret; + } +video_set_drvdata (vdec, vpu); + vpu->vdev_dec = vdec; + +return 0 ; +}
Signature · 1 line
2.32.0
PATCH v5 10/14 media: imx: imx8q: implement windsor encoder rpc interface
In reply to Ming QianThis part implements the windsor encoder rpc interface.
--- drivers/media/platform/imx/vpu-8q/vpu_imx8q.c | 218 +++ drivers/media/platform/imx/vpu-8q/vpu_imx8q.h | 116 ++ .../media/platform/imx/vpu-8q/vpu_windsor.c | 1244 +++++++++++++++++ .../media/platform/imx/vpu-8q/vpu_windsor.h | 39 + 4 files changed, 1617 insertions(+) create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_imx8q.c create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_imx8q.h create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_windsor.c create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_windsor.h
drivers/media/platform/imx/vpu-8q/vpu_imx8q.c new file +218 -0
@@ -0,0 +1,218 @@ +// SPDX-License-Identifier: GPL-2.0 +/* +* Copyright 2020-2021 NXP +*/ + +#define TAG "IMX8Q" + +#include <linux/init.h> +#include <linux/device.h> +#include <linux/ioctl.h> +#include <linux/list.h> +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/slab.h> +#include <linux/delay.h> +#include <linux/types.h> +#include "vpu.h" +#include "vpu_core.h" +#include "vpu_imx8q.h" +#include "vpu_rpc.h" +#include "vpu_log.h" + +#define IMX8Q_CSR_CM0Px_ADDR_OFFSET 0x00000000 +#define IMX8Q_CSR_CM0Px_CPUWAIT 0x00000004 + +#ifdef CONFIG_IMX_SCU +#include <linux/firmware/imx/ipc.h> +#include <linux/firmware/imx/svc/misc.h> + +#define VPU_DISABLE_BITS 0x7 +#define VPU_IMX_DECODER_FUSE_OFFSET 14 +#define VPU_ENCODER_MASK 0x1 +#define VPU_DECODER_MASK 0x3UL +#define VPU_DECODER_H264_MASK 0x2UL +#define VPU_DECODER_HEVC_MASK 0x1UL + +static u32 imx8q_fuse; + +struct vpu_sc_msg_misc { +struct imx_sc_rpc_msg hdr; +u32 word; +} __packed; +#endif + +int vpu_imx8q_set_system_cfg_common (struct vpu_rpc_system_config *config, +u32 regs,u32 core_id) +{ +if (!config) +return -EINVAL ; + +switch (core_id) { +case 0 : + config->malone_base_addr[0 ] = regs +DEC_MFD_XREG_SLV_BASE ; + config->num_malones =1 ; + config->num_windsors =0 ; +break ; +case 1 : + config->windsor_base_addr[0 ] = regs +ENC_MFD_XREG_SLV_0_BASE ; + config->num_windsors =1 ; + config->num_malones =0 ; +break ; +case 2 : + config->windsor_base_addr[0 ] = regs +ENC_MFD_XREG_SLV_1_BASE ; + config->num_windsors =1 ; + config->num_malones =0 ; +break ; +default : +return -EINVAL ; + } +if (config->num_windsors) { + config->windsor_irq_pin[0x0 ][0x0 ] =WINDSOR_PAL_IRQ_PIN_L ; + config->windsor_irq_pin[0x0 ][0x1 ] =WINDSOR_PAL_IRQ_PIN_H ; + } + + config->malone_base_addr[0x1 ] =0x0 ; + config->hif_offset[0x0 ] =MFD_HIF ; + config->hif_offset[0x1 ] =0x0 ; + + config->dpv_base_addr =0x0 ; + config->dpv_irq_pin =0x0 ; + config->pixif_base_addr = regs +DEC_MFD_XREG_SLV_BASE +MFD_PIX_IF ; + config->cache_base_addr[0 ] = regs +MC_CACHE_0_BASE ; + config->cache_base_addr[1 ] = regs +MC_CACHE_1_BASE ; + +return 0 ; +} + +int vpu_imx8q_boot_core (struct vpu_core *core) +{ +csr_writel (core, IMX8Q_CSR_CM0Px_ADDR_OFFSET, core->fw.phys); +csr_writel (core, IMX8Q_CSR_CM0Px_CPUWAIT,0 ); +return 0 ; +} + +int vpu_imx8q_get_power_state (struct vpu_core *core) +{ +if (csr_readl (core, IMX8Q_CSR_CM0Px_CPUWAIT) ==1 ) +return 0 ; +return 1 ; +} + +int vpu_imx8q_on_firmware_loaded (struct vpu_core *core) +{ +u8 *p; + + p = core->fw.virt; + p[16 ] = core->vpu->res->plat_type; + p[17 ] = core->id; + p[18 ] =1 ; + +return 0 ; +} + +u32 vpu_imx8q_check_memory_region (dma_addr_t base,dma_addr_t addr,u32 size) +{ +const struct vpu_rpc_region_t imx8q_regions[] = { + {0x00000000 ,0x08000000 ,VPU_CORE_MEMORY_CACHED }, + {0x08000000 ,0x10000000 ,VPU_CORE_MEMORY_UNCACHED }, + {0x10000000 ,0x20000000 ,VPU_CORE_MEMORY_CACHED }, + {0x20000000 ,0x40000000 ,VPU_CORE_MEMORY_UNCACHED } + }; +int i; + +if (addr < base) +return VPU_CORE_MEMORY_INVALID ; + + addr -= base; +for (i =0 ; i <ARRAY_SIZE (imx8q_regions); i++) { +const struct vpu_rpc_region_t *region = &imx8q_regions[i]; + +if (addr >= region->start && addr + size < region->end) +return region->type; + } + +return VPU_CORE_MEMORY_INVALID ; +} + +#ifdef CONFIG_IMX_SCU +u32 vpu_imx8q_get_fuse (void ) +{ +static u32 fuse_got; +struct imx_sc_ipc *ipc; +struct vpu_sc_msg_misc msg; +struct imx_sc_rpc_msg *hdr = &msg.hdr; +int ret; + +if (fuse_got) +return imx8q_fuse; + + ret =imx_scu_get_handle (&ipc); +if (ret) { +vpu_err ("error: scu get handle fail: %d\n" , ret); +return 0 ; + } + + hdr->ver =IMX_SC_RPC_VERSION ; + hdr->svc =IMX_SC_RPC_SVC_MISC ; + hdr->func =IMX_SC_MISC_FUNC_OTP_FUSE_READ ; + hdr->size =2 ; + + msg.word =VPU_DISABLE_BITS ; + + ret =imx_scu_call_rpc (ipc, &msg, true); +if (ret) +return 0 ; + + imx8q_fuse = msg.word; + fuse_got =1 ; +vpu_dbg (LVL_INFO ,"imx8q fuse = 0x%x\n" , imx8q_fuse); +return imx8q_fuse; +} + +bool vpu_imx8q_check_codec (enum vpu_core_type type) +{ +u32 fuse =vpu_imx8q_get_fuse (); + +if (type ==VPU_CORE_TYPE_ENC ) { +if (fuse &VPU_ENCODER_MASK ) +return false; + }else if (type ==VPU_CORE_TYPE_DEC ) { + fuse >>=VPU_IMX_DECODER_FUSE_OFFSET ; + fuse &=VPU_DECODER_MASK ; + +if (fuse ==VPU_DECODER_MASK ) +return false; + } +return true; +} + +bool vpu_imx8q_check_fmt (enum vpu_core_type type,u32 pixelfmt) +{ +u32 fuse =vpu_imx8q_get_fuse (); + +if (type ==VPU_CORE_TYPE_DEC ) { + fuse >>=VPU_IMX_DECODER_FUSE_OFFSET ; + fuse &=VPU_DECODER_MASK ; + +if (fuse ==VPU_DECODER_HEVC_MASK && pixelfmt ==V4L2_PIX_FMT_HEVC ) +return false; +if (fuse ==VPU_DECODER_H264_MASK && pixelfmt ==V4L2_PIX_FMT_H264 ) +return false; +if (fuse ==VPU_DECODER_MASK ) +return false; + } + +return true; +} +#else +bool vpu_imx8q_check_codec (enum vpu_core_type type) +{ +return true; +} + +bool vpu_imx8q_check_fmt (enum vpu_core_type type,u32 pixelfmt) +{ +return true; +} +#endif
drivers/media/platform/imx/vpu-8q/vpu_imx8q.h new file +116 -0
116 lines not on this page · raw message
drivers/media/platform/imx/vpu-8q/vpu_windsor.c new file +1244 -0
1,244 lines not on this page · raw message
drivers/media/platform/imx/vpu-8q/vpu_windsor.h new file +39 -0
@@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* +* Copyright 2020-2021 NXP +*/ + +#ifndef _IMX_VPU_WINDSOR_H +#define _IMX_VPU_WINDSOR_H + +u32 vpu_windsor_get_data_size (void ); +void vpu_windsor_init_rpc (struct vpu_shared_addr *shared, +struct vpu_buffer *rpc,dma_addr_t boot_addr); +void vpu_windsor_set_log_buf (struct vpu_shared_addr *shared, +struct vpu_buffer *log); +void vpu_windsor_set_system_cfg (struct vpu_shared_addr *shared, +u32 regs_base,void __iomem *regs,u32 core_id); +int vpu_windsor_get_stream_buffer_size (struct vpu_shared_addr *shared); +int vpu_windsor_pack_cmd (struct vpu_rpc_event *pkt, +u32 index,u32 id,void *data); +int vpu_windsor_convert_msg_id (u32 msg_id); +int vpu_windsor_unpack_msg_data (struct vpu_rpc_event *pkt,void *data); +int vpu_windsor_config_memory_resource (struct vpu_shared_addr *shared, +u32 instance,u32 type,u32 index, +struct vpu_buffer *buf); +int vpu_windsor_config_stream_buffer (struct vpu_shared_addr *shared, +u32 instance,struct vpu_buffer *buf); +int vpu_windsor_update_stream_buffer (struct vpu_shared_addr *shared, +u32 instance,u32 ptr,bool write); +int vpu_windsor_get_stream_buffer_desc (struct vpu_shared_addr *shared, +u32 instance,struct vpu_rpc_buffer_desc *desc); +u32 vpu_windsor_get_version (struct vpu_shared_addr *shared); +int vpu_windsor_set_encode_params (struct vpu_shared_addr *shared, +u32 instance, +struct vpu_encode_params *params, +u32 update); +int vpu_windsor_input_frame (struct vpu_shared_addr *shared, +struct vpu_inst *inst,struct vb2_buffer *vb); +u32 vpu_windsor_get_max_instance_count (struct vpu_shared_addr *shared); + +#endif
Signature · 1 line
2.32.0
PATCH v5 11/14 media: imx: imx8q: implement malone decoder rpc interface
In reply to Ming QianThis part implements the malone decoder rpc interface.
--- .../media/platform/imx/vpu-8q/vpu_malone.c | 1696 +++++++++++++++++ .../media/platform/imx/vpu-8q/vpu_malone.h | 42 + 2 files changed, 1738 insertions(+) create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_malone.c create mode 100644 drivers/media/platform/imx/vpu-8q/vpu_malone.h
drivers/media/platform/imx/vpu-8q/vpu_malone.c new file +1696 -0
@@ -0,0 +1,1696 @@ +// SPDX-License-Identifier: GPL-2.0 +/* +* Copyright 2020-2021 NXP +*/ + +#define TAG "MALONE" +#include <linux/init.h> +#include <linux/interconnect.h> +#include <linux/ioctl.h> +#include <linux/list.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <media/videobuf2-v4l2.h> +#include <media/videobuf2-dma-contig.h> +#include <linux/videodev2.h> +#include <linux/imx_vpu.h> +#include "vpu.h" +#include "vpu_rpc.h" +#include "vpu_defs.h" +#include "vpu_helpers.h" +#include "vpu_cmds.h" +#include "vpu_log.h" +#include "vpu_imx8q.h" +#include "vpu_malone.h" + +#define CMD_SIZE 25600 +#define MSG_SIZE 25600 +#define CODEC_SIZE 0x1000 +#define JPEG_SIZE 0x1000 +#define SEQ_SIZE 0x1000 +#define GOP_SIZE 0x1000 +#define PIC_SIZE 0x1000 +#define QMETER_SIZE 0x1000 +#define DBGLOG_SIZE 0x10000 +#define DEBUG_SIZE 0x80000 +#define ENG_SIZE 0x1000 +#define MALONE_SKIPPED_FRAME_ID 0x555 + +#define MALONE_TILE_W 8 +#define MALONE_TILE_H 128 +#define MALONE_ALIGN_W (MALONE_TILE_W * 1) +#define MALONE_ALIGN_H (MALONE_TILE_H * 2) +#define MALONE_ALIGN_LINE (256) +#define MALONE_ALIGN_MBI 0x800 +#define MALONE_DCP_CHUNK_BIT 16 +#define MALONE_DCP_SIZE_MAX 0x3000000 +#define MALONE_DCP_SIZE_MIN 0x100000 +#define MALONE_DCP_FIXED_MB_ALLOC 250 + +#define CONFIG_SET (val, cfg, pos, mask) \ + (*(cfg) |= (((val) << (pos)) & (mask))) +//x means source data , y means destination data +#define STREAM_CONFIG_FORMAT_SET (x, y) CONFIG_SET(x, y, 0, 0x0000000F) +#define STREAM_CONFIG_STRBUFIDX_SET (x, y) CONFIG_SET(x, y, 8, 0x00000300) +#define STREAM_CONFIG_NOSEQ_SET (x, y) CONFIG_SET(x, y, 10, 0x00000400) +#define STREAM_CONFIG_DEBLOCK_SET (x, y) CONFIG_SET(x, y, 11, 0x00000800) +#define STREAM_CONFIG_DERING_SET (x, y) CONFIG_SET(x, y, 12, 0x00001000) +#define STREAM_CONFIG_IBWAIT_SET (x, y) CONFIG_SET(x, y, 13, 0x00002000) +#define STREAM_CONFIG_FBC_SET (x, y) CONFIG_SET(x, y, 14, 0x00004000) +#define STREAM_CONFIG_PLAY_MODE_SET (x, y) CONFIG_SET(x, y, 16, 0x00030000) +#define STREAM_CONFIG_ENABLE_DCP_SET (x, y) CONFIG_SET(x, y, 20, 0x00100000) +#define STREAM_CONFIG_NUM_STR_BUF_SET (x, y) CONFIG_SET(x, y, 21, 0x00600000) +#define STREAM_CONFIG_MALONE_USAGE_SET (x, y) CONFIG_SET(x, y, 23, 0x01800000) +#define STREAM_CONFIG_MULTI_VID_SET (x, y) CONFIG_SET(x, y, 25, 0x02000000) +#define STREAM_CONFIG_OBFUSC_EN_SET (x, y) CONFIG_SET(x, y, 26, 0x04000000) +#define STREAM_CONFIG_RC4_EN_SET (x, y) CONFIG_SET(x, y, 27, 0x08000000) +#define STREAM_CONFIG_MCX_SET (x, y) CONFIG_SET(x, y, 28, 0x10000000) +#define STREAM_CONFIG_PES_SET (x, y) CONFIG_SET(x, y, 29, 0x20000000) +#define STREAM_CONFIG_NUM_DBE_SET (x, y) CONFIG_SET(x, y, 30, 0x40000000) +#define STREAM_CONFIG_FS_CTRL_MODE_SET (x, y) CONFIG_SET(x, y, 31, 0x80000000) + +enum vpu_malone_stream_input_mode { +INVALID_MODE =0 , +FRAME_LVL , +NON_FRAME_LVL +}; + +enum vpu_malone_format { +MALONE_FMT_NULL =0x0 , +MALONE_FMT_AVC =0x1 , +MALONE_FMT_MP2 =0x2 , +MALONE_FMT_VC1 =0x3 , +MALONE_FMT_AVS =0x4 , +MALONE_FMT_ASP =0x5 , +MALONE_FMT_JPG =0x6 , +MALONE_FMT_RV =0x7 , +MALONE_FMT_VP6 =0x8 , +MALONE_FMT_SPK =0x9 , +MALONE_FMT_VP8 =0xA , +MALONE_FMT_HEVC =0xB , +MALONE_FMT_LAST =MALONE_FMT_HEVC +}; + +enum { +VID_API_CMD_NULL =0x00 , +VID_API_CMD_PARSE_NEXT_SEQ =0x01 , +VID_API_CMD_PARSE_NEXT_I =0x02 , +VID_API_CMD_PARSE_NEXT_IP =0x03 , +VID_API_CMD_PARSE_NEXT_ANY =0x04 , +VID_API_CMD_DEC_PIC =0x05 , +VID_API_CMD_UPDATE_ES_WR_PTR =0x06 , +VID_API_CMD_UPDATE_ES_RD_PTR =0x07 , +VID_API_CMD_UPDATE_UDATA =0x08 , +VID_API_CMD_GET_FSINFO =0x09 , +VID_API_CMD_SKIP_PIC =0x0a , +VID_API_CMD_DEC_CHUNK =0x0b , +VID_API_CMD_START =0x10 , +VID_API_CMD_STOP =0x11 , +VID_API_CMD_ABORT =0x12 , +VID_API_CMD_RST_BUF =0x13 , +VID_API_CMD_FS_RELEASE =0x15 , +VID_API_CMD_MEM_REGION_ATTACH =0x16 , +VID_API_CMD_MEM_REGION_DETACH =0x17 , +VID_API_CMD_MVC_VIEW_SELECT =0x18 , +VID_API_CMD_FS_ALLOC =0x19 , +VID_API_CMD_DBG_GET_STATUS =0x1C , +VID_API_CMD_DBG_START_LOG =0x1D , +VID_API_CMD_DBG_STOP_LOG =0x1E , +VID_API_CMD_DBG_DUMP_LOG =0x1F , +VID_API_CMD_YUV_READY =0x20 , +VID_API_CMD_TS =0x21 , + +VID_API_CMD_FIRM_RESET =0x40 , + +VID_API_CMD_SNAPSHOT =0xAA , +VID_API_CMD_ROLL_SNAPSHOT =0xAB , +VID_API_CMD_LOCK_SCHEDULER =0xAC , +VID_API_CMD_UNLOCK_SCHEDULER =0xAD , +VID_API_CMD_CQ_FIFO_DUMP =0xAE , +VID_API_CMD_DBG_FIFO_DUMP =0xAF , +VID_API_CMD_SVC_ILP =0xBB , +VID_API_CMD_FW_STATUS =0xF0 , +VID_API_CMD_INVALID =0xFF +}; + +enum { +VID_API_EVENT_NULL =0x00 , +VID_API_EVENT_RESET_DONE =0x01 , +VID_API_EVENT_SEQ_HDR_FOUND =0x02 , +VID_API_EVENT_PIC_HDR_FOUND =0x03 , +VID_API_EVENT_PIC_DECODED =0x04 , +VID_API_EVENT_FIFO_LOW =0x05 , +VID_API_EVENT_FIFO_HIGH =0x06 , +VID_API_EVENT_FIFO_EMPTY =0x07 , +VID_API_EVENT_FIFO_FULL =0x08 , +VID_API_EVENT_BS_ERROR =0x09 , +VID_API_EVENT_UDATA_FIFO_UPTD =0x0A , +VID_API_EVENT_RES_CHANGE =0x0B , +VID_API_EVENT_FIFO_OVF =0x0C , +VID_API_EVENT_CHUNK_DECODED =0x0D , +VID_API_EVENT_REQ_FRAME_BUFF =0x10 , +VID_API_EVENT_FRAME_BUFF_RDY =0x11 , +VID_API_EVENT_REL_FRAME_BUFF =0x12 , +VID_API_EVENT_STR_BUF_RST =0x13 , +VID_API_EVENT_RET_PING =0x14 , +VID_API_EVENT_QMETER =0x15 , +VID_API_EVENT_STR_FMT_CHANGE =0x16 , +VID_API_EVENT_FIRMWARE_XCPT =0x17 , +VID_API_EVENT_START_DONE =0x18 , +VID_API_EVENT_STOPPED =0x19 , +VID_API_EVENT_ABORT_DONE =0x1A , +VID_API_EVENT_FINISHED =0x1B , +VID_API_EVENT_DBG_STAT_UPDATE =0x1C , +VID_API_EVENT_DBG_LOG_STARTED =0x1D , +VID_API_EVENT_DBG_LOG_STOPPED =0x1E , +VID_API_EVENT_DBG_LOG_UPDATED =0x1F , +VID_API_EVENT_DBG_MSG_DEC =0x20 , +VID_API_EVENT_DEC_SC_ERR =0x21 , +VID_API_EVENT_CQ_FIFO_DUMP =0x22 , +VID_API_EVENT_DBG_FIFO_DUMP =0x23 , +VID_API_EVENT_DEC_CHECK_RES =0x24 , +VID_API_EVENT_DEC_CFG_INFO =0x25 , +VID_API_EVENT_UNSUPPORTED_STREAM =0x26 , +VID_API_EVENT_STR_SUSPENDED =0x30 , +VID_API_EVENT_SNAPSHOT_DONE =0x40 , +VID_API_EVENT_FW_STATUS =0xF0 , +VID_API_EVENT_INVALID =0xFF +}; + +struct vpu_malone_buffer_desc { +struct vpu_rpc_buffer_desc buffer; +u32 low; +u32 high; +}; + +struct vpu_malone_str_buffer { +u32 wptr; +u32 rptr; +u32 start; +u32 end; +u32 lwm; +}; + +struct vpu_malone_picth_info { +u32 frame_pitch; +}; + +struct vpu_malone_table_desc { +u32 array_base; +u32 size; +}; + +struct vpu_malone_dbglog_desc { +u32 addr; +u32 size; +u32 level; +u32 reserved; +}; + +struct vpu_malone_frame_buffer { +u32 addr; +u32 size; +}; + +struct vpu_malone_udata { +u32 base; +u32 total_size; +u32 slot_size; +}; + +struct vpu_malone_buffer_info { +u32 stream_input_mode; +u32 stream_pic_input_count; +u32 stream_pic_parsed_count; +u32 stream_buffer_threshold; +u32 stream_pic_end_flag; +}; + +struct vpu_malone_encrypt_info { +u32 rec4key[8 ]; +u32 obfusc; +}; + +struct malone_iface { +u32 exec_base_addr; +u32 exec_area_size; +struct vpu_malone_buffer_desc cmd_buffer_desc; +struct vpu_malone_buffer_desc msg_buffer_desc; +u32 cmd_int_enable[VID_API_NUM_STREAMS ]; +struct vpu_malone_picth_info stream_pitch_info[VID_API_NUM_STREAMS ]; +u32 stream_config[VID_API_NUM_STREAMS ]; +struct vpu_malone_table_desc codec_param_tab_desc; +struct vpu_malone_table_desc jpeg_param_tab_desc; +u32 stream_buffer_desc[VID_API_NUM_STREAMS ][VID_API_MAX_BUF_PER_STR ]; +struct vpu_malone_table_desc seq_info_tab_desc; +struct vpu_malone_table_desc pic_info_tab_desc; +struct vpu_malone_table_desc gop_info_tab_desc; +struct vpu_malone_table_desc qmeter_info_tab_desc; +u32 stream_error[VID_API_NUM_STREAMS ]; +u32 fw_version; +u32 fw_offset; +u32 max_streams; +struct vpu_malone_dbglog_desc dbglog_desc; +struct vpu_rpc_buffer_desc api_cmd_buffer_desc[VID_API_NUM_STREAMS ]; +struct vpu_malone_udata udata_buffer[VID_API_NUM_STREAMS ]; +struct vpu_malone_buffer_desc debug_buffer_desc; +struct vpu_malone_buffer_desc eng_access_buff_desc[VID_API_NUM_STREAMS ]; +u32 encrypt_info[VID_API_NUM_STREAMS ]; +struct vpu_rpc_system_config system_cfg; +u32 api_version; +struct vpu_malone_buffer_info stream_buff_info[VID_API_NUM_STREAMS ]; +}; + +struct malone_jpg_params { +u32 rotation_angle; +u32 horiz_scale_factor; +u32 vert_scale_factor; +u32 rotation_mode; +u32 rgb_mode; +u32 chunk_mode;/* 0 ~ 1 */ +u32 last_chunk;/* 0 ~ 1 */ +u32 chunk_rows;/* 0 ~ 255 */ +u32 num_bytes; +u32 jpg_crop_x; +u32 jpg_crop_y; +u32 jpg_crop_width; +u32 jpg_crop_height; +u32 jpg_mjpeg_mode; +u32 jpg_mjpeg_interlaced; +}; + +struct malone_codec_params { +u32 disp_imm; +u32 fourcc; +u32 codec_version; +u32 frame_rate; +u32 dbglog_enable; +u32 bsdma_lwm; +u32 bbd_coring; +u32 bbd_s_thr_row; +u32 bbd_p_thr_row; +u32 bbd_s_thr_logo_row; +u32 bbd_p_thr_logo_row; +u32 bbd_s_thr_col; +u32 bbd_p_thr_col; +u32 bbd_chr_thr_row; +u32 bbd_chr_thr_col; +u32 bbd_uv_mid_level; +u32 bbd_excl_win_mb_left; +u32 bbd_excl_win_mb_right; +}; + +struct malone_padding_scode { +u32 scode_type; +u32 pixelformat; +u32 data[2 ]; +}; + +struct malone_fmt_mapping { +u32 pixelformat; +enum vpu_malone_format malone_format; +}; + +struct malone_scode_t { +struct vpu_inst *inst; +struct vb2_buffer *vb; +u32 wptr; +u32 need_data; +}; + +struct malone_scode_handler { +u32 pixelformat; +int (*insert_scode_seq)(struct malone_scode_t *scode); +int (*insert_scode_pic)(struct malone_scode_t *scode); +}; + +struct vpu_dec_ctrl { +struct malone_codec_params *codec_param; +struct malone_jpg_params *jpg; +void *seq_mem; +void *pic_mem; +void *gop_mem; +void *qmeter_mem; +void *dbglog_mem; +struct vpu_malone_str_buffer *str_buf[VID_API_NUM_STREAMS ]; +u32 buf_addr[VID_API_NUM_STREAMS ]; +}; + +u32 vpu_malone_get_data_size (void ) +{ +return sizeof (struct vpu_dec_ctrl ); +} + +void vpu_malone_init_rpc (struct vpu_shared_addr *shared, +struct vpu_buffer *rpc,dma_addr_t boot_addr) +{ +struct malone_iface *iface; +struct vpu_dec_ctrl *hc; +unsigned long base_phy_addr; +unsigned long phy_addr; +unsigned long offset; +unsigned int i; + +WARN_ON (!shared || !shared->priv); +WARN_ON (!rpc || !rpc->phys || !rpc->length || rpc->phys < boot_addr); + + iface = rpc->virt; + base_phy_addr = rpc->phys - boot_addr; + hc = shared->priv; + + shared->iface = iface; + shared->boot_addr = boot_addr; + + iface->exec_base_addr = base_phy_addr; + iface->exec_area_size = rpc->length; + + offset =sizeof (struct malone_iface ); + phy_addr = base_phy_addr + offset; + + shared->cmd_desc = &iface->cmd_buffer_desc.buffer; + shared->cmd_mem_vir = rpc->virt + offset; + iface->cmd_buffer_desc.buffer.start = + iface->cmd_buffer_desc.buffer.rptr = + iface->cmd_buffer_desc.buffer.wptr = phy_addr; + iface->cmd_buffer_desc.buffer.end = iface->cmd_buffer_desc.buffer.start +CMD_SIZE ; + offset +=CMD_SIZE ; + phy_addr = base_phy_addr + offset; + + shared->msg_desc = &iface->msg_buffer_desc.buffer; + shared->msg_mem_vir = rpc->virt + offset; + iface->msg_buffer_desc.buffer.start = + iface->msg_buffer_desc.buffer.wptr = + iface->msg_buffer_desc.buffer.rptr = phy_addr; + iface->msg_buffer_desc.buffer.end = iface->msg_buffer_desc.buffer.start +MSG_SIZE ; + offset +=MSG_SIZE ; + phy_addr = base_phy_addr + offset; + + iface->codec_param_tab_desc.array_base = phy_addr; + hc->codec_param = rpc->virt + offset; + offset +=CODEC_SIZE ; + phy_addr = base_phy_addr + offset; + + iface->jpeg_param_tab_desc.array_base = phy_addr; + hc->jpg = rpc->virt + offset; + offset +=JPEG_SIZE ; + phy_addr = base_phy_addr + offset; + + iface->seq_info_tab_desc.array_base = phy_addr; + hc->seq_mem = rpc->virt + offset; + offset +=SEQ_SIZE ; + phy_addr = base_phy_addr + offset; + + iface->pic_info_tab_desc.array_base = phy_addr; + hc->pic_mem = rpc->virt + offset; + offset +=PIC_SIZE ; + phy_addr = base_phy_addr + offset; + + iface->gop_info_tab_desc.array_base = phy_addr; + hc->gop_mem = rpc->virt + offset; + offset +=GOP_SIZE ; + phy_addr = base_phy_addr + offset; + + iface->qmeter_info_tab_desc.array_base = phy_addr; + hc->qmeter_mem = rpc->virt + offset; + offset +=QMETER_SIZE ; + phy_addr = base_phy_addr + offset; + + iface->dbglog_desc.addr = phy_addr; + iface->dbglog_desc.size =DBGLOG_SIZE ; + hc->dbglog_mem = rpc->virt + offset; + offset +=DBGLOG_SIZE ; + phy_addr = base_phy_addr + offset; + +for (i =0 ; i <VID_API_NUM_STREAMS ; i++) { + iface->eng_access_buff_desc[i].buffer.start = + iface->eng_access_buff_desc[i].buffer.wptr = + iface->eng_access_buff_desc[i].buffer.rptr = phy_addr; + iface->eng_access_buff_desc[i].buffer.end = + iface->eng_access_buff_desc[i].buffer.start +ENG_SIZE ; + offset +=ENG_SIZE ; + phy_addr = base_phy_addr + offset; + } + +for (i =0 ; i <VID_API_NUM_STREAMS ; i++) { + iface->encrypt_info[i] = phy_addr; + offset +=sizeof (struct vpu_malone_encrypt_info ); + phy_addr = base_phy_addr + offset; + } + + rpc->bytesused = offset; +} + +void vpu_malone_set_log_buf (struct vpu_shared_addr *shared, +struct vpu_buffer *log) +{ +struct malone_iface *iface; + +WARN_ON (!shared || !log || !log->phys); +vpu_dbg (LVL_DEBUG ,"set log area <0x%llx, 0x%x> (0x%lx)\n" , + log->phys, log->length, shared->boot_addr); + iface = shared->iface; + iface->debug_buffer_desc.buffer.start = + iface->debug_buffer_desc.buffer.wptr = + iface->debug_buffer_desc.buffer.rptr = log->phys - shared->boot_addr; + iface->debug_buffer_desc.buffer.end = iface->debug_buffer_desc.buffer.start + log->length; +} + +static u32 get_str_buffer_offset (u32 instance) +{ +return DEC_MFD_XREG_SLV_BASE +MFD_MCX +MFD_MCX_OFF * instance; +} + +void vpu_malone_set_system_cfg (struct vpu_shared_addr *shared, +u32 regs_base,void __iomem *regs,u32 core_id) +{ +struct malone_iface *iface; +struct vpu_rpc_system_config *config; +struct vpu_dec_ctrl *hc; +int i; + +WARN_ON (!shared || !shared->iface || !shared->core || !shared->priv); + + iface = shared->iface; + config = &iface->system_cfg; + hc = shared->priv; + +vpu_imx8q_set_system_cfg_common (config, regs_base, core_id); +for (i =0 ; i <VID_API_NUM_STREAMS ; i++) { +u32 offset =get_str_buffer_offset (i); + + hc->buf_addr[i] = regs_base + offset; + hc->str_buf[i] = regs + offset; + } +} + +u32 vpu_malone_get_version (struct vpu_shared_addr *shared) +{ +struct malone_iface *iface; + +WARN_ON (!shared || !shared->iface); + + iface = shared->iface; +return iface->fw_version; +} + +int vpu_malone_get_stream_buffer_size (struct vpu_shared_addr *shared) +{ +return 0xc00000 ; +} + +int vpu_malone_config_stream_buffer (struct vpu_shared_addr *shared, +u32 instance, +struct vpu_buffer *buf) +{ +struct malone_iface *iface; +struct vpu_dec_ctrl *hc; +struct vpu_malone_str_buffer *str_buf; + +WARN_ON (!shared || !shared->iface || !shared->core || !shared->priv); + + iface = shared->iface; + hc = shared->priv; + str_buf = hc->str_buf[instance]; + str_buf->wptr = str_buf->rptr = str_buf->start = buf->phys; + str_buf->end = buf->phys + buf->length; + str_buf->lwm =0x1 ; + + iface->stream_buffer_desc[instance][0 ] = hc->buf_addr[instance]; + +return 0 ; +} + +int vpu_malone_get_stream_buffer_desc (struct vpu_shared_addr *shared, +u32 instance,struct vpu_rpc_buffer_desc *desc) +{ +struct vpu_dec_ctrl *hc; +struct vpu_malone_str_buffer *str_buf; + +WARN_ON (!shared || !shared->iface || !shared->core || !shared->priv); + + hc = shared->priv; + str_buf = hc->str_buf[instance]; + +if (desc) { + desc->wptr = str_buf->wptr; + desc->rptr = str_buf->rptr; + desc->start = str_buf->start; + desc->end = str_buf->end; + } + +return 0 ; +} + +static void vpu_malone_update_wptr (struct vpu_malone_str_buffer *str_buf, +u32 wptr) +{ +u32 size = str_buf->end - str_buf->start; +u32 space = (str_buf->rptr + size - str_buf->wptr) % size; +u32 step = (wptr + size - str_buf->wptr) % size; + +if (space && step > space) +vpu_err ("update wptr from 0x%x to 0x%x, cross over rptr 0x%x\n" , + str_buf->wptr, wptr, str_buf->rptr); + +/*update wptr after data is written*/ +mb (); + str_buf->wptr = wptr; +} + +static void vpu_malone_update_rptr (struct vpu_malone_str_buffer *str_buf, +u32 rptr) +{ +u32 size = str_buf->end - str_buf->start; +u32 space = (str_buf->wptr + size - str_buf->rptr) % size; +u32 step = (rptr + size - str_buf->rptr) % size; + +if (step > space) +vpu_err ("update rptr from 0x%x to 0x%x, cross over wptr 0x%x\n" , + str_buf->rptr, rptr, str_buf->wptr); +/*update rptr after data is read*/ +mb (); + str_buf->rptr = rptr; +} + +int vpu_malone_update_stream_buffer (struct vpu_shared_addr *shared, +u32 instance,u32 ptr,bool write) +{ +struct vpu_dec_ctrl *hc; +struct vpu_malone_str_buffer *str_buf; + +WARN_ON (!shared || !shared->iface || !shared->core || !shared->priv); + + hc = shared->priv; + str_buf = hc->str_buf[instance]; + +if (write) +vpu_malone_update_wptr (str_buf, ptr); +else +vpu_malone_update_rptr (str_buf, ptr); + +return 0 ; +} + +static struct malone_fmt_mapping fmt_mappings[] = { + {V4L2_PIX_FMT_H264 ,MALONE_FMT_AVC }, + {V4L2_PIX_FMT_H264_MVC ,MALONE_FMT_AVC }, + {V4L2_PIX_FMT_HEVC ,MALONE_FMT_HEVC }, + {V4L2_PIX_FMT_VC1_ANNEX_G ,MALONE_FMT_VC1 }, + {V4L2_PIX_FMT_VC1_ANNEX_L ,MALONE_FMT_VC1 }, + {V4L2_PIX_FMT_MPEG2 ,MALONE_FMT_MP2 }, + {V4L2_PIX_FMT_MPEG4 ,MALONE_FMT_ASP }, + {V4L2_PIX_FMT_XVID ,MALONE_FMT_ASP }, + {V4L2_PIX_FMT_H263 ,MALONE_FMT_ASP }, + {V4L2_PIX_FMT_JPEG ,MALONE_FMT_JPG }, + {V4L2_PIX_FMT_VP8 ,MALONE_FMT_VP8 }, +}; + +static enum vpu_malone_format vpu_malone_format_remap (u32 pixelformat) +{ +u32 i; + +for (i =0 ; i <ARRAY_SIZE (fmt_mappings); i++) { +if (pixelformat == fmt_mappings[i].pixelformat) +return fmt_mappings[i].malone_format; + } + +return MALONE_FMT_NULL ; +} + +static void vpu_malone_set_stream_cfg (struct vpu_shared_addr *shared, +u32 instance,enum vpu_malone_format malone_format) +{ +struct malone_iface *iface; +u32 *curr_str_cfg; + + iface = shared->iface; + curr_str_cfg = &iface->stream_config[instance]; + + *curr_str_cfg =0 ; +STREAM_CONFIG_FORMAT_SET (malone_format, curr_str_cfg); +STREAM_CONFIG_STRBUFIDX_SET (0 , curr_str_cfg); +STREAM_CONFIG_NOSEQ_SET (0 , curr_str_cfg); +STREAM_CONFIG_DEBLOCK_SET (0 , curr_str_cfg); +STREAM_CONFIG_DERING_SET (0 , curr_str_cfg); +STREAM_CONFIG_PLAY_MODE_SET (0x3 , curr_str_cfg); +STREAM_CONFIG_FS_CTRL_MODE_SET (0x1 , curr_str_cfg); +STREAM_CONFIG_ENABLE_DCP_SET (1 , curr_str_cfg); +STREAM_CONFIG_NUM_STR_BUF_SET (1 , curr_str_cfg); +STREAM_CONFIG_MALONE_USAGE_SET (1 , curr_str_cfg); +STREAM_CONFIG_MULTI_VID_SET (0 , curr_str_cfg); +STREAM_CONFIG_OBFUSC_EN_SET (0 , curr_str_cfg); +STREAM_CONFIG_RC4_EN_SET (0 , curr_str_cfg); +STREAM_CONFIG_MCX_SET (1 , curr_str_cfg); +STREAM_CONFIG_PES_SET (0 , curr_str_cfg); +STREAM_CONFIG_NUM_DBE_SET (1 , curr_str_cfg); +} + +static int vpu_malone_set_params (struct vpu_shared_addr *shared, +u32 instance,struct vpu_decode_params *params) +{ +struct malone_iface *iface; +struct vpu_dec_ctrl *hc; +enum vpu_malone_format malone_format; + + iface = shared->iface; + hc = shared->priv; + malone_format =vpu_malone_format_remap (params->codec_format); + iface->udata_buffer[instance].base = params->udata.base; + iface->udata_buffer[instance].slot_size = params->udata.size; + +vpu_malone_set_stream_cfg (shared, instance, malone_format); + +if (malone_format ==MALONE_FMT_JPG ) { +//1:JPGD_MJPEG_MODE_A; 2:JPGD_MJPEG_MODE_B + hc->jpg[instance].jpg_mjpeg_mode =1 ; +//0: JPGD_MJPEG_PROGRESSIVE + hc->jpg[instance].jpg_mjpeg_interlaced =0 ; + } + + hc->codec_param[instance].disp_imm = params->b_dis_reorder ?1 :0 ; + hc->codec_param[instance].dbglog_enable =0 ; + iface->dbglog_desc.level =0 ; + +if (params->b_non_frame) + iface->stream_buff_info[instance].stream_input_mode =NON_FRAME_LVL ; +else + iface->stream_buff_info[instance].stream_input_mode =FRAME_LVL ; + iface->stream_buff_info[instance].stream_buffer_threshold =0 ; + iface->stream_buff_info[instance].stream_pic_input_count =0 ; + +return 0 ; +} + +static bool vpu_malone_is_non_frame_mode (struct vpu_shared_addr *shared, +u32 instance) +{ +struct malone_iface *iface; + + iface = shared->iface; +if (iface->stream_buff_info[instance].stream_input_mode ==NON_FRAME_LVL ) +return true; + +return false; +} + +static int vpu_malone_update_params (struct vpu_shared_addr *shared, +u32 instance,struct vpu_decode_params *params) +{ +struct malone_iface *iface; + + iface = shared->iface; + +if (params->end_flag) + iface->stream_buff_info[instance].stream_pic_end_flag = params->end_flag; + params->end_flag =0 ; + +return 0 ; +} + +int vpu_malone_set_decode_params (struct vpu_shared_addr *shared, +u32 instance,struct vpu_decode_params *params,u32 update) +{ +if (!params) +return -EINVAL ; + +if (!update) +return vpu_malone_set_params (shared, instance, params); +else +return vpu_malone_update_params (shared, instance, params); +} + +static struct vpu_pair malone_cmds[] = { + {VPU_CMD_ID_START ,VID_API_CMD_START }, + {VPU_CMD_ID_STOP ,VID_API_CMD_STOP }, + {VPU_CMD_ID_ABORT ,VID_API_CMD_ABORT }, + {VPU_CMD_ID_RST_BUF ,VID_API_CMD_RST_BUF }, + {VPU_CMD_ID_SNAPSHOT ,VID_API_CMD_SNAPSHOT }, + {VPU_CMD_ID_FIRM_RESET ,VID_API_CMD_FIRM_RESET }, + {VPU_CMD_ID_FS_ALLOC ,VID_API_CMD_FS_ALLOC }, + {VPU_CMD_ID_FS_RELEASE ,VID_API_CMD_FS_RELEASE }, + {VPU_CMD_ID_TIMESTAMP ,VID_API_CMD_TS }, + {VPU_CMD_ID_DEBUG ,VID_API_CMD_FW_STATUS }, +}; + +static struct vpu_pair malone_msgs[] = { + {VPU_MSG_ID_RESET_DONE ,VID_API_EVENT_RESET_DONE }, + {VPU_MSG_ID_START_DONE ,VID_API_EVENT_START_DONE }, + {VPU_MSG_ID_STOP_DONE ,VID_API_EVENT_STOPPED }, + {VPU_MSG_ID_ABORT_DONE ,VID_API_EVENT_ABORT_DONE }, + {VPU_MSG_ID_BUF_RST ,VID_API_EVENT_STR_BUF_RST }, + {VPU_MSG_ID_PIC_EOS ,VID_API_EVENT_FINISHED }, + {VPU_MSG_ID_SEQ_HDR_FOUND ,VID_API_EVENT_SEQ_HDR_FOUND }, + {VPU_MSG_ID_RES_CHANGE ,VID_API_EVENT_RES_CHANGE }, + {VPU_MSG_ID_PIC_HDR_FOUND ,VID_API_EVENT_PIC_HDR_FOUND }, + {VPU_MSG_ID_PIC_DECODED ,VID_API_EVENT_PIC_DECODED }, + {VPU_MSG_ID_DEC_DONE ,VID_API_EVENT_FRAME_BUFF_RDY }, + {VPU_MSG_ID_FRAME_REQ ,VID_API_EVENT_REQ_FRAME_BUFF }, + {VPU_MSG_ID_FRAME_RELEASE ,VID_API_EVENT_REL_FRAME_BUFF }, + {VPU_MSG_ID_FIFO_LOW ,VID_API_EVENT_FIFO_LOW }, + {VPU_MSG_ID_BS_ERROR ,VID_API_EVENT_BS_ERROR }, + {VPU_MSG_ID_UNSUPPORTED ,VID_API_EVENT_UNSUPPORTED_STREAM }, + {VPU_MSG_ID_FIRMWARE_XCPT ,VID_API_EVENT_FIRMWARE_XCPT }, +}; + +static void vpu_malone_pack_fs_alloc (struct vpu_rpc_event *pkt, +struct vpu_fs_info *fs) +{ +const u32 fs_type[] = { + [MEM_RES_FRAME ] =0 , + [MEM_RES_MBI ] =1 , + [MEM_RES_DCP ] =2 , + }; + + pkt->hdr.num =7 ; + pkt->data[0 ] = fs->id | (fs->tag <<24 ); + pkt->data[1 ] = fs->luma_addr; +if (fs->type ==MEM_RES_FRAME ) { +/* +* if luma_addr equal to chroma_addr, +* means luma(plane[0]) and chromau(plane[1]) used the +* same fd -- usage of NXP codec2. Need to manually +* offset chroma addr. +*/ +if (fs->luma_addr == fs->chroma_addr) + fs->chroma_addr = fs->luma_addr + fs->luma_size; + pkt->data[2 ] = fs->luma_addr + fs->luma_size /2 ; + pkt->data[3 ] = fs->chroma_addr; + pkt->data[4 ] = fs->chroma_addr + fs->chromau_size /2 ; + pkt->data[5 ] = fs->bytesperline; + }else { + pkt->data[2 ] = fs->luma_size; + pkt->data[3 ] =0 ; + pkt->data[4 ] =0 ; + pkt->data[5 ] =0 ; + } + pkt->data[6 ] = fs_type[fs->type]; +} + +static void vpu_malone_pack_fs_release (struct vpu_rpc_event *pkt, +struct vpu_fs_info *fs) +{ + pkt->hdr.num =1 ; + pkt->data[0 ] = fs->id | (fs->tag <<24 ); +} + +static void vpu_malone_pack_timestamp (struct vpu_rpc_event *pkt, +struct vpu_ts_info *info) +{ + pkt->hdr.num =3 ; +if (info->timestamp <0 ) { + pkt->data[0 ] = (u32)-1 ; + pkt->data[1 ] =0 ; + }else { + pkt->data[0 ] = info->timestamp /NSEC_PER_SEC ; + pkt->data[1 ] = info->timestamp %NSEC_PER_SEC ; + } + pkt->data[2 ] = info->size; +} + +int vpu_malone_pack_cmd (struct vpu_rpc_event *pkt,u32 index,u32 id,void *data) +{ +int ret; + +WARN_ON (!pkt); + + ret =vpu_find_dst_by_src (malone_cmds,ARRAY_SIZE (malone_cmds), id); +if (ret <0 ) +return ret; + + pkt->hdr.id = ret; + pkt->hdr.num =0 ; + pkt->hdr.index = index; + +switch (id) { +case VPU_CMD_ID_FS_ALLOC : +vpu_malone_pack_fs_alloc (pkt, data); +break ; +case VPU_CMD_ID_FS_RELEASE : +vpu_malone_pack_fs_release (pkt, data); +break ; +case VPU_CMD_ID_TIMESTAMP : +vpu_malone_pack_timestamp (pkt, data); +break ; + } + + pkt->hdr.index = index; +return 0 ; +} + +int vpu_malone_convert_msg_id (u32 id) +{ +return vpu_find_src_by_dst (malone_msgs,ARRAY_SIZE (malone_msgs), id); +} + +void vpu_malone_init_seq_hdr (struct vpu_dec_codec_info *info) +{ +const u32 align_width =MALONE_ALIGN_W ; +const u32 align_height =MALONE_ALIGN_H ; +u32 width; +u32 height; +u32 bytesperline; +u32 chunks = info->num_dfe_area >>MALONE_DCP_CHUNK_BIT ; + + width =ALIGN (info->decoded_width, align_width); + height =ALIGN (info->decoded_height, align_height); +if (!info->progressive) + height =ALIGN (info->decoded_height, align_height *2 ); + + bytesperline =DIV_ROUND_UP ((width * info->bit_depth_luma),BITS_PER_BYTE ); + bytesperline =ALIGN (bytesperline,MALONE_ALIGN_LINE ); + + info->bytesperline[0 ] = bytesperline; + info->bytesperline[1 ] = bytesperline; + info->sizeimage[0 ] = bytesperline * height; + info->sizeimage[1 ] = (bytesperline * height) >>1 ; + info->mbi_size = (info->sizeimage[0 ] + info->sizeimage[1 ]) >>2 ; + info->mbi_size =ALIGN (info->mbi_size,MALONE_ALIGN_MBI ); + + info->dcp_size =MALONE_DCP_SIZE_MAX ; +if (chunks) { +u32 mb_num; +u32 mb_w; +u32 mb_h; + + mb_w =DIV_ROUND_UP (info->decoded_width,16 ); + mb_h =DIV_ROUND_UP (info->decoded_height,16 ); + mb_num = mb_w * mb_h; + info->dcp_size = mb_num *MALONE_DCP_FIXED_MB_ALLOC * chunks; + info->dcp_size =clamp_t (u32, info->dcp_size, +MALONE_DCP_SIZE_MIN ,MALONE_DCP_SIZE_MAX ); + } + + info->decoded_width = width; + info->decoded_height = height; +} + +static void vpu_malone_unpack_seq_hdr (struct vpu_rpc_event *pkt, +struct vpu_dec_codec_info *info) +{ + info->num_ref_frms = pkt->data[0 ]; + info->num_dpb_frms = pkt->data[1 ]; + info->num_dfe_area = pkt->data[2 ]; + info->progressive = pkt->data[3 ]; + info->width = pkt->data[5 ]; + info->height = pkt->data[4 ]; + info->decoded_width = pkt->data[12 ]; + info->decoded_height = pkt->data[11 ]; + info->frame_rate = pkt->data[8 ]; + info->dsp_asp_ratio = pkt->data[9 ]; + info->level_idc = pkt->data[10 ]; + info->bit_depth_luma = pkt->data[13 ]; + info->bit_depth_chroma = pkt->data[14 ]; + info->chroma_fmt = pkt->data[15 ]; + info->color_primaries =vpu_color_cvrt_primaries_i2v (pkt->data[16 ]); + info->transfer_chars =vpu_color_cvrt_transfers_i2v (pkt->data[17 ]); + info->matrix_coeffs =vpu_color_cvrt_matrix_i2v (pkt->data[18 ]); + info->full_range =vpu_color_cvrt_full_range_i2v (pkt->data[19 ]); + info->vui_present = pkt->data[20 ]; + info->mvc_num_views = pkt->data[21 ]; + info->offset_x = pkt->data[23 ]; + info->offset_y = pkt->data[25 ]; + info->tag = pkt->data[27 ]; +if (info->bit_depth_luma >8 ) + info->pixfmt =V4L2_PIX_FMT_NT10 ; +else /* fix me: should set to V4L2_PIX_FMT_NT8 for NXP Tiled NV12 Format in future*/ + info->pixfmt =V4L2_PIX_FMT_NV12 ; +vpu_malone_init_seq_hdr (info); +} + +static void vpu_malone_unpack_pic_info (struct vpu_rpc_event *pkt, +struct vpu_dec_pic_info *info) +{ + info->id = pkt->data[7 ]; + info->luma = pkt->data[0 ]; + info->start = pkt->data[10 ]; + info->end = pkt->data[12 ]; + info->pic_size = pkt->data[11 ]; + info->stride = pkt->data[5 ]; + info->consumed_count = pkt->data[13 ]; +if (info->id ==MALONE_SKIPPED_FRAME_ID ) + info->skipped =1 ; +else + info->skipped =0 ; +} + +static void vpu_malone_unpack_req_frame (struct vpu_rpc_event *pkt, +struct vpu_fs_info *info) +{ + info->type = pkt->data[1 ]; +} + +static void vpu_malone_unpack_rel_frame (struct vpu_rpc_event *pkt, +struct vpu_fs_info *info) +{ + info->id = pkt->data[0 ]; + info->type = pkt->data[1 ]; + info->not_displayed = pkt->data[2 ]; +} + +static void vpu_malone_unpack_buff_rdy (struct vpu_rpc_event *pkt, +struct vpu_dec_pic_info *info) +{ + info->id = pkt->data[0 ]; + info->luma = pkt->data[1 ]; + info->stride = pkt->data[3 ]; +if (info->id ==MALONE_SKIPPED_FRAME_ID ) + info->skipped =1 ; +else + info->skipped =0 ; + info->timestamp =MAKE_TIMESTAMP (pkt->data[9 ], pkt->data[10 ]); +} + +int vpu_malone_unpack_msg_data (struct vpu_rpc_event *pkt,void *data) +{ +if (!pkt || !data) +return -EINVAL ; + +switch (pkt->hdr.id) { +case VID_API_EVENT_SEQ_HDR_FOUND : +vpu_malone_unpack_seq_hdr (pkt, data); +break ; +case VID_API_EVENT_PIC_DECODED : +vpu_malone_unpack_pic_info (pkt, data); +break ; +case VID_API_EVENT_REQ_FRAME_BUFF : +vpu_malone_unpack_req_frame (pkt, data); +break ; +case VID_API_EVENT_REL_FRAME_BUFF : +vpu_malone_unpack_rel_frame (pkt, data); +break ; +case VID_API_EVENT_FRAME_BUFF_RDY : +vpu_malone_unpack_buff_rdy (pkt, data); +break ; + } + +return 0 ; +} + +static const struct malone_padding_scode padding_scodes[] = { + {SCODE_PADDING_EOS ,V4L2_PIX_FMT_H264 , {0x0B010000 ,0 }}, + {SCODE_PADDING_EOS ,V4L2_PIX_FMT_H264_MVC , {0x0B010000 ,0 }}, + {SCODE_PADDING_EOS ,V4L2_PIX_FMT_HEVC , {0x4A010000 ,0x20 }}, + {SCODE_PADDING_EOS ,V4L2_PIX_FMT_VC1_ANNEX_G , {0x0a010000 ,0x0 }}, + {SCODE_PADDING_EOS ,V4L2_PIX_FMT_VC1_ANNEX_L , {0x0a010000 ,0x0 }}, + {SCODE_PADDING_EOS ,V4L2_PIX_FMT_MPEG2 , {0xCC010000 ,0x0 }}, + {SCODE_PADDING_EOS ,V4L2_PIX_FMT_MPEG4 , {0xb1010000 ,0x0 }}, + {SCODE_PADDING_EOS ,V4L2_PIX_FMT_XVID , {0xb1010000 ,0x0 }}, + {SCODE_PADDING_EOS ,V4L2_PIX_FMT_H263 , {0xb1010000 ,0x0 }}, + {SCODE_PADDING_EOS ,V4L2_PIX_FMT_VP8 , {0x34010000 ,0x0 }}, + {SCODE_PADDING_EOS ,V4L2_PIX_FMT_JPEG , {0xefff0000 ,0x0 }}, + {SCODE_PADDING_ABORT ,V4L2_PIX_FMT_H264 , {0x0B010000 ,0 }}, + {SCODE_PADDING_ABORT ,V4L2_PIX_FMT_H264_MVC , {0x0B010000 ,0 }}, + {SCODE_PADDING_ABORT ,V4L2_PIX_FMT_HEVC , {0x4A010000 ,0x20 }}, + {SCODE_PADDING_ABORT ,V4L2_PIX_FMT_VC1_ANNEX_G , {0x0a010000 ,0x0 }}, + {SCODE_PADDING_ABORT ,V4L2_PIX_FMT_VC1_ANNEX_L , {0x0a010000 ,0x0 }}, + {SCODE_PADDING_ABORT ,V4L2_PIX_FMT_MPEG2 , {0xb7010000 ,0x0 }}, + {SCODE_PADDING_ABORT ,V4L2_PIX_FMT_MPEG4 , {0xb1010000 ,0x0 }}, + {SCODE_PADDING_ABORT ,V4L2_PIX_FMT_XVID , {0xb1010000 ,0x0 }}, + {SCODE_PADDING_ABORT ,V4L2_PIX_FMT_H263 , {0xb1010000 ,0x0 }}, + {SCODE_PADDING_ABORT ,V4L2_PIX_FMT_VP8 , {0x34010000 ,0x0 }}, + {SCODE_PADDING_EOS ,V4L2_PIX_FMT_JPEG , {0x0 ,0x0 }}, + {SCODE_PADDING_BUFFLUSH ,V4L2_PIX_FMT_H264 , {0x15010000 ,0x0 }}, + {SCODE_PADDING_BUFFLUSH ,V4L2_PIX_FMT_H264_MVC , {0x15010000 ,0x0 }}, +}; +static const struct malone_padding_scode padding_scode_dft = {0x0 ,0x0 }; + +static const struct malone_padding_scode *get_padding_scode (u32 type,u32 fmt) +{ +const struct malone_padding_scode *s; +int i; + +for (i =0 ; i <ARRAY_SIZE (padding_scodes); i++) { + s = &padding_scodes[i]; + +if (s->scode_type == type && s->pixelformat == fmt) +return s; + } + +if (type !=SCODE_PADDING_BUFFLUSH ) +return &padding_scode_dft; + +return NULL ; +} + +static int vpu_malone_add_padding_scode (struct vpu_buffer *stream_buffer, +struct vpu_malone_str_buffer *str_buf, +u32 pixelformat,u32 scode_type) +{ +u32 wptr; +u32 size; +u32 total_size =0 ; +const struct malone_padding_scode *ps; +const u32 padding_size =4096 ; +int ret; + + ps =get_padding_scode (scode_type, pixelformat); +if (!ps) +return -EINVAL ; + + wptr = str_buf->wptr; + size =ALIGN (wptr,4 ) - wptr; +if (size) +vpu_helper_memset_stream_buffer (stream_buffer, &wptr,0 , size); + total_size += size; + + size =sizeof (ps->data); + ret =vpu_helper_copy_to_stream_buffer (stream_buffer, &wptr, size, (void *)ps->data); +if (ret < size) +return -EINVAL ; + total_size += size; + + size = padding_size -sizeof (ps->data); +vpu_helper_memset_stream_buffer (stream_buffer, &wptr,0 , size); + total_size += size; + +vpu_malone_update_wptr (str_buf, wptr); +return total_size; +} + +int vpu_malone_add_scode (struct vpu_shared_addr *shared, +u32 instance, +struct vpu_buffer *stream_buffer, +u32 pixelformat, +u32 scode_type) +{ +struct vpu_dec_ctrl *hc; +struct vpu_malone_str_buffer *str_buf; +int ret = -EINVAL ; + +WARN_ON (!shared || !shared->iface || !shared->core || !shared->priv); + + hc = shared->priv; + str_buf = hc->str_buf[instance]; + +switch (scode_type) { +case SCODE_PADDING_EOS : +case SCODE_PADDING_ABORT : +case SCODE_PADDING_BUFFLUSH : + ret =vpu_malone_add_padding_scode (stream_buffer, + str_buf, pixelformat, scode_type); +break ; +default : +break ; + } + +return ret; +} + +#define MALONE_PAYLOAD_HEADER_SIZE 16 +#define MALONE_CODEC_VERSION_ID 0x1 +#define MALONE_CODEC_ID_VC1_SIMPLE 0x10 +#define MALONE_CODEC_ID_VC1_MAIN 0x11 +#define MALONE_CODEC_ID_ARV8 0x28 +#define MALONE_CODEC_ID_ARV9 0x29 +#define MALONE_CODEC_ID_VP6 0x36 +#define MALONE_CODEC_ID_VP8 0x36 +#define MALONE_CODEC_ID_DIVX3 0x38 +#define MALONE_CODEC_ID_SPK 0x39 + +#define MALONE_VP8_IVF_SEQ_HEADER_LEN 32 +#define MALONE_VP8_IVF_FRAME_HEADER_LEN 8 + +#define MALONE_VC1_RCV_CODEC_V1_VERSION 0x85 +#define MALONE_VC1_RCV_CODEC_V2_VERSION 0xC5 +#define MALONE_VC1_RCV_NUM_FRAMES 0xFF +#define MALONE_VC1_RCV_SEQ_EXT_DATA_SIZE 4 +#define MALONE_VC1_RCV_SEQ_HEADER_LEN 20 +#define MALONE_VC1_RCV_PIC_HEADER_LEN 4 +#define MALONE_VC1_NAL_HEADER_LEN 4 +#define MALONE_VC1_CONTAIN_NAL (data) ((data & 0x00FFFFFF) == 0x00010000) + + +static void set_payload_hdr (u8 *dst,u32 scd_type,u32 codec_id, +u32 buffer_size,u32 width,u32 height) +{ +unsigned int payload_size; +/* payload_size = buffer_size + itself_size(16) - start_code(4) */ + payload_size = buffer_size +12 ; + + dst[0 ] =0x00 ; + dst[1 ] =0x00 ; + dst[2 ] =0x01 ; + dst[3 ] = scd_type; + +/* length */ + dst[4 ] = ((payload_size>>16 )&0xff ); + dst[5 ] = ((payload_size>>8 )&0xff ); + dst[6 ] =0x4e ; + dst[7 ] = ((payload_size>>0 )&0xff ); + +/* Codec ID and Version */ + dst[8 ] = codec_id; + dst[9 ] =MALONE_CODEC_VERSION_ID ; + +/* width */ + dst[10 ] = ((width>>8 )&0xff ); + dst[11 ] = ((width>>0 )&0xff ); + dst[12 ] =0x58 ; + +/* height */ + dst[13 ] = ((height>>8 )&0xff ); + dst[14 ] = ((height>>0 )&0xff ); + dst[15 ] =0x50 ; +} + +static void set_vp8_ivf_seqhdr (u8 *dst,u32 width,u32 height) +{ +/* 0-3byte signature "DKIF" */ + dst[0 ] =0x44 ; + dst[1 ] =0x4b ; + dst[2 ] =0x49 ; + dst[3 ] =0x46 ; +/* 4-5byte version: should be 0*/ + dst[4 ] =0x00 ; + dst[5 ] =0x00 ; +/* 6-7 length of Header */ + dst[6 ] =MALONE_VP8_IVF_SEQ_HEADER_LEN ; + dst[7 ] =MALONE_VP8_IVF_SEQ_HEADER_LEN >>8 ; +/* 8-11 VP8 fourcc */ + dst[8 ] =0x56 ; + dst[9 ] =0x50 ; + dst[10 ] =0x38 ; + dst[11 ] =0x30 ; +/* 12-13 width in pixels */ + dst[12 ] = width; + dst[13 ] = width >>8 ; +/* 14-15 height in pixels */ + dst[14 ] = height; + dst[15 ] = height >>8 ; +/* 16-19 frame rate */ + dst[16 ] =0xe8 ; + dst[17 ] =0x03 ; + dst[18 ] =0x00 ; + dst[19 ] =0x00 ; +/* 20-23 time scale */ + dst[20 ] =0x01 ; + dst[21 ] =0x00 ; + dst[22 ] =0x00 ; + dst[23 ] =0x00 ; +/* 24-27 number frames */ + dst[24 ] =0xdf ; + dst[25 ] =0xf9 ; + dst[26 ] =0x09 ; + dst[27 ] =0x00 ; +/* 28-31 reserved */ +} + +static void set_vp8_ivf_pichdr (u8 *dst,u32 frame_size) +{ +/* +* firmware just parse 64-bit timestamp(8 bytes). +* As not transfer timestamp to firmware, use default value(ZERO). +* No need to do anything here +*/ +} + +static void set_vc1_rcv_seqhdr (u8 *dst,u8 *src,u32 width,u32 height) +{ +u32 frames =MALONE_VC1_RCV_NUM_FRAMES ; +u32 ext_data_size =MALONE_VC1_RCV_SEQ_EXT_DATA_SIZE ; + +/* 0-2 Number of frames, used default value 0xFF */ + dst[0 ] = frames; + dst[1 ] = frames >>8 ; + dst[2 ] = frames >>16 ; + +/* 3 RCV version, used V1 */ + dst[3 ] =MALONE_VC1_RCV_CODEC_V1_VERSION ; + +/* 4-7 extension data size */ + dst[4 ] = ext_data_size; + dst[5 ] = ext_data_size >>8 ; + dst[6 ] = ext_data_size >>16 ; + dst[7 ] = ext_data_size >>24 ; +/* 8-11 extension data */ + dst[8 ] = src[0 ]; + dst[9 ] = src[1 ]; + dst[10 ] = src[2 ]; + dst[11 ] = src[3 ]; + +/* height */ + dst[12 ] = height; + dst[13 ] = (height >>8 ) &0xff ; + dst[14 ] = (height >>16 ) &0xff ; + dst[15 ] = (height >>24 ) &0xff ; +/* width */ + dst[16 ] = width; + dst[17 ] = (width >>8 ) &0xff ; + dst[18 ] = (width >>16 ) &0xff ; + dst[19 ] = (width >>24 ) &0xff ; +} + +static void set_vc1_rcv_pichdr (u8 *dst,u32 buffer_size) +{ + dst[0 ] = buffer_size; + dst[1 ] = buffer_size >>8 ; + dst[2 ] = buffer_size >>16 ; + dst[3 ] = buffer_size >>24 ; +} + +static void create_vc1_nal_pichdr (u8 *dst) +{ +/* need insert nal header: special ID */ + dst[0 ] =0x0 ; + dst[1 ] =0x0 ; + dst[2 ] =0x01 ; + dst[3 ] =0x0D ; +} + +static int vpu_malone_insert_scode_seq (struct malone_scode_t *scode,u32 codec_id,u32 ext_size) +{ +u8 hdr[MALONE_PAYLOAD_HEADER_SIZE ]; +int ret; + +set_payload_hdr (hdr, +SCODE_SEQUENCE , + codec_id, + ext_size, + scode->inst->out_format.width, + scode->inst->out_format.height); + ret =vpu_helper_copy_to_stream_buffer (&scode->inst->stream_buffer, + &scode->wptr, +sizeof (hdr), + hdr); +return ret; +} + +static int vpu_malone_insert_scode_pic (struct malone_scode_t *scode,u32 codec_id,u32 ext_size) +{ +u8 hdr[MALONE_PAYLOAD_HEADER_SIZE ]; +int ret; + +set_payload_hdr (hdr, +SCODE_PICTURE , + codec_id, + ext_size +vb2_get_plane_payload (scode->vb,0 ), + scode->inst->out_format.width, + scode->inst->out_format.height); + ret =vpu_helper_copy_to_stream_buffer (&scode->inst->stream_buffer, + &scode->wptr, +sizeof (hdr), + hdr); +return 0 ; +} + +static int vpu_malone_insert_scode_vc1_g_pic (struct malone_scode_t *scode) +{ +struct vb2_v4l2_buffer *vbuf; +u8 nal_hdr[MALONE_VC1_NAL_HEADER_LEN ]; +u32 *data =NULL ; + + vbuf =to_vb2_v4l2_buffer (scode->vb); + data =vb2_plane_vaddr (scode->vb,0 ); + +if (vbuf->sequence ==0 || (vbuf->flags &V4L2_BUF_FLAG_CODECCONFIG )) +return 0 ; +if (MALONE_VC1_CONTAIN_NAL (*data)) +return 0 ; + +create_vc1_nal_pichdr (nal_hdr); +return vpu_helper_copy_to_stream_buffer (&scode->inst->stream_buffer, + &scode->wptr, +sizeof (nal_hdr), + nal_hdr); +} + +static int vpu_malone_insert_scode_vc1_l_seq (struct malone_scode_t *scode) +{ +int ret; +int size =0 ; +u8 rcv_seqhdr[MALONE_VC1_RCV_SEQ_HEADER_LEN ]; + + scode->need_data =0 ; + + ret =vpu_malone_insert_scode_seq (scode,MALONE_CODEC_ID_VC1_SIMPLE , +sizeof (rcv_seqhdr)); +if (ret <0 ) +return ret; + size = ret; + +set_vc1_rcv_seqhdr (rcv_seqhdr, +vb2_plane_vaddr (scode->vb,0 ), + scode->inst->out_format.width, + scode->inst->out_format.height); + ret =vpu_helper_copy_to_stream_buffer (&scode->inst->stream_buffer, + &scode->wptr, +sizeof (rcv_seqhdr), + rcv_seqhdr); + +if (ret <0 ) +return ret; + size += ret; +return size; +} + +static int vpu_malone_insert_scode_vc1_l_pic (struct malone_scode_t *scode) +{ +int ret; +int size =0 ; +u8 rcv_pichdr[MALONE_VC1_RCV_PIC_HEADER_LEN ]; + + ret =vpu_malone_insert_scode_pic (scode,MALONE_CODEC_ID_VC1_SIMPLE , +sizeof (rcv_pichdr)); +if (ret <0 ) +return ret; + size = ret; + +set_vc1_rcv_pichdr (rcv_pichdr,vb2_get_plane_payload (scode->vb,0 )); + ret =vpu_helper_copy_to_stream_buffer (&scode->inst->stream_buffer, + &scode->wptr, +sizeof (rcv_pichdr), + rcv_pichdr); +if (ret <0 ) +return ret; + size += ret; +return size; +} + +static int vpu_malone_insert_scode_vp8_seq (struct malone_scode_t *scode) +{ +int ret; +int size =0 ; +u8 ivf_hdr[MALONE_VP8_IVF_SEQ_HEADER_LEN ]; + + ret =vpu_malone_insert_scode_seq (scode,MALONE_CODEC_ID_VP8 ,sizeof (ivf_hdr)); +if (ret <0 ) +return ret; + size = ret; + +set_vp8_ivf_seqhdr (ivf_hdr, + scode->inst->out_format.width, + scode->inst->out_format.height); + ret =vpu_helper_copy_to_stream_buffer (&scode->inst->stream_buffer, + &scode->wptr, +sizeof (ivf_hdr), + ivf_hdr); +if (ret <0 ) +return ret; + size += ret; + +return size; +} + +static int vpu_malone_insert_scode_vp8_pic (struct malone_scode_t *scode) +{ +int ret; +int size =0 ; +u8 ivf_hdr[MALONE_VP8_IVF_FRAME_HEADER_LEN ] = {0 }; + + ret =vpu_malone_insert_scode_pic (scode,MALONE_CODEC_ID_VP8 ,sizeof (ivf_hdr)); +if (ret <0 ) +return ret; + size = ret; + +set_vp8_ivf_pichdr (ivf_hdr,vb2_get_plane_payload (scode->vb,0 )); + ret =vpu_helper_copy_to_stream_buffer (&scode->inst->stream_buffer, + &scode->wptr, +sizeof (ivf_hdr), + ivf_hdr); +if (ret <0 ) +return ret; + size += ret; + +return size; +} + +static const struct malone_scode_handler scode_handlers[] = { + { +/* fix me, need to swap return operation after gstreamer swap */ + .pixelformat =V4L2_PIX_FMT_VC1_ANNEX_L , + .insert_scode_seq = vpu_malone_insert_scode_vc1_l_seq, + .insert_scode_pic = vpu_malone_insert_scode_vc1_l_pic, + }, + { + .pixelformat =V4L2_PIX_FMT_VC1_ANNEX_G , + .insert_scode_pic = vpu_malone_insert_scode_vc1_g_pic, + }, + { + .pixelformat =V4L2_PIX_FMT_VP8 , + .insert_scode_seq = vpu_malone_insert_scode_vp8_seq, + .insert_scode_pic = vpu_malone_insert_scode_vp8_pic, + }, +}; + +const struct malone_scode_handler *get_scode_handler (u32 pixelformat) +{ +int i; + +for (i =0 ; i <ARRAY_SIZE (scode_handlers); i++) { +if (scode_handlers[i].pixelformat == pixelformat) +return &scode_handlers[i]; + } + +return NULL ; +} + +static int vpu_malone_insert_scode (struct malone_scode_t *scode,u32 type) +{ +const struct malone_scode_handler *handler; +int ret =0 ; + +if (!scode || !scode->inst || !scode->vb) +return 0 ; + + scode->need_data =1 ; + handler =get_scode_handler (scode->inst->out_format.pixfmt); +if (!handler) +return 0 ; + +switch (type) { +case SCODE_SEQUENCE : +if (handler->insert_scode_seq) + ret = handler->insert_scode_seq (scode); +break ; +case SCODE_PICTURE : +if (handler->insert_scode_pic) + ret = handler->insert_scode_pic (scode); +break ; +default : +break ; + } + +return ret; +} + +static int vpu_malone_input_frame_data (struct vpu_malone_str_buffer *str_buf, +struct vpu_inst *inst,struct vb2_buffer *vb, +u32 disp_imm) +{ +struct malone_scode_t scode; +struct vb2_v4l2_buffer *vbuf; +u32 wptr; +int size =0 ; +int ret =0 ; + + wptr = str_buf->wptr; + +/*add scode: SCODE_SEQUENCE, SCODE_PICTURE, SCODE_SLICE*/ + vbuf =to_vb2_v4l2_buffer (vb); + scode.inst = inst; + scode.vb = vb; + scode.wptr = wptr; + scode.need_data =1 ; +if (vbuf->sequence ==0 || (vbuf->flags &V4L2_BUF_FLAG_CODECCONFIG )) + ret =vpu_malone_insert_scode (&scode,SCODE_SEQUENCE ); + +if (ret <0 ) +return -ENOMEM ; + size += ret; + wptr = scode.wptr; +if (!scode.need_data) { +vpu_malone_update_wptr (str_buf, wptr); +return size; + } + + ret =vpu_malone_insert_scode (&scode,SCODE_PICTURE ); +if (ret <0 ) +return -ENOMEM ; + size += ret; + wptr = scode.wptr; + + ret =vpu_helper_copy_to_stream_buffer (&inst->stream_buffer, + &wptr, +vb2_get_plane_payload (vb,0 ), +vb2_plane_vaddr (vb,0 )); +if (ret <vb2_get_plane_payload (vb,0 )) +return -ENOMEM ; + size += ret; + +vpu_malone_update_wptr (str_buf, wptr); + +if (disp_imm && !(vbuf->flags &V4L2_BUF_FLAG_CODECCONFIG )) { + ret =vpu_malone_add_scode (inst->core->iface, + inst->id, + &inst->stream_buffer, + inst->out_format.pixfmt, +SCODE_PADDING_BUFFLUSH ); +if (ret <0 ) +return ret; + size += ret; + } + +return size; +} + +static int vpu_malone_input_stream_data (struct vpu_malone_str_buffer *str_buf, +struct vpu_inst *inst,struct vb2_buffer *vb) +{ +struct vb2_v4l2_buffer *vbuf; +u32 wptr; +int ret =0 ; + + wptr = str_buf->wptr; + vbuf =to_vb2_v4l2_buffer (vb); + ret =vpu_helper_copy_to_stream_buffer (&inst->stream_buffer, + &wptr, +vb2_get_plane_payload (vb,0 ), +vb2_plane_vaddr (vb,0 )); +if (ret <vb2_get_plane_payload (vb,0 )) +return -ENOMEM ; + +vpu_malone_update_wptr (str_buf, wptr); + +return ret; +} + +static int vpu_malone_input_ts (struct vpu_inst *inst,s64 timestamp,u32 size) +{ +struct vpu_ts_info info; + +memset (&info,0 ,sizeof (info)); + info.timestamp = timestamp; + info.size = size; + +return vpu_session_fill_timestamp (inst, &info); +} + +int vpu_malone_input_frame (struct vpu_shared_addr *shared, +struct vpu_inst *inst,struct vb2_buffer *vb) +{ +struct vpu_dec_ctrl *hc; +struct vb2_v4l2_buffer *vbuf; +struct vpu_malone_str_buffer *str_buf; +u32 disp_imm =0 ; +u32 size; +int ret; + +WARN_ON (!shared || !shared->iface || !shared->core || !shared->priv); + hc = shared->priv; + str_buf = hc->str_buf[inst->id]; + disp_imm = hc->codec_param[inst->id].disp_imm; + +if (vpu_malone_is_non_frame_mode (shared, inst->id)) + ret =vpu_malone_input_stream_data (str_buf, inst, vb); +else + ret =vpu_malone_input_frame_data (str_buf, inst, vb, disp_imm); +if (ret <0 ) +return ret; + size = ret; + +/* +* if buffer only contain codec data, and the timestamp is invalid, +* don't put the invalid timestamp to resync +* merge the data to next frame +*/ + vbuf =to_vb2_v4l2_buffer (vb); +if ((vbuf->flags &V4L2_BUF_FLAG_CODECCONFIG ) && (s64 )vb->timestamp <0 ) { + inst->extra_size += size; +return 0 ; + } +if (inst->extra_size) { + size += inst->extra_size; + inst->extra_size =0 ; + } + + ret =vpu_malone_input_ts (inst, vb->timestamp, size); +if (ret) +return ret; + +return 0 ; +} + +static bool vpu_malone_check_ready (struct vpu_shared_addr *shared,u32 instance) +{ +struct malone_iface *iface; +struct vpu_rpc_buffer_desc *desc; +u32 size; +u32 rptr; +u32 wptr; +u32 used; + + iface = shared->iface; + desc = &iface->api_cmd_buffer_desc[instance]; + size = desc->end - desc->start; + rptr = desc->rptr; + wptr = desc->wptr; + used = (wptr + size - rptr) % size; +if (!size || used < size /2 ) +return true; + +vpu_dbg (LVL_DEBUG ,"[%d]api cmd used = %d/%d\n" , instance, used, size); + +return false; +} + +bool vpu_malone_is_ready (struct vpu_shared_addr *shared,u32 instance) +{ +u32 cnt =0 ; + +while (!vpu_malone_check_ready (shared, instance)) { +if (cnt >30 ) +return false; +mdelay (1 ); + cnt++; + } +return true; +} + +int vpu_malone_pre_cmd (struct vpu_shared_addr *shared,u32 instance) +{ +if (!vpu_malone_is_ready (shared, instance)) { +vpu_err ("[%d] is not ready\n" , instance); +return -EINVAL ; + } + +return 0 ; +} + +int vpu_malone_post_cmd (struct vpu_shared_addr *shared,u32 instance) +{ +struct malone_iface *iface; +struct vpu_rpc_buffer_desc *desc; + + iface = shared->iface; + desc = &iface->api_cmd_buffer_desc[instance]; + desc->wptr++; +if (desc->wptr == desc->end) + desc->wptr = desc->start; + +return 0 ; +} + +int vpu_malone_init_instance (struct vpu_shared_addr *shared,u32 instance) +{ +struct malone_iface *iface; +struct vpu_rpc_buffer_desc *desc; + + iface = shared->iface; + desc = &iface->api_cmd_buffer_desc[instance]; + desc->wptr = desc->rptr; +if (desc->wptr == desc->end) + desc->wptr = desc->start; + +return 0 ; +} + +u32 vpu_malone_get_max_instance_count (struct vpu_shared_addr *shared) +{ +struct malone_iface *iface = shared->iface; + +return iface->max_streams; +}
drivers/media/platform/imx/vpu-8q/vpu_malone.h new file +42 -0
42 lines not on this page · raw message
Signature · 1 line
2.32.0
PATCH v5 12/14 ARM64: dts: freescale: imx8q: add imx vpu codec entries
In reply to Ming QianAdd the Video Processing Unit node for IMX8Q SoC.
--- .../arm64/boot/dts/freescale/imx8-ss-vpu.dtsi | 72 +++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 17 +++++ arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 26 +++++++ 3 files changed, 115 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi
arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi new file +72 -0
@@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + * Dong Aisheng <[email protected]> + */ + +vpu: vpu@2c000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x2c000000 0x0 0x2c000000 0x2000000>; + reg = <0 0x2c000000 0 0x1000000>; + power-domains = <&pd IMX_SC_R_VPU>; + status = "disabled"; + + mu_m0: mailbox@2d000000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d000000 0x20000>; + interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_0>; + status = "okay"; + }; + + mu1_m0: mailbox@2d020000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d020000 0x20000>; + interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_1>; + status = "okay"; + }; + + mu2_m0: mailbox@2d040000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d040000 0x20000>; + interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_2>; + status = "disabled"; + }; + + vpu_core0: vpu_core@2d080000 { + reg = <0x2d080000 0x10000>; + compatible = "nxp,imx8q-vpu-decoder"; + power-domains = <&pd IMX_SC_R_VPU_DEC_0>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu_m0 0 0>, + <&mu_m0 0 1>, + <&mu_m0 1 0>; + status = "disabled"; + }; + vpu_core1: vpu_core@2d090000 { + reg = <0x2d090000 0x10000>; + compatible = "nxp,imx8q-vpu-encoder"; + power-domains = <&pd IMX_SC_R_VPU_ENC_0>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu1_m0 0 0>, + <&mu1_m0 0 1>, + <&mu1_m0 1 0>; + status = "disabled"; + }; + vpu_core2: vpu_core@2d0a0000 { + reg = <0x2d0a0000 0x10000>; + compatible = "nxp,imx8q-vpu-encoder"; + power-domains = <&pd IMX_SC_R_VPU_ENC_1>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu2_m0 0 0>, + <&mu2_m0 0 1>, + <&mu2_m0 1 0>; + status = "disabled"; + }; +};
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +17 -0
@@ -196,6 +196,23 @@ &usdhc2 { status = "okay"; }; +&vpu { + compatible = "nxp,imx8qxp-vpu"; + status = "okay"; +}; + +&vpu_core0 { + reg = <0x2d040000 0x10000>; + memory-region = <&decoder_boot>, <&decoder_rpc>; + status = "okay"; +}; + +&vpu_core1 { + reg = <0x2d050000 0x10000>; + memory-region = <&encoder_boot>, <&encoder_rpc>; + status = "okay"; +}; + &iomuxc { pinctrl_fec1: fec1grp { fsl,pins = <
arch/arm64/boot/dts/freescale/imx8qxp.dtsi +26 -0
@@ -45,6 +45,9 @@ aliases { serial1 = &adma_lpuart1; serial2 = &adma_lpuart2; serial3 = &adma_lpuart3; + vpu_core0 = &vpu_core0; + vpu_core1 = &vpu_core1; + vpu_core2 = &vpu_core2; }; cpus {
@@ -133,10 +136,30 @@ reserved-memory { #size-cells = <2>; ranges; + decoder_boot: decoder-boot@84000000 { + reg = <0 0x84000000 0 0x2000000>; + no-map; + }; + + encoder_boot: encoder-boot@86000000 { + reg = <0 0x86000000 0 0x200000>; + no-map; + }; + + decoder_rpc: decoder-rpc@0x92000000 { + reg = <0 0x92000000 0 0x100000>; + no-map; + }; + dsp_reserved: dsp@92400000 { reg = <0 0x92400000 0 0x2000000>; no-map; }; + + encoder_rpc: encoder-rpc@0x94400000 { + reg = <0 0x94400000 0 0x700000>; + no-map; + }; }; pmu {
@@ -629,4 +652,7 @@ map0 { }; }; }; + + /* sorted in register address */ + #include "imx8-ss-vpu.dtsi" };
Signature · 1 line
2.32.0
PATCH v5 13/14 firmware: imx: scu-pd: imx8q: add vpu mu resources
In reply to Ming Qianthe vpu core depends on the mu resources. if they're missed, the vpu can't work.
--- drivers/firmware/imx/scu-pd.c | 4 ++++ 1 file changed, 4 insertions(+)
drivers/firmware/imx/scu-pd.c +4 -0
@@ -145,6 +145,10 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { { "vpu-pid", IMX_SC_R_VPU_PID0, 8, true, 0 }, { "vpu-dec0", IMX_SC_R_VPU_DEC_0, 1, false, 0 }, { "vpu-enc0", IMX_SC_R_VPU_ENC_0, 1, false, 0 }, + { "vpu-enc1", IMX_SC_R_VPU_ENC_1, 1, false, 0 }, + { "vpu-mu0", IMX_SC_R_VPU_MU_0, 1, false, 0 }, + { "vpu-mu1", IMX_SC_R_VPU_MU_1, 1, false, 0 }, + { "vpu-mu2", IMX_SC_R_VPU_MU_2, 1, false, 0 },/* GPU SS */ { "gpu0-pid", IMX_SC_R_GPU_0_PID0, 4, true, 0 },
Signature · 1 line
2.32.0
PATCH v5 14/14 MAINTAINERS: add NXP IMX8Q VPU CODEC V4L2 driver entry
In reply to Ming QianAdd NXP IMX8Q VPU CODEC v4l2 driver entry
--- MAINTAINERS | 10 ++++++++++ 1 file changed, 10 insertions(+)
MAINTAINERS +10 -0
@@ -12600,6 +12600,16 @@ L: [email protected] (moderated for non-subscribers) S: Supported F: drivers/nfc/nxp-nci +NXP IMX8Q VPU CODEC V4L2 DRIVER +M: Ming Qian <[email protected]> +M: Shijie Qin <[email protected]> +M: Zhou Peng <[email protected]> +L: [email protected] +S: Maintained +F: Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml +F: drivers/media/platform/imx/vpu-8q +F: include/uapi/linux/imx_vpu.h + OBJAGG M: Jiri Pirko <[email protected]> L: [email protected]
Signature · 1 line
2.32.0
Re: [PATCH v5 14/14] MAINTAINERS: add NXP IMX8Q VPU CODEC V4L2 driver entry
Quoted 1 line · Ming Qian
Add NXP IMX8Q VPU CODEC v4l2 driver entry
[]
MAINTAINERS
Quoted 1 line
MAINTAINERS +0
-0
[]
MAINTAINERS L: [email protected] (moderated for non-subscribers) · line 12610
Quoted 12 lines
MAINTAINERS +0
-0@@ -12600,6 +12600,16 @@ L: [email protected] (moderated for non-subscribers)S: Supported
F:drivers/nfc/nxp-nciMAINTAINERS +8
-0+NXP IMX8Q VPU CODEC V4L2 DRIVER +M: Ming Qian <[email protected]> +M: Shijie Qin <[email protected]> +M: Zhou Peng <[email protected]> +L: [email protected] +S: Maintained +F: Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml +F: drivers/media/platform/imx/vpu-8q
Should have a trailing /
F: drivers/media/platform/imx/vpu-8q/
Quoted 5 lines
MAINTAINERS +2
-0+F: include/uapi/linux/imx_vpu.h +OBJAGG
M: Jiri Pirko <[email protected]>
L: [email protected]