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RK3568 GPU

PATCH Applied Ezequiel Garcia 3 participants 8 messages Aug 5, 2021 – Aug 20, 2021

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Ezequiel Garcia

author
#0 lore raw

v3 cover RK3568 GPU

I've decided to split the GPU off previous series:

https://lore.kernel.org/linux-rockchip/2147216.TLkxdtWsSY@diego/

This series now contains only the GPU support, as the VPU needs a tiny rework.

This is compiled tested only, in this case. Similar patches have been tested on a v5.10-based kernel, so I'd say it's good to go.

The mesa side is merged https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10771
and can be tested without a display, using something like weston --backend=headless-backend.so, which provides an environment for GL to work.

Ezequiel Garcia (4):
dt-bindings: gpu: mali-bifrost: Allow up to two clocks
dt-bindings: gpu: mali-bifrost: Add RK3568 compatible
arm64: dts: rockchip: Add GPU node for rk3568
arm64: dts: rockchip: Enable the GPU on Quartz64 Model A

 .../bindings/gpu/arm,mali-bifrost.yaml        |  8 ++-
 .../boot/dts/rockchip/rk3566-quartz64-a.dts   |  5 ++
 arch/arm64/boot/dts/rockchip/rk356x.dtsi      | 50 +++++++++++++++++++
 3 files changed, 62 insertions(+), 1 deletion(-)
Signature · 1 line
2.32.0
author
#1 lore raw

PATCH v3 1/4 dt-bindings: gpu: mali-bifrost: Allow up to two clocks

Commit b681af0bc1cc ("drm: panfrost: add optional bus_clock") added an optional bus_clock to support Allwinner H6 T-720 GPU. Increase the max clock items in the dt-binding to reflect this.

Signed-off-by Ezequiel Garcia <[email protected]>
---
 .../devicetree/bindings/gpu/arm,mali-bifrost.yaml          | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +6 -1
index 0f73f436bea7..01532140096e 100644
@@ -38,7 +38,12 @@ properties:
       - const: gpu
 
   clocks:
-    maxItems: 1
+    minItems: 1
+    maxItems: 2
+
+  clock-names:
+    minItems: 1
+    maxItems: 2
 
   mali-supply: true
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[email protected]
http://lists.infradead.org/mailman/listinfo/linux-rockchip
maintainer
#2 lore raw

Re: [PATCH v3 1/4] dt-bindings: gpu: mali-bifrost: Allow up to two clocks

Quoted 14 lines · Ezequiel Garcia

Commit b681af0bc1cc ("drm: panfrost: add optional bus_clock") added an optional bus_clock to support Allwinner H6 T-720 GPU. Increase the max clock items in the dt-binding to reflect this.

Signed-off-by Ezequiel Garcia <[email protected]>
---
 .../devicetree/bindings/gpu/arm,mali-bifrost.yaml          | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +0 -0
index 0f73f436bea7..01532140096e 100644

Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml properties: · line 46

Quoted 10 lines
Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +6 -1
@@ -38,7 +38,12 @@ properties:
       - const: gpu
 
   clocks:
-    maxItems: 1
+    minItems: 1
+    maxItems: 2
+
+  clock-names:
+    minItems: 1
+    maxItems: 2

You have to define what the names are.

Quoted 7 lines
Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +0 -0
   mali-supply: true
Signature · 1 line
2.32.0
author
#3 lore raw

PATCH v3 2/4 dt-bindings: gpu: mali-bifrost: Add RK3568 compatible

In reply to Ezequiel Garcia

The Rockchip RK3568 SoC has a Bifrost Mali-G52 GPU, add a compatible string for it.

Signed-off-by Ezequiel Garcia <[email protected]>
---
 Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml | 1 +
 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +1 -0
index 01532140096e..6afe7030b859 100644
@@ -20,6 +20,7 @@ properties:
           - mediatek,mt8183-mali
           - realtek,rtd1619-mali
           - rockchip,px30-mali
+          - rockchip,rk3568-mali
       - const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable
 
   reg:
Signature · 7 lines
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_______________________________________________
Linux-rockchip mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-rockchip
maintainer Applied
#4 lore raw

Re: [PATCH v3 2/4] dt-bindings: gpu: mali-bifrost: Add RK3568 compatible

Quoted 8 lines · Ezequiel Garcia

The Rockchip RK3568 SoC has a Bifrost Mali-G52 GPU, add a compatible string for it.

Signed-off-by Ezequiel Garcia <[email protected]>
---
 Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml | 1 +
 1 file changed, 1 insertion(+)

Applied, thanks!

author
#5 lore raw

PATCH v3 3/4 arm64: dts: rockchip: Add GPU node for rk3568

In reply to Ezequiel Garcia

Rockchip SoCs RK3566 and RK3568 have a Mali Gondul core which is based on the Bifrost architecture. It has one shader core and two execution engines.

Quoting the datasheet:

Mali-G52 1-Core-2EE
* Support 1600Mpix/s fill rate when 800MHz clock frequency
* Support 38.4GLOPs when 800MHz clock frequency

Signed-off-by Ezequiel Garcia <[email protected]>
---
 arch/arm64/boot/dts/rockchip/rk356x.dtsi | 50 ++++++++++++++++++++++++
 1 file changed, 50 insertions(+)
arch/arm64/boot/dts/rockchip/rk356x.dtsi +50 -0
index bef747fb1fe2..f8173ba63be0 100644
@@ -121,6 +121,40 @@ opp-1800000000 {
 		};
 	};
 
+	gpu_opp_table: gpu-opp-table {
+		compatible = "operating-points-v2";
+
+		opp-200000000 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-microvolt = <825000>;
+		};
+
+		opp-300000000 {
+			opp-hz = /bits/ 64 <300000000>;
+			opp-microvolt = <825000>;
+		};
+
+		opp-400000000 {
+			opp-hz = /bits/ 64 <400000000>;
+			opp-microvolt = <825000>;
+		};
+
+		opp-600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <825000>;
+		};
+
+		opp-700000000 {
+			opp-hz = /bits/ 64 <700000000>;
+			opp-microvolt = <900000>;
+		};
+
+		opp-800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			opp-microvolt = <1000000>;
+		};
+	};
+
 	firmware {
 		scmi: scmi {
 			compatible = "arm,scmi-smc";

@@ -332,6 +366,22 @@ power-domain@RK3568_PD_RKVENC {
 		};
 	};
 
+	gpu: gpu@fde60000 {
+		compatible = "rockchip,rk3568-mali", "arm,mali-bifrost";
+		reg = <0x0 0xfde60000 0x0 0x4000>;
+
+		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "job", "mmu", "gpu";
+		clocks = <&scmi_clk 1>, <&cru CLK_GPU>;
+		clock-names = "core", "bus";
+		operating-points-v2 = <&gpu_opp_table>;
+		#cooling-cells = <2>;
+		power-domains = <&power RK3568_PD_GPU>;
+		status = "disabled";
+	};
+
 	sdmmc2: mmc@fe000000 {
 		compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
 		reg = <0x0 0xfe000000 0x0 0x4000>;
Signature · 1 line
2.32.0
#6 lore raw

Re: [PATCH v3 3/4] arm64: dts: rockchip: Add GPU node for rk3568

Hi Ezequiel,

Some more comments. Have a look if it is useful.

Quoted 20 lines · Ezequiel Garcia

Rockchip SoCs RK3566 and RK3568 have a Mali Gondul core which is based on the Bifrost architecture. It has one shader core and two execution engines.

Quoting the datasheet:

Mali-G52 1-Core-2EE
* Support 1600Mpix/s fill rate when 800MHz clock frequency
* Support 38.4GLOPs when 800MHz clock frequency

Signed-off-by Ezequiel Garcia <[email protected]>
---
 arch/arm64/boot/dts/rockchip/rk356x.dtsi | 50 ++++++++++++++++++++++++
 1 file changed, 50 insertions(+)
arch/arm64/boot/dts/rockchip/rk356x.dtsi +0 -0
index bef747fb1fe2..f8173ba63be0 100644

arch/arm64/boot/dts/rockchip/rk356x.dtsi opp-1800000000 { · line 125

Quoted 5 lines
arch/arm64/boot/dts/rockchip/rk356x.dtsi +1 -0
@@ -121,6 +121,40 @@ opp-1800000000 {
 		};
 	};
 
 
+	gpu_opp_table: gpu-opp-table {

	gpu_opp_table: opp-table-1 {

Excuse for the inconvenience, but rob+dt just made a patch for opp last month...
See opp-v2-base.yaml:
'^opp-table(-[a-z0-9]+)?$'

[PATCH v3 3/3] dt-bindings: opp: Convert to DT schema
https://lore.kernel.org/lkml/[email protected]/

===
A look in the manufacturer tree we can expect one more opp table in the number sequence.

	npu_opp_table: opp-table-2 {}

https://github.com/rockchip-linux/kernel/blob/develop-4.19/arch/arm64/boot/dts/rockchip/rk3568.dtsi

Quoted 37 lines
arch/arm64/boot/dts/rockchip/rk356x.dtsi +33 -0
+		compatible = "operating-points-v2";
+
+		opp-200000000 {
+			opp-hz = /bits/ 64 <200000000>;
+			opp-microvolt = <825000>;
+		};
+
+		opp-300000000 {
+			opp-hz = /bits/ 64 <300000000>;
+			opp-microvolt = <825000>;
+		};
+
+		opp-400000000 {
+			opp-hz = /bits/ 64 <400000000>;
+			opp-microvolt = <825000>;
+		};
+
+		opp-600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <825000>;
+		};
+
+		opp-700000000 {
+			opp-hz = /bits/ 64 <700000000>;
+			opp-microvolt = <900000>;
+		};
+
+		opp-800000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			opp-microvolt = <1000000>;
+		};
+	};
+
 	firmware {
 		scmi: scmi {
arch/arm64/boot/dts/rockchip/rk356x.dtsi +0 -0
 			compatible = "arm,scmi-smc";

arch/arm64/boot/dts/rockchip/rk356x.dtsi power-domain@RK3568_PD_RKVENC { · line 373

Quoted 8 lines
arch/arm64/boot/dts/rockchip/rk356x.dtsi +4 -0
@@ -332,6 +366,22 @@ power-domain@RK3568_PD_RKVENC {
 		};
 	};
 
+	gpu: gpu@fde60000 {
+		compatible = "rockchip,rk3568-mali", "arm,mali-bifrost";
+		reg = <0x0 0xfde60000 0x0 0x4000>;
 
+

Maybe remove this empty line as well?

arch/arm64/boot/dts/rockchip/rk356x.dtsi power-domain@RK3568_PD_RKVENC { · line 380

Quoted 9 lines
arch/arm64/boot/dts/rockchip/rk356x.dtsi +8 -0
+		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "job", "mmu", "gpu";
+		clocks = <&scmi_clk 1>, <&cru CLK_GPU>;
+		clock-names = "core", "bus";
+		operating-points-v2 = <&gpu_opp_table>;
 
+		#cooling-cells = <2>;

Not a big issue, but things with "#" are only needed for dt interpretation (not a real property). I try to drop them as far down the list when not sort alphabetically or connected to a real property.

Quoted 9 lines
arch/arm64/boot/dts/rockchip/rk356x.dtsi +4 -0
+		power-domains = <&power RK3568_PD_GPU>;
 
+		status = "disabled";
+	};
+
arch/arm64/boot/dts/rockchip/rk356x.dtsi +0 -0
 	sdmmc2: mmc@fe000000 {
 		compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
 		reg = <0x0 0xfe000000 0x0 0x4000>;
author
#7 lore raw

PATCH v3 4/4 arm64: dts: rockchip: Enable the GPU on Quartz64 Model A

In reply to Ezequiel Garcia

Enable the GPU core on the Pine64 Quartz64 Model A.

Signed-off-by Ezequiel Garcia <[email protected]>
---
 arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 5 +++++
 1 file changed, 5 insertions(+)
arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +5 -0
index b239f314b38a..2114c7404a07 100644
@@ -147,6 +147,11 @@ &gmac1m0_clkinout
 	status = "okay";
 };
 
+&gpu {
+	mali-supply = <&vdd_gpu>;
+	status = "okay";
+};
+
 &i2c0 {
 	status = "okay";
Signature · 1 line
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