Add L3 provider support for SC7280

PATCH Applied Odelu Kukatla 5 participants 14 messages Oct 21, 2021 – Feb 24, 2022

Subsystems (5)

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Odelu Kukatla

author

2021-10-21 10:41 UTC #0 lore raw

v8 cover Add L3 provider support for SC7280

Add Epoch Subsystem (EPSS) L3 provider support on SM7280 SoCs.

v8:
- Addressed Stephen's comments from v7
- Resolved region mapping conflict between cpufreq-hw and epss_l3 devices.

Odelu Kukatla (3):
dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280
interconnect: qcom: Add EPSS L3 support on SC7280
arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider

 .../bindings/interconnect/qcom,osm-l3.yaml           |  1 +
 arch/arm64/boot/dts/qcom/sc7280.dtsi                 |  8 ++++++++
 drivers/interconnect/qcom/osm-l3.c                   | 20 +++++++++++++++++++-
 drivers/interconnect/qcom/sc7280.h                   |  2 ++
 4 files changed, 30 insertions(+), 1 deletion(-)

Signature · 2 lines

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Odelu Kukatla

author

2021-10-21 10:41 UTC #1 lore raw

PATCH v8 1/3 dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280

Add Epoch Subsystem (EPSS) L3 interconnect provider binding on SC7280 SoCs.

Signed-off-by Odelu Kukatla <[email protected]>

---
 Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml | 1 +
 1 file changed, 1 insertion(+)

Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml +1 -0

index e701524..116e434 100644
@@ -18,6 +18,7 @@ properties:
   compatible:
     enum:
       - qcom,sc7180-osm-l3
+      - qcom,sc7280-epss-l3
       - qcom,sc8180x-osm-l3
       - qcom,sdm845-osm-l3
       - qcom,sm8150-osm-l3

Signature · 2 lines

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Rob Herring

maintainer Acked-by on v8 1/3

2021-10-27 16:59 UTC #2 lore raw

Re: [v8 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280

Quoted 8 lines · Odelu Kukatla

Add Epoch Subsystem (EPSS) L3 interconnect provider binding on SC7280 SoCs.
Signed-off-by Odelu Kukatla <[email protected]>
---
 Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml | 1 +
 1 file changed, 1 insertion(+)

Acked-by Rob Herring <[email protected]>

Stephen Boyd

Reviewed-by on v8 1/3

2021-10-28 22:13 UTC #3 lore raw

Re: [v8 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280

In reply to Odelu Kukatla

Quoting Odelu Kukatla (2021-10-21 03:40:55)

Quoted 5 lines

Add Epoch Subsystem (EPSS) L3 interconnect provider binding on SC7280 SoCs.
Signed-off-by Odelu Kukatla <[email protected]>
---

Reviewed-by Stephen Boyd <[email protected]>

Odelu Kukatla

author

2021-10-21 10:41 UTC #4 lore raw

PATCH v8 2/3 interconnect: qcom: Add EPSS L3 support on SC7280

In reply to Odelu Kukatla

Add Epoch Subsystem (EPSS) L3 interconnect provider support on SC7280 SoCs.

Signed-off-by Odelu Kukatla <[email protected]>

---
 drivers/interconnect/qcom/osm-l3.c | 20 +++++++++++++++++++-
 drivers/interconnect/qcom/sc7280.h |  2 ++
 2 files changed, 21 insertions(+), 1 deletion(-)

drivers/interconnect/qcom/osm-l3.c +19 -1

index c7af143..eec1309 100644
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
  */
 
 #include <linux/bitfield.h>

@@ -15,6 +15,7 @@
 #include <dt-bindings/interconnect/qcom,osm-l3.h>
 
 #include "sc7180.h"
+#include "sc7280.h"
 #include "sc8180x.h"
 #include "sdm845.h"
 #include "sm8150.h"

@@ -114,6 +115,22 @@ static const struct qcom_osm_l3_desc sc7180_icc_osm_l3 = {
 	.reg_perf_state = OSM_REG_PERF_STATE,
 };
 
+DEFINE_QNODE(sc7280_epss_apps_l3, SC7280_MASTER_EPSS_L3_APPS, 32, SC7280_SLAVE_EPSS_L3);
+DEFINE_QNODE(sc7280_epss_l3, SC7280_SLAVE_EPSS_L3, 32);
+
+static const struct qcom_osm_l3_node *sc7280_epss_l3_nodes[] = {
+	[MASTER_EPSS_L3_APPS] = &sc7280_epss_apps_l3,
+	[SLAVE_EPSS_L3_SHARED] = &sc7280_epss_l3,
+};
+
+static const struct qcom_osm_l3_desc sc7280_icc_epss_l3 = {
+	.nodes = sc7280_epss_l3_nodes,
+	.num_nodes = ARRAY_SIZE(sc7280_epss_l3_nodes),
+	.lut_row_size = EPSS_LUT_ROW_SIZE,
+	.reg_freq_lut = EPSS_REG_FREQ_LUT,
+	.reg_perf_state = EPSS_REG_PERF_STATE,
+};
+
 DEFINE_QNODE(sc8180x_osm_apps_l3, SC8180X_MASTER_OSM_L3_APPS, 32, SC8180X_SLAVE_OSM_L3);
 DEFINE_QNODE(sc8180x_osm_l3, SC8180X_SLAVE_OSM_L3, 32);

@@ -326,6 +343,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
 
 static const struct of_device_id osm_l3_of_match[] = {
 	{ .compatible = "qcom,sc7180-osm-l3", .data = &sc7180_icc_osm_l3 },
+	{ .compatible = "qcom,sc7280-epss-l3", .data = &sc7280_icc_epss_l3 },
 	{ .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 },
 	{ .compatible = "qcom,sm8150-osm-l3", .data = &sm8150_icc_osm_l3 },
 	{ .compatible = "qcom,sc8180x-osm-l3", .data = &sc8180x_icc_osm_l3 },

drivers/interconnect/qcom/sc7280.h +2 -0

index 175e400..1fb9839 100644
@@ -150,5 +150,7 @@
 #define SC7280_SLAVE_PCIE_1			139
 #define SC7280_SLAVE_QDSS_STM			140
 #define SC7280_SLAVE_TCU			141
+#define SC7280_MASTER_EPSS_L3_APPS		142
+#define SC7280_SLAVE_EPSS_L3			143
 
 #endif

Signature · 2 lines

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Stephen Boyd

Reviewed-by on v8 2/3

2021-10-28 22:13 UTC #5 lore raw

Re: [v8 2/3] interconnect: qcom: Add EPSS L3 support on SC7280

Quoting Odelu Kukatla (2021-10-21 03:40:56)

Quoted 5 lines

Add Epoch Subsystem (EPSS) L3 interconnect provider support on SC7280 SoCs.
Signed-off-by Odelu Kukatla <[email protected]>
---

Reviewed-by Stephen Boyd <[email protected]>

Bjorn Andersson

Reviewed-by on v8 2/3

2021-11-18 20:53 UTC #6 lore raw

Re: [v8 2/3] interconnect: qcom: Add EPSS L3 support on SC7280

In reply to Odelu Kukatla

Quoted 3 lines · Odelu Kukatla

Add Epoch Subsystem (EPSS) L3 interconnect provider support on SC7280 SoCs.

Reviewed-by Bjorn Andersson <[email protected]>

@Georgi, do you intend to apply the two interconnect patches in this series?

Regards,
Bjorn

Quoted 73 lines

Signed-off-by Odelu Kukatla <[email protected]>

---
 drivers/interconnect/qcom/osm-l3.c | 20 +++++++++++++++++++-
 drivers/interconnect/qcom/sc7280.h |  2 ++
 2 files changed, 21 insertions(+), 1 deletion(-)

drivers/interconnect/qcom/osm-l3.c +19 -1

index c7af143..eec1309 100644
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
  */
 
 #include <linux/bitfield.h>

@@ -15,6 +15,7 @@
 #include <dt-bindings/interconnect/qcom,osm-l3.h>
 
 #include "sc7180.h"
+#include "sc7280.h"
 #include "sc8180x.h"
 #include "sdm845.h"
 #include "sm8150.h"

@@ -114,6 +115,22 @@ static const struct qcom_osm_l3_desc sc7180_icc_osm_l3 = {
 	.reg_perf_state = OSM_REG_PERF_STATE,
 };
 
+DEFINE_QNODE(sc7280_epss_apps_l3, SC7280_MASTER_EPSS_L3_APPS, 32, SC7280_SLAVE_EPSS_L3);
+DEFINE_QNODE(sc7280_epss_l3, SC7280_SLAVE_EPSS_L3, 32);
+
+static const struct qcom_osm_l3_node *sc7280_epss_l3_nodes[] = {
+	[MASTER_EPSS_L3_APPS] = &sc7280_epss_apps_l3,
+	[SLAVE_EPSS_L3_SHARED] = &sc7280_epss_l3,
+};
+
+static const struct qcom_osm_l3_desc sc7280_icc_epss_l3 = {
+	.nodes = sc7280_epss_l3_nodes,
+	.num_nodes = ARRAY_SIZE(sc7280_epss_l3_nodes),
+	.lut_row_size = EPSS_LUT_ROW_SIZE,
+	.reg_freq_lut = EPSS_REG_FREQ_LUT,
+	.reg_perf_state = EPSS_REG_PERF_STATE,
+};
+
 DEFINE_QNODE(sc8180x_osm_apps_l3, SC8180X_MASTER_OSM_L3_APPS, 32, SC8180X_SLAVE_OSM_L3);
 DEFINE_QNODE(sc8180x_osm_l3, SC8180X_SLAVE_OSM_L3, 32);

@@ -326,6 +343,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
 
 static const struct of_device_id osm_l3_of_match[] = {
 	{ .compatible = "qcom,sc7180-osm-l3", .data = &sc7180_icc_osm_l3 },
+	{ .compatible = "qcom,sc7280-epss-l3", .data = &sc7280_icc_epss_l3 },
 	{ .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 },
 	{ .compatible = "qcom,sm8150-osm-l3", .data = &sm8150_icc_osm_l3 },
 	{ .compatible = "qcom,sc8180x-osm-l3", .data = &sc8180x_icc_osm_l3 },

drivers/interconnect/qcom/sc7280.h +2 -0

index 175e400..1fb9839 100644
@@ -150,5 +150,7 @@
 #define SC7280_SLAVE_PCIE_1			139
 #define SC7280_SLAVE_QDSS_STM			140
 #define SC7280_SLAVE_TCU			141
+#define SC7280_MASTER_EPSS_L3_APPS		142
+#define SC7280_SLAVE_EPSS_L3			143
 
 #endif

Signature · 2 lines

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Georgi Djakov

maintainer

2021-11-22 15:25 UTC #7 lore raw

Re: [v8 2/3] interconnect: qcom: Add EPSS L3 support on SC7280

Quoted 7 lines · Bjorn Andersson

Quoted 3 lines · Odelu Kukatla
Add Epoch Subsystem (EPSS) L3 interconnect provider support on SC7280 SoCs.
Reviewed-by Bjorn Andersson <[email protected]>

Thanks!

Quoted 2 lines

@Georgi, do you intend to apply the two interconnect patches in this series?

Yes, applied!

BR,
Georgi

Quoted 77 lines

Regards,
Bjorn

Quoted 73 lines

Signed-off-by Odelu Kukatla <[email protected]>

---
  drivers/interconnect/qcom/osm-l3.c | 20 +++++++++++++++++++-
  drivers/interconnect/qcom/sc7280.h |  2 ++
  2 files changed, 21 insertions(+), 1 deletion(-)

drivers/interconnect/qcom/osm-l3.c +19 -1

index c7af143..eec1309 100644
@@ -1,6 +1,6 @@
  // SPDX-License-Identifier: GPL-2.0
  /*
- * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
   */
 
  #include <linux/bitfield.h>

@@ -15,6 +15,7 @@
  #include <dt-bindings/interconnect/qcom,osm-l3.h>
 
  #include "sc7180.h"
+#include "sc7280.h"
  #include "sc8180x.h"
  #include "sdm845.h"
  #include "sm8150.h"

@@ -114,6 +115,22 @@ static const struct qcom_osm_l3_desc sc7180_icc_osm_l3 = {
  	.reg_perf_state = OSM_REG_PERF_STATE,
  };
 
+DEFINE_QNODE(sc7280_epss_apps_l3, SC7280_MASTER_EPSS_L3_APPS, 32, SC7280_SLAVE_EPSS_L3);
+DEFINE_QNODE(sc7280_epss_l3, SC7280_SLAVE_EPSS_L3, 32);
+
+static const struct qcom_osm_l3_node *sc7280_epss_l3_nodes[] = {
+	[MASTER_EPSS_L3_APPS] = &sc7280_epss_apps_l3,
+	[SLAVE_EPSS_L3_SHARED] = &sc7280_epss_l3,
+};
+
+static const struct qcom_osm_l3_desc sc7280_icc_epss_l3 = {
+	.nodes = sc7280_epss_l3_nodes,
+	.num_nodes = ARRAY_SIZE(sc7280_epss_l3_nodes),
+	.lut_row_size = EPSS_LUT_ROW_SIZE,
+	.reg_freq_lut = EPSS_REG_FREQ_LUT,
+	.reg_perf_state = EPSS_REG_PERF_STATE,
+};
+
  DEFINE_QNODE(sc8180x_osm_apps_l3, SC8180X_MASTER_OSM_L3_APPS, 32, SC8180X_SLAVE_OSM_L3);
  DEFINE_QNODE(sc8180x_osm_l3, SC8180X_SLAVE_OSM_L3, 32);

@@ -326,6 +343,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
 
  static const struct of_device_id osm_l3_of_match[] = {
  	{ .compatible = "qcom,sc7180-osm-l3", .data = &sc7180_icc_osm_l3 },
+	{ .compatible = "qcom,sc7280-epss-l3", .data = &sc7280_icc_epss_l3 },
  	{ .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 },
  	{ .compatible = "qcom,sm8150-osm-l3", .data = &sm8150_icc_osm_l3 },
  	{ .compatible = "qcom,sc8180x-osm-l3", .data = &sc8180x_icc_osm_l3 },

drivers/interconnect/qcom/sc7280.h +2 -0

index 175e400..1fb9839 100644
@@ -150,5 +150,7 @@
  #define SC7280_SLAVE_PCIE_1			139
  #define SC7280_SLAVE_QDSS_STM			140
  #define SC7280_SLAVE_TCU			141
+#define SC7280_MASTER_EPSS_L3_APPS		142
+#define SC7280_SLAVE_EPSS_L3			143
 
  #endif

Signature · 2 lines

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Odelu Kukatla

author

2021-10-21 10:41 UTC #8 lore raw

PATCH v8 3/3 arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider

In reply to Odelu Kukatla

Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280 SoCs.

Signed-off-by Odelu Kukatla <[email protected]>

---
 arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

arch/arm64/boot/dts/qcom/sc7280.dtsi +8 -0

index d74a4c8..0b55742 100644
@@ -3687,6 +3687,14 @@
 			};
 		};
 
+		epss_l3: interconnect@18590000 {
+			compatible = "qcom,sc7280-epss-l3";
+			reg = <0 0x18590000 0 0x1000>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+			clock-names = "xo", "alternate";
+			#interconnect-cells = <1>;
+		};
+
 		cpufreq_hw: cpufreq@18591000 {
 			compatible = "qcom,cpufreq-epss";
 			reg = <0 0x18591000 0 0x1000>,

Signature · 2 lines

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Stephen Boyd

Reviewed-by on v8 3/3

2021-10-28 22:14 UTC #9 lore raw

Re: [v8 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider

Quoting Odelu Kukatla (2021-10-21 03:40:57)

Quoted 5 lines

Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280 SoCs.
Signed-off-by Odelu Kukatla <[email protected]>
---

Reviewed-by Stephen Boyd <[email protected]>

Bjorn Andersson

2021-10-28 23:25 UTC #10 lore raw

Re: [v8 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider

In reply to Odelu Kukatla

Quoted 13 lines · Odelu Kukatla

Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280 SoCs.
Signed-off-by Odelu Kukatla <[email protected]>
---
 arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)
arch/arm64/boot/dts/qcom/sc7280.dtsi +0 -0
index d74a4c8..0b55742 100644

arch/arm64/boot/dts/qcom/sc7280.dtsi line 3692

Quoted 6 lines

arch/arm64/boot/dts/qcom/sc7280.dtsi +3 -0

@@ -3687,6 +3687,14 @@
 			};
 		};
 
+		epss_l3: interconnect@18590000 {
+			compatible = "qcom,sc7280-epss-l3";
+			reg = <0 0x18590000 0 0x1000>;

This series looks like I would expect, with and without per-core dcvs. But can you please explain why this contradict what Sibi says here:
https://lore.kernel.org/all/[email protected]/

Regards,
Bjorn

Quoted 12 lines

arch/arm64/boot/dts/qcom/sc7280.dtsi +5 -0

+			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+			clock-names = "xo", "alternate";
+			#interconnect-cells = <1>;
+		};
+
 		cpufreq_hw: cpufreq@18591000 {
 			compatible = "qcom,cpufreq-epss";
 			reg = <0 0x18591000 0 0x1000>,

Signature · 2 lines

The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

[email protected]

author

2021-11-01 13:39 UTC #11 lore raw

Re: [v8 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider

Quoted 26 lines · Bjorn Andersson

Quoted 13 lines · Odelu Kukatla
Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280 SoCs.
Signed-off-by Odelu Kukatla <[email protected]>
---
 arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)
arch/arm64/boot/dts/qcom/sc7280.dtsi +0 -0
index d74a4c8..0b55742 100644
arch/arm64/boot/dts/qcom/sc7280.dtsi line 3692
Quoted 6 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +3 -0
@@ -3687,6 +3687,14 @@
 			};
 		};
 
+		epss_l3: interconnect@18590000 {
+			compatible = "qcom,sc7280-epss-l3";
+			reg = <0 0x18590000 0 0x1000>;
This series looks like I would expect, with and without per-core dcvs. But can you please explain why this contradict what Sibi says here:
https://lore.kernel.org/all/[email protected]/

Quoted 3 lines

Regards,
Bjorn

Thanks for Review!
Sibi's patch will be dropped, it is not required with my updated patch series:
https://lore.kernel.org/all/[email protected]/

Quoted 12 lines

Quoted 12 lines
arch/arm64/boot/dts/qcom/sc7280.dtsi +5 -1
+			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+			clock-names = "xo", "alternate";
+			#interconnect-cells = <1>;
+		};
+
 		cpufreq_hw: cpufreq@18591000 {
 			compatible = "qcom,cpufreq-epss";
 			reg = <0 0x18591000 0 0x1000>,
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

Georgi Djakov

maintainer Acked-by on v8 3/3

2021-11-22 15:25 UTC #12 lore raw

Re: [v8 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider

In reply to Odelu Kukatla

Quoted 4 lines · Odelu Kukatla

Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280 SoCs.
Signed-off-by Odelu Kukatla <[email protected]>

Acked-by Georgi Djakov <[email protected]>

Quoted 24 lines

---
  arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++++++++
  1 file changed, 8 insertions(+)

arch/arm64/boot/dts/qcom/sc7280.dtsi +8 -0

index d74a4c8..0b55742 100644
@@ -3687,6 +3687,14 @@
  			};
  		};
 
+		epss_l3: interconnect@18590000 {
+			compatible = "qcom,sc7280-epss-l3";
+			reg = <0 0x18590000 0 0x1000>;
+			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+			clock-names = "xo", "alternate";
+			#interconnect-cells = <1>;
+		};
+
  		cpufreq_hw: cpufreq@18591000 {
  			compatible = "qcom,cpufreq-epss";
  			reg = <0 0x18591000 0 0x1000>,

Bjorn Andersson

Applied

2022-02-24 20:54 UTC #13 lore raw

Re: (subset) [v8 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider

In reply to Odelu Kukatla

Quoted 4 lines · Odelu Kukatla

Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280 SoCs.

Applied, thanks!

[3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider

      commit: 8b93fbd95ed46bb0d57e63c65cef155a09a75bb9

Best regards,

Signature · 1 line

Bjorn Andersson <[email protected]>