Add Mali-G31 GPU support for RZ/G2L SoC
Subsystems (12)
v3 cover Add Mali-G31 GPU support for RZ/G2L SoC
RZ/G2L SoC embeds Mali-G31 bifrost GPU. This patch series aims to add support for the same
It is tested with latest drm-misc-next + mesa 21.3.0 + out of tree patch for (du + DSI) +
platform specific mesa configuration for RZ/G2L.
Tested the kmscube application.
test logs:-
root@smarc-rzg2l:~# kmscube Using display 0xaaaadb6e7d30 with EGL version 1.4 =================================== EGL information: version: "1.4" vendor: "Mesa Project" ..... =================================== OpenGL ES 2.x information: version: "OpenGL ES 3.1 Mesa 21.3.0" shading language version: "OpenGL ES GLSL ES 3.10" vendor: "Panfrost" renderer: "Mali-G31 (Panfrost)" .... =================================== ^C
root@smarc-rzg2l:~# cat /proc/interrupts | grep panfrost 82: 587287 0 GICv3 186 Level panfrost-job 83: 2 0 GICv3 187 Level panfrost-mmu 84: 8 0 GICv3 185 Level panfrost-gpu
root@smarc-rzg2l:~# cat /sys/class/devfreq/11840000.gpu/trans_stat
From : To
: 50000000 62500000 100000000 125000000 200000000 250000000 400000000 500000000 time(ms)
* 50000000: 0 0 0 0 0 0 0 0 72
62500000: 0 0 0 0 0 0 0 0 0
100000000: 0 0 0 0 0 0 0 0 0
125000000: 0 0 0 0 0 0 0 1 68
200000000: 0 0 0 0 0 0 0 1 68
250000000: 1 0 0 0 0 0 0 0 84
400000000: 0 0 0 0 0 0 0 0 0
500000000: 0 0 0 1 1 1 0 0 736
Total transition : 6
root@smarc-rzg2l:~# kmscube
Using display 0xaaaaf7a421b0 with EGL version 1.4
===================================
EGL information:
version: "1.4"
vendor: "Mesa Project"
.....
===================================
OpenGL ES 2.x information:
version: "OpenGL ES 3.1 Mesa 21.3.0"
shading language version: "OpenGL ES GLSL ES 3.10"
vendor: "Panfrost"
renderer: "Mali-G31 (Panfrost)"
......
===================================root@smarc-rzg2l:~#
root@smarc-rzg2l:~#
root@smarc-rzg2l:~# cat /sys/class/devfreq/11840000.gpu/trans_stat
From : To
: 50000000 62500000 100000000 125000000 200000000 250000000 400000000 500000000 time(ms)
* 50000000: 0 0 0 0 0 0 0 1 144
62500000: 0 0 0 0 0 0 0 0 0
100000000: 0 0 0 0 0 0 0 9 524
125000000: 0 0 9 0 0 0 0 3 2544
200000000: 0 0 0 11 0 0 0 46 3304
250000000: 1 0 0 0 33 0 0 0 7496
400000000: 0 0 0 0 16 19 0 0 2024
500000000: 1 0 0 1 8 15 35 0 4032
Total transition : 208Platform specific mesa configuration patch for RZ/G2L
---------------------
src/gallium/targets/dri/meson.build
+ 'rcar-du_dri.so',src/gallium/targets/dri/target.c +DEFINE_LOADER_DRM_ENTRYPOINT(rcar_du)
V2->V3:
* Moved optional clock-names and reset-names to SoC-specific conditional schemas.
* minimum number of reset for the generic GPU is set to 1.
* Documented number of clocks, resets, interrupts and interrupt-names in RZ/G2L SoC-specific conditional schemas.
* Updated commit description for patch#3V1->V2:
* Removed clock patches from this seies, as it is accepted for 5.17
* Added Rb tag from Geert
* Added reset-names required property for RZ/G2L and updated the board dtsi.
Biju Das (3):
dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
arm64: dts: renesas: r9a07g044: Add Mali-G31 GPU node
arm64: dts: renesas: rzg2l-smarc-som: Add vdd core regulator
.../bindings/gpu/arm,mali-bifrost.yaml | 45 ++++++++++++- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 65 +++++++++++++++++++ .../boot/dts/renesas/rzg2l-smarc-som.dtsi | 13 ++++ 3 files changed, 121 insertions(+), 2 deletions(-)
Signature · 1 line
2.17.1
PATCH v3 1/3 dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
The Renesas RZ/G2{L, LC} SoC (a.k.a R9A07G044) has a Bifrost Mali-G31 GPU, add a compatible string for it.
---v2->v3:
* Moved optional clock-names and reset-names to SoC-specific conditional schemas.
* minimum number of reset for the generic GPU is set to 1.
* Documented number of clocks, resets, interrupts and interrupt-names in RZ/G2L SoC-specific conditional schemas.v1->v2:
* Updated minItems for resets as 2
* Documented optional property reset-names
* Documented reset-names as required property for RZ/G2L SoC.
--- .../bindings/gpu/arm,mali-bifrost.yaml | 45 ++++++++++++++++++- 1 file changed, 43 insertions(+), 2 deletions(-)
Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +43 -2
@@ -19,6 +19,7 @@ properties: - amlogic,meson-g12a-mali - mediatek,mt8183-mali - realtek,rtd1619-mali + - renesas,r9a07g044-mali - rockchip,px30-mali - rockchip,rk3568-mali - const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable
@@ -27,19 +28,26 @@ properties: maxItems: 1 interrupts: + minItems: 3 items: - description: Job interrupt - description: MMU interrupt - description: GPU interrupt + - description: Event interrupt interrupt-names: + minItems: 3 items: - const: job - const: mmu - const: gpu + - const: event clocks: - maxItems: 1 + minItems: 1 + maxItems: 3 + + clock-names: true mali-supply: true
@@ -52,7 +60,10 @@ properties: maxItems: 3 resets: - maxItems: 2 + minItems: 1 + maxItems: 3 + + reset-names: true "#cooling-cells": const: 2
@@ -94,6 +105,36 @@ allOf: then: required: - resets + - if: + properties: + compatible: + contains: + const: renesas,r9a07g044-mali + then: + properties: + interrupts: + minItems: 4 + interrupt-names: + minItems: 4 + clocks: + minItems: 3 + clock-names: + items: + - const: gpu + - const: bus + - const: bus_ace + resets: + minItems: 3 + reset-names: + items: + - const: rst + - const: axi_rst + - const: ace_rst + required: + - clock-names + - power-domains + - resets + - reset-names - if: properties: compatible:
Signature · 1 line
2.17.1
RE: [PATCH v3 1/3] dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
Hi All,
Gentle ping.
Cheers,
Biju
Quoted 116 lines
Subject: [PATCH v3 1/3] dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
The Renesas RZ/G2{L, LC} SoC (a.k.a R9A07G044) has a Bifrost Mali-G31 GPU, add a compatible string for it.
Signed-off-by Biju Das <[email protected]>Reviewed-by Lad Prabhakar <[email protected]>---
v2->v3:
* Moved optional clock-names and reset-names to SoC-specific conditional
schemas.
* minimum number of reset for the generic GPU is set to 1.
* Documented number of clocks, resets, interrupts and interrupt-names in
RZ/G2L
SoC-specific conditional schemas.v1->v2:
* Updated minItems for resets as 2
* Documented optional property reset-names
* Documented reset-names as required property for RZ/G2L SoC.--- .../bindings/gpu/arm,mali-bifrost.yaml | 45 ++++++++++++++++++- 1 file changed, 43 insertions(+), 2 deletions(-)Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +1
-0@@ -19,6 +19,7 @@ properties: - amlogic,meson-g12a-mali - mediatek,mt8183-mali - realtek,rtd1619-mali + - renesas,r9a07g044-mali - rockchip,px30-mali - rockchip,rk3568-mali - const: arm,mali-bifrost # Mali Bifrost GPU model/revision isfully discoverable @@ -27,19 +28,26 @@ properties:
maxItems: 1interrupts:
Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +42
-3+ minItems: 3 items: - description: Job interrupt - description: MMU interrupt - description: GPU interrupt + - description: Event interrupt interrupt-names: + minItems: 3 items: - const: job - const: mmu - const: gpu + - const: event clocks: - maxItems: 1 + minItems: 1 + maxItems: 3 + + clock-names: true mali-supply: true@@ -52,7 +60,10 @@ properties: maxItems: 3 resets: - maxItems: 2 + minItems: 1 + maxItems: 3 + + reset-names: true "#cooling-cells": const: 2@@ -94,6 +105,36 @@ allOf: then: required: - resets + - if: + properties: + compatible: + contains: + const: renesas,r9a07g044-mali + then: + properties: + interrupts: + minItems: 4 + interrupt-names: + minItems: 4 + clocks: + minItems: 3 + clock-names: + items: + - const: gpu + - const: bus + - const: bus_ace + resets: + minItems: 3 + reset-names: + items: + - const: rst + - const: axi_rst + - const: ace_rst + required: + - clock-names + - power-domains + - resets + - reset-names - if: properties: compatible: --2.17.1
Rob Herring
maintainerRe: [PATCH v3 1/3] dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
Quoted 3 lines · Biju Das
Hi All,
Gentle ping.
2 days later is not a gentle ping. If you want to check status, go look at PW[1]. If it is in there, it's in my queue (only about 100 patches ATM).
Rob
[1] https://patchwork.ozlabs.org/project/devicetree-bindings/list/
Quoted 122 lines
Cheers,
BijuQuoted 116 lines
Subject: [PATCH v3 1/3] dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
The Renesas RZ/G2{L, LC} SoC (a.k.a R9A07G044) has a Bifrost Mali-G31 GPU, add a compatible string for it.
Signed-off-by Biju Das <[email protected]>Reviewed-by Lad Prabhakar <[email protected]>---
v2->v3:
* Moved optional clock-names and reset-names to SoC-specific conditional
schemas.
* minimum number of reset for the generic GPU is set to 1.
* Documented number of clocks, resets, interrupts and interrupt-names in
RZ/G2L
SoC-specific conditional schemas.v1->v2:
* Updated minItems for resets as 2
* Documented optional property reset-names
* Documented reset-names as required property for RZ/G2L SoC.--- .../bindings/gpu/arm,mali-bifrost.yaml | 45 ++++++++++++++++++- 1 file changed, 43 insertions(+), 2 deletions(-)Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +1
-0@@ -19,6 +19,7 @@ properties: - amlogic,meson-g12a-mali - mediatek,mt8183-mali - realtek,rtd1619-mali + - renesas,r9a07g044-mali - rockchip,px30-mali - rockchip,rk3568-mali - const: arm,mali-bifrost # Mali Bifrost GPU model/revision isfully discoverable @@ -27,19 +28,26 @@ properties:
maxItems: 1interrupts:
Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +42
-3+ minItems: 3 items: - description: Job interrupt - description: MMU interrupt - description: GPU interrupt + - description: Event interrupt interrupt-names: + minItems: 3 items: - const: job - const: mmu - const: gpu + - const: event clocks: - maxItems: 1 + minItems: 1 + maxItems: 3 + + clock-names: true mali-supply: true@@ -52,7 +60,10 @@ properties: maxItems: 3 resets: - maxItems: 2 + minItems: 1 + maxItems: 3 + + reset-names: true "#cooling-cells": const: 2@@ -94,6 +105,36 @@ allOf: then: required: - resets + - if: + properties: + compatible: + contains: + const: renesas,r9a07g044-mali + then: + properties: + interrupts: + minItems: 4 + interrupt-names: + minItems: 4 + clocks: + minItems: 3 + clock-names: + items: + - const: gpu + - const: bus + - const: bus_ace + resets: + minItems: 3 + reset-names: + items: + - const: rst + - const: axi_rst + - const: ace_rst + required: + - clock-names + - power-domains + - resets + - reset-names - if: properties: compatible: --2.17.1
RE: [PATCH v3 1/3] dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
Hi Rob,
Quoted 10 lines
Subject: Re: [PATCH v3 1/3] dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
Quoted 3 lines · Biju Das
Hi All,
Gentle ping.
2 days later is not a gentle ping. If you want to check status, go look at PW[1]. If it is in there, it's in my queue (only about 100 patches ATM).
Sorry. Next time will take care.
Cheers,
Biju
Quoted 133 lines
[1]
https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwor
k.ozlabs.org%2Fproject%2Fdevicetree- bindings%2Flist%2F&data=04%7C01%7Cbiju.das.jz%40bp.renesas.com%7C4c2f7 b12ae0c4fd541d608d9bf36f549%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C6 37751065028707898%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2lu MzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=1rccc5jxHMAu111IJrebdW PwTP%2BrQj8uG9iSuMO58EM%3D&reserved=0Quoted 26 lines
Cheers,
BijuQuoted 22 lines
Subject: [PATCH v3 1/3] dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
The Renesas RZ/G2{L, LC} SoC (a.k.a R9A07G044) has a Bifrost Mali-G31 GPU, add a compatible string for it.
Signed-off-by Biju Das <[email protected]>Reviewed-by Lad Prabhakar <[email protected]>---
v2->v3:
* Moved optional clock-names and reset-names to SoC-specific
conditional schemas.
* minimum number of reset for the generic GPU is set to 1.
* Documented number of clocks, resets, interrupts and
interrupt-names in RZ/G2L
SoC-specific conditional schemas.v1->v2:
* Updated minItems for resets as 2
* Documented optional property reset-names
* Documented reset-names as required property for RZ/G2L SoC.--- .../bindings/gpu/arm,mali-bifrost.yaml | 45++++++++++++++++++-
Quoted 97 lines
Quoted 95 lines
1 file changed, 43 insertions(+), 2 deletions(-)diff --git
a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yamlb/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yamlindex6f98dd55fb4c..63a08f3f321d100644Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +1
-0@@ -19,6 +19,7 @@ properties: - amlogic,meson-g12a-mali - mediatek,mt8183-mali - realtek,rtd1619-mali + - renesas,r9a07g044-mali - rockchip,px30-mali - rockchip,rk3568-mali - const: arm,mali-bifrost # Mali Bifrost GPU model/revisionis fully discoverable @@ -27,19 +28,26 @@ properties:
maxItems: 1interrupts:
Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +42
-3+ minItems: 3 items: - description: Job interrupt - description: MMU interrupt - description: GPU interrupt + - description: Event interrupt interrupt-names: + minItems: 3 items: - const: job - const: mmu - const: gpu + - const: event clocks: - maxItems: 1 + minItems: 1 + maxItems: 3 + + clock-names: true mali-supply: true@@ -52,7 +60,10 @@ properties: maxItems: 3 resets: - maxItems: 2 + minItems: 1 + maxItems: 3 + + reset-names: true "#cooling-cells": const: 2@@ -94,6 +105,36 @@ allOf: then: required: - resets + - if: + properties: + compatible: + contains: + const: renesas,r9a07g044-mali + then: + properties: + interrupts: + minItems: 4 + interrupt-names: + minItems: 4 + clocks: + minItems: 3 + clock-names: + items: + - const: gpu + - const: bus + - const: bus_ace + resets: + minItems: 3 + reset-names: + items: + - const: rst + - const: axi_rst + - const: ace_rst + required: + - clock-names + - power-domains + - resets + - reset-names - if: properties: compatible: --2.17.1
Re: [PATCH v3 1/3] dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
In reply to Biju DasQuoted 39 lines · Biju Das
The Renesas RZ/G2{L, LC} SoC (a.k.a R9A07G044) has a Bifrost Mali-G31 GPU, add a compatible string for it.
Signed-off-by Biju Das <[email protected]>Reviewed-by Lad Prabhakar <[email protected]>---
v2->v3:
* Moved optional clock-names and reset-names to SoC-specific conditional schemas.
* minimum number of reset for the generic GPU is set to 1.
* Documented number of clocks, resets, interrupts and interrupt-names in RZ/G2L SoC-specific conditional schemas.v1->v2:
* Updated minItems for resets as 2
* Documented optional property reset-names
* Documented reset-names as required property for RZ/G2L SoC.--- .../bindings/gpu/arm,mali-bifrost.yaml | 45 ++++++++++++++++++- 1 file changed, 43 insertions(+), 2 deletions(-)Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +2
-0@@ -19,6 +19,7 @@ properties: - amlogic,meson-g12a-mali - mediatek,mt8183-mali - realtek,rtd1619-mali + - renesas,r9a07g044-mali - rockchip,px30-mali - rockchip,rk3568-mali - const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable@@ -27,19 +28,26 @@ properties: maxItems: 1 interrupts: + minItems: 3 items: - description: Job interrupt - description: MMU interrupt
Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml properties: · line 44
Quoted 10 lines
Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +3
-0- description: GPU interrupt + - description: Event interrupt interrupt-names: + minItems: 3 items: - const: job - const: mmu - const: gpu + - const: event
FWIW: I think it's fair to add the "event" interrupt even if it isn't included in the bindings for kbase. While pretty much useless on Bifrost it is a hardware feature and in theory it could be used.
Steve
Quoted 60 lines
Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +38
-2clocks: - maxItems: 1 + minItems: 1 + maxItems: 3 + + clock-names: true mali-supply: true@@ -52,7 +60,10 @@ properties: maxItems: 3 resets: - maxItems: 2 + minItems: 1 + maxItems: 3 + + reset-names: true "#cooling-cells": const: 2@@ -94,6 +105,36 @@ allOf: then: required: - resets + - if: + properties: + compatible: + contains: + const: renesas,r9a07g044-mali + then: + properties: + interrupts: + minItems: 4 + interrupt-names: + minItems: 4 + clocks: + minItems: 3 + clock-names: + items: + - const: gpu + - const: bus + - const: bus_ace + resets: + minItems: 3 + reset-names: + items: + - const: rst + - const: axi_rst + - const: ace_rst + required: + - clock-names + - power-domains + - resets + - reset-names - if: properties: compatible:
Re: [PATCH v3 1/3] dt-bindings: gpu: mali-bifrost: Document RZ/G2L support
In reply to Biju DasQuoted 15 lines · Biju Das
The Renesas RZ/G2{L, LC} SoC (a.k.a R9A07G044) has a Bifrost Mali-G31 GPU, add a compatible string for it.
Signed-off-by Biju Das <[email protected]>Reviewed-by Lad Prabhakar <[email protected]>---
v2->v3:
* Moved optional clock-names and reset-names to SoC-specific conditional schemas.
* minimum number of reset for the generic GPU is set to 1.
* Documented number of clocks, resets, interrupts and interrupt-names in RZ/G2L SoC-specific conditional schemas.v1->v2:
* Updated minItems for resets as 2
* Documented optional property reset-names
* Documented reset-names as required property for RZ/G2L SoC.
Quoted 4 lines
--- .../bindings/gpu/arm,mali-bifrost.yaml | 45 ++++++++++++++++++- 1 file changed, 43 insertions(+), 2 deletions(-)
Applied, thanks!
PATCH v3 2/3 arm64: dts: renesas: r9a07g044: Add Mali-G31 GPU node
In reply to Biju DasAdd Mali-G31 GPU node to SoC DTSI.
---v2->v3:
* No change.v1->v2:
* Added reset-names.
* Added Rb tag from Geert
--- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 65 ++++++++++++++++++++++ 1 file changed, 65 insertions(+)
arch/arm64/boot/dts/renesas/r9a07g044.dtsi +65 -0
@@ -111,6 +111,50 @@ }; }; + gpu_opp_table: opp-table-1 { + compatible = "operating-points-v2"; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1100000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1100000>; + }; + + opp-250000000 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <1100000>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1100000>; + }; + + opp-125000000 { + opp-hz = /bits/ 64 <125000000>; + opp-microvolt = <1100000>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <1100000>; + }; + + opp-62500000 { + opp-hz = /bits/ 64 <62500000>; + opp-microvolt = <1100000>; + }; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <1100000>; + }; + }; + psci { compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc";
@@ -637,6 +681,27 @@ dma-channels = <16>; }; + gpu: gpu@11840000 { + compatible = "renesas,r9a07g044-mali", + "arm,mali-bifrost"; + reg = <0x0 0x11840000 0x0 0x10000>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "job", "mmu", "gpu", "event"; + clocks = <&cpg CPG_MOD R9A07G044_GPU_CLK>, + <&cpg CPG_MOD R9A07G044_GPU_AXI_CLK>, + <&cpg CPG_MOD R9A07G044_GPU_ACE_CLK>; + clock-names = "gpu", "bus", "bus_ace"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_GPU_RESETN>, + <&cpg R9A07G044_GPU_AXI_RESETN>, + <&cpg R9A07G044_GPU_ACE_RESETN>; + reset-names = "rst", "axi_rst", "ace_rst"; + operating-points-v2 = <&gpu_opp_table>; + }; + gic: interrupt-controller@11900000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>;
Signature · 1 line
2.17.1
PATCH v3 3/3 arm64: dts: renesas: rzg2l-smarc-som: Add vdd core regulator
In reply to Biju DasAdd vdd core regulator (1.1 V).
This patch add regulator support for gpu.
The H/W manual mentions nothing about a gpu regulator. So using vdd core regulator for gpu.
---v2->v3:
* Updated the commit description. Thanks to Sergey Shtylyov.v1->v2:
* Added Rb tag from Geert.
--- arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+)
arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi +13 -0
@@ -52,6 +52,15 @@ regulator-always-on; }; + reg_1p1v: regulator-vdd-core { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + vccq_sdhi0: regulator-vccq-sdhi0 { compatible = "regulator-gpio";
@@ -130,6 +139,10 @@ clock-frequency = <24000000>; }; +&gpu { + mali-supply = <®_1p1v>; +}; + &ostm1 { status = "okay"; };
Signature · 1 line
2.17.1
Quoted 4 lines · Geert Uytterhoeven
From: Biju Das <[email protected]>
RZ/G2L SoC embeds Mali-G31 bifrost GPU. This patch series aims to add support for the same
Oops, please ignore this email. Sorry for the noise.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Quoted 4 lines · Geert Uytterhoeven
From: Biju Das <[email protected]>
RZ/G2L SoC embeds Mali-G31 bifrost GPU. This patch series aims to add support for the same
Oops, please ignore this email. Sorry for the noise.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Quoted 4 lines · Geert Uytterhoeven
From: Biju Das <[email protected]>
RZ/G2L SoC embeds Mali-G31 bifrost GPU. This patch series aims to add support for the same
Oops, please ignore this email. Sorry for the noise.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Hi Biju,
Quoted 6 lines · Biju Das
RZ/G2L SoC embeds Mali-G31 bifrost GPU. This patch series aims to add support for the same
It is tested with latest drm-misc-next + mesa 21.3.0 + out of tree patch for (du + DSI) +
platform specific mesa configuration for RZ/G2L.
Could you please post the 'platform-specific Mesa configuration' patches as a merge request to Mesa? Thanks.
Cheers,
Daniel
Hi Daniel Stone,
Thanks for the feedback.
Quoted 8 lines
Subject: Re: [PATCH v3 0/3] Add Mali-G31 GPU support for RZ/G2L SoC
Hi Biju,
Quoted 3 lines · Biju Das
RZ/G2L SoC embeds Mali-G31 bifrost GPU. This patch series aims to add support for the same
Quoted 6 lines
Quoted 3 lines
It is tested with latest drm-misc-next + mesa 21.3.0 + out of tree patch for (du + DSI) + platform specific mesa configuration for RZ/G2L.
Could you please post the 'platform-specific Mesa configuration' patches as a merge request to Mesa?
Sure will send a merge request to Mesa.
Regards,
Biju
Miquel Raynal
maintainerv4 cover Renesas RZ/N1 NAND controller support
Hello,
Here is a short series bringing support for Renesas RZ/N1 NAND controller.
This time the driver has been tested with a fully-upstream device tree on top of a v5.16-rc4. The DT used is very close to the r9a06g032-db.
Cheers,
Miquèl
Changes in v4:
* Set unevaluatedProperties set to false in the bindings.
* Change the clock names by removing the nand_ prefix which is redundant, even though the clocks are named like this in the spec. The name remains clear enough anyway.
Changes in v3:
* Rebased on top of a fully-upstream recent kernel.
* Renamed the clocks in the bindings and the driver to match the documentation (lower-cased): nand_hclk & nand_eclk.
* Added a new commit describing the NAND controller in the r9a06g032 DTSI.
* Added the Reviewed-by and Tested-by tags received.
Changes in v2:
* Added the family-specific rzn1 compatible as suggested by Geert. Updated the bindings, the binding file name, the compatible used in the driver, the MAINTAINERS entry, etc.
* Added an ARCH_RENESAS Kconfig dependency.
* Changed the type (to unsigned) of a couple of variables.
* Returned earlier when possible to reduce indentation.
* Used platform_get_irq_optional() instead of platform_get_irq() to avoid a useless warning.
* Handled probe deferral correctly.
* Applied a massive s/nfc/nandc/ as suggested by Geert to avoid confusions with the near-field-communication device.
* Mentioned Evatronix as original authors of the IP in the commit log and in the header.
* Added an additional check on the validity of the child nodes reg property.
* A couple of style fixes.
Miquel Raynal (4):
dt-bindings: mtd: rzn1: Describe Renesas RZ/N1 NAND controller
mtd: rawnand: rzn1: Add new NAND controller driver
MAINTAINERS: Add an entry for Renesas RZ/N1 NAND controller
ARM: dts: r9a06g032: Describe NAND controller
.../mtd/renesas,rzn1-nand-controller.yaml | 64 + MAINTAINERS | 7 + arch/arm/boot/dts/r9a06g032.dtsi | 12 + drivers/mtd/nand/raw/Kconfig | 6 + drivers/mtd/nand/raw/Makefile | 1 + drivers/mtd/nand/raw/rzn1-nand-controller.c | 1422 +++++++++++++++++ 6 files changed, 1512 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/renesas,rzn1-nand-controller.yaml create mode 100644 drivers/mtd/nand/raw/rzn1-nand-controller.c
Signature · 6 lines
2.27.0 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
Miquel Raynal
maintainerPATCH v4 1/4 dt-bindings: mtd: rzn1: Describe Renesas RZ/N1 NAND controller
Add a Yaml description for this Renesas NAND controller bindings.
Provide a family-specific "rzn1" compatible and a more specific "r9a06g032" one.
--- .../mtd/renesas,rzn1-nand-controller.yaml | 64 +++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/renesas,rzn1-nand-controller.yaml
Documentation/devicetree/bindings/mtd/renesas,rzn1-nand-controller.yaml new file +64 -0
@@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/renesas,rzn1-nand-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/N1x NAND flash controller device tree bindings + +maintainers: + - Miquel Raynal <[email protected]> + +allOf: + - $ref: "nand-controller.yaml" + +properties: + compatible: + items: + - enum: + - renesas,r9a06g032-nand-controller + - const: renesas,rzn1-nand-controller + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: APB host controller clock + - description: External NAND bus clock + + clock-names: + items: + - const: hclk + - const: eclk + + "#address-cells": true + "#size-cells": true + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/r9a06g032-sysctrl.h> + + nand-controller@40102000 { + compatible = "renesas,r9a06g032-nand-controller", + "renesas,rzn1-nand-controller"; + reg = <0x40102000 0x2000>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysctrl R9A06G032_HCLK_NAND>, <&sysctrl R9A06G032_CLK_NAND>; + clock-names = "hclk", "eclk"; + #address-cells = <1>; + #size-cells = <0>; + };
Signature · 6 lines
2.27.0 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
Re: [PATCH v4 1/4] dt-bindings: mtd: rzn1: Describe Renesas RZ/N1 NAND controller
Quoted 47 lines · Miquel Raynal
Add a Yaml description for this Renesas NAND controller bindings.
Provide a family-specific "rzn1" compatible and a more specific "r9a06g032" one.
Signed-off-by Miquel Raynal <[email protected]>Reviewed-by Geert Uytterhoeven <[email protected]>--- .../mtd/renesas,rzn1-nand-controller.yaml | 64 +++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/renesas,rzn1-nand-controller.yamlDocumentation/devicetree/bindings/mtd/renesas,rzn1-nand-controller.yaml new file +29
-0@@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/renesas,rzn1-nand-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/N1x NAND flash controller device tree bindings + +maintainers: + - Miquel Raynal <[email protected]> + +allOf: + - $ref: "nand-controller.yaml" + +properties: + compatible: + items: + - enum: + - renesas,r9a06g032-nand-controller + - const: renesas,rzn1-nand-controller + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items:
Documentation/devicetree/bindings/mtd/renesas,rzn1-nand-controller.yaml line 39
Quoted 10 lines
Documentation/devicetree/bindings/mtd/renesas,rzn1-nand-controller.yaml new file +10
-0+ - description: APB host controller clock + - description: External NAND bus clock + + clock-names: + items: + - const: hclk + - const: eclk + + "#address-cells": true + "#size-cells": true
You can drop these 2 as nand-controller.yaml should cover them.
Miquel Raynal
maintainerPATCH v4 2/4 mtd: rawnand: rzn1: Add new NAND controller driver
In reply to Miquel RaynalIntroduce Renesas RZ/N1x NAND controller driver which supports:
- All ONFI timing modes
- Different configurations of its internal ECC controller
- On-die (not tested) and software ECC support
- Several chips (not tested)
- Subpage accesses
- DMA and PIO
This controller was originally provided by Evatronix before being bought by Cadence.
--- drivers/mtd/nand/raw/Kconfig | 6 + drivers/mtd/nand/raw/Makefile | 1 + drivers/mtd/nand/raw/rzn1-nand-controller.c | 1422 +++++++++++++++++++ 3 files changed, 1429 insertions(+) create mode 100644 drivers/mtd/nand/raw/rzn1-nand-controller.c
drivers/mtd/nand/raw/Kconfig +6 -0
@@ -461,6 +461,12 @@ config MTD_NAND_PL35X Enables support for PrimeCell SMC PL351 and PL353 NAND controller found on Zynq7000. +config MTD_NAND_RZN1 + tristate "Renesas RZ/N1D, RZ/N1S, RZ/N1L NAND controller" + depends on ARCH_RENESAS || COMPILE_TEST + help + Enables support for Renesas RZ/N1x SoC family NAND controller. + comment "Misc" config MTD_SM_COMMON
drivers/mtd/nand/raw/Makefile +1 -0
@@ -58,6 +58,7 @@ obj-$(CONFIG_MTD_NAND_ARASAN) += arasan-nand-controller.o obj-$(CONFIG_MTD_NAND_INTEL_LGM) += intel-nand-controller.o obj-$(CONFIG_MTD_NAND_ROCKCHIP) += rockchip-nand-controller.o obj-$(CONFIG_MTD_NAND_PL35X) += pl35x-nand-controller.o +obj-$(CONFIG_MTD_NAND_RZN1) += rzn1-nand-controller.o nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o nand-objs += nand_onfi.o
drivers/mtd/nand/raw/rzn1-nand-controller.c new file +1422 -0
1,422 lines not on this page · raw message
Signature · 6 lines
2.27.0 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
kernel test robot
build botRe: [PATCH v4 2/4] mtd: rawnand: rzn1: Add new NAND controller driver
I love your patch! Yet something to improve:
Hi Miquel,
I love your patch! Yet something to improve:
[auto build test ERROR on mtd/nand/next]
[also build test ERROR on geert-renesas-devel/next mtd/mtd/next mtd/mtd/fixes linus/master v5.16-rc5 next-20211214] [If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Miquel-Raynal/Renesas-RZ-N1-NAND-controller-support/20211215-234825 base: https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next config: sh-allmodconfig (https://download.01.org/0day-ci/archive/20211216/202112160417.TvfPZeKJ-lkp(a)intel.com/config) compiler: sh4-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/4899a382aebedd2033aba1a8c662767c86c8d74d
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Miquel-Raynal/Renesas-RZ-N1-NAND-controller-support/20211215-234825 git checkout 4899a382aebedd2033aba1a8c662767c86c8d74d
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=sh SHELL=/bin/bash drivers/mtd/nand/raw/
If you fix the issue, kindly add following tag as appropriate
All errors (new ones prefixed by >>):
In file included from drivers/mtd/nand/raw/rzn1-nand-controller.c:14:
>> drivers/mtd/nand/raw/rzn1-nand-controller.c:1408:25: error: 'nandc_id_table' undeclared here (not in a function); did you mean 'rzn1_nandc_id_table'?
1408 | MODULE_DEVICE_TABLE(of, nandc_id_table);
| ^~~~~~~~~~~~~~
include/linux/module.h:244:15: note: in definition of macro 'MODULE_DEVICE_TABLE'
244 | extern typeof(name) __mod_##type##__##name##_device_table \
| ^~~~
>> include/linux/module.h:244:21: error: '__mod_of__nandc_id_table_device_table' aliased to undefined symbol 'nandc_id_table'
244 | extern typeof(name) __mod_##type##__##name##_device_table \
| ^~~~~~
drivers/mtd/nand/raw/rzn1-nand-controller.c:1408:1: note: in expansion of macro 'MODULE_DEVICE_TABLE'
1408 | MODULE_DEVICE_TABLE(of, nandc_id_table);
| ^~~~~~~~~~~~~~~~~~~vim +1408 drivers/mtd/nand/raw/rzn1-nand-controller.c
1403
1404 static const struct of_device_id rzn1_nandc_id_table[] = {
1405 { .compatible = "renesas,rzn1-nand-controller" },
1406 {} /* sentinel */
1407 };
> 1408 MODULE_DEVICE_TABLE(of, nandc_id_table);
1409
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
Miquel Raynal
maintainerPATCH v4 3/4 MAINTAINERS: Add an entry for Renesas RZ/N1 NAND controller
In reply to Miquel RaynalPoint to the driver and the bindings.
--- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+)
MAINTAINERS +7 -0
@@ -16287,6 +16287,13 @@ S: Supported F: Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml F: drivers/iio/adc/rzg2l_adc.c +RENESAS RZ/N1X NAND CONTROLLER DRIVER +M: Miquel Raynal <[email protected]> +L: [email protected] +S: Maintained +F: Documentation/devicetree/bindings/mtd/renesas,rzn1-nand-controller.yaml +F: drivers/mtd/nand/raw/rzn1-nand-controller.c + RESET CONTROLLER FRAMEWORK M: Philipp Zabel <[email protected]> S: Maintained
Signature · 6 lines
2.27.0 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
Miquel Raynal
maintainerPATCH v4 4/4 ARM: dts: r9a06g032: Describe NAND controller
In reply to Miquel RaynalDescribe the NAND controller contained in r9a06g032 SoCs.
--- arch/arm/boot/dts/r9a06g032.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+)
arch/arm/boot/dts/r9a06g032.dtsi +12 -0
@@ -173,6 +173,18 @@ pinctrl: pinctrl@40067000 { status = "okay"; }; + nand_controller: nand-controller@40102000 { + compatible = "renesas,r9a06g032-nand-controller", + "renesas,rzn1-nand-controller"; + reg = <0x40102000 0x2000>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysctrl R9A06G032_HCLK_NAND>, <&sysctrl R9A06G032_CLK_NAND>; + clock-names = "hclk", "eclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@44101000 { compatible = "arm,gic-400", "arm,cortex-a7-gic"; interrupt-controller;
Signature · 6 lines
2.27.0 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
Re: [PATCH v4 4/4] ARM: dts: r9a06g032: Describe NAND controller
Quoted 3 lines · Miquel Raynal
Describe the NAND controller contained in r9a06g032 SoCs.
Signed-off-by Miquel Raynal <[email protected]>
i.e. will queue in renesas-devel once the bindings have been accepted in linux-next.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH v4 0/4] Renesas RZ/N1 NAND controller support
In reply to Miquel RaynalQuoted 6 lines · Geert Uytterhoeven
From: Miquel Raynal <[email protected]>
Hello,
Here is a short series bringing support for Renesas RZ/N1 NAND controller.
Oops, please ignore this email. Sorry for the noise.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH v4 0/4] Renesas RZ/N1 NAND controller support
In reply to Miquel RaynalQuoted 6 lines · Geert Uytterhoeven
From: Miquel Raynal <[email protected]>
Hello,
Here is a short series bringing support for Renesas RZ/N1 NAND controller.
Oops, please ignore this email. Sorry for the noise.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Re: [PATCH v4 0/4] Renesas RZ/N1 NAND controller support
In reply to Miquel RaynalQuoted 7 lines · Geert Uytterhoeven
From: Miquel Raynal <[email protected]>
Hello,
Here is a short series bringing support for Renesas RZ/N1 NAND controller.
Oops, please ignore this email. Sorry for the noise.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
v2 cover riscv: dts: Miscellaneous fixes
Hi Paul, Palmer, Albert,
This patch series contains miscellaneous fixes for the DTS files for RISC-V platforms.
Changes compared to v1[1]:
- Add Reviewed-by, Tested-by,
- Move mpfs refclk clock-frequency to board DTS,
- New patches "[PATCH v2 06/11] riscv: dts: microchip: mpfs: Fix clock controller node" and "[PATCH v2 11/11] riscv: dts: sifive:
fu540-c000: Fix PLIC node".
Thanks for applying!
[1] https://lore.kernel.org/r/[email protected]
Geert Uytterhoeven (11):
riscv: dts: canaan: Fix SPI FLASH node names
riscv: dts: canaan: Group tuples in interrupt properties
riscv: dts: microchip: mpfs: Drop empty chosen node
riscv: dts: microchip: mpfs: Fix PLIC node
riscv: dts: microchip: mpfs: Fix reference clock node
riscv: dts: microchip: mpfs: Fix clock controller node
riscv: dts: microchip: mpfs: Group tuples in interrupt properties
riscv: dts: sifive: Group tuples in interrupt properties
riscv: dts: sifive: Group tuples in register properties
riscv: dts: sifive: fu540-c000: Drop bogus soc node compatible values
riscv: dts: sifive: fu540-c000: Fix PLIC node
arch/riscv/boot/dts/canaan/k210.dtsi | 23 +++---- .../riscv/boot/dts/canaan/sipeed_maix_bit.dts | 2 +- .../boot/dts/canaan/sipeed_maix_dock.dts | 2 +- arch/riscv/boot/dts/canaan/sipeed_maix_go.dts | 2 +- .../boot/dts/canaan/sipeed_maixduino.dts | 2 +- .../microchip/microchip-mpfs-icicle-kit.dts | 4 ++ .../boot/dts/microchip/microchip-mpfs.dtsi | 60 ++++++++----------- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 40 +++++++------ arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 14 ++--- 9 files changed, 72 insertions(+), 77 deletions(-)
Signature · 12 lines
2.25.1
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus TorvaldsPATCH v2 1/11 riscv: dts: canaan: Fix SPI FLASH node names
"make dtbs_check":
arch/riscv/boot/dts/canaan/sipeed_maix_bit.dt.yaml: spi-flash@0: $nodename:0: 'spi-flash@0' does not match '^flash(@.*)?$'
From schema: Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
Fix this by renaming all SPI FLASH nodes to "flash".
---
v2:
- Add Reviewed-by, Tested-by.
--- arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts | 2 +- arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts | 2 +- arch/riscv/boot/dts/canaan/sipeed_maix_go.dts | 2 +- arch/riscv/boot/dts/canaan/sipeed_maixduino.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-)
arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts +1 -1
@@ -199,7 +199,7 @@ slot@0 { }; &spi3 { - spi-flash@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <50000000>;
arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts +1 -1
@@ -201,7 +201,7 @@ slot@0 { }; &spi3 { - spi-flash@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <50000000>;
arch/riscv/boot/dts/canaan/sipeed_maix_go.dts +1 -1
@@ -209,7 +209,7 @@ slot@0 { }; &spi3 { - spi-flash@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <50000000>;
arch/riscv/boot/dts/canaan/sipeed_maixduino.dts +1 -1
@@ -174,7 +174,7 @@ slot@0 { }; &spi3 { - spi-flash@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <50000000>;
Signature · 1 line
2.25.1
PATCH v2 2/11 riscv: dts: canaan: Group tuples in interrupt properties
In reply to Geert UytterhoevenTo improve human readability and enable automatic validation, the tuples in the various properties containing interrupt specifiers should be grouped.
Fix this by grouping the tuples of "interrupts" and "interrupts-extended" properties using angle brackets.
---
v2:
- Add Reviewed-by, Tested-by.
--- arch/riscv/boot/dts/canaan/k210.dtsi | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-)
arch/riscv/boot/dts/canaan/k210.dtsi +12 -11
@@ -103,8 +103,8 @@ rom0: nvmem@1000 { clint0: timer@2000000 { compatible = "canaan,k210-clint", "sifive,clint0"; reg = <0x2000000 0xC000>; - interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 - &cpu1_intc 3 &cpu1_intc 7>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>; }; plic0: interrupt-controller@c000000 {
@@ -113,7 +113,7 @@ plic0: interrupt-controller@c000000 { compatible = "canaan,k210-plic", "sifive,plic-1.0.0"; reg = <0xC000000 0x4000000>; interrupt-controller; - interrupts-extended = <&cpu0_intc 11 &cpu1_intc 11>; + interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>; riscv,ndev = <65>; };
@@ -130,10 +130,11 @@ gpio0: gpio-controller@38001000 { compatible = "canaan,k210-gpiohs", "sifive,gpio0"; reg = <0x38001000 0x1000>; interrupt-controller; - interrupts = <34 35 36 37 38 39 40 41 - 42 43 44 45 46 47 48 49 - 50 51 52 53 54 55 56 57 - 58 59 60 61 62 63 64 65>; + interrupts = <34>, <35>, <36>, <37>, <38>, <39>, <40>, + <41>, <42>, <43>, <44>, <45>, <46>, <47>, + <48>, <49>, <50>, <51>, <52>, <53>, <54>, + <55>, <56>, <57>, <58>, <59>, <60>, <61>, + <62>, <63>, <64>, <65>; gpio-controller; ngpios = <32>; };
@@ -141,7 +142,7 @@ gpio0: gpio-controller@38001000 { dmac0: dma-controller@50000000 { compatible = "snps,axi-dma-1.01a"; reg = <0x50000000 0x1000>; - interrupts = <27 28 29 30 31 32>; + interrupts = <27>, <28>, <29>, <30>, <31>, <32>; #dma-cells = <1>; clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>; clock-names = "core-clk", "cfgr-clk";
@@ -316,7 +317,7 @@ fpioa: pinmux@502b0000 { timer0: timer@502d0000 { compatible = "snps,dw-apb-timer"; reg = <0x502D0000 0x100>; - interrupts = <14 15>; + interrupts = <14>, <15>; clocks = <&sysclk K210_CLK_TIMER0>, <&sysclk K210_CLK_APB0>; clock-names = "timer", "pclk";
@@ -326,7 +327,7 @@ timer0: timer@502d0000 { timer1: timer@502e0000 { compatible = "snps,dw-apb-timer"; reg = <0x502E0000 0x100>; - interrupts = <16 17>; + interrupts = <16>, <17>; clocks = <&sysclk K210_CLK_TIMER1>, <&sysclk K210_CLK_APB0>; clock-names = "timer", "pclk";
@@ -336,7 +337,7 @@ timer1: timer@502e0000 { timer2: timer@502f0000 { compatible = "snps,dw-apb-timer"; reg = <0x502F0000 0x100>; - interrupts = <18 19>; + interrupts = <18>, <19>; clocks = <&sysclk K210_CLK_TIMER2>, <&sysclk K210_CLK_APB0>; clock-names = "timer", "pclk";
Signature · 1 line
2.25.1
PATCH v2 3/11 riscv: dts: microchip: mpfs: Drop empty chosen node
In reply to Geert UytterhoevenIt does not make sense to have an (empty) chosen node in an SoC-specific .dtsi, as chosen is meant for system-specific configuration. It is already provided in microchip-mpfs-icicle-kit.dts anyway.
---
v2:
- Add Reviewed-by.
--- arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 3 --- 1 file changed, 3 deletions(-)
arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +0 -3
@@ -9,9 +9,6 @@ / { model = "Microchip PolarFire SoC"; compatible = "microchip,mpfs"; - chosen { - }; - cpus { #address-cells = <1>; #size-cells = <0>;
Signature · 1 line
2.25.1
PATCH v2 4/11 riscv: dts: microchip: mpfs: Fix PLIC node
In reply to Geert UytterhoevenFix the device node for the Platform-Level Interrupt Controller (PLIC):
- Add missing "#address-cells" property,
- Sort properties according to DT bindings.
---
v2:
- Add Reviewed-by.
--- arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +3 -2
@@ -168,16 +168,17 @@ &cpu3_intc 3 &cpu3_intc 7 }; plic: interrupt-controller@c000000 { - #interrupt-cells = <1>; compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; reg = <0x0 0xc000000 0x0 0x4000000>; - riscv,ndev = <186>; + #address-cells = <0>; + #interrupt-cells = <1>; interrupt-controller; interrupts-extended = <&cpu0_intc 11 &cpu1_intc 11 &cpu1_intc 9 &cpu2_intc 11 &cpu2_intc 9 &cpu3_intc 11 &cpu3_intc 9 &cpu4_intc 11 &cpu4_intc 9>; + riscv,ndev = <186>; }; dma@3000000 {
Signature · 1 line
2.25.1
PATCH v2 5/11 riscv: dts: microchip: mpfs: Fix reference clock node
In reply to Geert Uytterhoeven"make dtbs_check" reports:
arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dt.yaml: soc: refclk: {'compatible': ['fixed-clock'], '#clock-cells': [[0]], 'clock-frequency': [[600000000]], 'clock-output-names': ['msspllclk'], 'phandle': [[7]]} should not be valid under {'type': 'object'}
From schema: dtschema/schemas/simple-bus.yaml
Fix this by moving the node out of the "soc" subnode.
While at it, rename it to "msspllclk", and drop the now superfluous "clock-output-names" property.
Move the actual clock-frequency value to the board DTS, since it is not set until bitstream programming time.
---
v2:
- Add Acked-by,
- Move clock-frequency to board DTS.
--- .../boot/dts/microchip/microchip-mpfs-icicle-kit.dts | 4 ++++ arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 12 +++++------- 2 files changed, 9 insertions(+), 7 deletions(-)
arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts +4 -0
@@ -35,6 +35,10 @@ memory@80000000 { }; }; +&refclk { + clock-frequency = <600000000>; +}; + &serial0 { status = "okay"; };
arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +5 -7
@@ -139,6 +139,11 @@ cpu4_intc: interrupt-controller { }; }; + refclk: msspllclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + soc { #address-cells = <2>; #size-cells = <2>;
@@ -189,13 +194,6 @@ dma@3000000 { #dma-cells = <1>; }; - refclk: refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <600000000>; - clock-output-names = "msspllclk"; - }; - clkcfg: clkcfg@20002000 { compatible = "microchip,mpfs-clkcfg"; reg = <0x0 0x20002000 0x0 0x1000>;
Signature · 1 line
2.25.1
Re: [PATCH v2 05/11] riscv: dts: microchip: mpfs: Fix reference clock node
Quoted 7 lines · Geert Uytterhoeven
EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
"make
dtbs_check" reports:
arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dt.yaml: soc: refclk: {'compatible': ['fixed-clock'], '#clock-cells': [[0]], 'clock-frequency': [[600000000]], 'clock-output-names': ['msspllclk'], 'phandle': [[7]]} should not be valid under {'type': 'object'}
From schema:dtschema/schemas/simple-bus.yaml
Quoted 8 lines
Fix this by moving the node out of the "soc" subnode.
While at it, rename it to "msspllclk", and drop the now superfluous "clock-output-names" property.
Move the actual clock-frequency value to the board DTS, since it is not set until bitstream programming time.Signed-off-by Geert Uytterhoeven <[email protected]>
Looks good to me.
Quoted 57 lines
---
v2:
- Add Acked-by,
- Move clock-frequency to board DTS.--- .../boot/dts/microchip/microchip-mpfs-icicle-kit.dts | 4 ++++ arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 12 +++++------- 2 files changed, 9 insertions(+), 7 deletions(-)arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts +4
-0@@ -35,6 +35,10 @@ memory@80000000 { }; }; +&refclk { + clock-frequency = <600000000>; +}; + &serial0 { status = "okay"; };arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +5
-8@@ -139,6 +139,11 @@ cpu4_intc: interrupt-controller { }; }; + refclk: msspllclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + soc { #address-cells = <2>; #size-cells = <2>;@@ -189,13 +194,6 @@ dma@3000000 { #dma-cells = <1>; }; - refclk: refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <600000000>; - clock-output-names = "msspllclk"; - }; - clkcfg: clkcfg@20002000 { compatible = "microchip,mpfs-clkcfg"; reg = <0x0 0x20002000 0x0 0x1000>; --2.25.1
PATCH v2 6/11 riscv: dts: microchip: mpfs: Fix clock controller node
In reply to Geert UytterhoevenFix the device node for the clock controller:
- Remove bogus "reg-names" property,
- Remove unneeded "clock-output-names" property.
---
v2:
- New.
--- arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 9 --------- 1 file changed, 9 deletions(-)
arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +0 -9
@@ -197,17 +197,8 @@ dma@3000000 { clkcfg: clkcfg@20002000 { compatible = "microchip,mpfs-clkcfg"; reg = <0x0 0x20002000 0x0 0x1000>; - reg-names = "mss_sysreg"; clocks = <&refclk>; #clock-cells = <1>; - clock-output-names = "cpu", "axi", "ahb", "envm", /* 0-3 */ - "mac0", "mac1", "mmc", "timer", /* 4-7 */ - "mmuart0", "mmuart1", "mmuart2", "mmuart3", /* 8-11 */ - "mmuart4", "spi0", "spi1", "i2c0", /* 12-15 */ - "i2c1", "can0", "can1", "usb", /* 16-19 */ - "rsvd", "rtc", "qspi", "gpio0", /* 20-23 */ - "gpio1", "gpio2", "ddrc", "fic0", /* 24-27 */ - "fic1", "fic2", "fic3", "athena", "cfm"; /* 28-32 */ }; serial0: serial@20000000 {
Signature · 1 line
2.25.1
Re: [PATCH v2 06/11] riscv: dts: microchip: mpfs: Fix clock controller node
Quoted 7 lines · Geert Uytterhoeven
EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
Fix the device node for the clock controller:
- Remove bogus "reg-names" property,
- Remove unneeded "clock-output-names" property.Signed-off-by Geert Uytterhoeven <[email protected]>
Ha, doing my job for me again - was hoping to send my v2 tomorrow too so good timing on your part.
(I have booted the 5 patches for the polarfire on my board, so
Quoted 32 lines
---
v2:
- New.--- arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 9 --------- 1 file changed, 9 deletions(-)arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +0
-10@@ -197,17 +197,8 @@ dma@3000000 { clkcfg: clkcfg@20002000 { compatible = "microchip,mpfs-clkcfg"; reg = <0x0 0x20002000 0x0 0x1000>; - reg-names = "mss_sysreg"; clocks = <&refclk>; #clock-cells = <1>; - clock-output-names = "cpu", "axi", "ahb", "envm", /* 0-3 */ - "mac0", "mac1", "mmc", "timer", /* 4-7 */ - "mmuart0", "mmuart1", "mmuart2", "mmuart3", /* 8-11 */ - "mmuart4", "spi0", "spi1", "i2c0", /* 12-15 */ - "i2c1", "can0", "can1", "usb", /* 16-19 */ - "rsvd", "rtc", "qspi", "gpio0", /* 20-23 */ - "gpio1", "gpio2", "ddrc", "fic0", /* 24-27 */ - "fic1", "fic2", "fic3", "athena", "cfm"; /* 28-32 */ }; serial0: serial@20000000 { --2.25.1
PATCH v2 7/11 riscv: dts: microchip: mpfs: Group tuples in interrupt properties
In reply to Geert UytterhoevenTo improve human readability and enable automatic validation, the tuples in the various properties containing interrupt specifiers should be grouped.
Fix this by grouping the tuples of "interrupts" and "interrupts-extended" properties using angle brackets.
---
v2:
- Add Reviewed-by.
--- .../boot/dts/microchip/microchip-mpfs.dtsi | 31 ++++++++++--------- 1 file changed, 16 insertions(+), 15 deletions(-)
arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +16 -15
@@ -158,18 +158,18 @@ cache-controller@2010000 { cache-size = <2097152>; cache-unified; interrupt-parent = <&plic>; - interrupts = <1 2 3>; + interrupts = <1>, <2>, <3>; reg = <0x0 0x2010000 0x0 0x1000>; }; clint@2000000 { compatible = "sifive,fu540-c000-clint", "sifive,clint0"; reg = <0x0 0x2000000 0x0 0xC000>; - interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 - &cpu1_intc 3 &cpu1_intc 7 - &cpu2_intc 3 &cpu2_intc 7 - &cpu3_intc 3 &cpu3_intc 7 - &cpu4_intc 3 &cpu4_intc 7>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>, + <&cpu4_intc 3>, <&cpu4_intc 7>; }; plic: interrupt-controller@c000000 {
@@ -178,11 +178,11 @@ plic: interrupt-controller@c000000 { #address-cells = <0>; #interrupt-cells = <1>; interrupt-controller; - interrupts-extended = <&cpu0_intc 11 - &cpu1_intc 11 &cpu1_intc 9 - &cpu2_intc 11 &cpu2_intc 9 - &cpu3_intc 11 &cpu3_intc 9 - &cpu4_intc 11 &cpu4_intc 9>; + interrupts-extended = <&cpu0_intc 11>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>, + <&cpu4_intc 11>, <&cpu4_intc 9>; riscv,ndev = <186>; };
@@ -190,7 +190,8 @@ dma@3000000 { compatible = "sifive,fu540-c000-pdma"; reg = <0x0 0x3000000 0x0 0x8000>; interrupt-parent = <&plic>; - interrupts = <23 24 25 26 27 28 29 30>; + interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, + <30>; #dma-cells = <1>; };
@@ -254,7 +255,7 @@ mmc: mmc@20008000 { compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc"; reg = <0x0 0x20008000 0x0 0x1000>; interrupt-parent = <&plic>; - interrupts = <88 89>; + interrupts = <88>, <89>; clocks = <&clkcfg 6>; max-frequency = <200000000>; status = "disabled";
@@ -264,7 +265,7 @@ emac0: ethernet@20110000 { compatible = "cdns,macb"; reg = <0x0 0x20110000 0x0 0x2000>; interrupt-parent = <&plic>; - interrupts = <64 65 66 67>; + interrupts = <64>, <65>, <66>, <67>; local-mac-address = [00 00 00 00 00 00]; clocks = <&clkcfg 4>, <&clkcfg 2>; clock-names = "pclk", "hclk";
@@ -277,7 +278,7 @@ emac1: ethernet@20112000 { compatible = "cdns,macb"; reg = <0x0 0x20112000 0x0 0x2000>; interrupt-parent = <&plic>; - interrupts = <70 71 72 73>; + interrupts = <70>, <71>, <72>, <73>; local-mac-address = [00 00 00 00 00 00]; clocks = <&clkcfg 5>, <&clkcfg 2>; status = "disabled";
Signature · 1 line
2.25.1
PATCH v2 8/11 riscv: dts: sifive: Group tuples in interrupt properties
In reply to Geert UytterhoevenTo improve human readability and enable automatic validation, the tuples in the various properties containing interrupt specifiers should be grouped.
Fix this by grouping the tuples of "interrupts" and "interrupts-extended" properties using angle brackets.
---
v2:
- Add Reviewed-by.
--- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 21 +++++++++++---------- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 14 +++++++------- 2 files changed, 18 insertions(+), 17 deletions(-)
arch/riscv/boot/dts/sifive/fu540-c000.dtsi +11 -10
@@ -145,12 +145,12 @@ plic0: interrupt-controller@c000000 { reg = <0x0 0xc000000 0x0 0x4000000>; riscv,ndev = <53>; interrupt-controller; - interrupts-extended = < - &cpu0_intc 0xffffffff - &cpu1_intc 0xffffffff &cpu1_intc 9 - &cpu2_intc 0xffffffff &cpu2_intc 9 - &cpu3_intc 0xffffffff &cpu3_intc 9 - &cpu4_intc 0xffffffff &cpu4_intc 9>; + interrupts-extended = + <&cpu0_intc 0xffffffff>, + <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>, + <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>, + <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>, + <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>; }; prci: clock-controller@10000000 { compatible = "sifive,fu540-c000-prci";
@@ -170,7 +170,8 @@ dma: dma@3000000 { compatible = "sifive,fu540-c000-pdma"; reg = <0x0 0x3000000 0x0 0x8000>; interrupt-parent = <&plic0>; - interrupts = <23 24 25 26 27 28 29 30>; + interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, + <30>; #dma-cells = <1>; }; uart1: serial@10011000 {
@@ -243,7 +244,7 @@ pwm0: pwm@10020000 { compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; reg = <0x0 0x10020000 0x0 0x1000>; interrupt-parent = <&plic0>; - interrupts = <42 43 44 45>; + interrupts = <42>, <43>, <44>, <45>; clocks = <&prci PRCI_CLK_TLCLK>; #pwm-cells = <3>; status = "disabled";
@@ -252,7 +253,7 @@ pwm1: pwm@10021000 { compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; reg = <0x0 0x10021000 0x0 0x1000>; interrupt-parent = <&plic0>; - interrupts = <46 47 48 49>; + interrupts = <46>, <47>, <48>, <49>; clocks = <&prci PRCI_CLK_TLCLK>; #pwm-cells = <3>; status = "disabled";
@@ -265,7 +266,7 @@ l2cache: cache-controller@2010000 { cache-size = <2097152>; cache-unified; interrupt-parent = <&plic0>; - interrupts = <1 2 3>; + interrupts = <1>, <2>, <3>; reg = <0x0 0x2010000 0x0 0x1000>; }; gpio: gpio@10060000 {
arch/riscv/boot/dts/sifive/fu740-c000.dtsi +7 -7
@@ -147,12 +147,12 @@ plic0: interrupt-controller@c000000 { reg = <0x0 0xc000000 0x0 0x4000000>; riscv,ndev = <69>; interrupt-controller; - interrupts-extended = < - &cpu0_intc 0xffffffff - &cpu1_intc 0xffffffff &cpu1_intc 9 - &cpu2_intc 0xffffffff &cpu2_intc 9 - &cpu3_intc 0xffffffff &cpu3_intc 9 - &cpu4_intc 0xffffffff &cpu4_intc 9>; + interrupts-extended = + <&cpu0_intc 0xffffffff>, + <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>, + <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>, + <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>, + <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>; }; prci: clock-controller@10000000 { compatible = "sifive,fu740-c000-prci";
@@ -273,7 +273,7 @@ ccache: cache-controller@2010000 { cache-size = <2097152>; cache-unified; interrupt-parent = <&plic0>; - interrupts = <19 21 22 20>; + interrupts = <19>, <21>, <22>, <20>; reg = <0x0 0x2010000 0x0 0x1000>; }; gpio: gpio@10060000 {
Signature · 1 line
2.25.1
PATCH v2 9/11 riscv: dts: sifive: Group tuples in register properties
In reply to Geert UytterhoevenTo improve human readability and enable automatic validation, the tuples in "reg" properties containing register blocks should be grouped using angle brackets.
---
v2:
- Add Reviewed-by.
--- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)
arch/riscv/boot/dts/sifive/fu540-c000.dtsi +6 -6
@@ -196,8 +196,8 @@ i2c0: i2c@10030000 { }; qspi0: spi@10040000 { compatible = "sifive,fu540-c000-spi", "sifive,spi0"; - reg = <0x0 0x10040000 0x0 0x1000 - 0x0 0x20000000 0x0 0x10000000>; + reg = <0x0 0x10040000 0x0 0x1000>, + <0x0 0x20000000 0x0 0x10000000>; interrupt-parent = <&plic0>; interrupts = <51>; clocks = <&prci PRCI_CLK_TLCLK>;
@@ -207,8 +207,8 @@ qspi0: spi@10040000 { }; qspi1: spi@10041000 { compatible = "sifive,fu540-c000-spi", "sifive,spi0"; - reg = <0x0 0x10041000 0x0 0x1000 - 0x0 0x30000000 0x0 0x10000000>; + reg = <0x0 0x10041000 0x0 0x1000>, + <0x0 0x30000000 0x0 0x10000000>; interrupt-parent = <&plic0>; interrupts = <52>; clocks = <&prci PRCI_CLK_TLCLK>;
@@ -230,8 +230,8 @@ eth0: ethernet@10090000 { compatible = "sifive,fu540-c000-gem"; interrupt-parent = <&plic0>; interrupts = <53>; - reg = <0x0 0x10090000 0x0 0x2000 - 0x0 0x100a0000 0x0 0x1000>; + reg = <0x0 0x10090000 0x0 0x2000>, + <0x0 0x100a0000 0x0 0x1000>; local-mac-address = [00 00 00 00 00 00]; clock-names = "pclk", "hclk"; clocks = <&prci PRCI_CLK_GEMGXLPLL>,
Signature · 1 line
2.25.1
PATCH v2 10/11 riscv: dts: sifive: fu540-c000: Drop bogus soc node compatible values
In reply to Geert Uytterhoeven"make dtbs_check":
arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml: soc: $nodename:0: '/' was expected
From schema: Documentation/devicetree/bindings/riscv/sifive.yaml
arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml: soc: compatible: 'oneOf' conditional failed, one must be fixed:
'sifive,fu540-c000' is not one of ['sifive,hifive-unleashed-a00']
'sifive,fu540-c000' is not one of ['sifive,hifive-unmatched-a00']
'sifive,fu540-c000' was expected
'sifive,fu740-c000' was expected
'sifive,fu540' was expected
'sifive,fu740' was expected
From schema: Documentation/devicetree/bindings/riscv/sifive.yaml
This happens because the "soc" subnode declares compatibility with "sifive,fu540-c000" and "sifive,fu540", while these are only intended for the root node.
Fix this by removing the bogus compatible values from the "soc" node.
---
v2:
- Add Reviewed-by.
--- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/riscv/boot/dts/sifive/fu540-c000.dtsi +1 -1
@@ -137,7 +137,7 @@ cpu4_intc: interrupt-controller { soc { #address-cells = <2>; #size-cells = <2>; - compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus"; + compatible = "simple-bus"; ranges; plic0: interrupt-controller@c000000 { #interrupt-cells = <1>;
Signature · 1 line
2.25.1
PATCH v2 11/11 riscv: dts: sifive: fu540-c000: Fix PLIC node
In reply to Geert UytterhoevenFix the device node for the Platform-Level Interrupt Controller (PLIC):
- Add missing "#address-cells" property,
- Sort properties according to DT bindings.
---
v2:
- New.
--- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
arch/riscv/boot/dts/sifive/fu540-c000.dtsi +3 -2
@@ -140,10 +140,10 @@ soc { compatible = "simple-bus"; ranges; plic0: interrupt-controller@c000000 { - #interrupt-cells = <1>; compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; reg = <0x0 0xc000000 0x0 0x4000000>; - riscv,ndev = <53>; + #address-cells = <0>; + #interrupt-cells = <1>; interrupt-controller; interrupts-extended = <&cpu0_intc 0xffffffff>,
@@ -151,6 +151,7 @@ plic0: interrupt-controller@c000000 { <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>, <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>, <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>; + riscv,ndev = <53>; }; prci: clock-controller@10000000 { compatible = "sifive,fu540-c000-prci";
Signature · 1 line
2.25.1
v2 cover dt-bindings: interrupt-controller: sifive,plic: Miscellaneous improvements
Hi all,
This patch series contains two improvements for the SiFive PLIC DT bindings.
Changes compared to v1[1]:
- Split in two patches,
- Improve patch description and document limit rationale.
Thanks!
[1] https://lore.kernel.org/r/[email protected]
Geert Uytterhoeven (2):
dt-bindings: interrupt-controller: sifive,plic: Fix number of
interrupts
dt-bindings: interrupt-controller: sifive,plic: Group interrupt tuples
.../interrupt-controller/sifive,plic-1.0.0.yaml | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)
Signature · 12 lines
2.25.1
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus TorvaldsPATCH v2 1/2 dt-bindings: interrupt-controller: sifive,plic: Fix number of interrupts
The number of interrupts lacks an upper bound, thus assuming one, causing properly grouped "interrupts-extended" properties to be flagged as an error by "make dtbs_check".
Fix this by adding the missing "maxItems". As the architectural maximum is 15872 interrupts, using that as the limit would be unpractical. Hence limit it to 9 interrupts (one interrupt for a system management core, and two interrupts per core for other cores). This should be sufficient for now, and the limit can always be increased when the need arises.
---
v2:
- Split in two patches,
- Improve patch description and document limit rationale.
--- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +1 -0
@@ -62,6 +62,7 @@ properties: interrupts-extended: minItems: 1 + maxItems: 9 description: Specifies which contexts are connected to the PLIC, with "-1" specifying that a context is not present. Each node pointed to should be a
Signature · 1 line
2.25.1
Re: [PATCH v2 1/2] dt-bindings: interrupt-controller: sifive,plic: Fix number of interrupts
Quoted 11 lines · Geert Uytterhoeven
The number of interrupts lacks an upper bound, thus assuming one, causing properly grouped "interrupts-extended" properties to be flagged as an error by "make
dtbs_check".Fix this by adding the missing "maxItems". As the architectural maximum is 15872 interrupts, using that as the limit would be unpractical. Hence limit it to 9 interrupts (one interrupt for a system management core, and two interrupts per core for other cores). This should be sufficient for now, and the limit can always be increased when the need arises.
Quoted 9 lines
Signed-off-by Geert Uytterhoeven <[email protected]>---
v2:
- Split in two patches,
- Improve patch description and document limit rationale.--- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 + 1 file changed, 1 insertion(+)
PATCH v2 2/2 dt-bindings: interrupt-controller: sifive,plic: Group interrupt tuples
In reply to Geert UytterhoevenTo improve human readability and enable automatic validation, the tuples in "interrupts-extended" properties should be grouped using angle brackets.
---
v2:
- Split in two patches.
--- .../interrupt-controller/sifive,plic-1.0.0.yaml | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-)
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +5 -6
@@ -91,12 +91,11 @@ examples: #interrupt-cells = <1>; compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; interrupt-controller; - interrupts-extended = < - &cpu0_intc 11 - &cpu1_intc 11 &cpu1_intc 9 - &cpu2_intc 11 &cpu2_intc 9 - &cpu3_intc 11 &cpu3_intc 9 - &cpu4_intc 11 &cpu4_intc 9>; + interrupts-extended = <&cpu0_intc 11>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>, + <&cpu4_intc 11>, <&cpu4_intc 9>; reg = <0xc000000 0x4000000>; riscv,ndev = <10>; };
Signature · 1 line
2.25.1
Re: [PATCH v2 2/2] dt-bindings: interrupt-controller: sifive,plic: Group interrupt tuples
Quoted 4 lines · Geert Uytterhoeven
To improve human readability and enable automatic validation, the tuples in "interrupts-extended" properties should be grouped using angle brackets.
Quoted 8 lines
Signed-off-by Geert Uytterhoeven <[email protected]>---
v2:
- Split in two patches.--- .../interrupt-controller/sifive,plic-1.0.0.yaml | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-)
Rob Herring
maintainerRe: [PATCH v2 0/2] dt-bindings: interrupt-controller: sifive,plic: Miscellaneous improvements
In reply to Geert Uytterhoeven+ Konstantin
Quoted 4 lines · Geert Uytterhoeven
Hi all,
This patch series contains two improvements for the SiFive PLIC DT bindings.
Lore is thoroughly confused with this and several other series. It seems to be doing subject matching and pretty loosely.
Rob
Quoted 31 lines
Changes compared to v1[1]:
- Split in two patches,
- Improve patch description and document limit rationale.Thanks!
[1] https://lore.kernel.org/r/[email protected]
Geert Uytterhoeven (2):
dt-bindings: interrupt-controller: sifive,plic: Fix number of
interrupts
dt-bindings: interrupt-controller: sifive,plic: Group interrupt tuples.../interrupt-controller/sifive,plic-1.0.0.yaml | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)Signature · 12 lines
2.25.1 Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected] In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Re: [PATCH v2 0/2] dt-bindings: interrupt-controller: sifive,plic: Miscellaneous improvements
Hi Rob,
Quoted 6 lines · Rob Herring
Quoted 2 lines · Geert Uytterhoeven
This patch series contains two improvements for the SiFive PLIC DT bindings.
Lore is thoroughly confused with this and several other series. It seems to be doing subject matching and pretty loosely.
My apologies, that's purely due to a silly mistake on my side. I sent out 3 patch series without noticing I still had two cover letters from previous "b4 am" sessions in my working dir, so they were mailed out as part of the series, too :-(
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
v2 cover dt-bindings: timer: sifive,clint: Miscellaneous improvements
Hi all,
This patch series contains two improvements for the SiFive PLIC DT bindings.
Changes compared to v1[1]:
- Split in two patches,
- Improve patch description and document limit rationale.
Thanks!
[1] https://lore.kernel.org/r/[email protected]
Geert Uytterhoeven (2):
dt-bindings: timer: sifive,clint: Fix number of interrupts
dt-bindings: timer: sifive,clint: Group interrupt tuples
.../devicetree/bindings/timer/sifive,clint.yaml | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-)
Signature · 12 lines
2.25.1
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus TorvaldsPATCH v2 1/2 dt-bindings: timer: sifive,clint: Fix number of interrupts
The number of interrupts lacks an upper bound, thus assuming one, causing properly grouped "interrupts-extended" properties to be flagged as an error by "make dtbs_check".
Fix this by adding the missing "maxItems". As the architectural maximum is 4095 interrupts, using that as the limit would be unpractical. Hence limit it to 10 interrupts (two interrupts for a system management core, and two interrupts per core for other cores). This should be sufficient for now, and the limit can always be increased when the need arises.
---
v2:
- Split in two patches,
- Improve patch description and document limit rationale.
--- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/timer/sifive,clint.yaml +1 -0
@@ -44,6 +44,7 @@ properties: interrupts-extended: minItems: 1 + maxItems: 10 additionalProperties: false
Signature · 1 line
2.25.1
Re: [PATCH v2 1/2] dt-bindings: timer: sifive,clint: Fix number of interrupts
Quoted 10 lines · Geert Uytterhoeven
The number of interrupts lacks an upper bound, thus assuming one, causing properly grouped "interrupts-extended" properties to be flagged as an error by "make
dtbs_check".Fix this by adding the missing "maxItems". As the architectural maximum is 4095 interrupts, using that as the limit would be unpractical. Hence limit it to 10 interrupts (two interrupts for a system management core, and two interrupts per core for other cores). This should be sufficient for now, and the limit can always be increased when the need arises.
Quoted 9 lines
Signed-off-by Geert Uytterhoeven <[email protected]>---
v2:
- Split in two patches,
- Improve patch description and document limit rationale.--- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + 1 file changed, 1 insertion(+)
PATCH v2 2/2 dt-bindings: timer: sifive,clint: Group interrupt tuples
In reply to Geert UytterhoevenTo improve human readability and enable automatic validation, the tuples in "interrupts-extended" properties should be grouped using angle brackets.
---
v2:
- Split in two patches.
--- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
Documentation/devicetree/bindings/timer/sifive,clint.yaml +4 -4
@@ -57,10 +57,10 @@ examples: - | timer@2000000 { compatible = "sifive,fu540-c000-clint", "sifive,clint0"; - interrupts-extended = <&cpu1intc 3 &cpu1intc 7 - &cpu2intc 3 &cpu2intc 7 - &cpu3intc 3 &cpu3intc 7 - &cpu4intc 3 &cpu4intc 7>; + interrupts-extended = <&cpu1intc 3>, <&cpu1intc 7>, + <&cpu2intc 3>, <&cpu2intc 7>, + <&cpu3intc 3>, <&cpu3intc 7>, + <&cpu4intc 3>, <&cpu4intc 7>; reg = <0x2000000 0x10000>; }; ...
Signature · 1 line
2.25.1
Re: [PATCH v2 2/2] dt-bindings: timer: sifive,clint: Group interrupt tuples
Quoted 4 lines · Geert Uytterhoeven
To improve human readability and enable automatic validation, the tuples in "interrupts-extended" properties should be grouped using angle brackets.
Quoted 8 lines
Signed-off-by Geert Uytterhoeven <[email protected]>---
v2:
- Split in two patches.--- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
Re: [PATCH v2 0/2] dt-bindings: timer: sifive,clint: Miscellaneous improvements
In reply to Geert UytterhoevenQuoted 11 lines · Geert Uytterhoeven
Hi all,
This patch series contains two improvements for the SiFive PLIC DT bindings.
Changes compared to v1[1]:
- Split in two patches,
- Improve patch description and document limit rationale.Thanks!
Quoted 8 lines
[1] https://lore.kernel.org/r/[email protected]
Geert Uytterhoeven (2):
dt-bindings: timer: sifive,clint: Fix number of interrupts
dt-bindings: timer: sifive,clint: Group interrupt tuples.../devicetree/bindings/timer/sifive,clint.yaml | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-)
Please resend the timer bindings changes, the GPU and NAND controller series are confusing the b4 tools
Thanks
-- Daniel
Signature · 5 lines
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook | <http://twitter.com/#!/linaroorg> Twitter | <http://www.linaro.org/linaro-blog/> Blog
Re: [PATCH v2 0/2] dt-bindings: timer: sifive,clint: Miscellaneous improvements
Quoted 18 lines · Daniel Lezcano
Quoted 17 lines · Geert Uytterhoeven
Hi all,
This patch series contains two improvements for the SiFive PLIC DT bindings.
Changes compared to v1[1]:
- Split in two patches,
- Improve patch description and document limit rationale.Thanks!
[1] https://lore.kernel.org/r/[email protected]
Geert Uytterhoeven (2):
dt-bindings: timer: sifive,clint: Fix number of interrupts
dt-bindings: timer: sifive,clint: Group interrupt tuples
Quoted 5 lines
Quoted 2 lines
.../devicetree/bindings/timer/sifive,clint.yaml | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-)Please resend the timer bindings changes, the GPU and NAND controller series are confusing the b4 tools
Never mind, I just noticed the V3 ;)
Signature · 5 lines
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook | <http://twitter.com/#!/linaroorg> Twitter | <http://www.linaro.org/linaro-blog/> Blog