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FAILED: patch "[PATCH] x86/cpu: Add Xeon Icelake-D to list of CPUs that support PPIN" failed to apply to 5.10-stable tree

PATCH In review [email protected] 2 participants 6 messages Jan 30, 2022 – Feb 3, 2022

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[email protected]

author maintainer
#0 lore raw

The patch below does not apply to the 5.10-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.

thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

From e464121f2d40eabc7d11823fb26db807ce945df4 Mon Sep 17 00:00:00 2001
From: Tony Luck <[email protected]>
Date: Fri, 21 Jan 2022 09:47:38 -0800
Subject: [PATCH] x86/cpu: Add Xeon Icelake-D to list of CPUs that support PPIN

Missed adding the Icelake-D CPU to the list. It uses the same MSRs to control and read the inventory number as all the other models.

Fixes dc6b025de95b ("x86/mce: Add Xeon Icelake to list of CPUs that support PPIN")
Reported-by Ailin Xu <[email protected]>
Signed-off-by Tony Luck <[email protected]>
Signed-off-by Borislav Petkov <[email protected]>
Cc <[email protected]>
Link https://lore.kernel.org/r/[email protected] open here
arch/x86/kernel/cpu/mce/intel.c +1 -0
index bb9a46a804bf..baafbb37be67 100644
@@ -486,6 +486,7 @@ static void intel_ppin_init(struct cpuinfo_x86 *c)
 	case INTEL_FAM6_BROADWELL_X:
 	case INTEL_FAM6_SKYLAKE_X:
 	case INTEL_FAM6_ICELAKE_X:
+	case INTEL_FAM6_ICELAKE_D:
 	case INTEL_FAM6_SAPPHIRERAPIDS_X:
 	case INTEL_FAM6_XEON_PHI_KNL:
 	case INTEL_FAM6_XEON_PHI_KNM:
maintainer
#1 lore raw

From 72a73811c4bd53e0ec8284c12180068468d7c733 Mon Sep 17 00:00:00 2001
From: Tony Luck <[email protected]>
Date: Mon, 31 Jan 2022 09:00:41 -0800
Subject: [PATCH] x86/cpu: Add Sapphire Rapids and Icelake-D to list of CPUs that support PPIN

commit a331f5fdd36dba1ffb0239a4dfaaf1df91ff1aab upstream commit e464121f2d40eabc7d11823fb26db807ce945df4 upstream

Add Sapphire Rapids and Icelake-D to list of CPUs that support PPIN

Signed-off-by Tony Luck <[email protected]>

---

Failed to backport because the sapphire rapids CPU model number patch had not been backported. Bundled both together here. But if that breaks stable rules or scripts, I can redo as two patches one for each upstream commit.

 arch/x86/kernel/cpu/mce/intel.c | 2 ++
 1 file changed, 2 insertions(+)
arch/x86/kernel/cpu/mce/intel.c +2 -0
index 2577d7875781..886d4648c9dd 100644
@@ -486,6 +486,8 @@ static void intel_ppin_init(struct cpuinfo_x86 *c)
 	case INTEL_FAM6_BROADWELL_X:
 	case INTEL_FAM6_SKYLAKE_X:
 	case INTEL_FAM6_ICELAKE_X:
+	case INTEL_FAM6_ICELAKE_D:
+	case INTEL_FAM6_SAPPHIRERAPIDS_X:
 	case INTEL_FAM6_XEON_PHI_KNL:
 	case INTEL_FAM6_XEON_PHI_KNM:
Signature · 1 line
2.31.1
author maintainer
#2 lore raw
Quoted 10 lines · Tony
Quoted 1 line

From 72a73811c4bd53e0ec8284c12180068468d7c733 Mon Sep 17 00:00:00 2001

From: Tony Luck <[email protected]>
Date: Mon, 31 Jan 2022 09:00:41 -0800
Subject: [PATCH] x86/cpu: Add Sapphire Rapids and Icelake-D to list of CPUs that support PPIN

commit a331f5fdd36dba1ffb0239a4dfaaf1df91ff1aab upstream commit e464121f2d40eabc7d11823fb26db807ce945df4 upstream

Add Sapphire Rapids and Icelake-D to list of CPUs that support PPIN

Quoted 7 lines
Signed-off-by Tony Luck <[email protected]>

---

Failed to backport because the sapphire rapids CPU model number patch had not been backported. Bundled both together here. But if that breaks stable rules or scripts, I can redo as two patches one for each upstream commit.

Two patches please.

thanks,

greg k-h

maintainer
#3 lore raw

PATCH 1/2 x86/mce: Add Xeon Sapphire Rapids to list of CPUs that support PPIN

commit a331f5fdd36dba1ffb0239a4dfaaf1df91ff1aab upstream

New CPU model, same MSRs to control and read the inventory number.

Signed-off-by Tony Luck <[email protected]>
Signed-off-by Ingo Molnar <[email protected]>
Link https://lore.kernel.org/r/[email protected] open here
---
 arch/x86/kernel/cpu/mce/intel.c | 1 +
 1 file changed, 1 insertion(+)
arch/x86/kernel/cpu/mce/intel.c +1 -0
index 2577d7875781..7cf08c1f082e 100644
@@ -486,6 +486,7 @@ static void intel_ppin_init(struct cpuinfo_x86 *c)
 	case INTEL_FAM6_BROADWELL_X:
 	case INTEL_FAM6_SKYLAKE_X:
 	case INTEL_FAM6_ICELAKE_X:
+	case INTEL_FAM6_SAPPHIRERAPIDS_X:
 	case INTEL_FAM6_XEON_PHI_KNL:
 	case INTEL_FAM6_XEON_PHI_KNM:
Signature · 1 line
2.31.1
maintainer
#4 lore raw

PATCH 2/2 x86/cpu: Add Xeon Icelake-D to list of CPUs that support PPIN

commit e464121f2d40eabc7d11823fb26db807ce945df4 upstream

Missed adding the Icelake-D CPU to the list. It uses the same MSRs to control and read the inventory number as all the other models.

Fixes dc6b025de95b ("x86/mce: Add Xeon Icelake to list of CPUs that support PPIN")
Reported-by Ailin Xu <[email protected]>
Signed-off-by Tony Luck <[email protected]>
Signed-off-by Borislav Petkov <[email protected]>
Cc <[email protected]>
Link https://lore.kernel.org/r/[email protected] open here
---
 arch/x86/kernel/cpu/mce/intel.c | 1 +
 1 file changed, 1 insertion(+)
arch/x86/kernel/cpu/mce/intel.c +1 -0
index 7cf08c1f082e..886d4648c9dd 100644
@@ -486,6 +486,7 @@ static void intel_ppin_init(struct cpuinfo_x86 *c)
 	case INTEL_FAM6_BROADWELL_X:
 	case INTEL_FAM6_SKYLAKE_X:
 	case INTEL_FAM6_ICELAKE_X:
+	case INTEL_FAM6_ICELAKE_D:
 	case INTEL_FAM6_SAPPHIRERAPIDS_X:
 	case INTEL_FAM6_XEON_PHI_KNL:
 	case INTEL_FAM6_XEON_PHI_KNM:
Signature · 1 line
2.31.1
author maintainer
#5 lore raw

Re: [v5.10 stable PATCH 2/2] x86/cpu: Add Xeon Icelake-D to list of CPUs that support PPIN

Quoted 30 lines · Tony Luck

commit e464121f2d40eabc7d11823fb26db807ce945df4 upstream

Missed adding the Icelake-D CPU to the list. It uses the same MSRs to control and read the inventory number as all the other models.

Fixes dc6b025de95b ("x86/mce: Add Xeon Icelake to list of CPUs that support PPIN")
Reported-by Ailin Xu <[email protected]>
Signed-off-by Tony Luck <[email protected]>
Signed-off-by Borislav Petkov <[email protected]>
Cc <[email protected]>
Link https://lore.kernel.org/r/[email protected] open here
---
 arch/x86/kernel/cpu/mce/intel.c | 1 +
 1 file changed, 1 insertion(+)
arch/x86/kernel/cpu/mce/intel.c +1 -0
index 7cf08c1f082e..886d4648c9dd 100644
@@ -486,6 +486,7 @@ static void intel_ppin_init(struct cpuinfo_x86 *c)
 	case INTEL_FAM6_BROADWELL_X:
 	case INTEL_FAM6_SKYLAKE_X:
 	case INTEL_FAM6_ICELAKE_X:
+	case INTEL_FAM6_ICELAKE_D:
 	case INTEL_FAM6_SAPPHIRERAPIDS_X:
 	case INTEL_FAM6_XEON_PHI_KNL:
 	case INTEL_FAM6_XEON_PHI_KNM:
Signature · 1 line
2.31.1

Both now queued up, thanks!

greg k-h