dt-bindings: pwm: Add Xilinx AXI Timer
Subsystems (6)
PATCH v14 1/2 dt-bindings: pwm: Add Xilinx AXI Timer
This adds a binding for the Xilinx LogiCORE IP AXI Timer. This device is a "soft" block, so it has some parameters which would not be configurable in most hardware. This binding is usually automatically generated by Xilinx's tools, so the names and values of some properties should be kept as they are, if possible. In addition, this binding is already in the kernel at arch/microblaze/boot/dts/system.dts, and in user software such as QEMU.
The existing driver uses the clock-frequency property, or alternatively the /cpus/timebase-frequency property as its frequency input. Because these properties are deprecated, they have not been included with this schema. All new bindings should use the clocks/clock-names properties to specify the parent clock.
Because we need to init timer devices so early in boot, we determine if we should use the PWM driver or the clocksource/clockevent driver by the presence/absence, respectively, of #pwm-cells. Because both counters are used by the PWM, there is no need for a separate property specifying which counters are to be used for the PWM.
---
(no changes since v8)
Changes in v8:
- Set additionalProperties: false
Changes in v7:
- Add #pwm-cells to properties
- Document why additionalProperties is true
Changes in v6:
- Enumerate possible counter widths
- Fix incorrect schema id
Changes in v5:
- Add example for timer binding
- Fix indentation lint
- Move schema into the timer directory
- Remove xlnx,axi-timer-2.0 compatible string
- Update commit message to reflect revisions
Changes in v4:
- Make some properties optional for clocksource drivers
- Predicate PWM driver on the presence of #pwm-cells
- Remove references to generate polarity so this can get merged
Changes in v3:
- Add an example with non-deprecated properties only.
- Add xlnx,pwm and xlnx,gen?-active-low properties.
- Make newer replacement properties mutually-exclusive with what they replace
- Mark all boolean-as-int properties as deprecated
Changes in v2:
- Use 32-bit addresses for example binding
.../bindings/timer/xlnx,xps-timer.yaml | 92 +++++++++++++++++++ 1 file changed, 92 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/xlnx,xps-timer.yaml
Documentation/devicetree/bindings/timer/xlnx,xps-timer.yaml new file +92 -0
@@ -0,0 +1,92 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/xlnx,xps-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx LogiCORE IP AXI Timer Device Tree Binding + +maintainers: + - Sean Anderson <[email protected]> + +properties: + compatible: + contains: + const: xlnx,xps-timer-1.00.a + + clocks: + maxItems: 1 + + clock-names: + const: s_axi_aclk + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + + '#pwm-cells': true + + xlnx,count-width: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [8, 16, 32] + default: 32 + description: + The width of the counter(s), in bits. + + xlnx,one-timer-only: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1 ] + description: + Whether only one timer is present in this block. + +required: + - compatible + - reg + - xlnx,one-timer-only + +allOf: + - if: + required: + - '#pwm-cells' + then: + allOf: + - required: + - clocks + - properties: + xlnx,one-timer-only: + const: 0 + else: + required: + - interrupts + - if: + required: + - clocks + then: + required: + - clock-names + +additionalProperties: false + +examples: + - | + timer@800e0000 { + clock-names = "s_axi_aclk"; + clocks = <&zynqmp_clk 71>; + compatible = "xlnx,xps-timer-1.00.a"; + reg = <0x800e0000 0x10000>; + interrupts = <0 39 2>; + xlnx,count-width = <16>; + xlnx,one-timer-only = <0x0>; + }; + + timer@800f0000 { + #pwm-cells = <0>; + clock-names = "s_axi_aclk"; + clocks = <&zynqmp_clk 71>; + compatible = "xlnx,xps-timer-1.00.a"; + reg = <0x800e0000 0x10000>; + xlnx,count-width = <32>; + xlnx,one-timer-only = <0x0>; + };
Signature · 1 line
2.25.1
PATCH v14 2/2 pwm: Add support for Xilinx AXI Timer
This adds PWM support for Xilinx LogiCORE IP AXI soft timers commonly found on Xilinx FPGAs. At the moment clock control is very basic: we just enable the clock during probe and pin the frequency. In the future, someone could add support for disabling the clock when not in use.
Some common code has been specially demarcated. While currently only used by the PWM driver, it is anticipated that it may be split off in the future to be used by the timer driver as well.
This driver was written with reference to Xilinx DS764 for v1.03.a [1].
[1] https://www.xilinx.com/support/documentation/ip_documentation/axi_timer/v1_03_a/axi_timer_ds764.pdf
---
Changes in v14:
- 1GHz -> 1 GHz
- Clarify that we will give a very wrong estimate for rate >= 1 GHz
- Remove duplicate blank line
- Remove forward declaration of xilinx_timer_common_init (which no longer exists).
Changes in v13:
- Clamp period/duty_cycle by assuming rate is at most U32_MAX
- Expand comment in xilinx_timer_get_period
- Note that the 100% duty cycle calculations may be wrong for very high clock rates
Changes in v12:
- Add a comment to the timer driver about #pwm-cells
- Combine/expand comments on rounding in xilinx_pwm_apply
Changes in v11:
- Add comment about why we test for #pwm-cells
- Clarify comment on generate out signal
- Rename pwm variables to xilinx_pwm
- Round like Uwe wants...
- s/xilinx_timer/xilinx_pwm/ for non-common functions
Changes in v10:
- Fix compilation error in timer driver
Changes in v9:
- Refactor "if { return } else if { }" to "if { return } if { }"
- Remove drivers/clocksource/timer-xilinx-common.c from MAINTAINERS
- Remove xilinx_timer_common_init and integrate it into xilinx_timer_probe
Changes in v8:
- Drop new timer driver; it has been deferred for future series
Changes in v7:
- Add dependency on OF_ADDRESS
- Fix period_cycles calculation
- Fix typo in limitations
Changes in v6:
- Capitalize error messages
- Don't disable regmap locking to allow inspection of registers via debugfs
- Prevent overflow when calculating period_cycles
- Remove enabled variable from xilinx_pwm_apply
- Swap order of period_cycle range comparisons
Changes in v5:
- Allow non-zero #pwm-cells
- Correctly set duty_cycle in get_state when TLR0=TLR1
- Elaborate on limitation section
- Perform some additional checks/rounding in apply_state
- Remove xlnx,axi-timer-2.0 compatible string
- Rework duty-cycle and period calculations with feedback from Uwe
- Switch to regmap to abstract endianness issues
- Use more verbose error messages
Changes in v4:
- Don't use volatile in read/write replacements. Some arches have it and some don't.
- Put common timer properties into their own struct to better reuse code.
- Remove references to properties which are not good enough for Linux.
Changes in v3:
- Add clockevent and clocksource support
- Remove old microblaze driver
- Rewrite probe to only use a device_node, since timers may need to be initialized before we have proper devices. This does bloat the code a bit since we can no longer rely on helpers such as dev_err_probe. We also cannot rely on device resources being free'd on failure, so we must free them manually.
- We now access registers through xilinx_timer_(read|write). This allows us to deal with endianness issues, as originally seen in the microblaze driver. CAVEAT EMPTOR: I have not tested this on big-endian!
Changes in v2:
- Add comment describing device
- Add comment explaining why we depend on !MICROBLAZE
- Add dependencies on COMMON_CLK and HAS_IOMEM
- Cast dividends to u64 to avoid overflow
- Check for over- and underflow when calculating TLR
- Check range of xlnx,count-width
- Don't compile this module by default for arm64
- Don't set pwmchip.base to -1
- Ensure the clock is always running when the pwm is registered
- Remove debugfs file :l
- Rename TCSR_(SET|CLEAR) to TCSR_RUN_(SET|CLEAR)
- Report errors with dev_error_probe
- Set xilinx_pwm_ops.owner
- Use NSEC_TO_SEC instead of defining our own
- Use TCSR_RUN_MASK to check if the PWM is enabled, as suggested by Uwe
MAINTAINERS | 6 + arch/microblaze/kernel/timer.c | 4 + drivers/pwm/Kconfig | 14 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-xilinx.c | 321 +++++++++++++++++++++++++++++ include/clocksource/timer-xilinx.h | 73 +++++++ 6 files changed, 419 insertions(+) create mode 100644 drivers/pwm/pwm-xilinx.c create mode 100644 include/clocksource/timer-xilinx.h
MAINTAINERS +6 -0
@@ -21201,6 +21201,12 @@ F: drivers/misc/Makefile F: drivers/misc/xilinx_sdfec.c F: include/uapi/misc/xilinx_sdfec.h +XILINX PWM DRIVER +M: Sean Anderson <[email protected]> +S: Maintained +F: drivers/pwm/pwm-xilinx.c +F: include/clocksource/timer-xilinx.h + XILINX UARTLITE SERIAL DRIVER M: Peter Korsgaard <[email protected]> L: [email protected]
arch/microblaze/kernel/timer.c +4 -0
@@ -251,6 +251,10 @@ static int __init xilinx_timer_init(struct device_node *timer)u32 timer_num =1 ;int ret; +/* If this property is present, the device is a PWM and not a timer */ +if (of_property_read_bool (timer,"#pwm-cells" )) +return 0 ; +if (initialized)return -EINVAL ;
drivers/pwm/Kconfig +14 -0
@@ -640,4 +640,18 @@ config PWM_VT8500 To compile this driver as a module, choose M here: the module will be called pwm-vt8500. +config PWM_XILINX + tristate "Xilinx AXI Timer PWM support" + depends on OF_ADDRESS + depends on COMMON_CLK + select REGMAP_MMIO + help + PWM driver for Xilinx LogiCORE IP AXI timers. This timer is + typically a soft core which may be present in Xilinx FPGAs. + This device may also be present in Microblaze soft processors. + If you don't have this IP in your design, choose N. + + To compile this driver as a module, choose M here: the module + will be called pwm-xilinx. + endif
drivers/pwm/Makefile +1 -0
@@ -60,3 +60,4 @@ obj-$(CONFIG_PWM_TWL) += pwm-twl.o obj-$(CONFIG_PWM_TWL_LED) += pwm-twl-led.o obj-$(CONFIG_PWM_VISCONTI) += pwm-visconti.o obj-$(CONFIG_PWM_VT8500) += pwm-vt8500.o +obj-$(CONFIG_PWM_XILINX) += pwm-xilinx.o
drivers/pwm/pwm-xilinx.c new file +321 -0
321 lines not on this page · raw message
include/clocksource/timer-xilinx.h new file +73 -0
73 lines not on this page · raw message
Signature · 1 line
2.25.1
Re: [PATCH v14 2/2] pwm: Add support for Xilinx AXI Timer
Hello,
Quoted 9 lines · Sean Anderson
This adds PWM support for Xilinx LogiCORE IP AXI soft timers commonly found on Xilinx FPGAs. At the moment clock control is very basic: we just enable the clock during probe and pin the frequency. In the future, someone could add support for disabling the clock when not in use.
Some common code has been specially demarcated. While currently only used by the PWM driver, it is anticipated that it may be split off in the future to be used by the timer driver as well.
Quoted 6 lines
This driver was written with reference to Xilinx DS764 for v1.03.a [1].
[1] https://www.xilinx.com/support/documentation/ip_documentation/axi_timer/v1_03_a/axi_timer_ds764.pdf
Signed-off-by Sean Anderson <[email protected]>Acked-by Michal Simek <[email protected]>
One little thing below. Not worth respinning for just that though, so:
drivers/pwm/pwm-xilinx.c line 191
Quoted 4 lines
drivers/pwm/pwm-xilinx.c new file +4
-0+/* +* 100% duty cycle results in constant low output. This may be (very) +* wrong if rate >= 1 GHz, so fix this if you have such hardware :) +*/
In v13 I asked for s/>= 1GHz/> 1 GHz/. You seem to have missed, that this contains two suggested changes. So there is s/>=/>/ left.
Best regards
Uwe
Signature · 2 lines
Pengutronix e.K. | Uwe Kleine-König | Industrial Linux Solutions | https://www.pengutronix.de/ |
Re: [PATCH v14 2/2] pwm: Add support for Xilinx AXI Timer
In reply to Sean AndersonQuoted 111 lines · Sean Anderson
This adds PWM support for Xilinx LogiCORE IP AXI soft timers commonly found on Xilinx FPGAs. At the moment clock control is very basic: we just enable the clock during probe and pin the frequency. In the future, someone could add support for disabling the clock when not in use.
Some common code has been specially demarcated. While currently only used by the PWM driver, it is anticipated that it may be split off in the future to be used by the timer driver as well.
This driver was written with reference to Xilinx DS764 for v1.03.a [1].
[1] https://www.xilinx.com/support/documentation/ip_documentation/axi_timer/v1_03_a/axi_timer_ds764.pdf
Signed-off-by Sean Anderson <[email protected]>Acked-by Michal Simek <[email protected]>---
Changes in v14:
- 1GHz -> 1 GHz
- Clarify that we will give a very wrong estimate for rate >= 1 GHz
- Remove duplicate blank line
- Remove forward declaration ofxilinx_timer_common_init(which no longer exists).Changes in v13:
- Clamp period/duty_cycle by assuming rate is at mostU32_MAX
- Expand comment inxilinx_timer_get_period
- Note that the 100% duty cycle calculations may be wrong for very high clock ratesChanges in v12:
- Add a comment to the timer driver about #pwm-cells
- Combine/expand comments on rounding inxilinx_pwm_applyChanges in v11:
- Add comment about why we test for #pwm-cells
- Clarify comment on generate out signal
- Rename pwm variables toxilinx_pwm
- Round like Uwe wants...
- s/xilinx_timer/xilinx_pwm/ for non-common functionsChanges in v10:
- Fix compilation error in timer driverChanges in v9:
- Refactor "if { return } else if { }" to "if { return } if { }"
- Removedrivers/clocksource/timer-xilinx-common.cfromMAINTAINERS
- Removexilinx_timer_common_initand integrate it intoxilinx_timer_probeChanges in v8:
- Drop new timer driver; it has been deferred for future seriesChanges in v7:
- Add dependency onOF_ADDRESS
- Fixperiod_cyclescalculation
- Fix typo in limitationsChanges in v6:
- Capitalize error messages
- Don't disable regmap locking to allow inspection of registers via debugfs
- Prevent overflow when calculatingperiod_cycles
- Remove enabled variable fromxilinx_pwm_apply
- Swap order ofperiod_cyclerange comparisonsChanges in v5:
- Allow non-zero #pwm-cells
- Correctly setduty_cycleinget_statewhen TLR0=TLR1
- Elaborate on limitation section
- Perform some additional checks/rounding inapply_state
- Remove xlnx,axi-timer-2.0 compatible string
- Rework duty-cycle and period calculations with feedback from Uwe
- Switch to regmap to abstract endianness issues
- Use more verbose error messagesChanges in v4:
- Don't use volatile in read/write replacements. Some arches have it and some don't.
- Put common timer properties into their own struct to better reuse code.
- Remove references to properties which are not good enough for Linux.Changes in v3:
- Add clockevent and clocksource support
- Remove old microblaze driver
- Rewrite probe to only use adevice_node, since timers may need to be initialized before we have proper devices. This does bloat the code a bit since we can no longer rely on helpers such asdev_err_probe. We also cannot rely on device resources being free'd on failure, so we must free them manually.
- We now access registers throughxilinx_timer_(read|write). This allows us to deal with endianness issues, as originally seen in the microblaze driver. CAVEAT EMPTOR: I have not tested this on big-endian!Changes in v2:
- Add comment describing device
- Add comment explaining why we depend on !MICROBLAZE
- Add dependencies onCOMMON_CLKandHAS_IOMEM
- Cast dividends to u64 to avoid overflow
- Check for over- and underflow when calculating TLR
- Check range of xlnx,count-width
- Don't compile this module by default for arm64
- Don't set pwmchip.base to -1
- Ensure the clock is always running when the pwm is registered
- Remove debugfs file :l
- RenameTCSR_(SET|CLEAR)toTCSR_RUN_(SET|CLEAR)
- Report errors withdev_error_probe
- Set xilinx_pwm_ops.owner
- UseNSEC_TO_SECinstead of defining our own
- UseTCSR_RUN_MASKto check if the PWM is enabled, as suggested by Uwe
Quoted 9 lines
MAINTAINERS | 6 + arch/microblaze/kernel/timer.c | 4 + drivers/pwm/Kconfig | 14 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-xilinx.c | 321 +++++++++++++++++++++++++++++ include/clocksource/timer-xilinx.h | 73 +++++++ 6 files changed, 419 insertions(+) create mode 100644 drivers/pwm/pwm-xilinx.c create mode 100644 include/clocksource/timer-xilinx.h
Applied with Uwe's s/>= 1 GHz/> 1 GHz/ ask applied. I've also changed the MODULE_LICENSE string to just "GPL" since that's what checkpatch requested.
Thanks,
Thierry
Thierry Reding
AppliedQuoted 55 lines · Sean Anderson
This adds a binding for the Xilinx LogiCORE IP AXI Timer. This device is a "soft" block, so it has some parameters which would not be configurable in most hardware. This binding is usually automatically generated by Xilinx's tools, so the names and values of some properties should be kept as they are, if possible. In addition, this binding is already in the kernel at
arch/microblaze/boot/dts/system.dts, and in user software such as QEMU.The existing driver uses the clock-frequency property, or alternatively the /cpus/timebase-frequency property as its frequency input. Because these properties are deprecated, they have not been included with this schema. All new bindings should use the clocks/clock-names properties to specify the parent clock.
Because we need to init timer devices so early in boot, we determine if we should use the PWM driver or the clocksource/clockevent driver by the presence/absence, respectively, of #pwm-cells. Because both counters are used by the PWM, there is no need for a separate property specifying which counters are to be used for the PWM.
Signed-off-by Sean Anderson <[email protected]>Reviewed-by Rob Herring <[email protected]>---
(no changes since v8)
Changes in v8:
- Set additionalProperties: falseChanges in v7:
- Add #pwm-cells to properties
- Document why additionalProperties is trueChanges in v6:
- Enumerate possible counter widths
- Fix incorrect schema idChanges in v5:
- Add example for timer binding
- Fix indentation lint
- Move schema into the timer directory
- Remove xlnx,axi-timer-2.0 compatible string
- Update commit message to reflect revisionsChanges in v4:
- Make some properties optional for clocksource drivers
- Predicate PWM driver on the presence of #pwm-cells
- Remove references to generate polarity so this can get mergedChanges in v3:
- Add an example with non-deprecated properties only.
- Add xlnx,pwm and xlnx,gen?-active-low properties.
- Make newer replacement properties mutually-exclusive with what they replace
- Mark all boolean-as-int properties as deprecated
Quoted 6 lines
Changes in v2:
- Use 32-bit addresses for example binding.../bindings/timer/xlnx,xps-timer.yaml | 92 +++++++++++++++++++ 1 file changed, 92 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/xlnx,xps-timer.yaml
Applied, thanks.
Thierry