PCI: qcom: Add support for SC8280XP and SA8540P

---
 .../devicetree/bindings/pci/qcom,pcie.yaml      | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

Documentation/devicetree/bindings/pci/qcom,pcie.yaml +15 -2

index 70984037df73..8142c891f18b 100644
@@ -625,7 +625,6 @@ allOf:
         - reset-names
 
     # On newer chipsets support either 1 or 8 msi interrupts
-    # On older chipsets it's always 1 msi interrupt
   - if:
       properties:
         compatible:

@@ -660,7 +659,21 @@ allOf:
                 - const: msi5
                 - const: msi6
                 - const: msi7
-    else:
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,pcie-apq8064
+              - qcom,pcie-apq8084
+              - qcom,pcie-ipq4019
+              - qcom,pcie-ipq6018
+              - qcom,pcie-ipq8064
+              - qcom,pcie-ipq8064-v2
+              - qcom,pcie-ipq8074
+              - qcom,pcie-qcs404
+    then:
       properties:
         interrupts:
           maxItems: 1

Signature · 1 line

2.35.1

Krzysztof Kozlowski

Acked-by on v2 1/8

2022-07-14 10:45 UTC #2 lore raw

Re: [PATCH v2 1/8] dt-bindings: PCI: qcom: Enumerate platforms with single msi interrupt

Quoted 8 lines · Johan Hovold

Explicitly enumerate the older platforms that have a single msi host interrupt. This allows for adding further platforms with, for example, four msi interrupts without resorting to nested conditionals.
Drop the redundant comment about older chipsets instead of moving it.
Reviewed-by Manivannan Sadhasivam <[email protected]>
Signed-off-by Johan Hovold <[email protected]>

Acked-by Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof

Johan Hovold

author

2022-07-14 07:14 UTC #3 lore raw

PATCH v2 2/8 dt-bindings: PCI: qcom: Add SC8280XP to binding

Add the SC8280XP platform to the binding.

SC8280XP use four host interrupts for MSI routing so remove the obsolete comment referring to newer chipsets supporting one or eight interrupts (e.g. for backwards compatibility).

Acked-by Krzysztof Kozlowski <[email protected]>

---
 .../devicetree/bindings/pci/qcom,pcie.yaml    | 50 ++++++++++++++++++-
 1 file changed, 49 insertions(+), 1 deletion(-)

Documentation/devicetree/bindings/pci/qcom,pcie.yaml +49 -1

index 8142c891f18b..577d166a7476 100644
@@ -27,6 +27,7 @@ properties:
       - qcom,pcie-qcs404
       - qcom,pcie-sc7280
       - qcom,pcie-sc8180x
+      - qcom,pcie-sc8280xp
       - qcom,pcie-sdm845
       - qcom,pcie-sm8150
       - qcom,pcie-sm8250

@@ -181,6 +182,7 @@ allOf:
             enum:
               - qcom,pcie-sc7280
               - qcom,pcie-sc8180x
+              - qcom,pcie-sc8280xp
               - qcom,pcie-sm8250
               - qcom,pcie-sm8450-pcie0
               - qcom,pcie-sm8450-pcie1

@@ -596,6 +598,35 @@ allOf:
           items:
             - const: pci # PCIe core reset
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,pcie-sc8280xp
+    then:
+      properties:
+        clocks:
+          minItems: 8
+          maxItems: 9
+        clock-names:
+          minItems: 8
+          items:
+            - const: aux # Auxiliary clock
+            - const: cfg # Configuration clock
+            - const: bus_master # Master AXI clock
+            - const: bus_slave # Slave AXI clock
+            - const: slave_q2a # Slave Q2A clock
+            - const: ddrss_sf_tbu # PCIe SF TBU clock
+            - const: noc_aggr_4 # NoC aggregate 4 clock
+            - const: noc_aggr_south_sf # NoC aggregate South SF clock
+            - const: cnoc_qx # Configuration NoC QX clock
+        resets:
+          maxItems: 1
+        reset-names:
+          items:
+            - const: pci # PCIe core reset
+
   - if:
       not:
         properties:

@@ -624,7 +655,6 @@ allOf:
         - resets
         - reset-names
 
-    # On newer chipsets support either 1 or 8 msi interrupts
   - if:
       properties:
         compatible:

@@ -660,6 +690,24 @@ allOf:
                 - const: msi6
                 - const: msi7
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,pcie-sc8280xp
+    then:
+      properties:
+        interrupts:
+          minItems: 4
+          maxItems: 4
+        interrupt-names:
+          items:
+            - const: msi0
+            - const: msi1
+            - const: msi2
+            - const: msi3
+
   - if:
       properties:
         compatible:

Signature · 1 line

2.35.1

Johan Hovold

author

2022-07-14 07:14 UTC #4 lore raw

PATCH v2 3/8 dt-bindings: PCI: qcom: Add SA8540P to binding

SA8540P is a new platform related to SC8280XP but which uses a single host interrupt for MSI routing.

Acked-by Krzysztof Kozlowski <[email protected]>

---
 Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 3 +++
 1 file changed, 3 insertions(+)

Documentation/devicetree/bindings/pci/qcom,pcie.yaml +3 -0

index 577d166a7476..22a2aac4c23f 100644
@@ -25,6 +25,7 @@ properties:
       - qcom,pcie-ipq4019
       - qcom,pcie-ipq8074
       - qcom,pcie-qcs404
+      - qcom,pcie-sa8540p
       - qcom,pcie-sc7280
       - qcom,pcie-sc8180x
       - qcom,pcie-sc8280xp

@@ -603,6 +604,7 @@ allOf:
         compatible:
           contains:
             enum:
+              - qcom,pcie-sa8540p
               - qcom,pcie-sc8280xp
     then:
       properties:

@@ -721,6 +723,7 @@ allOf:
               - qcom,pcie-ipq8064-v2
               - qcom,pcie-ipq8074
               - qcom,pcie-qcs404
+              - qcom,pcie-sa8540p
     then:
       properties:
         interrupts:

Signature · 1 line

2.35.1

Brian Masney

Reviewed-by on v2 3/8

2022-07-14 14:29 UTC #5 lore raw

Re: [PATCH v2 3/8] dt-bindings: PCI: qcom: Add SA8540P to binding

Quoted 5 lines · Johan Hovold

SA8540P is a new platform related to SC8280XP but which uses a single host interrupt for MSI routing.
Acked-by Krzysztof Kozlowski <[email protected]>
Signed-off-by Johan Hovold <[email protected]>

Johan Hovold

author

2022-07-14 07:15 UTC #6 lore raw

PATCH v2 4/8 PCI: qcom: Add support for SC8280XP

The SC8280XP platform has seven PCIe controllers: two used with USB4, two 4-lane, two 2-lane and one 1-lane.

Add a new "qcom,pcie-sc8280xp" compatible string and reuse the 1.9.0 ops.

Note that the SC8280XP controllers need two or three interconnect clocks to be enabled. Model these as optional clocks to avoid encoding devicetree data in the PCIe driver.

Note that the same could be done for the SM8450 interconnect clocks and possibly also for the TBU clocks.

Reviewed-by Manivannan Sadhasivam <[email protected]>

---
 drivers/pci/controller/dwc/pcie-qcom.c | 22 ++++++++++++++++++++--
 1 file changed, 20 insertions(+), 2 deletions(-)

drivers/pci/controller/dwc/pcie-qcom.c +20 -2

index d176c635016b..7a79bec81bba 100644
@@ -177,7 +177,7 @@ struct qcom_pcie_resources_2_3_3 {
 
 /* 6 clocks typically, 7 for sm8250 */
 struct qcom_pcie_resources_2_7_0 {
-	struct clk_bulk_data clks[9];
+	struct clk_bulk_data clks[12];
 	int num_clks;
 	struct regulator_bulk_data supplies[2];
 	struct reset_control *pci_reset;

@@ -1172,6 +1172,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
 	struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
 	struct dw_pcie *pci = pcie->pci;
 	struct device *dev = pci->dev;
+	unsigned int num_clks, num_opt_clks;
 	unsigned int idx;
 	int ret;

@@ -1201,9 +1202,20 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
 	if (pcie->cfg->has_aggre1_clk)
 		res->clks[idx++].id = "aggre1";
 
+	num_clks = idx;
+
+	ret = devm_clk_bulk_get(dev, num_clks, res->clks);
+	if (ret < 0)
+		return ret;
+
+	res->clks[idx++].id = "noc_aggr_4";
+	res->clks[idx++].id = "noc_aggr_south_sf";
+	res->clks[idx++].id = "cnoc_qx";
+
+	num_opt_clks = idx - num_clks;
 	res->num_clks = idx;
 
-	ret = devm_clk_bulk_get(dev, res->num_clks, res->clks);
+	ret = devm_clk_bulk_get_optional(dev, num_opt_clks, res->clks + num_clks);
 	if (ret < 0)
 		return ret;

@@ -1622,6 +1634,11 @@ static const struct qcom_pcie_cfg ipq4019_cfg = {
 	.ops = &ops_2_4_0,
 };
 
+static const struct qcom_pcie_cfg sc8280xp_cfg = {
+	.ops = &ops_1_9_0,
+	.has_ddrss_sf_tbu_clk = true,
+};
+
 static const struct qcom_pcie_cfg sdm845_cfg = {
 	.ops = &ops_2_7_0,
 	.has_tbu_clk = true,

@@ -1790,6 +1807,7 @@ static const struct of_device_id qcom_pcie_match[] = {
 	{ .compatible = "qcom,pcie-sm8150", .data = &sm8150_cfg },
 	{ .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg },
 	{ .compatible = "qcom,pcie-sc8180x", .data = &sc8180x_cfg },
+	{ .compatible = "qcom,pcie-sc8280xp", .data = &sc8280xp_cfg },
 	{ .compatible = "qcom,pcie-sm8450-pcie0", .data = &sm8450_pcie0_cfg },
 	{ .compatible = "qcom,pcie-sm8450-pcie1", .data = &sm8450_pcie1_cfg },
 	{ .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg },

Signature · 1 line

2.35.1

Johan Hovold

author

2022-07-14 07:15 UTC #7 lore raw

PATCH v2 5/8 PCI: qcom: Add support for SA8540P

The SA8540P platform has five PCIe controllers: two 4-lane, two 2-lane and one 1-lane.

Add a new "qcom,pcie-sa8540p" compatible string and reuse the 1.9.0 ops.

Note that like for SC8280XP, the SA8540P controllers need two or three interconnect clocks to be enabled.

Reviewed-by Rob Herring <[email protected]>

Reviewed-by Manivannan Sadhasivam <[email protected]>

---
 drivers/pci/controller/dwc/pcie-qcom.c | 6 ++++++
 1 file changed, 6 insertions(+)

drivers/pci/controller/dwc/pcie-qcom.c +6 -0

index 7a79bec81bba..699cd8b0f38e 100644
@@ -1634,6 +1634,11 @@ static const struct qcom_pcie_cfg ipq4019_cfg = {
 	.ops = &ops_2_4_0,
 };
 
+static const struct qcom_pcie_cfg sa8540p_cfg = {
+	.ops = &ops_1_9_0,
+	.has_ddrss_sf_tbu_clk = true,
+};
+
 static const struct qcom_pcie_cfg sc8280xp_cfg = {
 	.ops = &ops_1_9_0,
 	.has_ddrss_sf_tbu_clk = true,

@@ -1803,6 +1808,7 @@ static const struct of_device_id qcom_pcie_match[] = {
 	{ .compatible = "qcom,pcie-ipq8074", .data = &ipq8074_cfg },
 	{ .compatible = "qcom,pcie-ipq4019", .data = &ipq4019_cfg },
 	{ .compatible = "qcom,pcie-qcs404", .data = &ipq4019_cfg },
+	{ .compatible = "qcom,pcie-sa8540p", .data = &sa8540p_cfg },
 	{ .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg },
 	{ .compatible = "qcom,pcie-sm8150", .data = &sm8150_cfg },
 	{ .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg },

Signature · 1 line

2.35.1

Brian Masney

Reviewed-by on v2 5/8

2022-07-14 14:30 UTC #8 lore raw

Re: [PATCH v2 5/8] PCI: qcom: Add support for SA8540P

Quoted 11 lines · Johan Hovold

The SA8540P platform has five PCIe controllers: two 4-lane, two 2-lane and one 1-lane.
Add a new "qcom,pcie-sa8540p" compatible string and reuse the 1.9.0 ops.
Note that like for SC8280XP, the SA8540P controllers need two or three interconnect clocks to be enabled.
Reviewed-by Rob Herring <[email protected]>
Reviewed-by Manivannan Sadhasivam <[email protected]>
Signed-off-by Johan Hovold <[email protected]>

Johan Hovold

author

2022-07-14 07:15 UTC #9 lore raw

PATCH v2 6/8 PCI: qcom: Make all optional clocks optional

The kernel is not a devicetree validator and does not need to re-encode information which is already available in the devicetree.

This is specifically true for the optional PCIe clocks, some of which are really interconnect clocks.

Treat also the 2.7.0 optional clocks as truly optional instead of maintaining a list of clocks per compatible (including two compatible strings for the two identical controllers on sm8450) just to validate the devicetree.

Reviewed-by Rob Herring <[email protected]>

Reviewed-by Manivannan Sadhasivam <[email protected]>

---
 drivers/pci/controller/dwc/pcie-qcom.c | 28 ++++----------------------
 1 file changed, 4 insertions(+), 24 deletions(-)

drivers/pci/controller/dwc/pcie-qcom.c +4 ~~-24~~

index 699cd8b0f38e..1339f05bee65 100644
@@ -212,10 +212,6 @@ struct qcom_pcie_ops {
 
 struct qcom_pcie_cfg {
 	const struct qcom_pcie_ops *ops;
-	unsigned int has_tbu_clk:1;
-	unsigned int has_ddrss_sf_tbu_clk:1;
-	unsigned int has_aggre0_clk:1;
-	unsigned int has_aggre1_clk:1;
 };
 
 struct qcom_pcie {

@@ -1193,14 +1189,6 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
 	res->clks[idx++].id = "bus_master";
 	res->clks[idx++].id = "bus_slave";
 	res->clks[idx++].id = "slave_q2a";
-	if (pcie->cfg->has_tbu_clk)
-		res->clks[idx++].id = "tbu";
-	if (pcie->cfg->has_ddrss_sf_tbu_clk)
-		res->clks[idx++].id = "ddrss_sf_tbu";
-	if (pcie->cfg->has_aggre0_clk)
-		res->clks[idx++].id = "aggre0";
-	if (pcie->cfg->has_aggre1_clk)
-		res->clks[idx++].id = "aggre1";
 
 	num_clks = idx;

@@ -1208,6 +1196,10 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
 	if (ret < 0)
 		return ret;
 
+	res->clks[idx++].id = "tbu";
+	res->clks[idx++].id = "ddrss_sf_tbu";
+	res->clks[idx++].id = "aggre0";
+	res->clks[idx++].id = "aggre1";
 	res->clks[idx++].id = "noc_aggr_4";
 	res->clks[idx++].id = "noc_aggr_south_sf";
 	res->clks[idx++].id = "cnoc_qx";

@@ -1636,17 +1628,14 @@ static const struct qcom_pcie_cfg ipq4019_cfg = {
 
 static const struct qcom_pcie_cfg sa8540p_cfg = {
 	.ops = &ops_1_9_0,
-	.has_ddrss_sf_tbu_clk = true,
 };
 
 static const struct qcom_pcie_cfg sc8280xp_cfg = {
 	.ops = &ops_1_9_0,
-	.has_ddrss_sf_tbu_clk = true,
 };
 
 static const struct qcom_pcie_cfg sdm845_cfg = {
 	.ops = &ops_2_7_0,
-	.has_tbu_clk = true,
 };
 
 static const struct qcom_pcie_cfg sm8150_cfg = {

@@ -1658,31 +1647,22 @@ static const struct qcom_pcie_cfg sm8150_cfg = {
 
 static const struct qcom_pcie_cfg sm8250_cfg = {
 	.ops = &ops_1_9_0,
-	.has_tbu_clk = true,
-	.has_ddrss_sf_tbu_clk = true,
 };
 
 static const struct qcom_pcie_cfg sm8450_pcie0_cfg = {
 	.ops = &ops_1_9_0,
-	.has_ddrss_sf_tbu_clk = true,
-	.has_aggre0_clk = true,
-	.has_aggre1_clk = true,
 };
 
 static const struct qcom_pcie_cfg sm8450_pcie1_cfg = {
 	.ops = &ops_1_9_0,
-	.has_ddrss_sf_tbu_clk = true,
-	.has_aggre1_clk = true,
 };
 
 static const struct qcom_pcie_cfg sc7280_cfg = {
 	.ops = &ops_1_9_0,
-	.has_tbu_clk = true,
 };
 
 static const struct qcom_pcie_cfg sc8180x_cfg = {
 	.ops = &ops_1_9_0,
-	.has_tbu_clk = true,
 };
 
 static const struct qcom_pcie_cfg ipq6018_cfg = {

Signature · 1 line

2.35.1

Brian Masney

Reviewed-by on v2 6/8

2022-07-14 14:31 UTC #10 lore raw

Re: [PATCH v2 6/8] PCI: qcom: Make all optional clocks optional

Quoted 6 lines · Johan Hovold

The kernel is not a devicetree validator and does not need to re-encode information which is already available in the devicetree.
This is specifically true for the optional PCIe clocks, some of which are really interconnect clocks.

Quoted 8 lines

Treat also the 2.7.0 optional clocks as truly optional instead of maintaining a list of clocks per compatible (including two compatible strings for the two identical controllers on sm8450) just to validate the devicetree.
Reviewed-by Rob Herring <[email protected]>
Reviewed-by Manivannan Sadhasivam <[email protected]>
Signed-off-by Johan Hovold <[email protected]>

Dmitry Baryshkov

Reviewed-by on v2 6/8

2022-07-18 10:37 UTC #11 lore raw

Re: [PATCH v2 6/8] PCI: qcom: Make all optional clocks optional

Quoted 6 lines · Johan Hovold

The kernel is not a devicetree validator and does not need to re-encode information which is already available in the devicetree.
This is specifically true for the optional PCIe clocks, some of which are really interconnect clocks.

Quoted 7 lines

Treat also the 2.7.0 optional clocks as truly optional instead of maintaining a list of clocks per compatible (including two compatible strings for the two identical controllers on sm8450) just to validate the devicetree.
Reviewed-by Rob Herring <[email protected]>
Reviewed-by Manivannan Sadhasivam <[email protected]>

Reviewed-by Dmitry Baryshkov <[email protected]>

Quoted 1 line

Signed-off-by Johan Hovold <[email protected]>--

With best wishes
Dmitry

Johan Hovold

author

2022-07-14 07:14 UTC #12 lore raw

PATCH v2 7/8 PCI: qcom: Clean up IP configurations

The various IP versions have different configurations that are encoded in separate sets of operation callbacks. Currently, there is no need for also maintaining corresponding sets of data parameters, but it is conceivable that these may again be found useful (e.g. to implement minor variations of the operation callbacks).

Rename the default configuration structures after the IP version they apply to so that they can more easily be reused by different SoCs.

Note that SoC specific configurations can be added later if need arises (e.g. cfg_sc8280xp).

Reviewed-by Rob Herring <[email protected]>

Reviewed-by Manivannan Sadhasivam <[email protected]>

---
 drivers/pci/controller/dwc/pcie-qcom.c | 89 +++++++++-----------------
 1 file changed, 29 insertions(+), 60 deletions(-)

drivers/pci/controller/dwc/pcie-qcom.c +29 ~~-60~~

index 1339f05bee65..8dddb72f8647 100644
@@ -1606,66 +1606,35 @@ static const struct qcom_pcie_ops ops_2_9_0 = {
 	.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
 };
 
-static const struct qcom_pcie_cfg apq8084_cfg = {
+static const struct qcom_pcie_cfg cfg_1_0_0 = {
 	.ops = &ops_1_0_0,
 };
 
-static const struct qcom_pcie_cfg ipq8064_cfg = {
+static const struct qcom_pcie_cfg cfg_1_9_0 = {
+	.ops = &ops_1_9_0,
+};
+
+static const struct qcom_pcie_cfg cfg_2_1_0 = {
 	.ops = &ops_2_1_0,
 };
 
-static const struct qcom_pcie_cfg msm8996_cfg = {
+static const struct qcom_pcie_cfg cfg_2_3_2 = {
 	.ops = &ops_2_3_2,
 };
 
-static const struct qcom_pcie_cfg ipq8074_cfg = {
+static const struct qcom_pcie_cfg cfg_2_3_3 = {
 	.ops = &ops_2_3_3,
 };
 
-static const struct qcom_pcie_cfg ipq4019_cfg = {
+static const struct qcom_pcie_cfg cfg_2_4_0 = {
 	.ops = &ops_2_4_0,
 };
 
-static const struct qcom_pcie_cfg sa8540p_cfg = {
-	.ops = &ops_1_9_0,
-};
-
-static const struct qcom_pcie_cfg sc8280xp_cfg = {
-	.ops = &ops_1_9_0,
-};
-
-static const struct qcom_pcie_cfg sdm845_cfg = {
+static const struct qcom_pcie_cfg cfg_2_7_0 = {
 	.ops = &ops_2_7_0,
 };
 
-static const struct qcom_pcie_cfg sm8150_cfg = {
-	/* sm8150 has qcom IP rev 1.5.0. However 1.5.0 ops are same as
-	 * 1.9.0, so reuse the same.
-	 */
-	.ops = &ops_1_9_0,
-};
-
-static const struct qcom_pcie_cfg sm8250_cfg = {
-	.ops = &ops_1_9_0,
-};
-
-static const struct qcom_pcie_cfg sm8450_pcie0_cfg = {
-	.ops = &ops_1_9_0,
-};
-
-static const struct qcom_pcie_cfg sm8450_pcie1_cfg = {
-	.ops = &ops_1_9_0,
-};
-
-static const struct qcom_pcie_cfg sc7280_cfg = {
-	.ops = &ops_1_9_0,
-};
-
-static const struct qcom_pcie_cfg sc8180x_cfg = {
-	.ops = &ops_1_9_0,
-};
-
-static const struct qcom_pcie_cfg ipq6018_cfg = {
+static const struct qcom_pcie_cfg cfg_2_9_0 = {
 	.ops = &ops_2_9_0,
 };

@@ -1780,24 +1749,24 @@ static int qcom_pcie_remove(struct platform_device *pdev)
 }
 
 static const struct of_device_id qcom_pcie_match[] = {
-	{ .compatible = "qcom,pcie-apq8084", .data = &apq8084_cfg },
-	{ .compatible = "qcom,pcie-ipq8064", .data = &ipq8064_cfg },
-	{ .compatible = "qcom,pcie-ipq8064-v2", .data = &ipq8064_cfg },
-	{ .compatible = "qcom,pcie-apq8064", .data = &ipq8064_cfg },
-	{ .compatible = "qcom,pcie-msm8996", .data = &msm8996_cfg },
-	{ .compatible = "qcom,pcie-ipq8074", .data = &ipq8074_cfg },
-	{ .compatible = "qcom,pcie-ipq4019", .data = &ipq4019_cfg },
-	{ .compatible = "qcom,pcie-qcs404", .data = &ipq4019_cfg },
-	{ .compatible = "qcom,pcie-sa8540p", .data = &sa8540p_cfg },
-	{ .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg },
-	{ .compatible = "qcom,pcie-sm8150", .data = &sm8150_cfg },
-	{ .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg },
-	{ .compatible = "qcom,pcie-sc8180x", .data = &sc8180x_cfg },
-	{ .compatible = "qcom,pcie-sc8280xp", .data = &sc8280xp_cfg },
-	{ .compatible = "qcom,pcie-sm8450-pcie0", .data = &sm8450_pcie0_cfg },
-	{ .compatible = "qcom,pcie-sm8450-pcie1", .data = &sm8450_pcie1_cfg },
-	{ .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg },
-	{ .compatible = "qcom,pcie-ipq6018", .data = &ipq6018_cfg },
+	{ .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 },
+	{ .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
+	{ .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
+	{ .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
+	{ .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
+	{ .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
+	{ .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 },
+	{ .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
+	{ .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 },
+	{ .compatible = "qcom,pcie-sdm845", .data = &cfg_2_7_0 },
+	{ .compatible = "qcom,pcie-sm8150", .data = &cfg_1_9_0 },
+	{ .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 },
+	{ .compatible = "qcom,pcie-sc8180x", .data = &cfg_1_9_0 },
+	{ .compatible = "qcom,pcie-sc8280xp", .data = &cfg_1_9_0 },
+	{ .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 },
+	{ .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 },
+	{ .compatible = "qcom,pcie-sc7280", .data = &cfg_1_9_0 },
+	{ .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, qcom_pcie_match);

Signature · 1 line

2.35.1

Brian Masney

Reviewed-by on v2 7/8

2022-07-14 14:43 UTC #13 lore raw

Re: [PATCH v2 7/8] PCI: qcom: Clean up IP configurations

Quoted 9 lines · Johan Hovold

The various IP versions have different configurations that are encoded in separate sets of operation callbacks. Currently, there is no need for also maintaining corresponding sets of data parameters, but it is conceivable that these may again be found useful (e.g. to implement minor variations of the operation callbacks).
Rename the default configuration structures after the IP version they apply to so that they can more easily be reused by different SoCs.

Quoted 6 lines

Note that SoC specific configurations can be added later if need arises (e.g. cfg_sc8280xp).
Reviewed-by Rob Herring <[email protected]>
Reviewed-by Manivannan Sadhasivam <[email protected]>
Signed-off-by Johan Hovold <[email protected]>

Dmitry Baryshkov

Reviewed-by on v2 7/8

2022-07-18 10:39 UTC #14 lore raw

Re: [PATCH v2 7/8] PCI: qcom: Clean up IP configurations

Quoted 9 lines · Johan Hovold

The various IP versions have different configurations that are encoded in separate sets of operation callbacks. Currently, there is no need for also maintaining corresponding sets of data parameters, but it is conceivable that these may again be found useful (e.g. to implement minor variations of the operation callbacks).
Rename the default configuration structures after the IP version they apply to so that they can more easily be reused by different SoCs.

Quoted 6 lines

Note that SoC specific configurations can be added later if need arises (e.g. cfg_sc8280xp).
Reviewed-by Rob Herring <[email protected]>
Reviewed-by Manivannan Sadhasivam <[email protected]>
Signed-off-by Johan Hovold <[email protected]>

If we have nothing left in the qcom_pcie_cfg other than the .ops, what about dropping the qcom_pcie_cfg completely and using the qcom_pcie_ops as match data?

This patch is nevertheless:

Reviewed-by Dmitry Baryshkov <[email protected]>

Quoted 129 lines

---
  drivers/pci/controller/dwc/pcie-qcom.c | 89 +++++++++-----------------
  1 file changed, 29 insertions(+), 60 deletions(-)

drivers/pci/controller/dwc/pcie-qcom.c +29 ~~-60~~

index 1339f05bee65..8dddb72f8647 100644
@@ -1606,66 +1606,35 @@ static const struct qcom_pcie_ops ops_2_9_0 = {
  	.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
  };
 
-static const struct qcom_pcie_cfg apq8084_cfg = {
+static const struct qcom_pcie_cfg cfg_1_0_0 = {
  	.ops = &ops_1_0_0,
  };
 
-static const struct qcom_pcie_cfg ipq8064_cfg = {
+static const struct qcom_pcie_cfg cfg_1_9_0 = {
+	.ops = &ops_1_9_0,
+};
+
+static const struct qcom_pcie_cfg cfg_2_1_0 = {
  	.ops = &ops_2_1_0,
  };
 
-static const struct qcom_pcie_cfg msm8996_cfg = {
+static const struct qcom_pcie_cfg cfg_2_3_2 = {
  	.ops = &ops_2_3_2,
  };
 
-static const struct qcom_pcie_cfg ipq8074_cfg = {
+static const struct qcom_pcie_cfg cfg_2_3_3 = {
  	.ops = &ops_2_3_3,
  };
 
-static const struct qcom_pcie_cfg ipq4019_cfg = {
+static const struct qcom_pcie_cfg cfg_2_4_0 = {
  	.ops = &ops_2_4_0,
  };
 
-static const struct qcom_pcie_cfg sa8540p_cfg = {
-	.ops = &ops_1_9_0,
-};
-
-static const struct qcom_pcie_cfg sc8280xp_cfg = {
-	.ops = &ops_1_9_0,
-};
-
-static const struct qcom_pcie_cfg sdm845_cfg = {
+static const struct qcom_pcie_cfg cfg_2_7_0 = {
  	.ops = &ops_2_7_0,
  };
 
-static const struct qcom_pcie_cfg sm8150_cfg = {
-	/* sm8150 has qcom IP rev 1.5.0. However 1.5.0 ops are same as
-	 * 1.9.0, so reuse the same.
-	 */
-	.ops = &ops_1_9_0,
-};
-
-static const struct qcom_pcie_cfg sm8250_cfg = {
-	.ops = &ops_1_9_0,
-};
-
-static const struct qcom_pcie_cfg sm8450_pcie0_cfg = {
-	.ops = &ops_1_9_0,
-};
-
-static const struct qcom_pcie_cfg sm8450_pcie1_cfg = {
-	.ops = &ops_1_9_0,
-};
-
-static const struct qcom_pcie_cfg sc7280_cfg = {
-	.ops = &ops_1_9_0,
-};
-
-static const struct qcom_pcie_cfg sc8180x_cfg = {
-	.ops = &ops_1_9_0,
-};
-
-static const struct qcom_pcie_cfg ipq6018_cfg = {
+static const struct qcom_pcie_cfg cfg_2_9_0 = {
  	.ops = &ops_2_9_0,
  };

@@ -1780,24 +1749,24 @@ static int qcom_pcie_remove(struct platform_device *pdev)
  }
 
  static const struct of_device_id qcom_pcie_match[] = {
-	{ .compatible = "qcom,pcie-apq8084", .data = &apq8084_cfg },
-	{ .compatible = "qcom,pcie-ipq8064", .data = &ipq8064_cfg },
-	{ .compatible = "qcom,pcie-ipq8064-v2", .data = &ipq8064_cfg },
-	{ .compatible = "qcom,pcie-apq8064", .data = &ipq8064_cfg },
-	{ .compatible = "qcom,pcie-msm8996", .data = &msm8996_cfg },
-	{ .compatible = "qcom,pcie-ipq8074", .data = &ipq8074_cfg },
-	{ .compatible = "qcom,pcie-ipq4019", .data = &ipq4019_cfg },
-	{ .compatible = "qcom,pcie-qcs404", .data = &ipq4019_cfg },
-	{ .compatible = "qcom,pcie-sa8540p", .data = &sa8540p_cfg },
-	{ .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg },
-	{ .compatible = "qcom,pcie-sm8150", .data = &sm8150_cfg },
-	{ .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg },
-	{ .compatible = "qcom,pcie-sc8180x", .data = &sc8180x_cfg },
-	{ .compatible = "qcom,pcie-sc8280xp", .data = &sc8280xp_cfg },
-	{ .compatible = "qcom,pcie-sm8450-pcie0", .data = &sm8450_pcie0_cfg },
-	{ .compatible = "qcom,pcie-sm8450-pcie1", .data = &sm8450_pcie1_cfg },
-	{ .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg },
-	{ .compatible = "qcom,pcie-ipq6018", .data = &ipq6018_cfg },
+	{ .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 },
+	{ .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
+	{ .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
+	{ .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
+	{ .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
+	{ .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
+	{ .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 },
+	{ .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
+	{ .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 },
+	{ .compatible = "qcom,pcie-sdm845", .data = &cfg_2_7_0 },
+	{ .compatible = "qcom,pcie-sm8150", .data = &cfg_1_9_0 },
+	{ .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 },
+	{ .compatible = "qcom,pcie-sc8180x", .data = &cfg_1_9_0 },
+	{ .compatible = "qcom,pcie-sc8280xp", .data = &cfg_1_9_0 },
+	{ .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 },
+	{ .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 },
+	{ .compatible = "qcom,pcie-sc7280", .data = &cfg_1_9_0 },
+	{ .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 },
  	{ }
  };
  MODULE_DEVICE_TABLE(of, qcom_pcie_match);

Signature · 2 lines

With best wishes
Dmitry

Johan Hovold

2022-07-18 12:00 UTC #15 lore raw

Re: [PATCH v2 7/8] PCI: qcom: Clean up IP configurations

Quoted 13 lines · Dmitry Baryshkov

Quoted 12 lines · Johan Hovold
The various IP versions have different configurations that are encoded in separate sets of operation callbacks. Currently, there is no need for also maintaining corresponding sets of data parameters, but it is conceivable that these may again be found useful (e.g. to implement minor variations of the operation callbacks).
Rename the default configuration structures after the IP version they apply to so that they can more easily be reused by different SoCs.
Note that SoC specific configurations can be added later if need arises (e.g. cfg_sc8280xp).

Quoted 8 lines

Quoted 3 lines
Reviewed-by Rob Herring <[email protected]>
Reviewed-by Manivannan Sadhasivam <[email protected]>
Signed-off-by Johan Hovold <[email protected]>
If we have nothing left in the qcom_pcie_cfg other than the .ops, what about dropping the qcom_pcie_cfg completely and using the qcom_pcie_ops as match data?

As I mention above I decided to keep the config structures as they can be used to implement minor variations of the ops.

Quoted 3 lines

This patch is nevertheless:
Reviewed-by Dmitry Baryshkov <[email protected]>

Thanks for reviewing.

Johan

Johan Hovold

author

2022-07-14 07:14 UTC #16 lore raw

PATCH v2 8/8 PCI: qcom: Sort device-id table

Sort the device-id table entries alphabetically by compatible string to make it easier to find entries and add new ones.

---
 drivers/pci/controller/dwc/pcie-qcom.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

drivers/pci/controller/dwc/pcie-qcom.c +6 -6

index 8dddb72f8647..fea921cca8fa 100644
@@ -1749,24 +1749,24 @@ static int qcom_pcie_remove(struct platform_device *pdev)
 }
 
 static const struct of_device_id qcom_pcie_match[] = {
+	{ .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
 	{ .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 },
+	{ .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 },
 	{ .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
 	{ .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
-	{ .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
-	{ .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
 	{ .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
 	{ .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 },
+	{ .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
 	{ .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
 	{ .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 },
+	{ .compatible = "qcom,pcie-sc7280", .data = &cfg_1_9_0 },
+	{ .compatible = "qcom,pcie-sc8180x", .data = &cfg_1_9_0 },
+	{ .compatible = "qcom,pcie-sc8280xp", .data = &cfg_1_9_0 },
 	{ .compatible = "qcom,pcie-sdm845", .data = &cfg_2_7_0 },
 	{ .compatible = "qcom,pcie-sm8150", .data = &cfg_1_9_0 },
 	{ .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 },
-	{ .compatible = "qcom,pcie-sc8180x", .data = &cfg_1_9_0 },
-	{ .compatible = "qcom,pcie-sc8280xp", .data = &cfg_1_9_0 },
 	{ .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 },
 	{ .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 },
-	{ .compatible = "qcom,pcie-sc7280", .data = &cfg_1_9_0 },
-	{ .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, qcom_pcie_match);

Signature · 1 line

2.35.1

Brian Masney

2022-07-14 14:27 UTC #17 lore raw

Re: [PATCH v2 8/8] PCI: qcom: Sort device-id table

Quoted 15 lines · Johan Hovold

Sort the device-id table entries alphabetically by compatible string to make it easier to find entries and add new ones.
Signed-off-by Johan Hovold <[email protected]>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)
drivers/pci/controller/dwc/pcie-qcom.c +0 -0
index 8dddb72f8647..fea921cca8fa 100644
@@ -1749,24 +1749,24 @@ static int qcom_pcie_remove(struct platform_device *pdev)
 }
 

drivers/pci/controller/dwc/pcie-qcom.c static int qcom_pcie_remove(struct platform_device *pdev) · line 1758

Quoted 10 lines

drivers/pci/controller/dwc/pcie-qcom.c +2 -2

 static const struct of_device_id qcom_pcie_match[] = {
+	{ .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
 	{ .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 },
+	{ .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 },
 	{ .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
 	{ .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
-	{ .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
-	{ .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
 	{ .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
 	{ .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 },

qcom,pcie-ipq4019 should be moved up above qcom,pcie-ipq6018.

Brian

Johan Hovold

2022-07-15 07:43 UTC #18 lore raw

Re: [PATCH v2 8/8] PCI: qcom: Sort device-id table

Quoted 16 lines · Brian Masney

Quoted 15 lines · Johan Hovold
Sort the device-id table entries alphabetically by compatible string to make it easier to find entries and add new ones.
Signed-off-by Johan Hovold <[email protected]>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)
drivers/pci/controller/dwc/pcie-qcom.c +0 -0
index 8dddb72f8647..fea921cca8fa 100644
@@ -1749,24 +1749,24 @@ static int qcom_pcie_remove(struct platform_device *pdev)
 }
 

Quoted 12 lines

drivers/pci/controller/dwc/pcie-qcom.c static int qcom_pcie_remove(struct platform_device *pdev) · line 1758

Quoted 10 lines

drivers/pci/controller/dwc/pcie-qcom.c +2 -2

 static const struct of_device_id qcom_pcie_match[] = {
+	{ .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
 	{ .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 },
+	{ .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 },
 	{ .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
 	{ .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
-	{ .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
-	{ .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
 	{ .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
 	{ .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 },

qcom,pcie-ipq4019 should be moved up above qcom,pcie-ipq6018.

If we only had some sort of machine that could sort strings for us... ;) I'll rely on vim for this from now on.

Perhaps Bjorn H can fix that up when applying unless I'll be sending a v3 for some other reason. This series still depends on the MSI rework to be applied first.

Thanks for reviewing.

Johan

Brian Masney

Reviewed-by

2022-07-15 09:26 UTC #19 lore raw

Re: [PATCH v2 8/8] PCI: qcom: Sort device-id table

Quoted 8 lines · Johan Hovold

If we only had some sort of machine that could sort strings for us... ;) I'll rely on vim for this from now on.
Perhaps Bjorn H can fix that up when applying unless I'll be sending a v3 for some other reason. This series still depends on the MSI rework to be applied first.
Thanks for reviewing.

OK, sounds good... once it's fixed, my R-b can be added:

Lorenzo Pieralisi

maintainer

2022-08-16 16:10 UTC #20 lore raw

Re: [PATCH v2 8/8] PCI: qcom: Sort device-id table

[0] https://lore.kernel.org/all/[email protected]/

Quoted 30 lines · Johan Hovold

Quoted 16 lines · Brian Masney
Quoted 15 lines · Johan Hovold
Sort the device-id table entries alphabetically by compatible string to make it easier to find entries and add new ones.
Signed-off-by Johan Hovold <[email protected]>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)
drivers/pci/controller/dwc/pcie-qcom.c +0 -0
index 8dddb72f8647..fea921cca8fa 100644
@@ -1749,24 +1749,24 @@ static int qcom_pcie_remove(struct platform_device *pdev)
 }
 
Quoted 12 lines
drivers/pci/controller/dwc/pcie-qcom.c static int qcom_pcie_remove(struct platform_device *pdev) · line 1758
Quoted 10 lines
drivers/pci/controller/dwc/pcie-qcom.c +2 -2
 static const struct of_device_id qcom_pcie_match[] = {
+	{ .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
 	{ .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 },
+	{ .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 },
 	{ .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
 	{ .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
-	{ .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
-	{ .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
 	{ .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
 	{ .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 },
qcom,pcie-ipq4019 should be moved up above qcom,pcie-ipq6018.

Quoted 6 lines

If we only had some sort of machine that could sort strings for us... ;) I'll rely on vim for this from now on.
Perhaps Bjorn H can fix that up when applying unless I'll be sending a v3 for some other reason. This series still depends on the MSI rework to be applied first.

I can do it while applying. A link to the lore archive for the MSI rework please (I don't think it was merged for v6.0) ? I was away for two months, catching up with threads.

Thanks,
Lorenzo

Quoted 3 lines

Thanks for reviewing.
Johan

Andrew Halaney

2022-08-18 20:11 UTC #21 lore raw

Re: [PATCH v2 8/8] PCI: qcom: Sort device-id table

Hi Lorenzo,

Quoted 34 lines · Lorenzo Pieralisi

Quoted 33 lines · Johan Hovold
Quoted 16 lines · Brian Masney
Quoted 15 lines · Johan Hovold
Sort the device-id table entries alphabetically by compatible string to make it easier to find entries and add new ones.
Signed-off-by Johan Hovold <[email protected]>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)
drivers/pci/controller/dwc/pcie-qcom.c +0 -0
index 8dddb72f8647..fea921cca8fa 100644
@@ -1749,24 +1749,24 @@ static int qcom_pcie_remove(struct platform_device *pdev)
 }
 
Quoted 12 lines
drivers/pci/controller/dwc/pcie-qcom.c static int qcom_pcie_remove(struct platform_device *pdev) · line 1758
Quoted 10 lines
drivers/pci/controller/dwc/pcie-qcom.c +2 -2
 static const struct of_device_id qcom_pcie_match[] = {
+	{ .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
 	{ .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 },
+	{ .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 },
 	{ .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
 	{ .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
-	{ .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
-	{ .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
 	{ .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
 	{ .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 },
qcom,pcie-ipq4019 should be moved up above qcom,pcie-ipq6018.
If we only had some sort of machine that could sort strings for us... ;) I'll rely on vim for this from now on.

Quoted 7 lines

Quoted 3 lines
Perhaps Bjorn H can fix that up when applying unless I'll be sending a v3 for some other reason. This series still depends on the MSI rework to be applied first.
I can do it while applying. A link to the lore archive for the MSI rework please (I don't think it was merged for v6.0) ? I was away for two months, catching up with threads.

I don't see a reply to this, so here I am following up out of interest for getting this in mainline for my x13s laptop to use.

It appears the MSI rework[0] (which is in the cover letter here so I know I grabbed the right thing) was applied in 6.0:

ahalaney@halaneylaptop ~/git/linux (git)-[remotes/upstream/HEAD] % git log --oneline --abbrev=12 --grep=2436629 v6.0-rc1 -- drivers/pci/controller/dwc/ cd761378e62c PCI: dwc: Handle MSIs routed to multiple GIC interrupts
db388348acff PCI: dwc: Convert struct pcie_port.msi_irq to an array
226ec087497a PCI: dwc: Split MSI IRQ parsing/allocation to a separate function
3c62f878a969 PCI: dwc: Correct msi_irq condition in dw_pcie_free_msi()
ahalaney@halaneylaptop ~/git/linux (git)-[remotes/upstream/HEAD] %

Just a friendly FYI, hope that helps!

Thanks,
Andrew

Quoted 7 lines

Thanks,
Lorenzo
Quoted 3 lines
Thanks for reviewing.
Johan

Lorenzo Pieralisi

maintainer

2022-08-19 07:47 UTC #22 lore raw

Re: [PATCH v2 8/8] PCI: qcom: Sort device-id table

Quoted 51 lines · Andrew Halaney

Hi Lorenzo,
Quoted 34 lines · Lorenzo Pieralisi
Quoted 33 lines · Johan Hovold
Quoted 16 lines · Brian Masney
Quoted 15 lines · Johan Hovold
Sort the device-id table entries alphabetically by compatible string to make it easier to find entries and add new ones.
Signed-off-by Johan Hovold <[email protected]>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)
drivers/pci/controller/dwc/pcie-qcom.c +0 -0
index 8dddb72f8647..fea921cca8fa 100644
@@ -1749,24 +1749,24 @@ static int qcom_pcie_remove(struct platform_device *pdev)
 }
 
Quoted 12 lines
drivers/pci/controller/dwc/pcie-qcom.c static int qcom_pcie_remove(struct platform_device *pdev) · line 1758
Quoted 10 lines
drivers/pci/controller/dwc/pcie-qcom.c +2 -2
 static const struct of_device_id qcom_pcie_match[] = {
+	{ .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
 	{ .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 },
+	{ .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 },
 	{ .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
 	{ .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
-	{ .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
-	{ .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
 	{ .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
 	{ .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 },
qcom,pcie-ipq4019 should be moved up above qcom,pcie-ipq6018.
If we only had some sort of machine that could sort strings for us... ;) I'll rely on vim for this from now on.
Quoted 7 lines
Quoted 3 lines
Perhaps Bjorn H can fix that up when applying unless I'll be sending a v3 for some other reason. This series still depends on the MSI rework to be applied first.
I can do it while applying. A link to the lore archive for the MSI rework please (I don't think it was merged for v6.0) ? I was away for two months, catching up with threads.
I don't see a reply to this, so here I am following up out of interest for getting this in mainline for my x13s laptop to use.
It appears the MSI rework[0] (which is in the cover letter here so I know I grabbed the right thing) was applied in 6.0:

Quoted 8 lines

ahalaney@halaneylaptop ~/git/linux (git)-[remotes/upstream/HEAD] % git log --oneline --abbrev=12 --grep=2436629 v6.0-rc1 -- drivers/pci/controller/dwc/ cd761378e62c PCI: dwc: Handle MSIs routed to multiple GIC interrupts
db388348acff PCI: dwc: Convert struct pcie_port.msi_irq to an array
226ec087497a PCI: dwc: Split MSI IRQ parsing/allocation to a separate function
3c62f878a969 PCI: dwc: Correct msi_irq condition in dw_pcie_free_msi()
ahalaney@halaneylaptop ~/git/linux (git)-[remotes/upstream/HEAD] %
Just a friendly FYI, hope that helps!

Thanks for the heads-up, I will merge this series then.

Lorenzo

Quoted 13 lines

[0] https://lore.kernel.org/all/[email protected]/
Thanks,
Andrew
Quoted 7 lines
Thanks,
Lorenzo
Quoted 3 lines
Thanks for reviewing.
Johan

Johan Hovold

2022-08-22 12:46 UTC #23 lore raw

Re: [PATCH v2 8/8] PCI: qcom: Sort device-id table

Quoted 27 lines · Lorenzo Pieralisi

Quoted 26 lines · Andrew Halaney
Hi Lorenzo,
Quoted 9 lines · Lorenzo Pieralisi
Quoted 3 lines · Johan Hovold
Perhaps Bjorn H can fix that up when applying unless I'll be sending a v3 for some other reason. This series still depends on the MSI rework to be applied first.
I can do it while applying. A link to the lore archive for the MSI rework please (I don't think it was merged for v6.0) ? I was away for two months, catching up with threads.
I don't see a reply to this, so here I am following up out of interest for getting this in mainline for my x13s laptop to use.
It appears the MSI rework[0] (which is in the cover letter here so I know I grabbed the right thing) was applied in 6.0:
ahalaney@halaneylaptop ~/git/linux (git)-[remotes/upstream/HEAD] % git log --oneline --abbrev=12 --grep=2436629 v6.0-rc1 -- drivers/pci/controller/dwc/ cd761378e62c PCI: dwc: Handle MSIs routed to multiple GIC interrupts
db388348acff PCI: dwc: Convert struct pcie_port.msi_irq to an array
226ec087497a PCI: dwc: Split MSI IRQ parsing/allocation to a separate function
3c62f878a969 PCI: dwc: Correct msi_irq condition in dw_pcie_free_msi()
ahalaney@halaneylaptop ~/git/linux (git)-[remotes/upstream/HEAD] %

Quoted 3 lines

Quoted 1 line
Just a friendly FYI, hope that helps!
Thanks for the heads-up, I will merge this series then.

I was out-of-office last week so thanks for digging out that link, Andrew.

Johan

Bjorn Helgaas

2022-07-15 22:37 UTC #24 lore raw

[1] https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git/log/?h=839fbdee4c08
[2] https://lore.kernel.org/linux-pci/[email protected]/

Quoted 2 lines · Johan Hovold

This series adds support for the PCIe controllers found on SC8280XP and SA8540P.

These look fairly straightforward, and I don't mind doing minor tweaks and conflict resolution, but given that we've got four or five cooks in the qcom kitchen, I'm looking for an ack from Stan before spending too much time on this.

Quoted 8 lines

Included are also three patches that clean up the way the driver handles different IP revisions (e.g. by modelling optional clocks as being truly optional).
These patches depend on the recently merged (but currently held off?) PIPE clock series:
	https://lore.kernel.org/all/[email protected]/

As far as I know it's on pci/ctrl/qcom [1], in -next, and ready to go. It's based on Bjorn A's immutable branch [2].

Quoted 8 lines

as well as the about-to-be-merged MSI series (v17):
	https://lore.kernel.org/all/[email protected]/
Note that the final patch in the PIPE clock series is currently missing from the pci/ctrl/qcom-pending branch:
	https://lore.kernel.org/all/[email protected]/

I think I fixed that, let me know if not; see [1].

Quoted 27 lines

Changes in v2
- drop the two DT schema fixes which have been applied by Bjorn H and squashed into the MSI v17 series by Dmitry, respectively
- rebase on pci/ctrl/qcom-pending (2022-07-14)
- fix compatible sort order (Krzysztof)
- amend commit message for first patch to clarify motivation (Krzysztof)
- add acks and reviewed-by tags from Dmitry, Krzysztof, Mani and Rob
Johan Hovold (8):
dt-bindings: PCI: qcom: Enumerate platforms with single msi interrupt
dt-bindings: PCI: qcom: Add SC8280XP to binding
dt-bindings: PCI: qcom: Add SA8540P to binding
PCI: qcom: Add support for SC8280XP
PCI: qcom: Add support for SA8540P
PCI: qcom: Make all optional clocks optional
PCI: qcom: Clean up IP configurations
PCI: qcom: Sort device-id table
 .../devicetree/bindings/pci/qcom,pcie.yaml    |  70 +++++++++-
 drivers/pci/controller/dwc/pcie-qcom.c        | 121 +++++++-----------
 2 files changed, 114 insertions(+), 77 deletions(-)
Signature · 1 line
2.35.1

Johan Hovold

2022-07-18 10:16 UTC #25 lore raw

Quoted 8 lines · Bjorn Helgaas

Quoted 2 lines · Johan Hovold
This series adds support for the PCIe controllers found on SC8280XP and SA8540P.
These look fairly straightforward, and I don't mind doing minor tweaks and conflict resolution, but given that we've got four or five cooks in the qcom kitchen, I'm looking for an ack from Stan before spending too much time on this.

Sounds good. Stan's acked the series now too.

Since I rebased v2 on qcom-pending (and added the missing pipe clock patch), there shouldn't be any conflicts and the only fixup I'm aware of is the sort order of the "qcom,pcie-ipq4019" entry in patch 8/8.

Let me know if you prefer I fix that in a v3 otherwise these can be applied once the MSI series has been merged.

I saw Stan acking the binding in that series, not sure if the intention was to ack the whole series?

	https://lore.kernel.org/all/[email protected]/

Quoted 11 lines

Quoted 8 lines
Included are also three patches that clean up the way the driver handles different IP revisions (e.g. by modelling optional clocks as being truly optional).
These patches depend on the recently merged (but currently held off?) PIPE clock series:
	https://lore.kernel.org/all/[email protected]/
As far as I know it's on pci/ctrl/qcom [1], in -next, and ready to go. It's based on Bjorn A's immutable branch [2].

Right.

Quoted 7 lines

Quoted 7 lines
as well as the about-to-be-merged MSI series (v17):
	https://lore.kernel.org/all/[email protected]/
Note that the final patch in the PIPE clock series is currently missing from the pci/ctrl/qcom-pending branch:

Quoted 6 lines

Quoted 1 line
	https://lore.kernel.org/all/[email protected]/
I think I fixed that, let me know if not; see [1].
[1] https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git/log/?h=839fbdee4c08
[2] https://lore.kernel.org/linux-pci/[email protected]/

It appears to have been fixed in your branch now, but it hasn't yet made it into -next.

Quoted 10 lines

Quoted 10 lines
Changes in v2
- drop the two DT schema fixes which have been applied by Bjorn H and squashed into the MSI v17 series by Dmitry, respectively
- rebase on pci/ctrl/qcom-pending (2022-07-14)
- fix compatible sort order (Krzysztof)
- amend commit message for first patch to clarify motivation (Krzysztof)
- add acks and reviewed-by tags from Dmitry, Krzysztof, Mani and Rob

Quoted 9 lines

Quoted 9 lines
Johan Hovold (8):
dt-bindings: PCI: qcom: Enumerate platforms with single msi interrupt
dt-bindings: PCI: qcom: Add SC8280XP to binding
dt-bindings: PCI: qcom: Add SA8540P to binding
PCI: qcom: Add support for SC8280XP
PCI: qcom: Add support for SA8540P
PCI: qcom: Make all optional clocks optional
PCI: qcom: Clean up IP configurations
PCI: qcom: Sort device-id table

Johan

Stanimir Varbanov

Acked-by on the v2 series

2022-07-18 07:49 UTC #26 lore raw

Hi Johan,

Thank you for your work, especially for for the last three patches ;-)

Quoted 44 lines · Johan Hovold

This series adds support for the PCIe controllers found on SC8280XP and SA8540P.
Included are also three patches that clean up the way the driver handles different IP revisions (e.g. by modelling optional clocks as being truly optional).
These patches depend on the recently merged (but currently held off?) PIPE clock series:
	https://lore.kernel.org/all/[email protected]/
as well as the about-to-be-merged MSI series (v17):
	https://lore.kernel.org/all/[email protected]/
Note that the final patch in the PIPE clock series is currently missing from the pci/ctrl/qcom-pending branch:
	https://lore.kernel.org/all/[email protected]/
Johan
Changes in v2
- drop the two DT schema fixes which have been applied by Bjorn H and squashed into the MSI v17 series by Dmitry, respectively
- rebase on pci/ctrl/qcom-pending (2022-07-14)
- fix compatible sort order (Krzysztof)
- amend commit message for first patch to clarify motivation (Krzysztof)
- add acks and reviewed-by tags from Dmitry, Krzysztof, Mani and Rob
Johan Hovold (8):
dt-bindings: PCI: qcom: Enumerate platforms with single msi interrupt
dt-bindings: PCI: qcom: Add SC8280XP to binding
dt-bindings: PCI: qcom: Add SA8540P to binding
PCI: qcom: Add support for SC8280XP
PCI: qcom: Add support for SA8540P
PCI: qcom: Make all optional clocks optional
PCI: qcom: Clean up IP configurations
PCI: qcom: Sort device-id table

Quoted 4 lines

 .../devicetree/bindings/pci/qcom,pcie.yaml    |  70 +++++++++-
 drivers/pci/controller/dwc/pcie-qcom.c        | 121 +++++++-----------
 2 files changed, 114 insertions(+), 77 deletions(-)

For the whole set:

Acked-by Stanimir Varbanov <[email protected]>

Signature · 2 lines

regards,
Stan

Johan Hovold

2022-07-18 10:18 UTC #27 lore raw

Quoted 8 lines · Stanimir Varbanov

Hi Johan,
Thank you for your work, especially for for the last three patches ;-)
Quoted 3 lines · Johan Hovold
This series adds support for the PCIe controllers found on SC8280XP and SA8540P.

Quoted 7 lines

Quoted 3 lines
Included are also three patches that clean up the way the driver handles different IP revisions (e.g. by modelling optional clocks as being truly optional).
For the whole set:
Acked-by Stanimir Varbanov <[email protected]>

Thanks for the ack.

Could you take a look at Dmitry's MSI series that this series depends on as well?

I saw you acking the binding, but not the rest of the series it seems:

	https://lore.kernel.org/all/[email protected]/

Johan

Johan Hovold

2022-07-18 10:51 UTC #28 lore raw

Quoted 17 lines · Johan Hovold

Quoted 8 lines · Stanimir Varbanov
Hi Johan,
Thank you for your work, especially for for the last three patches ;-)
Quoted 3 lines · Johan Hovold
This series adds support for the PCIe controllers found on SC8280XP and SA8540P.
Quoted 7 lines
Quoted 3 lines
Included are also three patches that clean up the way the driver handles different IP revisions (e.g. by modelling optional clocks as being truly optional).
For the whole set:
Acked-by Stanimir Varbanov <[email protected]>

Quoted 8 lines

Thanks for the ack.
Could you take a look at Dmitry's MSI series that this series depends on as well?
I saw you acking the binding, but not the rest of the series it seems:
	https://lore.kernel.org/all/[email protected]/

Of course you only acked the single patched that touched the Qualcomm driver. Sorry about the noise.

Johan

Lorenzo Pieralisi

maintainer

2022-08-19 08:41 UTC #29 lore raw