arm64: qcom: sa8775p: add support for UFS
Subsystems (7)
v3 cover arm64: qcom: sa8775p: add support for UFS
From: Bartosz Golaszewski <[email protected]>
Update relevant DT bindings, add new config to the driver and add UFS and PHY nodes to the .dtsi and enable them in the board .dts for sa8775p-ride.
v2 -> v3:
- fix DT bindings: move allOf: below required:
- collect review tags
v1 -> v2:
- order new compatibles alphabetically
- rework the UFS PHY bindings to accomodate more clocks
- add a comment in the .dts regarding a non-standard clock used by the UFS PHY
Bartosz Golaszewski (5):
dt-bindings: ufs: qcom: add compatible for sa8775p
dt-bindings: phy: qmp-ufs: describe the UFS PHY for sa8775p
phy: qualcomm: phy-qcom-qmp-ufs: add definitions for sa8775p
arm64: dts: qcom: sa8775p: add UFS nodes
arm64: dts: qcom: sa8775p-ride: enable UFS
.../phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 26 ++++++++- .../devicetree/bindings/ufs/qcom,ufs.yaml | 2 + arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 19 ++++++ arch/arm64/boot/dts/qcom/sa8775p.dtsi | 58 +++++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 38 ++++++++++++ 5 files changed, 142 insertions(+), 1 deletion(-)
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2.37.2 -- linux-phy mailing list [email protected] https://lists.infradead.org/mailman/listinfo/linux-phy
PATCH v3 1/5 dt-bindings: ufs: qcom: add compatible for sa8775p
From: Bartosz Golaszewski <[email protected]>
Add the compatible string for the UFS on sa8775p platforms.
--- Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 2 ++ 1 file changed, 2 insertions(+)
Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +2 -0
@@ -26,6 +26,7 @@ properties: - qcom,msm8994-ufshc - qcom,msm8996-ufshc - qcom,msm8998-ufshc + - qcom,sa8775p-ufshc - qcom,sc8280xp-ufshc - qcom,sdm845-ufshc - qcom,sm6350-ufshc
@@ -105,6 +106,7 @@ allOf: contains: enum: - qcom,msm8998-ufshc + - qcom,sa8775p-ufshc - qcom,sc8280xp-ufshc - qcom,sm8250-ufshc - qcom,sm8350-ufshc
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2.37.2 -- linux-phy mailing list [email protected] https://lists.infradead.org/mailman/listinfo/linux-phy
Re: [PATCH v3 1/5] dt-bindings: ufs: qcom: add compatible for sa8775p
Quoted 32 lines · Bartosz Golaszewski
From: Bartosz Golaszewski <[email protected]>
Add the compatible string for the UFS on sa8775p platforms.
Signed-off-by Bartosz Golaszewski <[email protected]>Reviewed-by Krzysztof Kozlowski <[email protected]>--- Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 2 ++ 1 file changed, 2 insertions(+)Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +2
-1@@ -26,6 +26,7 @@ properties: - qcom,msm8994-ufshc - qcom,msm8996-ufshc - qcom,msm8998-ufshc + - qcom,sa8775p-ufshc - qcom,sc8280xp-ufshc - qcom,sdm845-ufshc - qcom,sm6350-ufshc@@ -105,6 +106,7 @@ allOf: contains: enum: - qcom,msm8998-ufshc + - qcom,sa8775p-ufshc - qcom,sc8280xp-ufshc - qcom,sm8250-ufshc - qcom,sm8350-ufshc --
Quoted 2 lines
2.37.2
Bjorn,
Are you picking this one up as well or should it go through Rob's tree?
Bart
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Re: [PATCH v3 1/5] dt-bindings: ufs: qcom: add compatible for sa8775p
Quoted 39 lines · Bartosz Golaszewski
Quoted 32 lines · Bartosz Golaszewski
From: Bartosz Golaszewski <[email protected]>
Add the compatible string for the UFS on sa8775p platforms.
Signed-off-by Bartosz Golaszewski <[email protected]>Reviewed-by Krzysztof Kozlowski <[email protected]>--- Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 2 ++ 1 file changed, 2 insertions(+)Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +2
-1@@ -26,6 +26,7 @@ properties: - qcom,msm8994-ufshc - qcom,msm8996-ufshc - qcom,msm8998-ufshc + - qcom,sa8775p-ufshc - qcom,sc8280xp-ufshc - qcom,sdm845-ufshc - qcom,sm6350-ufshc@@ -105,6 +106,7 @@ allOf: contains: enum: - qcom,msm8998-ufshc + - qcom,sa8775p-ufshc - qcom,sc8280xp-ufshc - qcom,sm8250-ufshc - qcom,sm8350-ufshc --Quoted 2 lines
2.37.2
Bjorn,
Quoted 3 lines
Are you picking this one up as well or should it go through Rob's tree?
Bart
Gentle ping.
Bart
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Re: [PATCH v3 1/5] dt-bindings: ufs: qcom: add compatible for sa8775p
Quoted 41 lines · Bartosz Golaszewski
Quoted 39 lines · Bartosz Golaszewski
Quoted 32 lines · Bartosz Golaszewski
From: Bartosz Golaszewski <[email protected]>
Add the compatible string for the UFS on sa8775p platforms.
Signed-off-by Bartosz Golaszewski <[email protected]>Reviewed-by Krzysztof Kozlowski <[email protected]>--- Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 2 ++ 1 file changed, 2 insertions(+)Documentation/devicetree/bindings/ufs/qcom,ufs.yaml +2
-1@@ -26,6 +26,7 @@ properties: - qcom,msm8994-ufshc - qcom,msm8996-ufshc - qcom,msm8998-ufshc + - qcom,sa8775p-ufshc - qcom,sc8280xp-ufshc - qcom,sdm845-ufshc - qcom,sm6350-ufshc@@ -105,6 +106,7 @@ allOf: contains: enum: - qcom,msm8998-ufshc + - qcom,sa8775p-ufshc - qcom,sc8280xp-ufshc - qcom,sm8250-ufshc - qcom,sm8350-ufshc --Quoted 2 lines
2.37.2
Bjorn,
Quoted 7 lines
Quoted 3 lines
Are you picking this one up as well or should it go through Rob's tree?
Bart
Gentle ping.
Bart
Hey UFS maintainers, could you please pick this one up for the next merge window?
Thanks in advance,
Bartosz
Martin K. Petersen
AppliedRe: [PATCH v3 1/5] dt-bindings: ufs: qcom: add compatible for sa8775p
Bartosz,
Quoted 2 lines
Hey UFS maintainers, could you please pick this one up for the next merge window?
Applied to 6.5/scsi-staging, thanks!
Signature · 6 lines
Martin K. Petersen Oracle Linux Engineering -- linux-phy mailing list [email protected] https://lists.infradead.org/mailman/listinfo/linux-phy
PATCH v3 2/5 dt-bindings: phy: qmp-ufs: describe the UFS PHY for sa8775p
In reply to Bartosz GolaszewskiFrom: Bartosz Golaszewski <[email protected]>
Add a new compatible for the QMP UFS PHY found on sa8775p platforms and update the clocks property to accommodate three clocks.
--- .../phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 26 ++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml +25 -1
@@ -16,6 +16,7 @@ description: properties: compatible: enum: + - qcom,sa8775p-qmp-ufs-phy - qcom,sc8280xp-qmp-ufs-phy - qcom,sm6125-qmp-ufs-phy - qcom,sm7150-qmp-ufs-phy
@@ -25,12 +26,15 @@ properties: maxItems: 1 clocks: - maxItems: 2 + minItems: 2 + maxItems: 3 clock-names: + minItems: 2 items: - const: ref - const: ref_aux + - const: qref power-domains: maxItems: 1
@@ -64,6 +68,26 @@ required: - vdda-pll-supply - "#phy-cells" +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,sa8775p-qmp-ufs-phy + then: + properties: + clocks: + maxItems: 3 + clock-names: + maxItems: 3 + else: + properties: + clocks: + maxItems: 2 + clock-names: + maxItems: 2 + additionalProperties: false examples:
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Re: [PATCH v3 2/5] dt-bindings: phy: qmp-ufs: describe the UFS PHY for sa8775p
Quoted 4 lines · Bartosz Golaszewski
From: Bartosz Golaszewski <[email protected]>
Add a new compatible for the QMP UFS PHY found on sa8775p platforms and update the clocks property to accommodate three clocks.
Applied, thanks
Signature · 6 lines
~Vinod -- linux-phy mailing list [email protected] https://lists.infradead.org/mailman/listinfo/linux-phy
PATCH v3 3/5 phy: qualcomm: phy-qcom-qmp-ufs: add definitions for sa8775p
In reply to Bartosz GolaszewskiFrom: Bartosz Golaszewski <[email protected]>
Add QMP PHY config for sa8775p and add support for the new compatible.
--- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 38 +++++++++++++++++++++++++ 1 file changed, 38 insertions(+)
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +38 -0
@@ -853,6 +853,41 @@ static const struct qmp_phy_cfg msm8996_ufsphy_cfg = { .no_pcs_sw_reset = true, }; + +static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = { + .lanes =2 , + + .offsets = &qmp_ufs_offsets, + + .tbls = { + .serdes = sm8350_ufsphy_serdes, + .serdes_num =ARRAY_SIZE (sm8350_ufsphy_serdes), + .tx = sm8350_ufsphy_tx, + .tx_num =ARRAY_SIZE (sm8350_ufsphy_tx), + .rx = sm8350_ufsphy_rx, + .rx_num =ARRAY_SIZE (sm8350_ufsphy_rx), + .pcs = sm8350_ufsphy_pcs, + .pcs_num =ARRAY_SIZE (sm8350_ufsphy_pcs), + }, + .tbls_hs_b = { + .serdes = sm8350_ufsphy_hs_b_serdes, + .serdes_num =ARRAY_SIZE (sm8350_ufsphy_hs_b_serdes), + }, + .tbls_hs_g4 = { + .tx = sm8350_ufsphy_g4_tx, + .tx_num =ARRAY_SIZE (sm8350_ufsphy_g4_tx), + .rx = sm8350_ufsphy_g4_rx, + .rx_num =ARRAY_SIZE (sm8350_ufsphy_g4_rx), + .pcs = sm8350_ufsphy_g4_pcs, + .pcs_num =ARRAY_SIZE (sm8350_ufsphy_g4_pcs), + }, + .clk_list = sm8450_ufs_phy_clk_l, + .num_clks =ARRAY_SIZE (sm8450_ufs_phy_clk_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs =ARRAY_SIZE (qmp_phy_vreg_l), + .regs = ufsphy_v5_regs_layout, +}; +static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = { .lanes =2 ,
@@ -1600,6 +1635,9 @@ static const struct of_device_id qmp_ufs_of_match_table[] = { }, { .compatible = "qcom,msm8998-qmp-ufs-phy", .data = &sdm845_ufsphy_cfg, + }, { + .compatible = "qcom,sa8775p-qmp-ufs-phy", + .data = &sa8775p_ufsphy_cfg, }, { .compatible = "qcom,sc8180x-qmp-ufs-phy", .data = &sm8150_ufsphy_cfg,
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2.37.2 -- linux-phy mailing list [email protected] https://lists.infradead.org/mailman/listinfo/linux-phy
Vinod Koul
maintainerRe: [PATCH v3 3/5] phy: qualcomm: phy-qcom-qmp-ufs: add definitions for sa8775p
Quoted 14 lines · Bartosz Golaszewski
From: Bartosz Golaszewski <[email protected]>
Add QMP PHY config for sa8775p and add support for the new compatible.
Signed-off-by Bartosz Golaszewski <[email protected]>--- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 38 +++++++++++++++++++++++++ 1 file changed, 38 insertions(+)drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +0
-0
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c static const struct qmp_phy_cfg msm8996_ufsphy_cfg = { · line 856
Quoted 4 lines
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +1
-0@@ -853,6 +853,41 @@ static const struct qmp_phy_cfg msm8996_ufsphy_cfg = { .no_pcs_sw_reset = true, }; +
There was already an empty line, this didnt make sense. Please run checkpatch to avoid missing these style issues
I have fixed it up and applied
Quoted 49 lines
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +37
-0+static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = { + .lanes =2 , + + .offsets = &qmp_ufs_offsets, + + .tbls = { + .serdes = sm8350_ufsphy_serdes, + .serdes_num =ARRAY_SIZE (sm8350_ufsphy_serdes), + .tx = sm8350_ufsphy_tx, + .tx_num =ARRAY_SIZE (sm8350_ufsphy_tx), + .rx = sm8350_ufsphy_rx, + .rx_num =ARRAY_SIZE (sm8350_ufsphy_rx), + .pcs = sm8350_ufsphy_pcs, + .pcs_num =ARRAY_SIZE (sm8350_ufsphy_pcs), + }, + .tbls_hs_b = { + .serdes = sm8350_ufsphy_hs_b_serdes, + .serdes_num =ARRAY_SIZE (sm8350_ufsphy_hs_b_serdes), + }, + .tbls_hs_g4 = { + .tx = sm8350_ufsphy_g4_tx, + .tx_num =ARRAY_SIZE (sm8350_ufsphy_g4_tx), + .rx = sm8350_ufsphy_g4_rx, + .rx_num =ARRAY_SIZE (sm8350_ufsphy_g4_rx), + .pcs = sm8350_ufsphy_g4_pcs, + .pcs_num =ARRAY_SIZE (sm8350_ufsphy_g4_pcs), + }, + .clk_list = sm8450_ufs_phy_clk_l, + .num_clks =ARRAY_SIZE (sm8450_ufs_phy_clk_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs =ARRAY_SIZE (qmp_phy_vreg_l), + .regs = ufsphy_v5_regs_layout, +}; +static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = { .lanes =2 ,@@ -1600,6 +1635,9 @@ static const struct of_device_id qmp_ufs_of_match_table[] = { }, { .compatible = "qcom,msm8998-qmp-ufs-phy", .data = &sdm845_ufsphy_cfg, + }, { + .compatible = "qcom,sa8775p-qmp-ufs-phy", + .data = &sa8775p_ufsphy_cfg, }, { .compatible = "qcom,sc8180x-qmp-ufs-phy", .data = &sm8150_ufsphy_cfg,Signature · 1 line
2.37.2
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~Vinod -- linux-phy mailing list [email protected] https://lists.infradead.org/mailman/listinfo/linux-phy
PATCH v3 4/5 arm64: dts: qcom: sa8775p: add UFS nodes
In reply to Bartosz GolaszewskiFrom: Bartosz Golaszewski <[email protected]>
Add nodes for the UFS and its PHY on sa8775p platforms.
--- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 58 +++++++++++++++++++++++++++ 1 file changed, 58 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p.dtsi +58 -0
@@ -585,6 +585,64 @@ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, }; }; + ufs_mem_hc: ufs@1d84000 { + compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; + reg = <0x0 0x01d84000 0x0 0x3000>; + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; + phys = <&ufs_mem_phy>; + phy-names = "ufsphy"; + lanes-per-direction = <2>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + power-domains = <&gcc UFS_PHY_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + iommus = <&apps_smmu 0x100 0x0>; + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + freq-table-hz = <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + status = "disabled"; + }; + + ufs_mem_phy: phy@1d87000 { + compatible = "qcom,sa8775p-qmp-ufs-phy"; + reg = <0x0 0x01d87000 0x0 0xe10>; + /* + * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It + * enables the CXO clock to eDP *and* UFS PHY. + */ + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_EDP_REF_CLKREF_EN>; + clock-names = "ref", "ref_aux", "qref"; + power-domains = <&gcc UFS_PHY_GDSC>; + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + #phy-cells = <0>; + status = "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>;
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Manivannan Sadhasivam
maintainerRe: [PATCH v3 4/5] arm64: dts: qcom: sa8775p: add UFS nodes
Quoted 46 lines · Bartosz Golaszewski
From: Bartosz Golaszewski <[email protected]>
Add nodes for the UFS and its PHY on sa8775p platforms.
Signed-off-by Bartosz Golaszewski <[email protected]>Reviewed-by Konrad Dybcio <[email protected]>--- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 58 +++++++++++++++++++++++++++ 1 file changed, 58 insertions(+)arch/arm64/boot/dts/qcom/sa8775p.dtsi +28
-0@@ -585,6 +585,64 @@ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, }; }; + ufs_mem_hc: ufs@1d84000 { + compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; + reg = <0x0 0x01d84000 0x0 0x3000>; + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; + phys = <&ufs_mem_phy>; + phy-names = "ufsphy"; + lanes-per-direction = <2>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + power-domains = <&gcc UFS_PHY_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + iommus = <&apps_smmu 0x100 0x0>; + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk",
arch/arm64/boot/dts/qcom/sa8775p.dtsi &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, · line 625
Quoted 10 lines
arch/arm64/boot/dts/qcom/sa8775p.dtsi +10
-0+ "rx_lane1_sync_clk"; + freq-table-hz = <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + status = "disabled";
I'm pretty sure that the UFS controllers found in latest SoCs are cache coherent. So you'd need "dma-coherent" property here.
- Mani
Quoted 26 lines
arch/arm64/boot/dts/qcom/sa8775p.dtsi +20
-0+ }; + + ufs_mem_phy: phy@1d87000 { + compatible = "qcom,sa8775p-qmp-ufs-phy"; + reg = <0x0 0x01d87000 0x0 0xe10>; + /* + * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It + * enables the CXO clock to eDP *and* UFS PHY. + */ + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&gcc GCC_EDP_REF_CLKREF_EN>; + clock-names = "ref", "ref_aux", "qref"; + power-domains = <&gcc UFS_PHY_GDSC>; + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + #phy-cells = <0>; + status = "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x20000>;Signature · 1 line
2.37.2
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மணிவண்ணன் சதாசிவம் -- linux-phy mailing list [email protected] https://lists.infradead.org/mailman/listinfo/linux-phy
PATCH v3 5/5 arm64: dts: qcom: sa8775p-ride: enable UFS
In reply to Bartosz GolaszewskiFrom: Bartosz Golaszewski <[email protected]>
Enable the UFS and its PHY on sa8775p-ride.
--- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)
arch/arm64/boot/dts/qcom/sa8775p-ride.dts +19 -0
@@ -5,6 +5,7 @@ /dts-v1/; +#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include "sa8775p.dtsi"
@@ -20,6 +21,7 @@ aliases { serial2 = &uart17; i2c18 = &i2c18; spi16 = &spi16; + ufshc1 = &ufs_mem_hc; }; chosen {
@@ -426,6 +428,23 @@ &uart17 { status = "okay"; }; +&ufs_mem_hc { + reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l8a>; + vcc-max-microamp = <1100000>; + vccq-supply = <&vreg_l4c>; + vccq-max-microamp = <1200000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l4a>; + vdda-pll-supply = <&vreg_l1c>; + + status = "okay"; +}; + &xo_board_clk { clock-frequency = <38400000>; };
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Re: [PATCH v3 5/5] arm64: dts: qcom: sa8775p-ride: enable UFS
Quoted 6 lines · Bartosz Golaszewski
From: Bartosz Golaszewski <[email protected]>
Enable the UFS and its PHY on sa8775p-ride.
Signed-off-by Bartosz Golaszewski <[email protected]>---
Konrad
Quoted 47 lines
arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)arch/arm64/boot/dts/qcom/sa8775p-ride.dts +19
-0@@ -5,6 +5,7 @@ /dts-v1/; +#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/regulator/qcom,rpmh-regulator.h> #include "sa8775p.dtsi"@@ -20,6 +21,7 @@ aliases { serial2 = &uart17; i2c18 = &i2c18; spi16 = &spi16; + ufshc1 = &ufs_mem_hc; }; chosen {@@ -426,6 +428,23 @@ &uart17 { status = "okay"; }; +&ufs_mem_hc { + reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l8a>; + vcc-max-microamp = <1100000>; + vccq-supply = <&vreg_l4c>; + vccq-max-microamp = <1200000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l4a>; + vdda-pll-supply = <&vreg_l1c>; + + status = "okay"; +}; + &xo_board_clk { clock-frequency = <38400000>; };
Re: (subset) [PATCH v3 0/5] arm64: qcom: sa8775p: add support for UFS
In reply to Bartosz GolaszewskiQuoted 11 lines · Bartosz Golaszewski
From: Bartosz Golaszewski <[email protected]>
Update relevant DT bindings, add new config to the driver and add UFS and PHY nodes to the .dtsi and enable them in the board .dts for sa8775p-ride.
v2 -> v3:
- fix DT bindings: move allOf: below required:
- collect review tags[...]
Applied, thanks!
[4/5] arm64: dts: qcom: sa8775p: add UFS nodes
commit: be543efeee17b93edaac61e49c6361d2209bd3d3
[5/5] arm64: dts: qcom: sa8775p-ride: enable UFS
commit: 35c45a1125fc0772b95aa41acc25deddcf5492beBest regards,
Signature · 6 lines
Bjorn Andersson <[email protected]> -- linux-phy mailing list [email protected] https://lists.infradead.org/mailman/listinfo/linux-phy
Martin K. Petersen
AppliedQuoted 9 lines · Bartosz Golaszewski
Update relevant DT bindings, add new config to the driver and add UFS and PHY nodes to the .dtsi and enable them in the board .dts for sa8775p-ride.
v2 -> v3:
- fix DT bindings: move allOf: below required:
- collect review tags[...]
Applied to 6.5/scsi-queue, thanks!
[1/5] dt-bindings: ufs: qcom: add compatible for sa8775p
https://git.kernel.org/mkp/scsi/c/8f0c17bf6bf3
Signature · 6 lines
Martin K. Petersen Oracle Linux Engineering -- linux-phy mailing list [email protected] https://lists.infradead.org/mailman/listinfo/linux-phy