riscv: kprobes: allow writing to x0
Subsystems (2)
PATCH 1/1 riscv: kprobes: allow writing to x0
Instructions can write to x0, so we should simulate these instructions normally.
Currently, the kernel hangs if an instruction who writes to x0 is simulated.
--- arch/riscv/kernel/probes/simulate-insn.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/riscv/kernel/probes/simulate-insn.c +1 -1
@@ -24,7 +24,7 @@ static inline bool rv_insn_reg_set_val(struct pt_regs *regs, u32 index, unsigned long val) {if (index ==0 ) -return false; +return true;else if (index <=31 ) *((unsigned long *)regs + index) = val;else
Signature · 7 lines
2.34.1 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv
Quoted 34 lines · Nam Cao
Instructions can write to x0, so we should simulate these instructions normally.
Currently, the kernel hangs if an instruction who writes to x0 is simulated.
Fixes c22b0bcb1dd0 ("riscv: Add kprobes supported")Signed-off-by Nam Cao <[email protected]>--- arch/riscv/kernel/probes/simulate-insn.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)arch/riscv/kernel/probes/simulate-insn.c +1
-1@@ -24,7 +24,7 @@ static inline bool rv_insn_reg_set_val(struct pt_regs *regs, u32 index, unsigned long val) {if (index ==0 ) -return false; +return true;else if (index <=31 ) *((unsigned long *)regs + index) = val;else Signature · 7 lines
2.34.1 _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv
Thank you for this change.
simulate_auipc would previously fail with an rd = 0 which made sense because auipc it is defined as a HINT in the riscv spec when rd = 0, but QEMU and spike don't say it is an illegal instruction so I think it is okay to make this change.
_______________________________________________
linux-riscv mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-riscv
Quoted 19 lines · Nam Cao
Instructions can write to x0, so we should simulate these instructions normally.
Currently, the kernel hangs if an instruction who writes to x0 is simulated.
Fixes c22b0bcb1dd0 ("riscv: Add kprobes supported")Signed-off-by Nam Cao <[email protected]>--- arch/riscv/kernel/probes/simulate-insn.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)arch/riscv/kernel/probes/simulate-insn.c +0
-0
arch/riscv/kernel/probes/simulate-insn.c static inline bool rv_insn_reg_set_val(struct pt_regs *regs, u32 index, · line 27
Quoted 5 lines
arch/riscv/kernel/probes/simulate-insn.c +1
-1@@ -24,7 +24,7 @@ static inline bool rv_insn_reg_set_val(struct pt_regs *regs, u32 index, unsigned long val) {if (index ==0 ) -return false; +return true;
Quoted 6 lines
arch/riscv/kernel/probes/simulate-insn.c +0
-1else if (index <=31 ) *((unsigned long *)regs + index) = val;else --2.34.1
Signature · 7 lines
Best Regards Guo Ren _______________________________________________ linux-riscv mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-riscv
This patch was applied to riscv/linux.git (for-next) by Palmer Dabbelt <[email protected]>:
Hello:
This patch was applied to riscv/linux.git (for-next) by Palmer Dabbelt <[email protected]>:
Quoted 11 lines · On Tue, 29 Aug 2023 20:25:00 +0200 you wrote:
Instructions can write to x0, so we should simulate these instructions normally.
Currently, the kernel hangs if an instruction who writes to x0 is simulated.
Fixes c22b0bcb1dd0 ("riscv: Add kprobes supported")Signed-off-by Nam Cao <[email protected]>[...]
Here is the summary with links:
- riscv: kprobes: allow writing to x0
https://git.kernel.org/riscv/c/8cb22bec1426
You are awesome, thank you!
Signature · 2 lines
Deet-doot-dot, I am a bot. https://korg.docs.kernel.org/patchwork/pwbot.html