Add support for 10G Ethernet SerDes on MT7988
Subsystems (9)
Daniel Golle
maintainercover Add support for 10G Ethernet SerDes on MT7988
This series aims to add support for GMAC2 and GMAC3 of the MediaTek MT7988 SoC. While the vendor SDK stuffs all this into their Ethernet driver, I've tried to seperate things into a PHY driver, a PCS driver as well as changes to the existing Ethernet and LynxI PCS driver.
+----------------+
+--------------+ | USXGMII PCS | +------------------+
| Ethernet MAC +--+-------------+ +---+ PEXTP SerDes PHY |
+--------------+ | SGMII PCS | | +------------------+
+-------------+--+Alltogether this allows using GMAC2 and GMAC3 with all possible interface modes, including in-band-status if needed.
Daniel Golle (8):
dt-bindings: phy: mediatek,xfi-pextp: add new bindings
phy: add driver for MediaTek pextp 10GE SerDes PHY
net: pcs: pcs-mtk-lynxi: use 2500Base-X without AN
net: pcs: pcs-mtk-lynxi: allow calling with NULL advertising
dt-bindings: net: pcs: add bindings for MediaTek USXGMII PCS
net: pcs: add driver for MediaTek USXGMII PCS
dt-bindings: net: mediatek,net: fix and complete mt7988-eth binding
net: ethernet: mtk_eth_soc: add paths and SerDes modes for MT7988
.../devicetree/bindings/net/mediatek,net.yaml | 171 ++++- .../bindings/net/pcs/mediatek,usxgmii.yaml | 105 +++ .../bindings/phy/mediatek,xfi-pextp.yaml | 71 ++ MAINTAINERS | 3 + drivers/net/ethernet/mediatek/Kconfig | 17 + drivers/net/ethernet/mediatek/mtk_eth_path.c | 122 +++- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 178 ++++- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 105 ++- drivers/net/pcs/Kconfig | 10 + drivers/net/pcs/Makefile | 1 + drivers/net/pcs/pcs-mtk-lynxi.c | 38 +- drivers/net/pcs/pcs-mtk-usxgmii.c | 688 ++++++++++++++++++ drivers/phy/mediatek/Kconfig | 11 + drivers/phy/mediatek/Makefile | 1 + drivers/phy/mediatek/phy-mtk-pextp.c | 355 +++++++++ include/linux/pcs/pcs-mtk-usxgmii.h | 18 + 16 files changed, 1813 insertions(+), 81 deletions(-) create mode 100644 Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml create mode 100644 Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.yaml create mode 100644 drivers/net/pcs/pcs-mtk-usxgmii.c create mode 100644 drivers/phy/mediatek/phy-mtk-pextp.c create mode 100644 include/linux/pcs/pcs-mtk-usxgmii.h
Signature · 1 line
2.42.1
Daniel Golle
maintainerRFC PATCH 1/8 dt-bindings: phy: mediatek,xfi-pextp: add new bindings
Add bindings for the MediaTek PEXTP Ethernet SerDes PHY found in the MediaTek MT7988 SoC which can operate at various interfaces modes:
* USXGMII
* 10GBase-R
* 5GBase-R
* 2500Base-X
* 1000Base-X
* Cisco SGMII (MAC side)
--- .../bindings/phy/mediatek,xfi-pextp.yaml | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.yaml
Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.yaml new file +71 -0
@@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/mediatek,xfi-pextp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek XFI PEXTP SerDes PHY + +maintainers: + - Daniel Golle <[email protected]> + +description: | + The MediaTek XFI PEXTP SerDes PHY provides the physical SerDes lanes + used by the MediaTek USXGMII PCS. + +properties: + $nodename: + pattern: "^phy@[0-9a-f]+$" + + compatible: + const: mediatek,mt7988-xfi-pextp + + reg: + maxItems: 1 + + clocks: + items: + - description: XFI PHY clock + + resets: + items: + - description: PEXTP reset + + mediatek,usxgmii-performance-errata: + $ref: /schemas/types.yaml#/definitions/flag + description: + USXGMII0 on MT7988 suffers from a performance problem in 10GBase-R + mode which needs a work-around in the driver. The work-around is + enabled using this flag. + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - resets + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mediatek,mt7988-clk.h> + #include <dt-bindings/reset/mediatek,mt7988-resets.h> + soc { + #address-cells = <2>; + #size-cells = <2>; + + xfi_pextp0: phy@11f20000 { + compatible = "mediatek,mt7988-xfi-pextp"; + reg = <0 0x11f20000 0 0x10000>; + clocks = <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>; + resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP0_GRST>; + mediatek,usxgmii-performance-errata; + #phy-cells = <0>; + }; + }; + +...
Signature · 1 line
2.42.1
Andrew Lunn
maintainerRe: [RFC PATCH 1/8] dt-bindings: phy: mediatek,xfi-pextp: add new bindings
Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.yaml line 39
Quoted 6 lines
Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.yaml new file +6
-0+ mediatek,usxgmii-performance-errata: + $ref: /schemas/types.yaml#/definitions/flag + description: + USXGMII0 on MT7988 suffers from a performance problem in 10GBase-R + mode which needs a work-around in the driver. The work-around is + enabled using this flag.
Is there more details about this? I'm just wondering if this should be based on the compatible, rather than a bool property.
Andrew
Daniel Golle
maintainerRe: [RFC PATCH 1/8] dt-bindings: phy: mediatek,xfi-pextp: add new bindings
Hi Andrew,
Quoted 9 lines · Andrew Lunn
Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.yaml line 39
Quoted 6 lines
Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.yaml new file +6
-0+ mediatek,usxgmii-performance-errata: + $ref: /schemas/types.yaml#/definitions/flag + description: + USXGMII0 on MT7988 suffers from a performance problem in 10GBase-R + mode which needs a work-around in the driver. The work-around is + enabled using this flag.Is there more details about this? I'm just wondering if this should be based on the compatible, rather than a bool property.
The vendor sources where this is coming from are here:
And I'm afraid this is as much detail as it gets. And yes, we could also base this on the compatible and just have two different ones for the two PEXTP instances found in MT7988.
Let me know your conclusion in that regard.
Cheers
Daniel
Rob Herring
maintainerRe: [RFC PATCH 1/8] dt-bindings: phy: mediatek,xfi-pextp: add new bindings
Quoted 13 lines · Daniel Golle
Hi Andrew,
Quoted 9 lines · Andrew Lunn
Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.yaml line 39
Quoted 6 lines
Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.yaml new file +6
-0+ mediatek,usxgmii-performance-errata: + $ref: /schemas/types.yaml#/definitions/flag + description: + USXGMII0 on MT7988 suffers from a performance problem in 10GBase-R + mode which needs a work-around in the driver. The work-around is + enabled using this flag.Is there more details about this? I'm just wondering if this should be based on the compatible, rather than a bool property.
Quoted 8 lines
The vendor sources where this is coming from are here:
And I'm afraid this is as much detail as it gets. And yes, we could also base this on the compatible and just have two different ones for the two PEXTP instances found in MT7988.
Let me know your conclusion in that regard.
I'd go with a property in this case unless you think there may be other per instance differences.
Rob
Rob Herring
maintainerRe: [RFC PATCH 1/8] dt-bindings: phy: mediatek,xfi-pextp: add new bindings
In reply to Daniel GolleQuoted 10 lines · Daniel Golle
Add bindings for the MediaTek PEXTP Ethernet SerDes PHY found in the MediaTek MT7988 SoC which can operate at various interfaces modes:
* USXGMII
* 10GBase-R
* 5GBase-R
* 2500Base-X
* 1000Base-X
* Cisco SGMII (MAC side)
Quoted 6 lines
Signed-off-by Daniel Golle <[email protected]>--- .../bindings/phy/mediatek,xfi-pextp.yaml | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.yaml
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.example.dts:18:18: fatal error: dt-bindings/clock/mediatek,mt7988-clk.h: No such file or directory
18 | #include <dt-bindings/clock/mediatek,mt7988-clk.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[2]: *** [scripts/Makefile.lib:419: Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.example.dtb] Error 1 make[2]: *** Waiting for unfinished jobs....
make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1427: dt_binding_check] Error 2
make: *** [Makefile:234: __sub-make] Error 2
doc reference errors (make refcheckdocs):
The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.
Rob Herring
maintainerRe: [RFC PATCH 1/8] dt-bindings: phy: mediatek,xfi-pextp: add new bindings
In reply to Daniel GolleQuoted 24 lines · Daniel Golle
Add bindings for the MediaTek PEXTP Ethernet SerDes PHY found in the MediaTek MT7988 SoC which can operate at various interfaces modes:
* USXGMII
* 10GBase-R
* 5GBase-R
* 2500Base-X
* 1000Base-X
* Cisco SGMII (MAC side)Signed-off-by Daniel Golle <[email protected]>--- .../bindings/phy/mediatek,xfi-pextp.yaml | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.yamlDocumentation/devicetree/bindings/phy/mediatek,xfi-pextp.yaml new file +2
-0@@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2
Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.yaml line 12
Quoted 10 lines
Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.yaml new file +10
-0+--- +$id: http://devicetree.org/schemas/phy/mediatek,xfi-pextp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek XFI PEXTP SerDes PHY + +maintainers: + - Daniel Golle <[email protected]> + +description: |
Don't need '|' here.
Quoted 39 lines
Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.yaml new file +39
-0+ The MediaTek XFI PEXTP SerDes PHY provides the physical SerDes lanes + used by the MediaTek USXGMII PCS. + +properties: + $nodename: + pattern: "^phy@[0-9a-f]+$" + + compatible: + const: mediatek,mt7988-xfi-pextp + + reg: + maxItems: 1 + + clocks: + items: + - description: XFI PHY clock + + resets: + items: + - description: PEXTP reset + + mediatek,usxgmii-performance-errata: + $ref: /schemas/types.yaml#/definitions/flag + description: + USXGMII0 on MT7988 suffers from a performance problem in 10GBase-R + mode which needs a work-around in the driver. The work-around is + enabled using this flag. + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - resets + - "#phy-cells" + +additionalProperties: false
Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.yaml line 61
Quoted 10 lines
Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.yaml new file +10
-0+ +examples: + - | + #include <dt-bindings/clock/mediatek,mt7988-clk.h> + #include <dt-bindings/reset/mediatek,mt7988-resets.h> + soc { + #address-cells = <2>; + #size-cells = <2>; + + xfi_pextp0: phy@11f20000 {
Drop unused labels.
Quoted 12 lines
Documentation/devicetree/bindings/phy/mediatek,xfi-pextp.yaml new file +10
-0+ compatible = "mediatek,mt7988-xfi-pextp"; + reg = <0 0x11f20000 0 0x10000>; + clocks = <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>; + resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP0_GRST>; + mediatek,usxgmii-performance-errata; + #phy-cells = <0>; + }; + }; + +...Signature · 1 line
2.42.1
Daniel Golle
maintainerRFC PATCH 2/8 phy: add driver for MediaTek pextp 10GE SerDes PHY
In reply to Daniel GolleAdd driver for MediaTek's pextp 10 Gigabit/s Ethernet SerDes PHY which can be found in the MT7988 SoC.
The PHY can operates only in PHY_MODE_ETHERNET, the submode is one of PHY_INTERFACE_MODE_* corresponding to the supported modes:
* USXGMII
* 10GBase-R
* 5GBase-R
* 2500Base-X
* 1000Base-X
* Cisco SGMII (MAC side)
In order to work-around a performance issue present on the first of two PEXTP present in MT7988 special tuning is applied which can be selected by adding the mediatek,usxgmii-performance-errata property to the device tree node.
There is no documentation what-so-ever for the pextp registers and this driver is based on a GPL licensed implementation found in MediaTek's SDK.
--- MAINTAINERS | 1 + drivers/phy/mediatek/Kconfig | 11 + drivers/phy/mediatek/Makefile | 1 + drivers/phy/mediatek/phy-mtk-pextp.c | 355 +++++++++++++++++++++++++++ 4 files changed, 368 insertions(+) create mode 100644 drivers/phy/mediatek/phy-mtk-pextp.c
MAINTAINERS +1 -0
@@ -13527,6 +13527,7 @@ L: [email protected] S: Maintained F: drivers/net/phy/mediatek-ge-soc.c F: drivers/net/phy/mediatek-ge.c +F: drivers/phy/mediatek/phy-mediatek-pextp.c MEDIATEK I2C CONTROLLER DRIVER M: Qii Wang <[email protected]>
drivers/phy/mediatek/Kconfig +11 -0
@@ -13,6 +13,17 @@ config PHY_MTK_PCIE callback for PCIe GEN3 port, it supports software efuse initialization. +config PHY_MTK_PEXTP + tristate "MediaTek PEXTP Driver" + depends on ARCH_MEDIATEK || COMPILE_TEST + depends on OF && OF_ADDRESS + depends on HAS_IOMEM + select GENERIC_PHY + help + Say 'Y' here to add support for MediaTek pextp PHY driver. + The driver provides access to the Ethernet SerDes PHY supporting + various 1GE, 2.5GE, 5GE and 10GE modes. + config PHY_MTK_TPHY tristate "MediaTek T-PHY Driver" depends on ARCH_MEDIATEK || COMPILE_TEST
drivers/phy/mediatek/Makefile +1 -0
@@ -8,6 +8,7 @@ obj-$(CONFIG_PHY_MTK_PCIE) += phy-mtk-pcie.o obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o obj-$(CONFIG_PHY_MTK_UFS) += phy-mtk-ufs.o obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o +obj-$(CONFIG_PHY_MTK_PEXTP) += phy-mtk-pextp.o phy-mtk-hdmi-drv-y := phy-mtk-hdmi.o phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt2701.o
drivers/phy/mediatek/phy-mtk-pextp.c new file +355 -0
355 lines not on this page · raw message
Signature · 1 line
2.42.1
Vinod Koul
maintainerRe: [RFC PATCH 2/8] phy: add driver for MediaTek pextp 10GE SerDes PHY
Quoted 126 lines · Daniel Golle
Add driver for MediaTek's pextp 10 Gigabit/s Ethernet SerDes PHY which can be found in the MT7988 SoC.
The PHY can operates only in
PHY_MODE_ETHERNET, the submode is one of PHY_INTERFACE_MODE_* corresponding to the supported modes:* USXGMII
* 10GBase-R
* 5GBase-R
* 2500Base-X
* 1000Base-X
* Cisco SGMII (MAC side)In order to work-around a performance issue present on the first of two PEXTP present in MT7988 special tuning is applied which can be selected by adding the mediatek,usxgmii-performance-errata property to the device tree node.
There is no documentation what-so-ever for the pextp registers and this driver is based on a GPL licensed implementation found in MediaTek's SDK.
Signed-off-by Daniel Golle <[email protected]>--- MAINTAINERS | 1 + drivers/phy/mediatek/Kconfig | 11 + drivers/phy/mediatek/Makefile | 1 + drivers/phy/mediatek/phy-mtk-pextp.c | 355 +++++++++++++++++++++++++++ 4 files changed, 368 insertions(+) create mode 100644 drivers/phy/mediatek/phy-mtk-pextp.cMAINTAINERS +1
-0@@ -13527,6 +13527,7 @@ L: [email protected] S: Maintained F: drivers/net/phy/mediatek-ge-soc.c F: drivers/net/phy/mediatek-ge.c +F: drivers/phy/mediatek/phy-mediatek-pextp.c MEDIATEK I2C CONTROLLER DRIVER M: Qii Wang <[email protected]>drivers/phy/mediatek/Kconfig +11
-0@@ -13,6 +13,17 @@ config PHY_MTK_PCIE callback for PCIe GEN3 port, it supports software efuse initialization. +config PHY_MTK_PEXTP + tristate "MediaTek PEXTP Driver" + depends on ARCH_MEDIATEK || COMPILE_TEST + depends on OF && OF_ADDRESS + depends on HAS_IOMEM + select GENERIC_PHY + help + Say 'Y' here to add support for MediaTek pextp PHY driver. + The driver provides access to the Ethernet SerDes PHY supporting + various 1GE, 2.5GE, 5GE and 10GE modes. + config PHY_MTK_TPHY tristate "MediaTek T-PHY Driver" depends on ARCH_MEDIATEK || COMPILE_TESTdrivers/phy/mediatek/Makefile +1
-0@@ -8,6 +8,7 @@ obj-$(CONFIG_PHY_MTK_PCIE) += phy-mtk-pcie.o obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o obj-$(CONFIG_PHY_MTK_UFS) += phy-mtk-ufs.o obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o +obj-$(CONFIG_PHY_MTK_PEXTP) += phy-mtk-pextp.o phy-mtk-hdmi-drv-y := phy-mtk-hdmi.o phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt2701.odrivers/phy/mediatek/phy-mtk-pextp.c new file +43
-0@@ -0,0 +1,355 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* MediaTek 10GE SerDes PHY driver +* +* Copyright (c) 2023 Daniel Golle <[email protected]> +* based on mtk_usxgmii.c found in MediaTek's SDK released under GPL-2.0 +* Copyright (c) 2022 MediaTek Inc. +* Author: Henry Yen <[email protected]> +*/ + +#include <linux/module.h> +#include <linux/device.h> +#include <linux/netdevice.h> +#include <linux/platform_device.h> +#include <linux/of.h> +#include <linux/io.h> +#include <linux/clk.h> +#include <linux/reset.h> +#include <linux/phy.h> +#include <linux/phy/phy.h> + +struct mtk_pextp_phy { +void __iomem *base; +struct device *dev; +struct reset_control *reset; +struct clk *clk; +bool da_war; +}; + +static inline bool mtk_interface_mode_is_xgmii (phy_interface_t interface) +{ +switch (interface) { +case PHY_INTERFACE_MODE_INTERNAL : +case PHY_INTERFACE_MODE_USXGMII : +case PHY_INTERFACE_MODE_10GBASER : +case PHY_INTERFACE_MODE_5GBASER : +return true; +default : +return false; + } +} + +static void mtk_pextp_setup (struct mtk_pextp_phy *pextp,phy_interface_t interface) +{
drivers/phy/mediatek/phy-mtk-pextp.c line 53
Quoted 10 lines
drivers/phy/mediatek/phy-mtk-pextp.c new file +10
-0+bool is_10g = (interface ==PHY_INTERFACE_MODE_10GBASER || + interface ==PHY_INTERFACE_MODE_USXGMII ); +bool is_2p5g = (interface ==PHY_INTERFACE_MODE_2500BASEX ); +bool is_5g = (interface ==PHY_INTERFACE_MODE_5GBASER ); + +dev_dbg (pextp->dev,"setting up for mode %s\n" ,phy_modes (interface)); + +/* Setup operation mode */ +if (is_10g) +iowrite32 (0x00C9071C , pextp->base +0x9024 );
what are these magic numbers? also lower case hex values pls
Quoted 304 lines
drivers/phy/mediatek/phy-mtk-pextp.c new file +302
-0+else +iowrite32 (0x00D9071C , pextp->base +0x9024 ); + +if (is_5g) +iowrite32 (0xAAA5A5AA , pextp->base +0x2020 ); +else +iowrite32 (0xAA8585AA , pextp->base +0x2020 ); + +if (is_2p5g || is_5g || is_10g) { +iowrite32 (0x0C020707 , pextp->base +0x2030 ); +iowrite32 (0x0E050F0F , pextp->base +0x2034 ); +iowrite32 (0x00140032 , pextp->base +0x2040 ); + }else { +iowrite32 (0x0C020207 , pextp->base +0x2030 ); +iowrite32 (0x0E05050F , pextp->base +0x2034 ); +iowrite32 (0x00200032 , pextp->base +0x2040 ); + } + +if (is_2p5g || is_10g) +iowrite32 (0x00C014AA , pextp->base +0x50F0 ); +else if (is_5g) +iowrite32 (0x00C018AA , pextp->base +0x50F0 ); +else +iowrite32 (0x00C014BA , pextp->base +0x50F0 ); + +if (is_5g) { +iowrite32 (0x3777812B , pextp->base +0x50E0 ); +iowrite32 (0x005C9CFF , pextp->base +0x506C ); +iowrite32 (0x9DFAFAFA , pextp->base +0x5070 ); +iowrite32 (0x273F3F3F , pextp->base +0x5074 ); +iowrite32 (0xA8883868 , pextp->base +0x5078 ); +iowrite32 (0x14661466 , pextp->base +0x507C ); + }else { +iowrite32 (0x3777C12B , pextp->base +0x50E0 ); +iowrite32 (0x005F9CFF , pextp->base +0x506C ); +iowrite32 (0x9D9DFAFA , pextp->base +0x5070 ); +iowrite32 (0x27273F3F , pextp->base +0x5074 ); +iowrite32 (0xA7883C68 , pextp->base +0x5078 ); +iowrite32 (0x11661166 , pextp->base +0x507C ); + } + +if (is_2p5g || is_10g) { +iowrite32 (0x0E000AAF , pextp->base +0x5080 ); +iowrite32 (0x08080D0D , pextp->base +0x5084 ); +iowrite32 (0x02030909 , pextp->base +0x5088 ); + }else if (is_5g) { +iowrite32 (0x0E001ABF , pextp->base +0x5080 ); +iowrite32 (0x080B0D0D , pextp->base +0x5084 ); +iowrite32 (0x02050909 , pextp->base +0x5088 ); + }else { +iowrite32 (0x0E000EAF , pextp->base +0x5080 ); +iowrite32 (0x08080E0D , pextp->base +0x5084 ); +iowrite32 (0x02030B09 , pextp->base +0x5088 ); + } + +if (is_5g) { +iowrite32 (0x0C000000 , pextp->base +0x50E4 ); +iowrite32 (0x04000000 , pextp->base +0x50E8 ); + }else { +iowrite32 (0x0C0C0000 , pextp->base +0x50E4 ); +iowrite32 (0x04040000 , pextp->base +0x50E8 ); + } + +if (is_2p5g ||mtk_interface_mode_is_xgmii (interface)) +iowrite32 (0x0F0F0C06 , pextp->base +0x50EC ); +else +iowrite32 (0x0F0F0606 , pextp->base +0x50EC ); + +if (is_5g) { +iowrite32 (0x50808C8C , pextp->base +0x50A8 ); +iowrite32 (0x18000000 , pextp->base +0x6004 ); + }else { +iowrite32 (0x506E8C8C , pextp->base +0x50A8 ); +iowrite32 (0x18190000 , pextp->base +0x6004 ); + } + +if (is_10g) +iowrite32 (0x01423342 , pextp->base +0x00F8 ); +else if (is_5g) +iowrite32 (0x00A132A1 , pextp->base +0x00F8 ); +else if (is_2p5g) +iowrite32 (0x009C329C , pextp->base +0x00F8 ); +else +iowrite32 (0x00FA32FA , pextp->base +0x00F8 ); + +/* Force SGDT_OUT off and select PCS */ +if (mtk_interface_mode_is_xgmii (interface)) +iowrite32 (0x80201F20 , pextp->base +0x00F4 ); +else +iowrite32 (0x80201F21 , pextp->base +0x00F4 ); + +/* Force GLB_CKDET_OUT */ +iowrite32 (0x00050C00 , pextp->base +0x0030 ); + +/* Force AEQ on */ +iowrite32 (0x02002800 , pextp->base +0x0070 ); +ndelay (1020 ); + +/* Setup DA default value */ +iowrite32 (0x00000020 , pextp->base +0x30B0 ); +iowrite32 (0x00008A01 , pextp->base +0x3028 ); +iowrite32 (0x0000A884 , pextp->base +0x302C ); +iowrite32 (0x00083002 , pextp->base +0x3024 ); +if (mtk_interface_mode_is_xgmii (interface)) { +iowrite32 (0x00022220 , pextp->base +0x3010 ); +iowrite32 (0x0F020A01 , pextp->base +0x5064 ); +iowrite32 (0x06100600 , pextp->base +0x50B4 ); +if (interface ==PHY_INTERFACE_MODE_USXGMII ) +iowrite32 (0x40704000 , pextp->base +0x3048 ); +else +iowrite32 (0x47684100 , pextp->base +0x3048 ); + }else { +iowrite32 (0x00011110 , pextp->base +0x3010 ); +iowrite32 (0x40704000 , pextp->base +0x3048 ); + } + +if (!mtk_interface_mode_is_xgmii (interface) && !is_2p5g) +iowrite32 (0x0000C000 , pextp->base +0x3064 ); + +if (interface ==PHY_INTERFACE_MODE_USXGMII ) { +iowrite32 (0xA8000000 , pextp->base +0x3050 ); +iowrite32 (0x000000AA , pextp->base +0x3054 ); + }else if (mtk_interface_mode_is_xgmii (interface)) { +iowrite32 (0x00000000 , pextp->base +0x3050 ); +iowrite32 (0x00000000 , pextp->base +0x3054 ); + }else { +iowrite32 (0xA8000000 , pextp->base +0x3050 ); +iowrite32 (0x000000AA , pextp->base +0x3054 ); + } + +if (mtk_interface_mode_is_xgmii (interface)) +iowrite32 (0x00000F00 , pextp->base +0x306C ); +else if (is_2p5g) +iowrite32 (0x22000F00 , pextp->base +0x306C ); +else +iowrite32 (0x20200F00 , pextp->base +0x306C ); + +if (interface ==PHY_INTERFACE_MODE_10GBASER && pextp->da_war) +iowrite32 (0x0007B400 , pextp->base +0xA008 ); + +if (mtk_interface_mode_is_xgmii (interface)) +iowrite32 (0x00040000 , pextp->base +0xA060 ); +else +iowrite32 (0x00050000 , pextp->base +0xA060 ); + +if (is_10g) +iowrite32 (0x00000001 , pextp->base +0x90D0 ); +else if (is_5g) +iowrite32 (0x00000003 , pextp->base +0x90D0 ); +else if (is_2p5g) +iowrite32 (0x00000005 , pextp->base +0x90D0 ); +else +iowrite32 (0x00000007 , pextp->base +0x90D0 ); + +/* Release reset */ +iowrite32 (0x0200E800 , pextp->base +0x0070 ); +usleep_range (150 ,500 ); + +/* Switch to P0 */ +iowrite32 (0x0200C111 , pextp->base +0x0070 ); +ndelay (1020 ); +iowrite32 (0x0200C101 , pextp->base +0x0070 ); +usleep_range (15 ,50 ); + +if (mtk_interface_mode_is_xgmii (interface)) { +/* Switch to Gen3 */ +iowrite32 (0x0202C111 , pextp->base +0x0070 ); + }else { +/* Switch to Gen2 */ +iowrite32 (0x0201C111 , pextp->base +0x0070 ); + } +ndelay (1020 ); +if (mtk_interface_mode_is_xgmii (interface)) +iowrite32 (0x0202C101 , pextp->base +0x0070 ); +else +iowrite32 (0x0201C101 , pextp->base +0x0070 ); +usleep_range (100 ,500 ); +iowrite32 (0x00000030 , pextp->base +0x30B0 ); +if (mtk_interface_mode_is_xgmii (interface)) +iowrite32 (0x80201F00 , pextp->base +0x00F4 ); +else +iowrite32 (0x80201F01 , pextp->base +0x00F4 ); + +iowrite32 (0x30000000 , pextp->base +0x3040 ); +usleep_range (400 ,1000 ); +} + +static int mtk_pextp_set_mode (struct phy *phy,enum phy_mode mode,int submode) +{ +struct mtk_pextp_phy *pextp =phy_get_drvdata (phy); + +if (mode !=PHY_MODE_ETHERNET ) +return -EINVAL ; + +switch (submode) { +case PHY_INTERFACE_MODE_1000BASEX : +case PHY_INTERFACE_MODE_2500BASEX : +case PHY_INTERFACE_MODE_SGMII : +case PHY_INTERFACE_MODE_5GBASER : +case PHY_INTERFACE_MODE_10GBASER : +case PHY_INTERFACE_MODE_USXGMII : +mtk_pextp_setup (pextp, submode); +return 0 ; +default : +return -EINVAL ; + } +} + +static int mtk_pextp_reset (struct phy *phy) +{ +struct mtk_pextp_phy *pextp =phy_get_drvdata (phy); + +reset_control_assert (pextp->reset); +usleep_range (100 ,500 ); +reset_control_deassert (pextp->reset); +mdelay (10 ); + +return 0 ; +} + +static int mtk_pextp_power_on (struct phy *phy) +{ +struct mtk_pextp_phy *pextp =phy_get_drvdata (phy); + +return clk_prepare_enable (pextp->clk); +} + +static int mtk_pextp_power_off (struct phy *phy) +{ +struct mtk_pextp_phy *pextp =phy_get_drvdata (phy); + +clk_disable_unprepare (pextp->clk); + +return 0 ; +} + +static const struct phy_ops mtk_pextp_ops = { + .power_on = mtk_pextp_power_on, + .power_off = mtk_pextp_power_off, + .set_mode = mtk_pextp_set_mode, + .reset = mtk_pextp_reset, + .owner =THIS_MODULE , +}; + +static int mtk_pextp_probe (struct platform_device *pdev) +{ +struct device_node *np = pdev->dev.of_node; +struct phy_provider *phy_provider; +struct mtk_pextp_phy *pextp; +struct phy *phy; + +if (!np) +return -ENODEV ; + + pextp =devm_kzalloc (&pdev->dev,sizeof (*pextp),GFP_KERNEL ); +if (!pextp) +return -ENOMEM ; + + pextp->base =devm_of_iomap (&pdev->dev, np,0 ,NULL ); +if (!pextp->base) +return -EIO ; + + pextp->dev = &pdev->dev; + pextp->clk =devm_clk_get (&pdev->dev,NULL ); +if (IS_ERR (pextp->clk)) +return PTR_ERR (pextp->clk); + + pextp->reset =devm_reset_control_get_exclusive (&pdev->dev,NULL ); +if (IS_ERR (pextp->reset)) +return PTR_ERR (pextp->reset); + + pextp->da_war =of_property_read_bool (np,"mediatek,usxgmii-performance-errata" ); + + phy =devm_phy_create (&pdev->dev,NULL , &mtk_pextp_ops); +if (IS_ERR (phy)) +return PTR_ERR (phy); + +phy_set_drvdata (phy, pextp); + + phy_provider =devm_of_phy_provider_register (&pdev->dev, of_phy_simple_xlate); + +return PTR_ERR_OR_ZERO (phy_provider); +} + +static const struct of_device_id mtk_pextp_match[] = { + { .compatible ="mediatek,mt7988-xfi-pextp" , }, + { } +}; +MODULE_DEVICE_TABLE (of, mtk_pextp_match); + +static struct platform_driver mtk_pextp_driver = { + .probe = mtk_pextp_probe, + .driver = { + .name ="mtk-pextp" , + .of_match_table = mtk_pextp_match, + }, +}; +module_platform_driver (mtk_pextp_driver); + +MODULE_DESCRIPTION ("MediaTek pextp SerDes PHY driver" ); +MODULE_AUTHOR ("Daniel Golle <[email protected]>" ); +MODULE_LICENSE ("GPL" );Signature · 1 line
2.42.1
Signature · 1 line
~Vinod
Daniel Golle
maintainerRFC PATCH 3/8 net: pcs: pcs-mtk-lynxi: use 2500Base-X without AN
In reply to Daniel GolleUsing 2500Base-T SFP modules e.g. on the BananaPi R3 requires manually disabling auto-negotiation, e.g. using ethtool. While a proper fix using SFP quirks is being discussed upstream, bring a work-around to restore user experience to what it was before the switch to the dedicated SGMII PCS driver.
--- drivers/net/pcs/pcs-mtk-lynxi.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-)
drivers/net/pcs/pcs-mtk-lynxi.c +15 -5
@@ -92,14 +92,23 @@ static void mtk_pcs_lynxi_get_state(struct phylink_pcs *pcs, struct phylink_link_state *state) {struct mtk_pcs_lynxi *mpcs =pcs_to_mtk_pcs_lynxi (pcs); -unsigned int bm, adv; +unsigned int bm, bmsr, adv;/* Read the BMSR and LPA */ regmap_read (mpcs->regmap,SGMSYS_PCS_CONTROL_1 , &bm); -regmap_read (mpcs->regmap,SGMSYS_PCS_ADVERTISE , &adv); + bmsr =FIELD_GET (SGMII_BMSR , bm); + +if (state->interface ==PHY_INTERFACE_MODE_2500BASEX ) { + state->link = !!(bmsr &BMSR_LSTATUS ); + state->an_complete = !!(bmsr &BMSR_ANEGCOMPLETE ); + state->speed =SPEED_2500 ; + state->duplex =DUPLEX_FULL ; + +return ; + } -phylink_mii_c22_pcs_decode_state (state,FIELD_GET (SGMII_BMSR , bm), -FIELD_GET (SGMII_LPA , adv)); +regmap_read (mpcs->regmap,SGMSYS_PCS_ADVERTISE , &adv); +phylink_mii_c22_pcs_decode_state (state, bmsr,FIELD_GET (SGMII_LPA , adv)); } static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int neg_mode,
@@ -129,7 +138,8 @@ static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int neg_mode,if (neg_mode &PHYLINK_PCS_NEG_INBAND ) sgm_mode |=SGMII_REMOTE_FAULT_DIS ; -if (neg_mode ==PHYLINK_PCS_NEG_INBAND_ENABLED ) { +if (neg_mode ==PHYLINK_PCS_NEG_INBAND_ENABLED && + interface !=PHY_INTERFACE_MODE_2500BASEX ) {if (interface ==PHY_INTERFACE_MODE_SGMII ) sgm_mode |=SGMII_SPEED_DUPLEX_AN ; bmcr =BMCR_ANENABLE ;
Signature · 1 line
2.42.1
Russell King (Oracle)
reviewerRe: [RFC PATCH 3/8] net: pcs: pcs-mtk-lynxi: use 2500Base-X without AN
Quoted 5 lines · Daniel Golle
Using 2500Base-T SFP modules e.g. on the BananaPi R3 requires manually disabling auto-negotiation, e.g. using ethtool. While a proper fix using SFP quirks is being discussed upstream, bring a work-around to restore user experience to what it was before the switch to the dedicated SGMII PCS driver.
No.
drivers/net/pcs/pcs-mtk-lynxi.c static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int neg_mode, · line 145
Quoted 10 lines
drivers/net/pcs/pcs-mtk-lynxi.c +2
-1@@ -129,7 +138,8 @@ static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int neg_mode,if (neg_mode &PHYLINK_PCS_NEG_INBAND ) sgm_mode |=SGMII_REMOTE_FAULT_DIS ; -if (neg_mode ==PHYLINK_PCS_NEG_INBAND_ENABLED ) { +if (neg_mode ==PHYLINK_PCS_NEG_INBAND_ENABLED && + interface !=PHY_INTERFACE_MODE_2500BASEX ) {if (interface ==PHY_INTERFACE_MODE_SGMII ) sgm_mode |=SGMII_SPEED_DUPLEX_AN ; bmcr =BMCR_ANENABLE ;
Phylink is asking you to have inband enabled. If inband needs to be disabled, then we need to arrange for phylink to pass PHYLINK_PCS_NEG_INBAND_DISABLED.
Please don't hack special handling and behaviour into drivers.
Thanks.
Signature · 2 lines
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
Daniel Golle
maintainerRFC PATCH 4/8 net: pcs: pcs-mtk-lynxi: allow calling with NULL advertising
In reply to Daniel GolleAllow calling pcs_config with advertising set to NULL and in this case keep the previously assigned advertisement.
--- drivers/net/pcs/pcs-mtk-lynxi.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-)
drivers/net/pcs/pcs-mtk-lynxi.c +14 -4
@@ -81,6 +81,7 @@ struct mtk_pcs_lynxi {phy_interface_t interface;struct phylink_pcs pcs;u32 flags; +int advertise; };static struct mtk_pcs_lynxi *pcs_to_mtk_pcs_lynxi (struct phylink_pcs *pcs)
@@ -121,11 +122,19 @@ static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int neg_mode,unsigned int rgc3, sgm_mode, bmcr;int advertise, link_timer; - advertise =phylink_mii_c22_pcs_encode_advertisement (interface, - advertising); -if (advertise <0 ) -return advertise; +if (advertising) { + advertise =phylink_mii_c22_pcs_encode_advertisement (interface, + advertising); +if (advertise <0 ) +return advertise; + mpcs->advertise = advertise; + }else { +if (mpcs->advertise <0 ) +return -EINVAL ; + + advertise = mpcs->advertise; + }/* Clearing IF_MODE_BIT0 switches the PCS to BASE-X mode, and * we assume that fixes it's speed at bitrate = line rate (in * other words, 1000Mbps or 2500Mbps).
@@ -299,6 +308,7 @@ struct phylink_pcs *mtk_pcs_lynxi_create(struct device *dev, mpcs->pcs.neg_mode = true; mpcs->pcs.poll = true; mpcs->interface =PHY_INTERFACE_MODE_NA ; + mpcs->advertise =-1 ;return &mpcs->pcs; }
Signature · 1 line
2.42.1
Daniel Golle
maintainerRFC PATCH 5/8 dt-bindings: net: pcs: add bindings for MediaTek USXGMII PCS
In reply to Daniel GolleMediaTek's USXGMII can be found in the MT7988 SoC. We need to access it in order to configure and monitor the Ethernet SerDes link in USXGMII, 10GBase-R and 5GBase-R mode. By including a wrapped legacy 1000Base-X/2500Base-X/Cisco SGMII LynxI PCS as well, those interface modes are also available.
--- .../bindings/net/pcs/mediatek,usxgmii.yaml | 105 ++++++++++++++++++ 1 file changed, 105 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml
Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml new file +105 -0
@@ -0,0 +1,105 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/pcs/mediatek,usxgmii.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek USXGMII PCS + +maintainers: + - Daniel Golle <[email protected]> + +description: + The MediaTek USXGMII PCS provides physical link control and status + for USXGMII, 10GBase-R and 5GBase-R links on the SerDes interfaces + provided by the PEXTP PHY. + In order to also support legacy 2500Base-X, 1000Base-X and Cisco + SGMII an existing mediatek,*-sgmiisys LynxI PCS is wrapped to + provide those interfaces modes on the same SerDes interfaces shared + with the USXGMII PCS. + +properties: + $nodename: + pattern: "^pcs@[0-9a-f]+$" + + compatible: + const: mediatek,mt7988-usxgmiisys + + reg: + maxItems: 1 + + clocks: + items: + - description: USXGMII top-level clock + - description: SGMII top-level clock + - description: SGMII subsystem TX clock + - description: SGMII subsystem RX clock + - description: XFI PLL clock + + clock-names: + items: + - const: usxgmii + - const: sgmii_sel + - const: sgmii_tx + - const: sgmii_rx + - const: xfi_pll + + phys: + items: + - description: PEXTP SerDes PHY + + mediatek,sgmiisys: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon node of the corresponding SGMII LynxI PCS. + + resets: + items: + - description: XFI reset + - description: SGMII reset + + reset-names: + items: + - const: xfi + - const: sgmii + + "#pcs-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - phys + - mediatek,sgmiisys + - resets + - reset-names + - "#pcs-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mediatek,mt7988-clk.h> + #include <dt-bindings/reset/mediatek,mt7988-resets.h> + soc { + #address-cells = <2>; + #size-cells = <2>; + usxgmiisys0: pcs@10080000 { + compatible = "mediatek,mt7988-usxgmiisys"; + reg = <0 0x10080000 0 0x1000>; + clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>, + <&topckgen CLK_TOP_SGM_0_SEL>, + <&sgmiisys0 CLK_SGM0_TX_EN>, + <&sgmiisys0 CLK_SGM0_RX_EN>, + <&xfi_pll CLK_XFIPLL_PLL_EN>; + clock-names = "usxgmii", "sgmii_sel", "sgmii_tx", "sgmii_rx", "xfi_pll"; + resets = <&watchdog MT7988_TOPRGU_XFI0_GRST>, + <&watchdog MT7988_TOPRGU_SGMII0_GRST>; + reset-names = "xfi", "sgmii"; + phys = <&xfi_pextp0>; + mediatek,sgmiisys = <&sgmiisys0>; + #pcs-cells = <0>; + }; + };
Signature · 1 line
2.42.1
Re: [RFC PATCH 5/8] dt-bindings: net: pcs: add bindings for MediaTek USXGMII PCS
Quoted 6 lines · Daniel Golle
MediaTek's USXGMII can be found in the MT7988 SoC. We need to access it in order to configure and monitor the Ethernet SerDes link in USXGMII, 10GBase-R and 5GBase-R mode. By including a wrapped legacy 1000Base-X/2500Base-X/Cisco SGMII LynxI PCS as well, those interface modes are also available.
A nit, subject: drop second/last, redundant "bindings for". The "dt-bindings" prefix is already stating that these are bindings.
Quoted 3 lines
Signed-off-by Daniel Golle <[email protected]>--- .../bindings/net/pcs/mediatek,usxgmii.yaml | 105 ++++++++++++++++++
Use compatible as filename (especially that you do not expect it to grow).
Quoted 9 lines
1 file changed, 105 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yamlDocumentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml new file +0
-0
Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml line 7
Quoted 7 lines
Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml new file +7
-0@@ -0,0 +1,105 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/pcs/mediatek,usxgmii.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek USXGMII PCS
MT7888 I guess?
Quoted 6 lines
Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml new file +6
-0+ +maintainers: + - Daniel Golle <[email protected]> + +description: + The MediaTek USXGMII PCS provides physical link control and status
Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml line 23
Quoted 10 lines
Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml new file +10
-0+ for USXGMII, 10GBase-R and 5GBase-R links on the SerDes interfaces + provided by the PEXTP PHY. + In order to also support legacy 2500Base-X, 1000Base-X and Cisco + SGMII an existing mediatek,*-sgmiisys LynxI PCS is wrapped to + provide those interfaces modes on the same SerDes interfaces shared + with the USXGMII PCS. + +properties: + $nodename: + pattern: "^pcs@[0-9a-f]+$"
Drop, we do not enforce naming in individual device schemas.
Quoted 21 lines
Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml new file +21
-0+ + compatible: + const: mediatek,mt7988-usxgmiisys + + reg: + maxItems: 1 + + clocks: + items: + - description: USXGMII top-level clock + - description: SGMII top-level clock + - description: SGMII subsystem TX clock + - description: SGMII subsystem RX clock + - description: XFI PLL clock + + clock-names: + items: + - const: usxgmii + - const: sgmii_sel + - const: sgmii_tx + - const: sgmii_rx
Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml line 54
Quoted 10 lines
Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml new file +10
-0+ - const: xfi_pll + + phys: + items: + - description: PEXTP SerDes PHY + + mediatek,sgmiisys: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon node of the corresponding SGMII LynxI PCS.
"syscon node" is Linux term. Instead describe to what part of hardware this phandle is and why do you need it.
Quoted 25 lines
Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml new file +25
-0+ + resets: + items: + - description: XFI reset + - description: SGMII reset + + reset-names: + items: + - const: xfi + - const: sgmii + + "#pcs-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - phys + - mediatek,sgmiisys + - resets + - reset-names + - "#pcs-cells" +
Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml line 89
Quoted 10 lines
Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml new file +10
-0+additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mediatek,mt7988-clk.h> + #include <dt-bindings/reset/mediatek,mt7988-resets.h> + soc { + #address-cells = <2>; + #size-cells = <2>; + usxgmiisys0: pcs@10080000 {
Odd/Messed indentation.
Use 4 spaces for example indentation.
Best regards,
Krzysztof
Rob Herring
maintainerRe: [RFC PATCH 5/8] dt-bindings: net: pcs: add bindings for MediaTek USXGMII PCS
In reply to Daniel GolleQuoted 74 lines · Daniel Golle
MediaTek's USXGMII can be found in the MT7988 SoC. We need to access it in order to configure and monitor the Ethernet SerDes link in USXGMII, 10GBase-R and 5GBase-R mode. By including a wrapped legacy 1000Base-X/2500Base-X/Cisco SGMII LynxI PCS as well, those interface modes are also available.
Signed-off-by Daniel Golle <[email protected]>--- .../bindings/net/pcs/mediatek,usxgmii.yaml | 105 ++++++++++++++++++ 1 file changed, 105 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yamlDocumentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml new file +56
-0@@ -0,0 +1,105 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/pcs/mediatek,usxgmii.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek USXGMII PCS + +maintainers: + - Daniel Golle <[email protected]> + +description: + The MediaTek USXGMII PCS provides physical link control and status + for USXGMII, 10GBase-R and 5GBase-R links on the SerDes interfaces + provided by the PEXTP PHY. + In order to also support legacy 2500Base-X, 1000Base-X and Cisco + SGMII an existing mediatek,*-sgmiisys LynxI PCS is wrapped to + provide those interfaces modes on the same SerDes interfaces shared + with the USXGMII PCS. + +properties: + $nodename: + pattern: "^pcs@[0-9a-f]+$" + + compatible: + const: mediatek,mt7988-usxgmiisys + + reg: + maxItems: 1 + + clocks: + items: + - description: USXGMII top-level clock + - description: SGMII top-level clock + - description: SGMII subsystem TX clock + - description: SGMII subsystem RX clock + - description: XFI PLL clock + + clock-names: + items: + - const: usxgmii + - const: sgmii_sel + - const: sgmii_tx + - const: sgmii_rx + - const: xfi_pll + + phys: + items: + - description: PEXTP SerDes PHY + + mediatek,sgmiisys: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon node of the corresponding SGMII LynxI PCS. + + resets:
Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml line 66
Quoted 10 lines
Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml new file +10
-0+ items: + - description: XFI reset + - description: SGMII reset + + reset-names: + items: + - const: xfi + - const: sgmii + + "#pcs-cells":
There is no such property defined.
Rob
Russell King (Oracle)
reviewerRe: [RFC PATCH 5/8] dt-bindings: net: pcs: add bindings for MediaTek USXGMII PCS
In reply to Daniel GolleQuoted 5 lines · Daniel Golle
MediaTek's USXGMII can be found in the MT7988 SoC. We need to access it in order to configure and monitor the Ethernet SerDes link in USXGMII, 10GBase-R and 5GBase-R mode. By including a wrapped legacy 1000Base-X/2500Base-X/Cisco SGMII LynxI PCS as well, those interface modes are also available.
I think this binding is based on the implementation than on hardware.
What I believe you have is this setup:
.---- LynxI PCS ----.
MAC ---+ +--- PEXTP --- world
`--- USXGMII PCS ---'You are representing the PEXTP as a separate entity in DT, but then you're representing the LynxI PCS and the USXGMII PCS as a single block, which seems to be how you've decided to implement it.
Given that the LynxI PCS is already in use elsewhere in the Mediatek range, I suggest that the LynxI PCS is one block of IP, and the USXGMII PCS is a separate block of IP.
1) Would it not be better to model the two PCS seperately?
2) The addition of the SGMII reset needs more information - is this controlling a reset for the LynxI block? If so, it should be part of a LynxI PCS binding.
3) The PEXTP is presumably a separate block which can be shared between several devices - for example, the LynxI, USXGMII, and probably SATA and PCIe as well. From the 802.3's network model, the PEXTP is the PMA/PMD.
From the point of view of 802.3's model, a network interface has various layers such as the MAC, PCS and PMA/PMD, and sitting above these layers is the management of the system. Rather than chasing the data flow (which in a network device can be complex) wouldn't it be better to continue with the 802.3 model as we are doing with other devices, rather than trying to go with a new approach here?
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RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
Daniel Golle
maintainerRFC PATCH 6/8 net: pcs: add driver for MediaTek USXGMII PCS
In reply to Daniel GolleAdd driver for USXGMII PCS found in the MediaTek MT7988 SoC and supporting USXGMII, 10GBase-R and 5GBase-R interface modes. In order to support Cisco SGMII, 1000Base-X and 2500Base-X via the also present LynxI PCS create a wrapped PCS taking care of the components shared between the new USXGMII PCS and the legacy LynxI PCS.
--- MAINTAINERS | 2 + drivers/net/pcs/Kconfig | 10 + drivers/net/pcs/Makefile | 1 + drivers/net/pcs/pcs-mtk-usxgmii.c | 688 ++++++++++++++++++++++++++++ include/linux/pcs/pcs-mtk-usxgmii.h | 18 + 5 files changed, 719 insertions(+) create mode 100644 drivers/net/pcs/pcs-mtk-usxgmii.c create mode 100644 include/linux/pcs/pcs-mtk-usxgmii.h
MAINTAINERS +2 -0
@@ -13517,7 +13517,9 @@ M: Daniel Golle <[email protected]> L: [email protected] S: Maintained F: drivers/net/pcs/pcs-mtk-lynxi.c +F: drivers/net/pcs/pcs-mtk-usxgmii.c F: include/linux/pcs/pcs-mtk-lynxi.h +F: include/linux/pcs/pcs-mtk-usxgmii.h MEDIATEK ETHERNET PHY DRIVERS M: Daniel Golle <[email protected]>
drivers/net/pcs/Kconfig +10 -0
@@ -25,6 +25,16 @@ config PCS_MTK_LYNXI This module provides helpers to phylink for managing the LynxI PCS which is part of MediaTek's SoC and Ethernet switch ICs. +config PCS_MTK_USXGMII + tristate "MediaTek USXGMII PCS" + select PCS_MTK_LYNXI + select PHY_MTK_PEXTP + help + This module provides a driver for MediaTek's USXGMII PCS supporting + 10GBase-R, 5GBase-R and USXGMII interface modes. + 1000Base-X, 2500Base-X and Cisco SGMII are supported on the same + differential pairs via an embedded LynxI PHY. + config PCS_RZN1_MIIC tristate "Renesas RZ/N1 MII converter" depends on OF && (ARCH_RZN1 || COMPILE_TEST)
drivers/net/pcs/Makefile +1 -0
@@ -6,4 +6,5 @@ pcs_xpcs-$(CONFIG_PCS_XPCS) := pcs-xpcs.o pcs-xpcs-nxp.o pcs-xpcs-wx.o obj-$(CONFIG_PCS_XPCS) += pcs_xpcs.o obj-$(CONFIG_PCS_LYNX) += pcs-lynx.o obj-$(CONFIG_PCS_MTK_LYNXI) += pcs-mtk-lynxi.o +obj-$(CONFIG_PCS_MTK_USXGMII) += pcs-mtk-usxgmii.o obj-$(CONFIG_PCS_RZN1_MIIC) += pcs-rzn1-miic.o
drivers/net/pcs/pcs-mtk-usxgmii.c new file +688 -0
688 lines not on this page · raw message
include/linux/pcs/pcs-mtk-usxgmii.h new file +18 -0
@@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __LINUX_PCS_MTK_USXGMII_H +#define __LINUX_PCS_MTK_USXGMII_H + +#include <linux/phylink.h> + +/** +* mtk_usxgmii_select_pcs +* Return PCS indentified by a device node and the PHY interface mode in use +* +* @param np Pointer to device node indentifying a MediaTek USXGMII PCS +* @param mode Ethernet PHY interface mode +* +* @return Pointer to phylink PCS instance of NULL +*/ +struct phylink_pcs *mtk_usxgmii_select_pcs (struct device_node *np,phy_interface_t mode); + +#endif /* __LINUX_PCS_MTK_USXGMII_H */
Signature · 1 line
2.42.1
kernel test robot
build botRe: [RFC PATCH 6/8] net: pcs: add driver for MediaTek USXGMII PCS
kernel test robot noticed the following build errors:
Hi Daniel,
[This is a private test report for your RFC patch.] kernel test robot noticed the following build errors:
[auto build test ERROR on robh/for-next]
[also build test ERROR on net-next/main net/main linus/master v6.6 next-20231110] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Daniel-Golle/dt-bindings-phy-mediatek-xfi-pextp-add-new-bindings/20231110-055440 base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next patch link: https://lore.kernel.org/r/b9f787f3e4aa36e148d7595495af60db53f74417.1699565880.git.daniel%40makrotopia.org patch subject: [RFC PATCH 6/8] net: pcs: add driver for MediaTek USXGMII PCS config: x86_64-buildonly-randconfig-003-20231111 (https://download.01.org/0day-ci/archive/20231111/[email protected]/config) compiler: gcc-12 (Debian 12.2.0-14) 12.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231111/[email protected]/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
All errors (new ones prefixed by >>):
ld: vmlinux.o: in function `mtk_pcs_lynxi_get_state':
>> pcs-mtk-lynxi.c:(.text+0x13acb97): undefined reference to `phylink_mii_c22_pcs_decode_state' ld: vmlinux.o: in function `mtk_pcs_lynxi_config': >> pcs-mtk-lynxi.c:(.text+0x13acf7b): undefined reference to `phylink_mii_c22_pcs_encode_advertisement' ld: vmlinux.o: in function `mtk_usxgmii_pcs_get_state': >> pcs-mtk-usxgmii.c:(.text+0x13ada3d): undefined reference to `phylink_decode_usxgmii_word'
Kconfig warnings: (for reference only)
WARNING: unmet direct dependencies detected for PHY_MTK_PEXTP
Depends on [n]: (ARCH_MEDIATEK || COMPILE_TEST [=y]) && OF [=n] && OF_ADDRESS [=n] && HAS_IOMEM [=y] Selected by [y]:
- PCS_MTK_USXGMII [=y] && NETDEVICES [=y]
Signature · 2 lines
0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki
Re: [RFC PATCH 6/8] net: pcs: add driver for MediaTek USXGMII PCS
In reply to Daniel GolleQuoted 8 lines · Daniel Golle
Add driver for USXGMII PCS found in the MediaTek MT7988 SoC and supporting USXGMII, 10GBase-R and 5GBase-R interface modes. In order to support Cisco SGMII, 1000Base-X and 2500Base-X via the also present LynxI PCS create a wrapped PCS taking care of the components shared between the new USXGMII PCS and the legacy LynxI PCS.
Signed-off-by Daniel Golle <[email protected]>---
[...]
Quoted 6 lines
drivers/net/pcs/pcs-mtk-usxgmii.c new file +0
-0@@ -0,0 +1,688 @@
[...]
Quoted 3 lines
drivers/net/pcs/pcs-mtk-usxgmii.c new file +3
-0+static int mtk_sgmii_wrapper_init (struct mtk_usxgmii_pcs *mpcs) +{ +struct device_node *r = mpcs->dev->of_node, *np;
[...]
drivers/net/pcs/pcs-mtk-usxgmii.c line 281
Quoted 2 lines
drivers/net/pcs/pcs-mtk-usxgmii.c new file +2
-0+ rstc =of_reset_control_get_shared (r,"sgmii" ); +
Superfluous whitespace.
drivers/net/pcs/pcs-mtk-usxgmii.c line 283
Quoted 2 lines
drivers/net/pcs/pcs-mtk-usxgmii.c new file +2
-0+if (IS_ERR (rstc)) +return PTR_ERR (rstc);
Here you correctly check rstc for errors ...
[...]
Quoted 1 line
drivers/net/pcs/pcs-mtk-usxgmii.c new file +1
-0+ wp->reset = rstc;
[...]
drivers/net/pcs/pcs-mtk-usxgmii.c line 330
Quoted 3 lines
drivers/net/pcs/pcs-mtk-usxgmii.c new file +3
-0+ +if (IS_ERR (wp->reset)) +return PTR_ERR (wp->reset);
And here you check it again. The second check can be dropped.
regards
Philipp
Russell King (Oracle)
reviewerRe: [RFC PATCH 6/8] net: pcs: add driver for MediaTek USXGMII PCS
In reply to Daniel GolleQuoted 5 lines · Daniel Golle
Add driver for USXGMII PCS found in the MediaTek MT7988 SoC and supporting USXGMII, 10GBase-R and 5GBase-R interface modes. In order to support Cisco SGMII, 1000Base-X and 2500Base-X via the also present LynxI PCS create a wrapped PCS taking care of the components shared between the new USXGMII PCS and the legacy LynxI PCS.
What is the actual hardware setup here?
From what I can tell, it's something like this:
.---- LynxI PCS ----.
MAC ---+ +--- PEXP --- external
`--- USXGMII PCS ---'Where PEXP is the serdes, handled by the drivers/phy layer in the kernel. This is not an unusual setup, but we don't have the serdes PHY controlled by the PCS driver.
You seem to be combining the whole lot into one driver, which seems rather odd.
I would suggest that the serdes PHY is handled in the MAC driver, using the mac_prepare(), mac_config() and mac_finish() methods, as well as other parts of the driver:
- when the netdev is opened, call phy_power_on(pextp)
- when the netdev is closed, call phy_power_off(pextp)
- in mac_prepare(), if the interface has changed, call phy_reset(pextp)
- in mac_finish(), if the interface has changed, update your recorded interface mode to detect future changes in either mac_prepare() or mac_finish(), and call phy_set_mode_ext(pextp, PHY_MODE_ETHERNET, interface).
That will move most of what seems to be duplicated between the two PCS instances out of the PCS driver and to MAC level, and then the PCS parts become more about just driving the PCS hardware and nothing beyond that. More specifically, the wrapping's only function then is to deal with the sgmii reset. What exactly is that reset signal controlling? The reset to the LynxI PCS or something else?
If you don't do that (and I prefer that you _do_ the above), then the following comments apply to the code here:
1. the use of phy_power_on() without any calls to phy_power_off(). These are counted calls, and after the first call to phy_power_on(), the only effect will be to increase the enable-counts of any associated regulator and the power count. So, basically you're missing calls to phy_power_off(). I suggest a call to phy_power_off() in the pcs_disable() function.
2. calling phy_power_on() in pcs_config() is entirely unnecessary. pcs_config() will not be called unless pcs_enable() has _already_ been called, so the call to phy_power_on() in the pcs_enable() function is entirely sufficient.
With these two fixed, it means that the pextp PHY will be powered up when one of the pcs_enable() functions is called, and powered down when one of the pcs_disable() functions is called.
3. the complicated reset sequence, which is basically:
- phy_reset(pextp)
- reset_control_assert(sgmii or xfi reset)
- *sleep* 100-500us (yes, sleep)
- reset_control_deassert(sgmii or xfi reset)
- *delay* 10ms (not sleep, but spin wait)
If we are in a schedulable context (which the usleep_range() suggests we are) then why bother sleeping for the short delay, and spin-waiting for the longer delay? A bit of consistency seems to be needed here.
4. really needs to explain why it's necessary to repeatedly call the pcs_config() function at each get_state() if the link is down.
Note that with the code the way it is, phy_power_on() will be repeatedly called, and at some point the "power_count" will overflow which would probably be bad. The counting in the regulator core will probably also overflow as well. So this is bad.
Apart from the overflow issue, the only thing I can see that this achieves is to call the core of the pcs_config function. In the case of the lynxi, calling its pcs_config() repeatedly with the same parameters. Looking at pcs-mtk-lynxi.c, I can't see what this would achieve.
With the above issues dealt with, from the point of view of the lynxi / sgmii code, the only things I can see that the wrapping achieves are:
a) when pcs_enable() is called, call phy_power_on(pextp)
b) when pcs_disable() is called, call phy_power_offpextp)
c) when pcs_config() is called, if the interface has changed:
i) call phy_reset() and assert/deassert the "sgmii" reset before calling the lynxi PCS
ii) call phy_set_mode_ext(pextp) for the new interface mode after
calling the lynxi PCS
I haven't picked through the usxgmii code completely, so I'm not specifically commenting on it, although some of the above applies there as well.
Thanks.
Signature · 2 lines
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
Daniel Golle
maintainerRFC PATCH 7/8 dt-bindings: net: mediatek,net: fix and complete mt7988-eth binding
In reply to Daniel GolleRemove clocks which were copied from the vendor driver but are now taken care of by dedicated drivers for PCS and PHY in the upstream driver. Also remove mediatek,sgmiisys phandle which isn't required on MT7988 because we use pcs-handle on the MAC nodes instead.
Last but not least, add an example for MT7988.
--- .../devicetree/bindings/net/mediatek,net.yaml | 171 +++++++++++++++--- 1 file changed, 142 insertions(+), 29 deletions(-)
Documentation/devicetree/bindings/net/mediatek,net.yaml +142 -29
@@ -27,9 +27,6 @@ properties: - mediatek,mt7988-eth - ralink,rt5350-eth - reg: - maxItems: 1 - clocks: true clock-names: true
@@ -115,6 +112,9 @@ allOf: - mediatek,mt7623-eth then: properties: + reg: + maxItems: 1 + interrupts: maxItems: 3
@@ -149,6 +149,9 @@ allOf: - mediatek,mt7621-eth then: properties: + reg: + maxItems: 1 + interrupts: maxItems: 1
@@ -174,6 +177,9 @@ allOf: const: mediatek,mt7622-eth then: properties: + reg: + maxItems: 1 + interrupts: maxItems: 3
@@ -215,6 +221,9 @@ allOf: const: mediatek,mt7629-eth then: properties: + reg: + maxItems: 1 + interrupts: maxItems: 3
@@ -257,6 +266,9 @@ allOf: const: mediatek,mt7981-eth then: properties: + reg: + maxItems: 1 + interrupts: minItems: 4
@@ -295,6 +307,9 @@ allOf: const: mediatek,mt7986-eth then: properties: + reg: + maxItems: 1 + interrupts: minItems: 4
@@ -333,36 +348,32 @@ allOf: const: mediatek,mt7988-eth then: properties: + reg: + maxItems: 2 + minItems: 2 + interrupts: minItems: 4 + maxItems: 4 clocks: - minItems: 34 - maxItems: 34 + minItems: 24 + maxItems: 24 clock-names: items: - - const: crypto + - const: xgp1 + - const: xgp2 + - const: xgp3 - const: fe - const: gp2 - const: gp1 - const: gp3 + - const: esw + - const: crypto - const: ethwarp_wocpu2 - const: ethwarp_wocpu1 - const: ethwarp_wocpu0 - - const: esw - - const: netsys0 - - const: netsys1 - - const: sgmii_tx250m - - const: sgmii_rx250m - - const: sgmii2_tx250m - - const: sgmii2_rx250m - - const: top_usxgmii0_sel - - const: top_usxgmii1_sel - - const: top_sgm0_sel - - const: top_sgm1_sel - - const: top_xfi_phy0_xtal_sel - - const: top_xfi_phy1_xtal_sel - const: top_eth_gmii_sel - const: top_eth_refck_50m_sel - const: top_eth_sys_200m_sel
@@ -375,18 +386,9 @@ allOf: - const: top_netsys_sync_250m_sel - const: top_netsys_ppefb_250m_sel - const: top_netsys_warp_sel - - const: wocpu1 - - const: wocpu0 - - const: xgp1 - - const: xgp2 - - const: xgp3 - - mediatek,sgmiisys: - minItems: 2 - maxItems: 2 patternProperties: - "^mac@[0-1]$": + "^mac@[0-2]$": type: object unevaluatedProperties: false allOf:
@@ -577,3 +579,114 @@ examples: }; }; }; + + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/clock/mediatek,mt7988-clk.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + ethernet@15100000 { + compatible = "mediatek,mt7988-eth"; + reg = <0 0x15100000 0 0x80000>, <0 0x15400000 0 0x380000>; + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <ðsys CLK_ETHDMA_XGP1_EN>, + <ðsys CLK_ETHDMA_XGP2_EN>, + <ðsys CLK_ETHDMA_XGP3_EN>, + <ðsys CLK_ETHDMA_FE_EN>, + <ðsys CLK_ETHDMA_GP2_EN>, + <ðsys CLK_ETHDMA_GP1_EN>, + <ðsys CLK_ETHDMA_GP3_EN>, + <ðsys CLK_ETHDMA_ESW_EN>, + <ðsys CLK_ETHDMA_CRYPT0_EN>, + <ðwarp CLK_ETHWARP_WOCPU2_EN>, + <ðwarp CLK_ETHWARP_WOCPU1_EN>, + <ðwarp CLK_ETHWARP_WOCPU0_EN>, + <&topckgen CLK_TOP_ETH_GMII_SEL>, + <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>, + <&topckgen CLK_TOP_ETH_SYS_200M_SEL>, + <&topckgen CLK_TOP_ETH_SYS_SEL>, + <&topckgen CLK_TOP_ETH_XGMII_SEL>, + <&topckgen CLK_TOP_ETH_MII_SEL>, + <&topckgen CLK_TOP_NETSYS_SEL>, + <&topckgen CLK_TOP_NETSYS_500M_SEL>, + <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>, + <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>, + <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>, + <&topckgen CLK_TOP_NETSYS_WARP_SEL>; + + clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1", + "gp3", "esw", "crypto", + "ethwarp_wocpu2", "ethwarp_wocpu1", + "ethwarp_wocpu0", "top_eth_gmii_sel", + "top_eth_refck_50m_sel", "top_eth_sys_200m_sel", + "top_eth_sys_sel", "top_eth_xgmii_sel", + "top_eth_mii_sel", "top_netsys_sel", + "top_netsys_500m_sel", "top_netsys_pao_2x_sel", + "top_netsys_sync_250m_sel", + "top_netsys_ppefb_250m_sel", + "top_netsys_warp_sel"; + assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, + <&topckgen CLK_TOP_NETSYS_GSW_SEL>, + <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>, + <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>, + <&topckgen CLK_TOP_SGM_0_SEL>, + <&topckgen CLK_TOP_SGM_1_SEL>; + assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, + <&topckgen CLK_TOP_NET1PLL_D4>, + <&topckgen CLK_TOP_NET1PLL_D8_D4>, + <&topckgen CLK_TOP_NET1PLL_D8_D4>, + <&apmixedsys CLK_APMIXED_SGMPLL>, + <&apmixedsys CLK_APMIXED_SGMPLL>; + mediatek,ethsys = <ðsys>; + mediatek,infracfg = <&topmisc>; + #address-cells = <1>; + #size-cells = <0>; + + mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "internal"; + status = "disabled"; + + fixed-link { + speed = <10000>; + full-duplex; + pause; + }; + }; + + mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + status = "disabled"; + pcs-handle = <&usxgmiisys1>; + }; + + mac@2 { + compatible = "mediatek,eth-mac"; + reg = <2>; + status = "disabled"; + pcs-handle = <&usxgmiisys0>; + }; + + mdio_bus: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + /* internal 2.5G PHY */ + int_2p5g_phy: ethernet-phy@15 { + reg = <15>; + compatible = "ethernet-phy-ieee802.3-c45"; + phy-mode = "internal"; + }; + }; + }; + };
Signature · 1 line
2.42.1
Rob Herring
maintainerRe: [RFC PATCH 7/8] dt-bindings: net: mediatek,net: fix and complete mt7988-eth binding
Quoted 5 lines · Daniel Golle
Remove clocks which were copied from the vendor driver but are now taken care of by dedicated drivers for PCS and PHY in the upstream driver. Also remove mediatek,sgmiisys phandle which isn't required on MT7988 because we use pcs-handle on the MAC nodes instead.
Last but not least, add an example for MT7988.
'Also' is a clue for it should be a separate patch. These changes are all ABI breakage. Please explain why that's okay.
Quoted 12 lines
Fixes c94a9aabec36 ("dt-bindings: net: mediatek,net: add mt7988-eth binding")Signed-off-by Daniel Golle <[email protected]>--- .../devicetree/bindings/net/mediatek,net.yaml | 171 +++++++++++++++--- 1 file changed, 142 insertions(+), 29 deletions(-)Documentation/devicetree/bindings/net/mediatek,net.yaml +0
-0
Documentation/devicetree/bindings/net/mediatek,net.yaml properties: · line 32
Quoted 6 lines
Documentation/devicetree/bindings/net/mediatek,net.yaml +0
-3@@ -27,9 +27,6 @@ properties: - mediatek,mt7988-eth - ralink,rt5350-eth - reg: - maxItems: 1 -
It's not clear what this change is from the commit msg.
This should stay and be:
reg:
minItems: 1
items:
- description: what's in the 1st region
- description: what's in the 2nd region
Quoted 54 lines
Documentation/devicetree/bindings/net/mediatek,net.yaml +15
-0clocks: true clock-names: true@@ -115,6 +112,9 @@ allOf: - mediatek,mt7623-eth then: properties: + reg: + maxItems: 1 + interrupts: maxItems: 3@@ -149,6 +149,9 @@ allOf: - mediatek,mt7621-eth then: properties: + reg: + maxItems: 1 + interrupts: maxItems: 1@@ -174,6 +177,9 @@ allOf: const: mediatek,mt7622-eth then: properties: + reg: + maxItems: 1 + interrupts: maxItems: 3@@ -215,6 +221,9 @@ allOf: const: mediatek,mt7629-eth then: properties: + reg: + maxItems: 1 + interrupts: maxItems: 3@@ -257,6 +266,9 @@ allOf: const: mediatek,mt7981-eth then: properties: + reg: + maxItems: 1 + interrupts: minItems: 4
Documentation/devicetree/bindings/net/mediatek,net.yaml allOf: · line 312
Quoted 6 lines
Documentation/devicetree/bindings/net/mediatek,net.yaml +3
-0@@ -295,6 +307,9 @@ allOf: const: mediatek,mt7986-eth then: properties: + reg: + maxItems: 1 +
Looks like lots of duplication. Perhaps there's a cleaner way.
Quoted 142 lines
Documentation/devicetree/bindings/net/mediatek,net.yaml +79
-26interrupts: minItems: 4@@ -333,36 +348,32 @@ allOf: const: mediatek,mt7988-eth then: properties: + reg: + maxItems: 2 + minItems: 2 + interrupts: minItems: 4 + maxItems: 4 clocks: - minItems: 34 - maxItems: 34 + minItems: 24 + maxItems: 24 clock-names: items: - - const: crypto + - const: xgp1 + - const: xgp2 + - const: xgp3 - const: fe - const: gp2 - const: gp1 - const: gp3 + - const: esw + - const: crypto - const: ethwarp_wocpu2 - const: ethwarp_wocpu1 - const: ethwarp_wocpu0 - - const: esw - - const: netsys0 - - const: netsys1 - - const: sgmii_tx250m - - const: sgmii_rx250m - - const: sgmii2_tx250m - - const: sgmii2_rx250m - - const: top_usxgmii0_sel - - const: top_usxgmii1_sel - - const: top_sgm0_sel - - const: top_sgm1_sel - - const: top_xfi_phy0_xtal_sel - - const: top_xfi_phy1_xtal_sel - const: top_eth_gmii_sel - const: top_eth_refck_50m_sel - const: top_eth_sys_200m_sel@@ -375,18 +386,9 @@ allOf: - const: top_netsys_sync_250m_sel - const: top_netsys_ppefb_250m_sel - const: top_netsys_warp_sel - - const: wocpu1 - - const: wocpu0 - - const: xgp1 - - const: xgp2 - - const: xgp3 - - mediatek,sgmiisys: - minItems: 2 - maxItems: 2 patternProperties: - "^mac@[0-1]$": + "^mac@[0-2]$": type: object unevaluatedProperties: false allOf:@@ -577,3 +579,114 @@ examples: }; }; }; + + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/clock/mediatek,mt7988-clk.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + ethernet@15100000 { + compatible = "mediatek,mt7988-eth"; + reg = <0 0x15100000 0 0x80000>, <0 0x15400000 0 0x380000>; + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <ðsys CLK_ETHDMA_XGP1_EN>, + <ðsys CLK_ETHDMA_XGP2_EN>, + <ðsys CLK_ETHDMA_XGP3_EN>, + <ðsys CLK_ETHDMA_FE_EN>, + <ðsys CLK_ETHDMA_GP2_EN>, + <ðsys CLK_ETHDMA_GP1_EN>, + <ðsys CLK_ETHDMA_GP3_EN>, + <ðsys CLK_ETHDMA_ESW_EN>, + <ðsys CLK_ETHDMA_CRYPT0_EN>, + <ðwarp CLK_ETHWARP_WOCPU2_EN>, + <ðwarp CLK_ETHWARP_WOCPU1_EN>, + <ðwarp CLK_ETHWARP_WOCPU0_EN>, + <&topckgen CLK_TOP_ETH_GMII_SEL>, + <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>, + <&topckgen CLK_TOP_ETH_SYS_200M_SEL>, + <&topckgen CLK_TOP_ETH_SYS_SEL>, + <&topckgen CLK_TOP_ETH_XGMII_SEL>, + <&topckgen CLK_TOP_ETH_MII_SEL>, + <&topckgen CLK_TOP_NETSYS_SEL>, + <&topckgen CLK_TOP_NETSYS_500M_SEL>, + <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>, + <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>, + <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>, + <&topckgen CLK_TOP_NETSYS_WARP_SEL>; + + clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1", + "gp3", "esw", "crypto", + "ethwarp_wocpu2", "ethwarp_wocpu1", + "ethwarp_wocpu0", "top_eth_gmii_sel", + "top_eth_refck_50m_sel", "top_eth_sys_200m_sel", + "top_eth_sys_sel", "top_eth_xgmii_sel", + "top_eth_mii_sel", "top_netsys_sel", + "top_netsys_500m_sel", "top_netsys_pao_2x_sel", + "top_netsys_sync_250m_sel", + "top_netsys_ppefb_250m_sel", + "top_netsys_warp_sel"; + assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, + <&topckgen CLK_TOP_NETSYS_GSW_SEL>, + <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>, + <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>, + <&topckgen CLK_TOP_SGM_0_SEL>, + <&topckgen CLK_TOP_SGM_1_SEL>; + assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, + <&topckgen CLK_TOP_NET1PLL_D4>, + <&topckgen CLK_TOP_NET1PLL_D8_D4>, + <&topckgen CLK_TOP_NET1PLL_D8_D4>, + <&apmixedsys CLK_APMIXED_SGMPLL>, + <&apmixedsys CLK_APMIXED_SGMPLL>;
Documentation/devicetree/bindings/net/mediatek,net.yaml examples: · line 657
Quoted 10 lines
Documentation/devicetree/bindings/net/mediatek,net.yaml +10
-0+ mediatek,ethsys = <ðsys>; + mediatek,infracfg = <&topmisc>; + #address-cells = <1>; + #size-cells = <0>; + + mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "internal"; + status = "disabled";
Examples should be enabled.
Quoted 13 lines
Documentation/devicetree/bindings/net/mediatek,net.yaml +13
-0+ + fixed-link { + speed = <10000>; + full-duplex; + pause; + }; + }; + + mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + status = "disabled"; + pcs-handle = <&usxgmiisys1>;
Documentation/devicetree/bindings/net/mediatek,net.yaml examples: · line 680
Quoted 10 lines
Documentation/devicetree/bindings/net/mediatek,net.yaml +10
-0+ }; + + mac@2 { + compatible = "mediatek,eth-mac"; + reg = <2>; + status = "disabled"; + pcs-handle = <&usxgmiisys0>; + }; + + mdio_bus: mdio-bus {
mdio {
Quoted 14 lines
Documentation/devicetree/bindings/net/mediatek,net.yaml +12
-0+ #address-cells = <1>; + #size-cells = <0>; + + /* internal 2.5G PHY */ + int_2p5g_phy: ethernet-phy@15 { + reg = <15>; + compatible = "ethernet-phy-ieee802.3-c45"; + phy-mode = "internal"; + }; + }; + }; + };Signature · 1 line
2.42.1
Daniel Golle
maintainerRe: [RFC PATCH 7/8] dt-bindings: net: mediatek,net: fix and complete mt7988-eth binding
Hi Rob,
thank you for reviewing this patch.
Quoted 9 lines · Rob Herring
Quoted 5 lines · Daniel Golle
Remove clocks which were copied from the vendor driver but are now taken care of by dedicated drivers for PCS and PHY in the upstream driver. Also remove mediatek,sgmiisys phandle which isn't required on MT7988 because we use pcs-handle on the MAC nodes instead.
Last but not least, add an example for MT7988.'Also' is a clue for it should be a separate patch. These changes are all ABI breakage. Please explain why that's okay.
I hope that it's ok because the driver at this point never supported any SerDes modes and we are still in the process of bringing up mainline support for this SoC. All of clk, pinctrl, reset, ... driver and dt-bindings are still pending or being prepared for submission.
Quoted 22 lines
Quoted 13 lines
Fixes c94a9aabec36 ("dt-bindings: net: mediatek,net: add mt7988-eth binding")Signed-off-by Daniel Golle <[email protected]>--- .../devicetree/bindings/net/mediatek,net.yaml | 171 +++++++++++++++--- 1 file changed, 142 insertions(+), 29 deletions(-)Documentation/devicetree/bindings/net/mediatek,net.yaml +0
-0Documentation/devicetree/bindings/net/mediatek,net.yaml properties: · line 32
Quoted 6 lines
Documentation/devicetree/bindings/net/mediatek,net.yaml +0
-3@@ -27,9 +27,6 @@ properties: - mediatek,mt7988-eth - ralink,rt5350-eth - reg: - maxItems: 1 -It's not clear what this change is from the commit msg.
Quoted 7 lines
This should stay and be:
reg:
minItems: 1
items:
- description: what's in the 1st region
- description: what's in the 2nd region
Ack.
Quoted 54 lines
Quoted 54 lines
Documentation/devicetree/bindings/net/mediatek,net.yaml +15
-0clocks: true clock-names: true@@ -115,6 +112,9 @@ allOf: - mediatek,mt7623-eth then: properties: + reg: + maxItems: 1 + interrupts: maxItems: 3@@ -149,6 +149,9 @@ allOf: - mediatek,mt7621-eth then: properties: + reg: + maxItems: 1 + interrupts: maxItems: 1@@ -174,6 +177,9 @@ allOf: const: mediatek,mt7622-eth then: properties: + reg: + maxItems: 1 + interrupts: maxItems: 3@@ -215,6 +221,9 @@ allOf: const: mediatek,mt7629-eth then: properties: + reg: + maxItems: 1 + interrupts: maxItems: 3@@ -257,6 +266,9 @@ allOf: const: mediatek,mt7981-eth then: properties: + reg: + maxItems: 1 + interrupts: minItems: 4
Quoted 9 lines
Documentation/devicetree/bindings/net/mediatek,net.yaml allOf: · line 312
Quoted 7 lines
Documentation/devicetree/bindings/net/mediatek,net.yaml +3
-0@@ -295,6 +307,9 @@ allOf: const: mediatek,mt7986-eth then: properties: + reg: + maxItems: 1 +Looks like lots of duplication. Perhaps there's a cleaner way.
Hm, I don't really see any better way. Suggestions anyone?
Quoted 147 lines
Quoted 147 lines
Documentation/devicetree/bindings/net/mediatek,net.yaml +83
-26interrupts: minItems: 4@@ -333,36 +348,32 @@ allOf: const: mediatek,mt7988-eth then: properties: + reg: + maxItems: 2 + minItems: 2 + interrupts: minItems: 4 + maxItems: 4 clocks: - minItems: 34 - maxItems: 34 + minItems: 24 + maxItems: 24 clock-names: items: - - const: crypto + - const: xgp1 + - const: xgp2 + - const: xgp3 - const: fe - const: gp2 - const: gp1 - const: gp3 + - const: esw + - const: crypto - const: ethwarp_wocpu2 - const: ethwarp_wocpu1 - const: ethwarp_wocpu0 - - const: esw - - const: netsys0 - - const: netsys1 - - const: sgmii_tx250m - - const: sgmii_rx250m - - const: sgmii2_tx250m - - const: sgmii2_rx250m - - const: top_usxgmii0_sel - - const: top_usxgmii1_sel - - const: top_sgm0_sel - - const: top_sgm1_sel - - const: top_xfi_phy0_xtal_sel - - const: top_xfi_phy1_xtal_sel - const: top_eth_gmii_sel - const: top_eth_refck_50m_sel - const: top_eth_sys_200m_sel@@ -375,18 +386,9 @@ allOf: - const: top_netsys_sync_250m_sel - const: top_netsys_ppefb_250m_sel - const: top_netsys_warp_sel - - const: wocpu1 - - const: wocpu0 - - const: xgp1 - - const: xgp2 - - const: xgp3 - - mediatek,sgmiisys: - minItems: 2 - maxItems: 2 patternProperties: - "^mac@[0-1]$": + "^mac@[0-2]$": type: object unevaluatedProperties: false allOf:@@ -577,3 +579,114 @@ examples: }; }; }; + + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/clock/mediatek,mt7988-clk.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + ethernet@15100000 { + compatible = "mediatek,mt7988-eth"; + reg = <0 0x15100000 0 0x80000>, <0 0x15400000 0 0x380000>; + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <ðsys CLK_ETHDMA_XGP1_EN>, + <ðsys CLK_ETHDMA_XGP2_EN>, + <ðsys CLK_ETHDMA_XGP3_EN>, + <ðsys CLK_ETHDMA_FE_EN>, + <ðsys CLK_ETHDMA_GP2_EN>, + <ðsys CLK_ETHDMA_GP1_EN>, + <ðsys CLK_ETHDMA_GP3_EN>, + <ðsys CLK_ETHDMA_ESW_EN>, + <ðsys CLK_ETHDMA_CRYPT0_EN>, + <ðwarp CLK_ETHWARP_WOCPU2_EN>, + <ðwarp CLK_ETHWARP_WOCPU1_EN>, + <ðwarp CLK_ETHWARP_WOCPU0_EN>, + <&topckgen CLK_TOP_ETH_GMII_SEL>, + <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>, + <&topckgen CLK_TOP_ETH_SYS_200M_SEL>, + <&topckgen CLK_TOP_ETH_SYS_SEL>, + <&topckgen CLK_TOP_ETH_XGMII_SEL>, + <&topckgen CLK_TOP_ETH_MII_SEL>, + <&topckgen CLK_TOP_NETSYS_SEL>, + <&topckgen CLK_TOP_NETSYS_500M_SEL>, + <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>, + <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>, + <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>, + <&topckgen CLK_TOP_NETSYS_WARP_SEL>; + + clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1", + "gp3", "esw", "crypto", + "ethwarp_wocpu2", "ethwarp_wocpu1", + "ethwarp_wocpu0", "top_eth_gmii_sel", + "top_eth_refck_50m_sel", "top_eth_sys_200m_sel", + "top_eth_sys_sel", "top_eth_xgmii_sel", + "top_eth_mii_sel", "top_netsys_sel", + "top_netsys_500m_sel", "top_netsys_pao_2x_sel", + "top_netsys_sync_250m_sel", + "top_netsys_ppefb_250m_sel", + "top_netsys_warp_sel"; + assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, + <&topckgen CLK_TOP_NETSYS_GSW_SEL>, + <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>, + <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>, + <&topckgen CLK_TOP_SGM_0_SEL>, + <&topckgen CLK_TOP_SGM_1_SEL>; + assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, + <&topckgen CLK_TOP_NET1PLL_D4>, + <&topckgen CLK_TOP_NET1PLL_D8_D4>, + <&topckgen CLK_TOP_NET1PLL_D8_D4>, + <&apmixedsys CLK_APMIXED_SGMPLL>, + <&apmixedsys CLK_APMIXED_SGMPLL>; + mediatek,ethsys = <ðsys>; + mediatek,infracfg = <&topmisc>; + #address-cells = <1>; + #size-cells = <0>;
Quoted 8 lines
Documentation/devicetree/bindings/net/mediatek,net.yaml examples: · line 657
Quoted 6 lines
Documentation/devicetree/bindings/net/mediatek,net.yaml +6
-0+ + mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "internal"; + status = "disabled";Examples should be enabled.
Ack.
Quoted 42 lines
Quoted 14 lines
Documentation/devicetree/bindings/net/mediatek,net.yaml +13
-0+ + fixed-link { + speed = <10000>; + full-duplex; + pause; + }; + }; + + mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + status = "disabled"; + pcs-handle = <&usxgmiisys1>;Documentation/devicetree/bindings/net/mediatek,net.yaml examples: · line 680
Quoted 10 lines
Documentation/devicetree/bindings/net/mediatek,net.yaml +10
-0+ }; + + mac@2 { + compatible = "mediatek,eth-mac"; + reg = <2>; + status = "disabled"; + pcs-handle = <&usxgmiisys0>; + }; + + mdio_bus: mdio-bus {mdio {
Quoted 14 lines
Documentation/devicetree/bindings/net/mediatek,net.yaml +12
-0+ #address-cells = <1>; + #size-cells = <0>; + + /* internal 2.5G PHY */ + int_2p5g_phy: ethernet-phy@15 { + reg = <15>; + compatible = "ethernet-phy-ieee802.3-c45"; + phy-mode = "internal"; + }; + }; + }; + };Signature · 1 line
2.42.1
Daniel Golle
maintainerRFC PATCH 8/8 net: ethernet: mtk_eth_soc: add paths and SerDes modes for MT7988
In reply to Daniel GolleMT7988 comes with a built-in 2.5G PHY as well as SerDes lanes to connect external PHYs or transceivers in USXGMII, 10GBase-R, 5GBase-R, 2500Base-X, 1000Base-X and Cisco SGMII interface modes.
Implement support for configuring for the new paths to SerDes interfaces and the internal 2.5G PHY.
Add USXGMII PCS driver for 10GBase-R, 5GBase-R and USXGMII mode, and setup the new PHYA on MT7988 to access the also still existing old LynxI PCS for 1000Base-X, 2500Base-X and Cisco SGMII PCS interface modes.
--- drivers/net/ethernet/mediatek/Kconfig | 17 ++ drivers/net/ethernet/mediatek/mtk_eth_path.c | 122 ++++++++++++- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 178 ++++++++++++++++--- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 105 +++++++++-- 4 files changed, 379 insertions(+), 43 deletions(-)
drivers/net/ethernet/mediatek/Kconfig +17 -0
@@ -21,10 +21,27 @@ config NET_MEDIATEK_SOC select PAGE_POOL_STATS select PCS_MTK_LYNXI select REGMAP_MMIO + select PCS_MTK_USXGMII if NET_MEDIATEK_SOC_USXGMII help This driver supports the gigabit ethernet MACs in the MediaTek SoC family. +config NET_MEDIATEK_SOC_USXGMII + bool "Support USXGMII SerDes on MT7988" + depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST + def_bool NET_MEDIATEK_SOC != n + help + Include support for 10GE SerDes which can be found on MT7988. + If this kernel should run on SoCs with 10 GBit/s Ethernet you + will need to select this option to use GMAC2 and GMAC3 with + external PHYs, SFP(+) cages in 10GBase-R, 5GBase-R or USXGMII + interface modes. + + Note that as the 2500Base-X/1000Base-X/Cisco SGMII SerDes PCS + unit (MediaTek LynxI) in MT7988 is connected via the new 10GE + SerDes, you will also need to select this option in case you + want to use any of those SerDes modes. + config NET_MEDIATEK_STAR_EMAC tristate "MediaTek STAR Ethernet MAC support" select PHYLIB
drivers/net/ethernet/mediatek/mtk_eth_path.c +118 -4
172 lines not on this page · raw message
drivers/net/ethernet/mediatek/mtk_eth_soc.c +155 -23
277 lines not on this page · raw message
drivers/net/ethernet/mediatek/mtk_eth_soc.h +89 -16
247 lines not on this page · raw message
Signature · 1 line
2.42.1
Re: [RFC PATCH 8/8] net: ethernet: mtk_eth_soc: add paths and SerDes modes for MT7988
Quoted 14 lines · Daniel Golle
MT7988 comes with a built-in 2.5G PHY as well as SerDes lanes to connect external PHYs or transceivers in USXGMII, 10GBase-R, 5GBase-R, 2500Base-X, 1000Base-X and Cisco SGMII interface modes.
Implement support for configuring for the new paths to SerDes interfaces and the internal 2.5G PHY.
Add USXGMII PCS driver for 10GBase-R, 5GBase-R and USXGMII mode, and setup the new PHYA on MT7988 to access the also still existing old LynxI PCS for 1000Base-X, 2500Base-X and Cisco SGMII PCS interface modes.
Signed-off-by Daniel Golle <[email protected]>---
[...]
drivers/net/ethernet/mediatek/mtk_eth_soc.h line 18
Quoted 9 lines
drivers/net/ethernet/mediatek/mtk_eth_soc.h +1
-0@@ -15,6 +15,7 @@#include <linux/u64_stats_sync.h> #include <linux/refcount.h> #include <linux/phylink.h> +#include <linux/reset.h>
I can't see what this is required for?
regards
Philipp