dmaengine: dw: Fix src/dst addr width misconfig

Currently the src_addr_width and dst_addr_width fields of the dma_slave_config structure are mapped to the CTLx.SRC_TR_WIDTH and CTLx.DST_TR_WIDTH fields of the peripheral bus side in order to have the properly aligned data passed to the target device. It's done just by converting the passed peripheral bus width to the encoded value using the __ffs() function. This implementation has several problematic sides:

1. __ffs() is undefined if no bit exist in the passed value. Thus if the specified addr-width is DMA_SLAVE_BUSWIDTH_UNDEFINED, __ffs() may return unexpected value depending on the platform-specific implementation.

2. DW AHB DMA-engine permits having the power-of-2 transfer width limited by the DMAH_Mk_HDATA_WIDTH IP-core synthesize parameter. Specifying bus-width out of that constraints scope will definitely cause unexpected result since the destination reg will be only partly touched than the client driver implied.

Let's fix all of that by adding the peripheral bus width verification method which would make sure that the passed source or destination address width is valid and if undefined then the driver will just fallback to the 1-byte width transfer.

(quoted diff) +2 -0

+	return 0;
+}

Quoted 17 lines · Serge Semin

Currently the src_addr_width and dst_addr_width fields of the dma_slave_config structure are mapped to the CTLx.SRC_TR_WIDTH and CTLx.DST_TR_WIDTH fields of the peripheral bus side in order to have the properly aligned data passed to the target device. It's done just by converting the passed peripheral bus width to the encoded value using the __ffs() function. This implementation has several problematic sides:

1. __ffs() is undefined if no bit exist in the passed value. Thus if the specified addr-width is DMA_SLAVE_BUSWIDTH_UNDEFINED, __ffs() may return unexpected value depending on the platform-specific implementation.

2. DW AHB DMA-engine permits having the power-of-2 transfer width limited by the DMAH_Mk_HDATA_WIDTH IP-core synthesize parameter. Specifying bus-width out of that constraints scope will definitely cause unexpected result since the destination reg will be only partly touched than the client driver implied.

Quoted 4 lines

Let's fix all of that by adding the peripheral bus width verification method which would make sure that the passed source or destination address width is valid and if undefined then the driver will just fallback to the 1-byte width transfer.

Please, add a word that you apply the check in the dwc_config() which is supposed to be called before preparing any transfer?

...

Quoted 10 lines

drivers/dma/dw/core.c +10 -0

+static int dwc_verify_p_buswidth(struct dma_chan *chan)
+{
+	struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
+	struct dw_dma *dw = to_dw_dma(chan->device);
+	u32 reg_width, max_width;
+
+	if (dwc->dma_sconfig.direction == DMA_MEM_TO_DEV)
+		reg_width = dwc->dma_sconfig.dst_addr_width;
+	else if (dwc->dma_sconfig.direction == DMA_DEV_TO_MEM)
+		reg_width = dwc->dma_sconfig.src_addr_width;

drivers/dma/dw/core.c bool dw_dma_filter(struct dma_chan *chan, void *param) · line 794

Quoted 1 line

drivers/dma/dw/core.c +1 -0

+	else /* DMA_MEM_TO_MEM */

Actually not only this direction,

but TBH I do not see value in these comments.

drivers/dma/dw/core.c bool dw_dma_filter(struct dma_chan *chan, void *param) · line 799

Quoted 6 lines

drivers/dma/dw/core.c +5 -0

+		return 0;
+
+	max_width = dw->pdata->data_width[dwc->dws.p_master];
+
+	/* Fall-back to 1byte transfer width if undefined */

1-byte
(as you even used in the commit message correctly)

drivers/dma/dw/core.c bool dw_dma_filter(struct dma_chan *chan, void *param) · line 811

Quoted 13 lines

drivers/dma/dw/core.c +12 -0

+	if (reg_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
+		reg_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
+	else if (!is_power_of_2(reg_width) || reg_width > max_width)
+		return -EINVAL;
+	else /* bus width is valid */
+		return 0;
+
+	/* Update undefined addr width value */
+	if (dwc->dma_sconfig.direction == DMA_MEM_TO_DEV)
+		dwc->dma_sconfig.dst_addr_width = reg_width;
+	else /* DMA_DEV_TO_MEM */
+		dwc->dma_sconfig.src_addr_width = reg_width;

So, can't you simply call clamp() for both fields in dwc_config()?

Quoted 3 lines

(quoted diff) +2 -0

+	return 0;
+}

...

drivers/dma/dw/core.c bool dw_dma_filter(struct dma_chan *chan, void *param) · line 820

Quoted 1 line

drivers/dma/dw/core.c +1 -0

+	int err;

Hmm... we have two functions one of which is using different name for this.

Can we have a patch to convert to err the other one?

Signature · 3 lines

-- 
With Best Regards,
Andy Shevchenko

Quoted 1 line · Andy Shevchenko

On Tue, Apr 16, 2024 at 07:28:55PM +0300, Serge Semin wrote:

Quoted 13 lines

Quoted 12 lines

drivers/dma/dw/core.c +12 -0

+	if (reg_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
+		reg_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
+	else if (!is_power_of_2(reg_width) || reg_width > max_width)
+		return -EINVAL;
+	else /* bus width is valid */
+		return 0;
+
+	/* Update undefined addr width value */
+	if (dwc->dma_sconfig.direction == DMA_MEM_TO_DEV)
+		dwc->dma_sconfig.dst_addr_width = reg_width;
+	else /* DMA_DEV_TO_MEM */
+		dwc->dma_sconfig.src_addr_width = reg_width;

Quoted 1 line

So, can't you simply call clamp() for both fields in dwc_config()?

Alas I can't. Because the addr-width is the non-memory peripheral setting. We can't change it since the client drivers calculate it on the application-specific basis (CSR widths, transfer length, etc). So we must make sure that the specified value is supported.

Quoted 2 lines

Quoted 2 lines

(quoted diff) +2 -0

+	return 0;
+}

Quoted 3 lines

drivers/dma/dw/core.c bool dw_dma_filter(struct dma_chan *chan, void *param) · line 820

Quoted 1 line

drivers/dma/dw/core.c +1 -0

+	int err;

Hmm... we have two functions one of which is using different name for this.

Right, the driver uses both variants (see of.c, platform.c, pci.c too).

Quoted 1 line

Can we have a patch to convert to err the other one?

To be honest I'd prefer to use the "ret" name instead. It better describes the variable usage context (Although the statements like "if (err) ..." look a bit more readable). So I'd rather convert the "err" vars to "ret". What do you think?

Quoted 2 lines · Serge Semin

Quoted 1 line · Andy Shevchenko

On Tue, Apr 16, 2024 at 07:28:55PM +0300, Serge Semin wrote:

...

Quoted 14 lines

Quoted 13 lines

Quoted 12 lines

drivers/dma/dw/core.c +12 -0

+	if (reg_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
+		reg_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
+	else if (!is_power_of_2(reg_width) || reg_width > max_width)
+		return -EINVAL;
+	else /* bus width is valid */
+		return 0;
+
+	/* Update undefined addr width value */
+	if (dwc->dma_sconfig.direction == DMA_MEM_TO_DEV)
+		dwc->dma_sconfig.dst_addr_width = reg_width;
+	else /* DMA_DEV_TO_MEM */
+		dwc->dma_sconfig.src_addr_width = reg_width;

Quoted 6 lines

Quoted 1 line

So, can't you simply call clamp() for both fields in dwc_config()?

Alas I can't. Because the addr-width is the non-memory peripheral setting. We can't change it since the client drivers calculate it on the application-specific basis (CSR widths, transfer length, etc). So we must make sure that the specified value is supported.

What I meant is to convert this "update" part to the clamping, so we will have the check as the above like

_verify_()

{
	if (reg_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
		return -E...;
	if (!is_power_of_2(reg_width) || reg_width > max_width)
		return -EINVAL;

	/* bus width is valid */
	return 0;
}

dwc_config()

{
	err = ...
	if (err = ...)
		clamp?
	else if (err)
		return err;
}

But it's up to you to choose the better variant. I just share the idea.

Quoted 3 lines

Quoted 3 lines

Quoted 3 lines

(quoted diff) +2 -0

+	return 0;
+}

...

Quoted 8 lines

Quoted 3 lines

drivers/dma/dw/core.c bool dw_dma_filter(struct dma_chan *chan, void *param) · line 820

Quoted 1 line

drivers/dma/dw/core.c +1 -0

+	int err;

Hmm... we have two functions one of which is using different name for this.

Right, the driver uses both variants (see of.c, platform.c, pci.c too).

Quoted 1 line

Can we have a patch to convert to err the other one?

Quoted 4 lines

To be honest I'd prefer to use the "ret" name instead. It better describes the variable usage context (Although the statements like "if (err) ..." look a bit more readable). So I'd rather convert the "err" vars to "ret". What do you think?

I'm fine with any choice, just my point is to get it consistent across the driver.

Signature · 3 lines

-- 
With Best Regards,
Andy Shevchenko

Currently in case of the DEV_TO_MEM or MEM_TO_DEV DMA transfers the memory data width (single transfer width) is determined based on the buffer length, buffer base address or DMA master-channel max address width capability. It isn't enough in case of the channel disabling prior the block transfer is finished. Here is what DW AHB DMA IP-core databook says regarding the port suspension (DMA-transfer pause) implementation in the controller:

"When CTLx.SRC_TR_WIDTH < CTLx.DST_TR_WIDTH and the CFGx.CH_SUSP bit is high, the CFGx.FIFO_EMPTY is asserted once the contents of the FIFO do not permit a single word of CTLx.DST_TR_WIDTH to be formed. However, there may still be data in the channel FIFO, but not enough to form a single transfer of CTLx.DST_TR_WIDTH. In this scenario, once the channel is disabled, the remaining data in the channel FIFO is not transferred to the destination peripheral."

So in case if the port gets to be suspended and then disabled it's possible to have the data silently discarded even though the controller reported that FIFO is empty and the CTLx.BLOCK_TS indicated the dropped data already received from the source device. This looks as if the data somehow got lost on a way from the peripheral device to memory and causes problems for instance in the DW APB UART driver, which pauses and disables the DMA-transfer as soon as the recv data timeout happens. Here is the way it looks:

Memory <------- DMA FIFO <------ UART FIFO <---------------- UART

  DST_TR_WIDTH -+--------|       |         |
                |        |       |         |                No more data
   Current lvl -+--------|       |---------+- DMA-burst lvl
                |        |       |---------+- Leftover data
                |        |       |---------+- SRC_TR_WIDTH
               -+--------+-------+---------+

In the example above: no more data is getting received over the UART port and BLOCK_TS is not even close to be fully received; some data is left in the UART FIFO, but not enough to perform a bursted DMA-xfer to the DMA FIFO; some data is left in the DMA FIFO, but not enough to be passed further to the system memory in a single transfer. In this situation the 8250 UART driver catches the recv timeout interrupt, pauses the DMA-transfer and terminates it completely, after which the IRQ handler manually fetches the leftover data from the UART FIFO into the recv-buffer. But since the DMA-channel has been disabled with the data left in the DMA FIFO, that data will be just discarded and the recv-buffer will have a gap of the "current lvl" size in the recv-buffer at the tail of the lately received data portion. So the data will be lost just due to the misconfigured DMA transfer.

Note this is only relevant for the case of the transfer suspension and _disabling_. No problem will happen if the transfer will be re-enabled afterwards or the block transfer is fully completed. In the later case the "FIFO flush mode" will be executed at the transfer final stage in order to push out the data left in the DMA FIFO.

In order to fix the denoted problem the DW AHB DMA-engine driver needs to make sure that the _bursted_ source transfer width is greater or equal to the single destination transfer (note the HW databook describes more strict constraint than actually required). Since the peripheral-device side is prescribed by the client driver logic, the memory-side can be only used for that. The solution can be easily implemented for the DEV_TO_MEM transfers just by adjusting the memory-channel address width. Sadly it's not that easy for the MEM_TO_DEV transfers since the mem-to-dma burst size is normally dynamically determined by the controller. So the only thing that can be done is to make sure that memory-side address width can be greater than the peripheral device address width.

drivers/dma/dw/core.c +10 -0

+static int dwc_verify_m_buswidth(struct dma_chan *chan)
+{
+	struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
+	struct dw_dma *dw = to_dw_dma(chan->device);
+	u32 reg_width, reg_burst, mem_width;
+
+	mem_width = dw->pdata->data_width[dwc->dws.m_master];
+
+	/* Make sure src and dst word widths are coherent */
+	if (dwc->dma_sconfig.direction == DMA_MEM_TO_DEV) {

drivers/dma/dw/core.c +2 -2

 	dwc->dma_sconfig.src_maxburst =
-		clamp(dwc->dma_sconfig.src_maxburst, 0U, dwc->max_burst);
+		clamp(dwc->dma_sconfig.src_maxburst, 1U, dwc->max_burst);
 	dwc->dma_sconfig.dst_maxburst =
-		clamp(dwc->dma_sconfig.dst_maxburst, 0U, dwc->max_burst);
+		clamp(dwc->dma_sconfig.dst_maxburst, 1U, dwc->max_burst);

Quoted 64 lines · Serge Semin

Currently in case of the DEV_TO_MEM or MEM_TO_DEV DMA transfers the memory data width (single transfer width) is determined based on the buffer length, buffer base address or DMA master-channel max address width capability. It isn't enough in case of the channel disabling prior the block transfer is finished. Here is what DW AHB DMA IP-core databook says regarding the port suspension (DMA-transfer pause) implementation in the controller:

"When CTLx.SRC_TR_WIDTH < CTLx.DST_TR_WIDTH and the CFGx.CH_SUSP bit is high, the CFGx.FIFO_EMPTY is asserted once the contents of the FIFO do not permit a single word of CTLx.DST_TR_WIDTH to be formed. However, there may still be data in the channel FIFO, but not enough to form a single transfer of CTLx.DST_TR_WIDTH. In this scenario, once the channel is disabled, the remaining data in the channel FIFO is not transferred to the destination peripheral."

So in case if the port gets to be suspended and then disabled it's possible to have the data silently discarded even though the controller reported that FIFO is empty and the CTLx.BLOCK_TS indicated the dropped data already received from the source device. This looks as if the data somehow got lost on a way from the peripheral device to memory and causes problems for instance in the DW APB UART driver, which pauses and disables the DMA-transfer as soon as the recv data timeout happens. Here is the way it looks:

Memory <------- DMA FIFO <------ UART FIFO <---------------- UART

  DST_TR_WIDTH -+--------|       |         |
                |        |       |         |                No more data
   Current lvl -+--------|       |---------+- DMA-burst lvl
                |        |       |---------+- Leftover data
                |        |       |---------+- SRC_TR_WIDTH
               -+--------+-------+---------+

In the example above: no more data is getting received over the UART port and BLOCK_TS is not even close to be fully received; some data is left in the UART FIFO, but not enough to perform a bursted DMA-xfer to the DMA FIFO; some data is left in the DMA FIFO, but not enough to be passed further to the system memory in a single transfer. In this situation the 8250 UART driver catches the recv timeout interrupt, pauses the DMA-transfer and terminates it completely, after which the IRQ handler manually fetches the leftover data from the UART FIFO into the recv-buffer. But since the DMA-channel has been disabled with the data left in the DMA FIFO, that data will be just discarded and the recv-buffer will have a gap of the "current lvl" size in the recv-buffer at the tail of the lately received data portion. So the data will be lost just due to the misconfigured DMA transfer.

Note this is only relevant for the case of the transfer suspension and _disabling_. No problem will happen if the transfer will be re-enabled afterwards or the block transfer is fully completed. In the later case the "FIFO flush mode" will be executed at the transfer final stage in order to push out the data left in the DMA FIFO.

In order to fix the denoted problem the DW AHB DMA-engine driver needs to make sure that the _bursted_ source transfer width is greater or equal to the single destination transfer (note the HW databook describes more strict constraint than actually required). Since the peripheral-device side is prescribed by the client driver logic, the memory-side can be only used for that. The solution can be easily implemented for the DEV_TO_MEM transfers just by adjusting the memory-channel address width. Sadly it's not that easy for the MEM_TO_DEV transfers since the mem-to-dma burst size is normally dynamically determined by the controller. So the only thing that can be done is to make sure that memory-side address width can be greater than the peripheral device address width.

...

Quoted 16 lines

drivers/dma/dw/core.c +16 -0

+static int dwc_verify_m_buswidth(struct dma_chan *chan)
+{
+	struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
+	struct dw_dma *dw = to_dw_dma(chan->device);
+	u32 reg_width, reg_burst, mem_width;
+
+	mem_width = dw->pdata->data_width[dwc->dws.m_master];
+
+	/* Make sure src and dst word widths are coherent */
+	if (dwc->dma_sconfig.direction == DMA_MEM_TO_DEV) {
+		reg_width = dwc->dma_sconfig.dst_addr_width;
+		if (mem_width < reg_width)
+			return -EINVAL;
+
+		dwc->dma_sconfig.src_addr_width = mem_width;
+	} else if (dwc->dma_sconfig.direction == DMA_DEV_TO_MEM) {

drivers/dma/dw/core.c static int dwc_verify_p_buswidth(struct dma_chan *chan) · line 833

Quoted 4 lines

drivers/dma/dw/core.c +4 -0

+		reg_width = dwc->dma_sconfig.src_addr_width;
+		reg_burst = rounddown_pow_of_two(dwc->dma_sconfig.src_maxburst);
+
+		dwc->dma_sconfig.dst_addr_width = min(mem_width, reg_width * reg_burst);

I understand the desire to go this way, but wouldn't be better to have a symmetrical check and return an error?

drivers/dma/dw/core.c static int dwc_verify_p_buswidth(struct dma_chan *chan) · line 837

Quoted 5 lines

drivers/dma/dw/core.c +4 -0

+	}
+
+	return 0;
+}

IIRC MEM side of the DMA channel will ignore those in HW, so basically you are (re-)using them purely for the __ffs() corrections.

...

Quoted 6 lines

drivers/dma/dw/core.c +2 -2

 	dwc->dma_sconfig.src_maxburst =
-		clamp(dwc->dma_sconfig.src_maxburst, 0U, dwc->max_burst);
+		clamp(dwc->dma_sconfig.src_maxburst, 1U, dwc->max_burst);
 	dwc->dma_sconfig.dst_maxburst =
-		clamp(dwc->dma_sconfig.dst_maxburst, 0U, dwc->max_burst);
+		clamp(dwc->dma_sconfig.dst_maxburst, 1U, dwc->max_burst);

Signature · 2 lines

With Best Regards,
Andy Shevchenko

Quoted 65 lines · Andy Shevchenko

Quoted 64 lines · Serge Semin

Currently in case of the DEV_TO_MEM or MEM_TO_DEV DMA transfers the memory data width (single transfer width) is determined based on the buffer length, buffer base address or DMA master-channel max address width capability. It isn't enough in case of the channel disabling prior the block transfer is finished. Here is what DW AHB DMA IP-core databook says regarding the port suspension (DMA-transfer pause) implementation in the controller:

"When CTLx.SRC_TR_WIDTH < CTLx.DST_TR_WIDTH and the CFGx.CH_SUSP bit is high, the CFGx.FIFO_EMPTY is asserted once the contents of the FIFO do not permit a single word of CTLx.DST_TR_WIDTH to be formed. However, there may still be data in the channel FIFO, but not enough to form a single transfer of CTLx.DST_TR_WIDTH. In this scenario, once the channel is disabled, the remaining data in the channel FIFO is not transferred to the destination peripheral."

So in case if the port gets to be suspended and then disabled it's possible to have the data silently discarded even though the controller reported that FIFO is empty and the CTLx.BLOCK_TS indicated the dropped data already received from the source device. This looks as if the data somehow got lost on a way from the peripheral device to memory and causes problems for instance in the DW APB UART driver, which pauses and disables the DMA-transfer as soon as the recv data timeout happens. Here is the way it looks:

Memory <------- DMA FIFO <------ UART FIFO <---------------- UART

  DST_TR_WIDTH -+--------|       |         |
                |        |       |         |                No more data
   Current lvl -+--------|       |---------+- DMA-burst lvl
                |        |       |---------+- Leftover data
                |        |       |---------+- SRC_TR_WIDTH
               -+--------+-------+---------+

In the example above: no more data is getting received over the UART port and BLOCK_TS is not even close to be fully received; some data is left in the UART FIFO, but not enough to perform a bursted DMA-xfer to the DMA FIFO; some data is left in the DMA FIFO, but not enough to be passed further to the system memory in a single transfer. In this situation the 8250 UART driver catches the recv timeout interrupt, pauses the DMA-transfer and terminates it completely, after which the IRQ handler manually fetches the leftover data from the UART FIFO into the recv-buffer. But since the DMA-channel has been disabled with the data left in the DMA FIFO, that data will be just discarded and the recv-buffer will have a gap of the "current lvl" size in the recv-buffer at the tail of the lately received data portion. So the data will be lost just due to the misconfigured DMA transfer.

Note this is only relevant for the case of the transfer suspension and _disabling_. No problem will happen if the transfer will be re-enabled afterwards or the block transfer is fully completed. In the later case the "FIFO flush mode" will be executed at the transfer final stage in order to push out the data left in the DMA FIFO.

In order to fix the denoted problem the DW AHB DMA-engine driver needs to make sure that the _bursted_ source transfer width is greater or equal to the single destination transfer (note the HW databook describes more strict constraint than actually required). Since the peripheral-device side is prescribed by the client driver logic, the memory-side can be only used for that. The solution can be easily implemented for the DEV_TO_MEM transfers just by adjusting the memory-channel address width. Sadly it's not that easy for the MEM_TO_DEV transfers since the mem-to-dma burst size is normally dynamically determined by the controller. So the only thing that can be done is to make sure that memory-side address width can be greater than the peripheral device address width.

Quoted 16 lines

Quoted 16 lines

drivers/dma/dw/core.c +16 -0

+static int dwc_verify_m_buswidth(struct dma_chan *chan)
+{
+	struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
+	struct dw_dma *dw = to_dw_dma(chan->device);
+	u32 reg_width, reg_burst, mem_width;
+
+	mem_width = dw->pdata->data_width[dwc->dws.m_master];
+
+	/* Make sure src and dst word widths are coherent */
+	if (dwc->dma_sconfig.direction == DMA_MEM_TO_DEV) {
+		reg_width = dwc->dma_sconfig.dst_addr_width;
+		if (mem_width < reg_width)
+			return -EINVAL;
+
+		dwc->dma_sconfig.src_addr_width = mem_width;
+	} else if (dwc->dma_sconfig.direction == DMA_DEV_TO_MEM) {

Quoted 8 lines

drivers/dma/dw/core.c static int dwc_verify_p_buswidth(struct dma_chan *chan) · line 833

Quoted 4 lines

drivers/dma/dw/core.c +4 -0

+		reg_width = dwc->dma_sconfig.src_addr_width;
+		reg_burst = rounddown_pow_of_two(dwc->dma_sconfig.src_maxburst);
+
+		dwc->dma_sconfig.dst_addr_width = min(mem_width, reg_width * reg_burst);

I understand the desire to go this way, but wouldn't be better to have a symmetrical check and return an error?

Sadly the situation isn't symmetrical.

The main idea of the solution proposed in this patch is to make sure that the DMA transactions would fill in the DMA FIFO in a way so in case of the suspension all the data would be delivered to the destination with nothing left in the DMA FIFO and the CFGx.FIFO_EMPTY flag would mean the real FIFO emptiness. It can be reached only if (CTLx.SRC_TR_WIDTH * CTLx.SRC_MSIZE) >= CTLx.DST_TR_WIDTH (calculated in the real values of course). But CTLx.SRC_MSIZE is only relevant for the flow-control/non-memory peripherals. Thus the

conditions under which the problem can be avoided are:

DMA_MEM_TO_DEV: CTLx.SRC_TR_WIDTH >= CTLx.DST_TR_WIDTH
DMA_DEV_TO_MEM: CTLx.SRC_TR_WIDTH * CTLx.SRC_MSIZE >= CTLx.DST_TR_WIDTH

In both cases the non-memory peripheral side parameters (DEV-side) can't be changed because they are selected by the client drivers based on their specific logic (Device FIFO depth, watermarks, CSR widths, etc). But we can vary the memory-side transfer width as long as it's within the permitted limits.

In case of the DMA_MEM_TO_DEV transfers we can change the CTLx.SRC_TR_WIDTH because it represents the memory side transfer width. But if the maximum memory transfer width is smaller than the specified destination register width, there is nothing we can do. Thus returning the EINVAL error. Note this is mainly a hypothetical situation since normally the max width of the memory master xfers is greater than the peripheral master xfer max width (in my case it's 128 and 32 bits respectively).

In case of the DMA_DEV_TO_MEM transfers we can change the CTLx.DST_TR_WIDTH parameter because it's the memory side. Thus if the maximum memory transfer width is smaller than the bursted source transfer, then we can stick to the maximum memory transfer width. But if it's greater than the bursted source transfer, we can freely reduce it so to support the safe suspension+disable DMA-usage pattern.

Quoted 9 lines

drivers/dma/dw/core.c static int dwc_verify_p_buswidth(struct dma_chan *chan) · line 837

Quoted 5 lines

drivers/dma/dw/core.c +4 -0

+	}
+
+	return 0;
+}

IIRC MEM side of the DMA channel will ignore those in HW, so basically you are (re-)using them purely for the __ffs() corrections.

No. DMAC ignores the _burst length_ parameters CTLx.SRC_MSIZE and CTLx.DEST_MSIZE for the memory side (also see my comment above):

"The CTLx.SRC_MSIZE and CTLx.DEST_MSIZE are properties valid only for peripherals with a handshaking interface; they cannot be used for defining the burst length for memory peripherals.

When the peripherals are memory, the DW_ahb_dmac is always the flow controller and uses DMA transfers to move blocks; thus the CTLx.SRC_MSIZE and CTLx.DEST_MSIZE values are not used for memory peripherals. The SRC_MSIZE/DEST_MSIZE limitations are used to accommodate devices that have limited resources, such as a FIFO. Memory does not normally have limitations similar to the FIFOs."

In my case the problem is in the CTLx.SRC_TR_WIDTH and CTLx.DST_TR_WIDTH values misconfiguration. Here is the crucial comment in the HW-manual about that (cited in the commit messages):

"When CTLx.SRC_TR_WIDTH < CTLx.DST_TR_WIDTH and the CFGx.CH_SUSP bit is high, the CFGx.FIFO_EMPTY is asserted once the contents of the FIFO do not permit a single word of CTLx.DST_TR_WIDTH to be formed. However, there may still be data in the channel FIFO, but not enough to form a single transfer of CTLx.DST_TR_WIDTH. In this scenario, once the channel is disabled, the remaining data in the channel FIFO is not transferred to the destination peripheral."

See Chapter 7.7 "Disabling a Channel Prior to Transfer Completion" of the DW DMAC HW manual for more details.

Quoted 6 lines

Quoted 6 lines

drivers/dma/dw/core.c +2 -2

 	dwc->dma_sconfig.src_maxburst =
-		clamp(dwc->dma_sconfig.src_maxburst, 0U, dwc->max_burst);
+		clamp(dwc->dma_sconfig.src_maxburst, 1U, dwc->max_burst);
 	dwc->dma_sconfig.dst_maxburst =
-		clamp(dwc->dma_sconfig.dst_maxburst, 0U, dwc->max_burst);
+		clamp(dwc->dma_sconfig.dst_maxburst, 1U, dwc->max_burst);

Quoted 66 lines · Serge Semin

Quoted 65 lines · Andy Shevchenko

Quoted 64 lines · Serge Semin

Currently in case of the DEV_TO_MEM or MEM_TO_DEV DMA transfers the memory data width (single transfer width) is determined based on the buffer length, buffer base address or DMA master-channel max address width capability. It isn't enough in case of the channel disabling prior the block transfer is finished. Here is what DW AHB DMA IP-core databook says regarding the port suspension (DMA-transfer pause) implementation in the controller:

"When CTLx.SRC_TR_WIDTH < CTLx.DST_TR_WIDTH and the CFGx.CH_SUSP bit is high, the CFGx.FIFO_EMPTY is asserted once the contents of the FIFO do not permit a single word of CTLx.DST_TR_WIDTH to be formed. However, there may still be data in the channel FIFO, but not enough to form a single transfer of CTLx.DST_TR_WIDTH. In this scenario, once the channel is disabled, the remaining data in the channel FIFO is not transferred to the destination peripheral."

So in case if the port gets to be suspended and then disabled it's possible to have the data silently discarded even though the controller reported that FIFO is empty and the CTLx.BLOCK_TS indicated the dropped data already received from the source device. This looks as if the data somehow got lost on a way from the peripheral device to memory and causes problems for instance in the DW APB UART driver, which pauses and disables the DMA-transfer as soon as the recv data timeout happens. Here is the way it looks:

Memory <------- DMA FIFO <------ UART FIFO <---------------- UART

  DST_TR_WIDTH -+--------|       |         |
                |        |       |         |                No more data
   Current lvl -+--------|       |---------+- DMA-burst lvl
                |        |       |---------+- Leftover data
                |        |       |---------+- SRC_TR_WIDTH
               -+--------+-------+---------+

In the example above: no more data is getting received over the UART port and BLOCK_TS is not even close to be fully received; some data is left in the UART FIFO, but not enough to perform a bursted DMA-xfer to the DMA FIFO; some data is left in the DMA FIFO, but not enough to be passed further to the system memory in a single transfer. In this situation the 8250 UART driver catches the recv timeout interrupt, pauses the DMA-transfer and terminates it completely, after which the IRQ handler manually fetches the leftover data from the UART FIFO into the recv-buffer. But since the DMA-channel has been disabled with the data left in the DMA FIFO, that data will be just discarded and the recv-buffer will have a gap of the "current lvl" size in the recv-buffer at the tail of the lately received data portion. So the data will be lost just due to the misconfigured DMA transfer.

Note this is only relevant for the case of the transfer suspension and _disabling_. No problem will happen if the transfer will be re-enabled afterwards or the block transfer is fully completed. In the later case the "FIFO flush mode" will be executed at the transfer final stage in order to push out the data left in the DMA FIFO.

In order to fix the denoted problem the DW AHB DMA-engine driver needs to make sure that the _bursted_ source transfer width is greater or equal to the single destination transfer (note the HW databook describes more strict constraint than actually required). Since the peripheral-device side is prescribed by the client driver logic, the memory-side can be only used for that. The solution can be easily implemented for the DEV_TO_MEM transfers just by adjusting the memory-channel address width. Sadly it's not that easy for the MEM_TO_DEV transfers since the mem-to-dma burst size is normally dynamically determined by the controller. So the only thing that can be done is to make sure that memory-side address width can be greater than the peripheral device address width.

...

Quoted 27 lines

Quoted 16 lines

Quoted 16 lines

drivers/dma/dw/core.c +16 -0

+static int dwc_verify_m_buswidth(struct dma_chan *chan)
+{
+	struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
+	struct dw_dma *dw = to_dw_dma(chan->device);
+	u32 reg_width, reg_burst, mem_width;
+
+	mem_width = dw->pdata->data_width[dwc->dws.m_master];
+
+	/* Make sure src and dst word widths are coherent */
+	if (dwc->dma_sconfig.direction == DMA_MEM_TO_DEV) {
+		reg_width = dwc->dma_sconfig.dst_addr_width;
+		if (mem_width < reg_width)
+			return -EINVAL;
+
+		dwc->dma_sconfig.src_addr_width = mem_width;
+	} else if (dwc->dma_sconfig.direction == DMA_DEV_TO_MEM) {

Quoted 8 lines

drivers/dma/dw/core.c static int dwc_verify_p_buswidth(struct dma_chan *chan) · line 833

Quoted 4 lines

drivers/dma/dw/core.c +4 -0

+		reg_width = dwc->dma_sconfig.src_addr_width;
+		reg_burst = rounddown_pow_of_two(dwc->dma_sconfig.src_maxburst);
+
+		dwc->dma_sconfig.dst_addr_width = min(mem_width, reg_width * reg_burst);

I understand the desire to go this way, but wouldn't be better to have a symmetrical check and return an error?

Sadly the situation isn't symmetrical.

Quoted 8 lines

The main idea of the solution proposed in this patch is to make sure that the DMA transactions would fill in the DMA FIFO in a way so in case of the suspension all the data would be delivered to the destination with nothing left in the DMA FIFO and the CFGx.FIFO_EMPTY flag would mean the real FIFO emptiness. It can be reached only if (CTLx.SRC_TR_WIDTH * CTLx.SRC_MSIZE) >= CTLx.DST_TR_WIDTH (calculated in the real values of course). But CTLx.SRC_MSIZE is only relevant for the flow-control/non-memory peripherals. Thus the

Oh, if it involves flow control, shouldn't you check for that as well? We have a (PPC? IIRC) hardware with this IP that can have peripheral as flow control.

Quoted 64 lines

conditions under which the problem can be avoided are:

DMA_MEM_TO_DEV: CTLx.SRC_TR_WIDTH >= CTLx.DST_TR_WIDTH
DMA_DEV_TO_MEM: CTLx.SRC_TR_WIDTH * CTLx.SRC_MSIZE >= CTLx.DST_TR_WIDTH

In both cases the non-memory peripheral side parameters (DEV-side) can't be changed because they are selected by the client drivers based on their specific logic (Device FIFO depth, watermarks, CSR widths, etc). But we can vary the memory-side transfer width as long as it's within the permitted limits.

In case of the DMA_MEM_TO_DEV transfers we can change the CTLx.SRC_TR_WIDTH because it represents the memory side transfer width. But if the maximum memory transfer width is smaller than the specified destination register width, there is nothing we can do. Thus returning the EINVAL error. Note this is mainly a hypothetical situation since normally the max width of the memory master xfers is greater than the peripheral master xfer max width (in my case it's 128 and 32 bits respectively).

In case of the DMA_DEV_TO_MEM transfers we can change the CTLx.DST_TR_WIDTH parameter because it's the memory side. Thus if the maximum memory transfer width is smaller than the bursted source transfer, then we can stick to the maximum memory transfer width. But if it's greater than the bursted source transfer, we can freely reduce it so to support the safe suspension+disable DMA-usage pattern.

Quoted 9 lines

drivers/dma/dw/core.c static int dwc_verify_p_buswidth(struct dma_chan *chan) · line 837

Quoted 5 lines

drivers/dma/dw/core.c +4 -0

+	}
+
+	return 0;
+}

IIRC MEM side of the DMA channel will ignore those in HW, so basically you are (re-)using them purely for the __ffs() corrections.

No. DMAC ignores the _burst length_ parameters CTLx.SRC_MSIZE and CTLx.DEST_MSIZE for the memory side (also see my comment above):

"The CTLx.SRC_MSIZE and CTLx.DEST_MSIZE are properties valid only for peripherals with a handshaking interface; they cannot be used for defining the burst length for memory peripherals.

When the peripherals are memory, the DW_ahb_dmac is always the flow controller and uses DMA transfers to move blocks; thus the CTLx.SRC_MSIZE and CTLx.DEST_MSIZE values are not used for memory peripherals. The SRC_MSIZE/DEST_MSIZE limitations are used to accommodate devices that have limited resources, such as a FIFO. Memory does not normally have limitations similar to the FIFOs."

In my case the problem is in the CTLx.SRC_TR_WIDTH and CTLx.DST_TR_WIDTH values misconfiguration. Here is the crucial comment in the HW-manual about that (cited in the commit messages):

"When CTLx.SRC_TR_WIDTH < CTLx.DST_TR_WIDTH and the CFGx.CH_SUSP bit is high, the CFGx.FIFO_EMPTY is asserted once the contents of the FIFO do not permit a single word of CTLx.DST_TR_WIDTH to be formed. However, there may still be data in the channel FIFO, but not enough to form a single transfer of CTLx.DST_TR_WIDTH. In this scenario, once the channel is disabled, the remaining data in the channel FIFO is not transferred to the destination peripheral."

Quoted 2 lines

See Chapter 7.7 "Disabling a Channel Prior to Transfer Completion" of the DW DMAC HW manual for more details.

Got it. Maybe a little summary in the code to explain all this magic?

...

Quoted 6 lines

Quoted 6 lines

Quoted 6 lines

drivers/dma/dw/core.c +2 -2

 	dwc->dma_sconfig.src_maxburst =
-		clamp(dwc->dma_sconfig.src_maxburst, 0U, dwc->max_burst);
+		clamp(dwc->dma_sconfig.src_maxburst, 1U, dwc->max_burst);
 	dwc->dma_sconfig.dst_maxburst =
-		clamp(dwc->dma_sconfig.dst_maxburst, 0U, dwc->max_burst);
+		clamp(dwc->dma_sconfig.dst_maxburst, 1U, dwc->max_burst);

Signature · 2 lines

With Best Regards,
Andy Shevchenko

Quoted 1 line · Andy Shevchenko

On Wed, Apr 17, 2024 at 08:13:59PM +0300, Serge Semin wrote:

Quoted 1 line

Got it. Maybe a little summary in the code to explain all this magic?

Will it be enough to add something like this:
/*
* It's possible to have a data portion locked in the DMA FIFO in case
* of the channel suspension. Subsequent channel disabling will cause
* that data silent loss. In order to prevent that maintain the src
* and dst transfer widths coherency by means of the relation:
* (CTLx.SRC_TR_WIDTH * CTLx.SRC_MSIZE >= CTLx.DST_TR_WIDTH) */

Quoted 2 lines · Serge Semin

Quoted 1 line · Andy Shevchenko

On Wed, Apr 17, 2024 at 08:13:59PM +0300, Serge Semin wrote:

...

Quoted 10 lines

Quoted 1 line

Got it. Maybe a little summary in the code to explain all this magic?

Will it be enough to add something like this:
/*
* It's possible to have a data portion locked in the DMA FIFO in case
* of the channel suspension. Subsequent channel disabling will cause
* that data silent loss. In order to prevent that maintain the src
* and dst transfer widths coherency by means of the relation:
* (CTLx.SRC_TR_WIDTH * CTLx.SRC_MSIZE >= CTLx.DST_TR_WIDTH) */

Yes, and you may add something like
"Look for the details in the commit message that brings this change." at the end of it.

Signature · 3 lines

-- 
With Best Regards,
Andy Shevchenko

Currently the CTL LO fields are calculated on the platform-specific basis. It's implemented by means of the prepare_ctllo() callbacks using the ternary operator within the local variables init block at the beginning of the block scope. The functions code currently is relatively hard to comprehend and isn't that optimal since implies four conditional statements executed and two additional local variables defined. Let's simplify the DW AHB DMA prepare_ctllo() method by unrolling the ternary operators into the normal if-else statement, dropping redundant master-interface ID variables and initializing the local variables based on the singly evaluated DMA-transfer direction check. Thus the method will look much more readable since now the fields content can be easily inferred right from the if-else branch. Provide the same update in the Intel DMA32 core driver for sake of the driver code unification.

Note besides of the effects described above this update is basically a preparation before dropping the max burst encoding callback. It will require calling the burst fields calculation methods right in the prepare_ctllo() callbacks, which would have made the later function code even more complex.

static u32 idma32_prepare_ctllo(struct dw_dma_chan *dwc) {

drivers/dma/dw/idma32.c +2 -2

 	struct dma_slave_config	*sconfig = &dwc->dma_sconfig;
-	u8 smsize = (dwc->direction == DMA_DEV_TO_MEM) ? sconfig->src_maxburst : 0;
-	u8 dmsize = (dwc->direction == DMA_MEM_TO_DEV) ? sconfig->dst_maxburst : 0;
+	u8 smsize, dmsize;
+

Quoted 14 lines · Serge Semin

Currently the CTL LO fields are calculated on the platform-specific basis. It's implemented by means of the prepare_ctllo() callbacks using the ternary operator within the local variables init block at the beginning of the block scope. The functions code currently is relatively hard to comprehend and isn't that optimal since implies four conditional statements executed and two additional local variables defined. Let's simplify the DW AHB DMA prepare_ctllo() method by unrolling the ternary operators into the normal if-else statement, dropping redundant master-interface ID variables and initializing the local variables based on the singly evaluated DMA-transfer direction check. Thus the method will look much more readable since now the fields content can be easily inferred right from the if-else branch. Provide the same update in the Intel DMA32 core driver for sake of the driver code unification.

Quoted 5 lines

Note besides of the effects described above this update is basically a preparation before dropping the max burst encoding callback. It will require calling the burst fields calculation methods right in the prepare_ctllo() callbacks, which would have made the later function code even more complex.

Yeah, this is inherited from the original driver where it used to be a macro.

...

drivers/dma/dw/dw.c static size_t dw_dma_block2bytes(struct dw_dma_chan *dwc, u32 block, u32 width) · line 76

Quoted 5 lines

drivers/dma/dw/dw.c +5 -0

+	if (dwc->direction == DMA_MEM_TO_DEV) {
+		sms = dwc->dws.m_master;
+		smsize = 0;
+		dms = dwc->dws.p_master;
+		dmsize = sconfig->dst_maxburst;

I would group it differently, i.e.

		sms = dwc->dws.m_master;
		dms = dwc->dws.p_master;
		smsize = 0;
		dmsize = sconfig->dst_maxburst;

drivers/dma/dw/dw.c static size_t dw_dma_block2bytes(struct dw_dma_chan *dwc, u32 block, u32 width) · line 87

Quoted 12 lines

drivers/dma/dw/dw.c +11 -0

+	} else if (dwc->direction == DMA_DEV_TO_MEM) {
+		sms = dwc->dws.p_master;
+		smsize = sconfig->src_maxburst;
+		dms = dwc->dws.m_master;
+		dmsize = 0;
+	} else /* DMA_MEM_TO_MEM */ {
+		sms = dwc->dws.m_master;
+		smsize = 0;
+		dms = dwc->dws.m_master;
+		dmsize = 0;
+	}

Ditto for two above cases.

Quoted 8 lines

static u32 idma32_prepare_ctllo(struct dw_dma_chan *dwc) {

drivers/dma/dw/idma32.c +2 -2

 	struct dma_slave_config	*sconfig = &dwc->dma_sconfig;
-	u8 smsize = (dwc->direction == DMA_DEV_TO_MEM) ? sconfig->src_maxburst : 0;
-	u8 dmsize = (dwc->direction == DMA_MEM_TO_DEV) ? sconfig->dst_maxburst : 0;
 
+	u8 smsize, dmsize;
+

drivers/dma/dw/idma32.c static size_t idma32_block2bytes(struct dw_dma_chan *dwc, u32 block, u32 width) · line 216

Quoted 10 lines

drivers/dma/dw/idma32.c +10 -0

+	if (dwc->direction == DMA_MEM_TO_DEV) {
+		smsize = 0;
+		dmsize = sconfig->dst_maxburst;
+	} else if (dwc->direction == DMA_DEV_TO_MEM) {
+		smsize = sconfig->src_maxburst;
+		dmsize = 0;
+	} else /* DMA_MEM_TO_MEM */ {
+		smsize = 0;
+		dmsize = 0;
+	}

	u8 smsize = 0, dmsize = 0;

	if (dwc->direction == DMA_MEM_TO_DEV)
		dmsize = sconfig->dst_maxburst;
	else if (dwc->direction == DMA_DEV_TO_MEM)
		smsize = sconfig->src_maxburst;

?

Something similar also can be done in the Synopsys case above, no?

Signature · 3 lines

-- 
With Best Regards,
Andy Shevchenko

Quoted 1 line · Andy Shevchenko

On Tue, Apr 16, 2024 at 07:28:57PM +0300, Serge Semin wrote:

Quoted 9 lines

drivers/dma/dw/dw.c static size_t dw_dma_block2bytes(struct dw_dma_chan *dwc, u32 block, u32 width) · line 76

Quoted 5 lines

drivers/dma/dw/dw.c +5 -0

+	if (dwc->direction == DMA_MEM_TO_DEV) {
+		sms = dwc->dws.m_master;
+		smsize = 0;
+		dms = dwc->dws.p_master;
+		dmsize = sconfig->dst_maxburst;

I would group it differently, i.e.

Quoted 4 lines

		sms = dwc->dws.m_master;
		dms = dwc->dws.p_master;
		smsize = 0;
		dmsize = sconfig->dst_maxburst;

Could you please clarify, why? From my point of view it was better to group the source master ID and the source master burst size inits together.

Quoted 13 lines

drivers/dma/dw/dw.c static size_t dw_dma_block2bytes(struct dw_dma_chan *dwc, u32 block, u32 width) · line 87

Quoted 11 lines

drivers/dma/dw/dw.c +11 -0

+	} else if (dwc->direction == DMA_DEV_TO_MEM) {
+		sms = dwc->dws.p_master;
+		smsize = sconfig->src_maxburst;
+		dms = dwc->dws.m_master;
+		dmsize = 0;
+	} else /* DMA_MEM_TO_MEM */ {
+		sms = dwc->dws.m_master;
+		smsize = 0;
+		dms = dwc->dws.m_master;
+		dmsize = 0;
+	}

Ditto for two above cases.

Quoted 26 lines

Quoted 8 lines

static u32 idma32_prepare_ctllo(struct dw_dma_chan *dwc) {

drivers/dma/dw/idma32.c +2 -2

 	struct dma_slave_config	*sconfig = &dwc->dma_sconfig;
-	u8 smsize = (dwc->direction == DMA_DEV_TO_MEM) ? sconfig->src_maxburst : 0;
-	u8 dmsize = (dwc->direction == DMA_MEM_TO_DEV) ? sconfig->dst_maxburst : 0;
 
+	u8 smsize, dmsize;
+

drivers/dma/dw/idma32.c static size_t idma32_block2bytes(struct dw_dma_chan *dwc, u32 block, u32 width) · line 216

Quoted 10 lines

drivers/dma/dw/idma32.c +10 -0

+	if (dwc->direction == DMA_MEM_TO_DEV) {
+		smsize = 0;
+		dmsize = sconfig->dst_maxburst;
+	} else if (dwc->direction == DMA_DEV_TO_MEM) {
+		smsize = sconfig->src_maxburst;
+		dmsize = 0;
+	} else /* DMA_MEM_TO_MEM */ {
+		smsize = 0;
+		dmsize = 0;
+	}

	u8 smsize = 0, dmsize = 0;

	if (dwc->direction == DMA_MEM_TO_DEV)
		dmsize = sconfig->dst_maxburst;
	else if (dwc->direction == DMA_DEV_TO_MEM)
		smsize = sconfig->src_maxburst;

Quoted 3 lines

?

Something similar also can be done in the Synopsys case above, no?

As in case of the patch #1 the if-else statement here was designed like that intentionally: to signify that the else clause implies the DMA_MEM_TO_MEM transfer. Any other one (like DMA_DEV_TO_DEV) would need to have the statement alteration.

Moreover even though your
version looks smaller, but it causes one redundant store operation.

Do you think it still would be better to use your version despite of my reasoning?

Quoted 2 lines · Serge Semin

Quoted 1 line · Andy Shevchenko

On Tue, Apr 16, 2024 at 07:28:57PM +0300, Serge Semin wrote:

...

Quoted 9 lines

Quoted 9 lines

drivers/dma/dw/dw.c static size_t dw_dma_block2bytes(struct dw_dma_chan *dwc, u32 block, u32 width) · line 76

Quoted 5 lines

drivers/dma/dw/dw.c +5 -0

+	if (dwc->direction == DMA_MEM_TO_DEV) {
+		sms = dwc->dws.m_master;
+		smsize = 0;
+		dms = dwc->dws.p_master;
+		dmsize = sconfig->dst_maxburst;

I would group it differently, i.e.

Quoted 8 lines

Quoted 4 lines

		sms = dwc->dws.m_master;
		dms = dwc->dws.p_master;
		smsize = 0;
		dmsize = sconfig->dst_maxburst;

Could you please clarify, why? From my point of view it was better to group the source master ID and the source master burst size inits together.

Sure. The point here is that when you look at the DMA channel configuration usually you operate with the semantically tied fields for source and destination. At least this is my experience, I always check both sides of the transfer for the same field, e.g., master setting, hence I want to have them coupled.

Quoted 14 lines

Quoted 14 lines

drivers/dma/dw/dw.c static size_t dw_dma_block2bytes(struct dw_dma_chan *dwc, u32 block, u32 width) · line 87

Quoted 12 lines

drivers/dma/dw/dw.c +11 -0

+	} else if (dwc->direction == DMA_DEV_TO_MEM) {
+		sms = dwc->dws.p_master;
+		smsize = sconfig->src_maxburst;
+		dms = dwc->dws.m_master;
+		dmsize = 0;
+	} else /* DMA_MEM_TO_MEM */ {
+		sms = dwc->dws.m_master;
+		smsize = 0;
+		dms = dwc->dws.m_master;
+		dmsize = 0;
+	}

Ditto for two above cases.

...

Quoted 26 lines

Quoted 26 lines

Quoted 8 lines

static u32 idma32_prepare_ctllo(struct dw_dma_chan *dwc) {

drivers/dma/dw/idma32.c +2 -2

 	struct dma_slave_config	*sconfig = &dwc->dma_sconfig;
-	u8 smsize = (dwc->direction == DMA_DEV_TO_MEM) ? sconfig->src_maxburst : 0;
-	u8 dmsize = (dwc->direction == DMA_MEM_TO_DEV) ? sconfig->dst_maxburst : 0;
 
+	u8 smsize, dmsize;
+

drivers/dma/dw/idma32.c static size_t idma32_block2bytes(struct dw_dma_chan *dwc, u32 block, u32 width) · line 216

Quoted 10 lines

drivers/dma/dw/idma32.c +10 -0

+	if (dwc->direction == DMA_MEM_TO_DEV) {
+		smsize = 0;
+		dmsize = sconfig->dst_maxburst;
+	} else if (dwc->direction == DMA_DEV_TO_MEM) {
+		smsize = sconfig->src_maxburst;
+		dmsize = 0;
+	} else /* DMA_MEM_TO_MEM */ {
+		smsize = 0;
+		dmsize = 0;
+	}

	u8 smsize = 0, dmsize = 0;

	if (dwc->direction == DMA_MEM_TO_DEV)
		dmsize = sconfig->dst_maxburst;
	else if (dwc->direction == DMA_DEV_TO_MEM)
		smsize = sconfig->src_maxburst;

Quoted 8 lines

Quoted 3 lines

?

Something similar also can be done in the Synopsys case above, no?

As in case of the patch #1 the if-else statement here was designed like that intentionally: to signify that the else clause implies the DMA_MEM_TO_MEM transfer. Any other one (like DMA_DEV_TO_DEV) would need to have the statement alteration.

My version as I read it:
- for M2D the dmsize is important
- for D2M the smsize is important
- for anything else use defaults (which are 0)

Quoted 2 lines

Moreover even though your
version looks smaller, but it causes one redundant store operation.

Most likely not. Any assembler here? I can check on x86_64, but I believe it simply assigns 0 for both u8 at once using xor r16,r16 or so.

Maybe ARM or MIPS (what do you use?) sucks? :-)

Quoted 3 lines

Do you think it still would be better to use your version despite of my reasoning?

Signature · 2 lines

With Best Regards,
Andy Shevchenko

Quoted 3 lines · Andy Shevchenko

Quoted 2 lines · Serge Semin

Quoted 1 line · Andy Shevchenko

On Tue, Apr 16, 2024 at 07:28:57PM +0300, Serge Semin wrote:

Quoted 17 lines

Quoted 8 lines

Quoted 8 lines

drivers/dma/dw/dw.c static size_t dw_dma_block2bytes(struct dw_dma_chan *dwc, u32 block, u32 width) · line 76

Quoted 5 lines

drivers/dma/dw/dw.c +5 -0

+	if (dwc->direction == DMA_MEM_TO_DEV) {
+		sms = dwc->dws.m_master;
+		smsize = 0;
+		dms = dwc->dws.p_master;
+		dmsize = sconfig->dst_maxburst;

I would group it differently, i.e.

Quoted 8 lines

Quoted 4 lines

		sms = dwc->dws.m_master;
		dms = dwc->dws.p_master;
		smsize = 0;
		dmsize = sconfig->dst_maxburst;

Could you please clarify, why? From my point of view it was better to group the source master ID and the source master burst size inits together.

Quoted 5 lines

Sure. The point here is that when you look at the DMA channel configuration usually you operate with the semantically tied fields for source and destination. At least this is my experience, I always check both sides of the transfer for the same field, e.g., master setting, hence I want to have them coupled.

Ok. I see. Thanks for clarification. I normally do that in another
order: group the functionally related fields together - all source-related configs first, then all destination-related configs. Honestly I don't have strong opinion about this part, it's just my personal preference. Am I right to think that from your experience in kernel it's normally done in the order you described?

Quoted 13 lines

Quoted 13 lines

Quoted 13 lines

drivers/dma/dw/dw.c static size_t dw_dma_block2bytes(struct dw_dma_chan *dwc, u32 block, u32 width) · line 87

Quoted 11 lines

drivers/dma/dw/dw.c +11 -0

+	} else if (dwc->direction == DMA_DEV_TO_MEM) {
+		sms = dwc->dws.p_master;
+		smsize = sconfig->src_maxburst;
+		dms = dwc->dws.m_master;
+		dmsize = 0;
+	} else /* DMA_MEM_TO_MEM */ {
+		sms = dwc->dws.m_master;
+		smsize = 0;
+		dms = dwc->dws.m_master;
+		dmsize = 0;
+	}

Ditto for two above cases.

Quoted 4 lines · Serge Semin

Quoted 3 lines · Andy Shevchenko

Quoted 2 lines · Serge Semin

Quoted 1 line · Andy Shevchenko

On Tue, Apr 16, 2024 at 07:28:57PM +0300, Serge Semin wrote:

...

Quoted 23 lines

Quoted 17 lines

Quoted 8 lines

Quoted 8 lines

drivers/dma/dw/dw.c static size_t dw_dma_block2bytes(struct dw_dma_chan *dwc, u32 block, u32 width) · line 76

Quoted 5 lines

drivers/dma/dw/dw.c +5 -0

+	if (dwc->direction == DMA_MEM_TO_DEV) {
+		sms = dwc->dws.m_master;
+		smsize = 0;
+		dms = dwc->dws.p_master;
+		dmsize = sconfig->dst_maxburst;

I would group it differently, i.e.

Quoted 8 lines

Quoted 4 lines

		sms = dwc->dws.m_master;
		dms = dwc->dws.p_master;
		smsize = 0;
		dmsize = sconfig->dst_maxburst;

Could you please clarify, why? From my point of view it was better to group the source master ID and the source master burst size inits together.

Quoted 5 lines

Sure. The point here is that when you look at the DMA channel configuration usually you operate with the semantically tied fields for source and destination. At least this is my experience, I always check both sides of the transfer for the same field, e.g., master setting, hence I want to have them coupled.

Quoted 6 lines

Ok. I see. Thanks for clarification. I normally do that in another
order: group the functionally related fields together - all source-related configs first, then all destination-related configs. Honestly I don't have strong opinion about this part, it's just my personal preference. Am I right to think that from your experience in kernel it's normally done in the order you described?

In this driver I believe I have followed that one, yes.

Quoted 14 lines

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drivers/dma/dw/dw.c static size_t dw_dma_block2bytes(struct dw_dma_chan *dwc, u32 block, u32 width) · line 87

Quoted 12 lines

drivers/dma/dw/dw.c +11 -0

+	} else if (dwc->direction == DMA_DEV_TO_MEM) {
+		sms = dwc->dws.p_master;
+		smsize = sconfig->src_maxburst;
+		dms = dwc->dws.m_master;
+		dmsize = 0;
+	} else /* DMA_MEM_TO_MEM */ {
+		sms = dwc->dws.m_master;
+		smsize = 0;
+		dms = dwc->dws.m_master;
+		dmsize = 0;
+	}

Ditto for two above cases.

Signature · 2 lines

With Best Regards,
Andy Shevchenko

In order to have a more coherent DW AHB DMA slave configuration method let's simplify the source and destination channel max-burst calculation procedure:

1. Create the max-burst verification method as it has been just done for the memory and peripheral address widths. Thus the DWC DMA slave config

method will turn to a set of the verification methods execution.

2. Since both the generic DW AHB DMA and Intel DMA32 engines support the

power-of-2 bursts only, then the specified by the client driver max-burst values can be converted to being power-of-2 right in the max-burst verification method.

3. Since max-burst encoded value is required on the CTL_LO fields calculation stage, the encode_maxburst() callback can be easily dropped from the dw_dma structure meanwhile the encoding procedure will be executed right in the CTL_LO register value calculation.

Thus the update will provide the next positive effects: the internal DMA-slave config structure will contain only the real DMA-transfer config value, which will be encoded to the DMA-controller register fields only when it's required on the buffer mapping; the redundant encode_maxburst() callback will be dropped simplifying the internal HW-abstraction API; DWC-config method will look more readable executing the verification

functions one-by-one.

+static void dwc_verify_maxburst(struct dma_chan *chan)

drivers/dma/dw/core.c +13 -0

+{
+	struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
+
+	dwc->dma_sconfig.src_maxburst =
+		clamp(dwc->dma_sconfig.src_maxburst, 1U, dwc->max_burst);
+	dwc->dma_sconfig.dst_maxburst =
+		clamp(dwc->dma_sconfig.dst_maxburst, 1U, dwc->max_burst);
+
+	dwc->dma_sconfig.src_maxburst =
+		rounddown_pow_of_two(dwc->dma_sconfig.src_maxburst);
+	dwc->dma_sconfig.dst_maxburst =
+		rounddown_pow_of_two(dwc->dma_sconfig.dst_maxburst);
+}

Quoted 4 lines · Serge Semin

In order to have a more coherent DW AHB DMA slave configuration method let's simplify the source and destination channel max-burst calculation procedure:

Quoted 2 lines

1. Create the max-burst verification method as it has been just done for the memory and peripheral address widths. Thus the DWC DMA slave config

dwc_config() method

?

Quoted 4 lines

method will turn to a set of the verification methods execution.

2. Since both the generic DW AHB DMA and Intel DMA32 engines support the

"i" in iDMA 32-bit stands for "integrated", so 'Intel iDMA 32-bit'

Quoted 10 lines

power-of-2 bursts only, then the specified by the client driver max-burst values can be converted to being power-of-2 right in the max-burst verification method.

3. Since max-burst encoded value is required on the CTL_LO fields calculation stage, the encode_maxburst() callback can be easily dropped from the dw_dma structure meanwhile the encoding procedure will be executed right in the CTL_LO register value calculation.

Quoted 6 lines

Thus the update will provide the next positive effects: the internal DMA-slave config structure will contain only the real DMA-transfer config value, which will be encoded to the DMA-controller register fields only when it's required on the buffer mapping; the redundant encode_maxburst() callback will be dropped simplifying the internal HW-abstraction API; DWC-config method will look more readable executing the verification

dwc_config() method

?

Quoted 2 lines

functions one-by-one.

...

Quoted 1 line

+static void dwc_verify_maxburst(struct dma_chan *chan)

It's inconsistent to the rest of _verify methods. It doesn't verify as it doesn't return anything. Make it int or rename the function.

Quoted 14 lines

drivers/dma/dw/core.c +13 -0

+{
+	struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
+
+	dwc->dma_sconfig.src_maxburst =
+		clamp(dwc->dma_sconfig.src_maxburst, 1U, dwc->max_burst);
+	dwc->dma_sconfig.dst_maxburst =
+		clamp(dwc->dma_sconfig.dst_maxburst, 1U, dwc->max_burst);
+
+	dwc->dma_sconfig.src_maxburst =
+		rounddown_pow_of_two(dwc->dma_sconfig.src_maxburst);
+	dwc->dma_sconfig.dst_maxburst =
+		rounddown_pow_of_two(dwc->dma_sconfig.dst_maxburst);
+}

...

drivers/dma/dw/core.c static int dwc_verify_m_buswidth(struct dma_chan *chan) · line 846

Quoted 3 lines

static int dwc_verify_p_buswidth(struct dma_chan *chan)

drivers/dma/dw/core.c +1 -1

-		reg_burst = rounddown_pow_of_two(dwc->dma_sconfig.src_maxburst);
+		reg_burst = dwc->dma_sconfig.src_maxburst;

Seems you have a dependency, need a comment below that maxburst has to be "verified" [whatever] first.

...

drivers/dma/dw/dw.c static size_t dw_dma_block2bytes(struct dw_dma_chan *dwc, u32 block, u32 width) · line 74

Quoted 8 lines

drivers/dma/dw/dw.c +8 -0

+static inline u8 dw_dma_encode_maxburst(u32 maxburst)
+{
+	/*
+	 * Fix burst size according to dw_dmac. We need to convert them as:
+	 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
+	 */
+	return maxburst > 1 ? fls(maxburst) - 2 : 0;
+}

Split these moves to another preparatory patch.

Signature · 3 lines

-- 
With Best Regards,
Andy Shevchenko

Quoted 1 line · Andy Shevchenko

On Tue, Apr 16, 2024 at 07:28:58PM +0300, Serge Semin wrote:

Quoted 4 lines

Quoted 1 line

+static void dwc_verify_maxburst(struct dma_chan *chan)

It's inconsistent to the rest of _verify methods. It doesn't verify as it doesn't return anything. Make it int or rename the function.

Making it int won't make much sense since currently the method doesn't imply returning an error status. IMO using "verify" was ok, but since you don't see it suitable please suggest a better alternative. mend, fix, align?

Quoted 2 lines · Serge Semin

Quoted 1 line · Andy Shevchenko

On Tue, Apr 16, 2024 at 07:28:58PM +0300, Serge Semin wrote:

...

Quoted 5 lines

Quoted 4 lines

Quoted 1 line

+static void dwc_verify_maxburst(struct dma_chan *chan)

It's inconsistent to the rest of _verify methods. It doesn't verify as it doesn't return anything. Make it int or rename the function.

Quoted 4 lines

Making it int won't make much sense since currently the method doesn't imply returning an error status. IMO using "verify" was ok, but since you don't see it suitable please suggest a better alternative. mend, fix, align?

My suggestion is (and was) to have it return 0 for now.

Signature · 3 lines

-- 
With Best Regards,
Andy Shevchenko

The main goal of this series is to fix the data disappearance in case of the DW UART handled by the DW AHB DMA engine. The problem happens on a portion of the data received when the pre-initialized DEV_TO_MEM DMA-transfer is paused and then disabled. The data just hangs up in the DMA-engine FIFO and isn't flushed out to the memory on the DMA-channel suspension (see the second commit log for details). On a way to find the denoted problem fix it was discovered that the driver doesn't verify the peripheral device address width specified by a client driver, which in its turn if unsupported or undefined value passed may cause DMA-transfer being misconfigured. It's fixed in the first patch of the series.

In addition to that two cleanup patch follow the fixes described above in order to make the DWC-engine configuration procedure more coherent. First one simplifies the CTL_LO register setup methods. Second one simplifies the max-burst calculation procedure and unifies it with the rest of the verification methods. Please see the patches log for more details.

Quoted 11 lines · Serge Semin

The main goal of this series is to fix the data disappearance in case of the DW UART handled by the DW AHB DMA engine. The problem happens on a portion of the data received when the pre-initialized DEV_TO_MEM DMA-transfer is paused and then disabled. The data just hangs up in the DMA-engine FIFO and isn't flushed out to the memory on the DMA-channel suspension (see the second commit log for details). On a way to find the denoted problem fix it was discovered that the driver doesn't verify the peripheral device address width specified by a client driver, which in its turn if unsupported or undefined value passed may cause DMA-transfer being misconfigured. It's fixed in the first patch of the series.

Quoted 5 lines

In addition to that two cleanup patch follow the fixes described above in order to make the DWC-engine configuration procedure more coherent. First one simplifies the CTL_LO register setup methods. Second one simplifies the max-burst calculation procedure and unifies it with the rest of the verification methods. Please see the patches log for more details.

Thank you for this.

I have looked into all of them and most worrying (relatively to the rest) to me is the second patch that does some tricks.

The rest are the cosmetics that can
be easily addressed.

Signature · 3 lines

-- 
With Best Regards,
Andy Shevchenko