tools headers arm64: Sync arm64's cputype.h with the kernel sources

To get the changes in:

0ce85db6c2141b7f ("arm64: cputype: Add Neoverse-V3 definitions") 02a0a04676fa7796 ("arm64: cputype: Add Cortex-X4 definitions") f4d9d9dcc70b96b5 ("arm64: Add Neoverse-V2 part")

That makes this perf source code to be rebuilt:

CC /tmp/build/perf-tools/util/arm-spe.o

The changes in the above patch add MIDR_NEOVERSE_V[23] and MIDR_NEOVERSE_V1 is used in arm-spe.c, so probably we need to add those and perhaps MIDR_CORTEX_X4 to that array? Or maybe we need to leave this for later when this is all tested on those machines?

  static const struct midr_range neoverse_spe[] = {
          MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),
          MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
          MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),
          {},
  };

That addresses this perf build warning:

Warning: Kernel ABI header differences:
diff -u tools/arch/arm64/include/asm/cputype.h arch/arm64/include/asm/cputype.h

Cc Adrian Hunter <[email protected]>

Cc Besar Wicaksono <[email protected]>

Cc Ian Rogers <[email protected]>

Cc Jiri Olsa <[email protected]>

Cc Kan Liang <[email protected]>

Cc Mark Rutland <[email protected]>

Cc Namhyung Kim <[email protected]>

Cc Will Deacon <[email protected]>

Link https://lore.kernel.org/lkml/

Signed-off-by Arnaldo Carvalho de Melo <[email protected]>

---
 tools/arch/arm64/include/asm/cputype.h | 6 ++++++
 1 file changed, 6 insertions(+)

tools/arch/arm64/include/asm/cputype.h +6 -0

index 52f076afeb96006c..7b32b99023a21d3a 100644
@@ -86,6 +86,9 @@
 #define ARM_CPU_PART_CORTEX_X2		0xD48
 #define ARM_CPU_PART_NEOVERSE_N2	0xD49
 #define ARM_CPU_PART_CORTEX_A78C	0xD4B
+#define ARM_CPU_PART_NEOVERSE_V2	0xD4F
+#define ARM_CPU_PART_CORTEX_X4		0xD82
+#define ARM_CPU_PART_NEOVERSE_V3	0xD84
 
 #define APM_CPU_PART_XGENE		0x000
 #define APM_CPU_VAR_POTENZA		0x00

@@ -159,6 +162,9 @@
 #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
 #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
 #define MIDR_CORTEX_A78C	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C)
+#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2)
+#define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4)
+#define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
 #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
 #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)

Signature · 1 line

2.44.0

Hi Arnaldo,

Quoted 5 lines · Arnaldo Carvalho de Melo

To get the changes in:

0ce85db6c2141b7f ("arm64: cputype: Add Neoverse-V3 definitions") 02a0a04676fa7796 ("arm64: cputype: Add Cortex-X4 definitions") f4d9d9dcc70b96b5 ("arm64: Add Neoverse-V2 part")

As a heads-up, there are likely to be a couple more updates here shortly:

https://lore.kernel.org/linux-arm-kernel/[email protected]/

Quoted 8 lines

That makes this perf source code to be rebuilt:

CC /tmp/build/perf-tools/util/arm-spe.o

The changes in the above patch add MIDR_NEOVERSE_V[23] and MIDR_NEOVERSE_V1 is used in arm-spe.c, so probably we need to add those and perhaps MIDR_CORTEX_X4 to that array? Or maybe we need to leave this for later when this is all tested on those machines?

Hmm... looking at where that was added this is somewhat misnamed, this is really saying that these cores use the same IMPLEMENTATION DEFINED encoding of the source field. That's not really a property of Neoverse specifically, and I'm not sure what Arm's policy is here going forwards.

We should probably rename that to something like common_data_source_encoding, with a big comment about exactly what it implies.

I would not touch this for now -- someone would have to go audit the

TRMs to check that those other cores have the same encoding, and I think it'd be better to do that as a follow-up.

The relevant commit was:

4e6430cbb1a9f1dc ("perf arm-spe: Use SPE data source for neoverse cores")

Mark.

Quoted 53 lines

  static const struct midr_range neoverse_spe[] = {
          MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),
          MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
          MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),
          {},
  };

That addresses this perf build warning:

Warning: Kernel ABI header differences:
diff -u tools/arch/arm64/include/asm/cputype.h arch/arm64/include/asm/cputype.h

Cc Adrian Hunter <[email protected]>

Cc Besar Wicaksono <[email protected]>

Cc Ian Rogers <[email protected]>

Cc Jiri Olsa <[email protected]>

Cc Kan Liang <[email protected]>

Cc Mark Rutland <[email protected]>

Cc Namhyung Kim <[email protected]>

Cc Will Deacon <[email protected]>

Link https://lore.kernel.org/lkml/

Signed-off-by Arnaldo Carvalho de Melo <[email protected]>

---
 tools/arch/arm64/include/asm/cputype.h | 6 ++++++
 1 file changed, 6 insertions(+)

tools/arch/arm64/include/asm/cputype.h +6 -0

index 52f076afeb96006c..7b32b99023a21d3a 100644
@@ -86,6 +86,9 @@
 #define ARM_CPU_PART_CORTEX_X2		0xD48
 #define ARM_CPU_PART_NEOVERSE_N2	0xD49
 #define ARM_CPU_PART_CORTEX_A78C	0xD4B
+#define ARM_CPU_PART_NEOVERSE_V2	0xD4F
+#define ARM_CPU_PART_CORTEX_X4		0xD82
+#define ARM_CPU_PART_NEOVERSE_V3	0xD84
 
 #define APM_CPU_PART_XGENE		0x000
 #define APM_CPU_VAR_POTENZA		0x00

@@ -159,6 +162,9 @@
 #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
 #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
 #define MIDR_CORTEX_A78C	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C)
+#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2)
+#define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4)
+#define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
 #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
 #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)

Signature · 1 line

2.44.0

Quoted 15 lines · Mark Rutland

Quoted 4 lines · Arnaldo Carvalho de Melo

The changes in the above patch add MIDR_NEOVERSE_V[23] and MIDR_NEOVERSE_V1 is used in arm-spe.c, so probably we need to add those and perhaps MIDR_CORTEX_X4 to that array? Or maybe we need to leave this for later when this is all tested on those machines?

Hmm... looking at where that was added this is somewhat misnamed, this is really saying that these cores use the same IMPLEMENTATION DEFINED encoding of the source field. That's not really a property of Neoverse specifically, and I'm not sure what Arm's policy is here going forwards.

We should probably rename that to something like common_data_source_encoding, with a big comment about exactly what it implies.

Quoted 1 line

I would not touch this for now -- someone would have to go audit the

Ok, you mean not touch tools/perf/util/arm-spe.c, right, can I just go ahead and update the copy of that header so that we have a clean (of build warnings) build?

Quoted 16 lines · Arnaldo Carvalho de Melo

Quoted 15 lines · Mark Rutland

Quoted 4 lines · Arnaldo Carvalho de Melo

The changes in the above patch add MIDR_NEOVERSE_V[23] and MIDR_NEOVERSE_V1 is used in arm-spe.c, so probably we need to add those and perhaps MIDR_CORTEX_X4 to that array? Or maybe we need to leave this for later when this is all tested on those machines?

Hmm... looking at where that was added this is somewhat misnamed, this is really saying that these cores use the same IMPLEMENTATION DEFINED encoding of the source field. That's not really a property of Neoverse specifically, and I'm not sure what Arm's policy is here going forwards.

We should probably rename that to something like common_data_source_encoding, with a big comment about exactly what it implies.

Quoted 5 lines

Quoted 1 line

I would not touch this for now -- someone would have to go audit the

Ok, you mean not touch tools/perf/util/arm-spe.c, right, can I just go ahead and update the copy of that header so that we have a clean (of build warnings) build?

Yes: update the header, but leave arm-spe.c unchanged. Sorry for not being clear!

It'd be nice if we could update the commit message to note that we're deliberately leaving that as-is.

Either way:

Acked-by Mark Rutland <[email protected]>

Hi Arnaldo,

Quoted 5 lines · Arnaldo Carvalho de Melo

To get the changes in:

   0ce85db6c2141b7f ("arm64: cputype: Add Neoverse-V3 definitions")
   02a0a04676fa7796 ("arm64: cputype: Add Cortex-X4 definitions")
   f4d9d9dcc70b96b5 ("arm64: Add Neoverse-V2 part")

As a heads-up, there are likely to be a couple more updates here shortly:

   https://lore.kernel.org/linux-arm-kernel/[email protected]/

Quoted 8 lines

That makes this perf source code to be rebuilt:

CC /tmp/build/perf-tools/util/arm-spe.o

The changes in the above patch add MIDR_NEOVERSE_V[23] and MIDR_NEOVERSE_V1 is used in arm-spe.c, so probably we need to add those and perhaps MIDR_CORTEX_X4 to that array? Or maybe we need to leave this for later when this is all tested on those machines?

Hmm... looking at where that was added this is somewhat misnamed, this is really saying that these cores use the same IMPLEMENTATION DEFINED encoding of the source field. That's not really a property of Neoverse specifically, and I'm not sure what Arm's policy is here going forwards.

We should probably rename that to something like common_data_source_encoding, with a big comment about exactly what it implies.

I would not touch this for now -- someone would have to go audit the TRMs to check that those other cores have the same encoding, and I think it'd be better to do that as a follow-up.

Quoted 23 lines · Mark Rutland

Hi Arnaldo,

Quoted 5 lines · Arnaldo Carvalho de Melo

To get the changes in:

   0ce85db6c2141b7f ("arm64: cputype: Add Neoverse-V3 definitions")
   02a0a04676fa7796 ("arm64: cputype: Add Cortex-X4 definitions")
   f4d9d9dcc70b96b5 ("arm64: Add Neoverse-V2 part")

As a heads-up, there are likely to be a couple more updates here shortly:

   https://lore.kernel.org/linux-arm-kernel/[email protected]/

Quoted 8 lines

That makes this perf source code to be rebuilt:

CC /tmp/build/perf-tools/util/arm-spe.o

The changes in the above patch add MIDR_NEOVERSE_V[23] and MIDR_NEOVERSE_V1 is used in arm-spe.c, so probably we need to add those and perhaps MIDR_CORTEX_X4 to that array? Or maybe we need to leave this for later when this is all tested on those machines?

Quoted 8 lines

Hmm... looking at where that was added this is somewhat misnamed, this is really saying that these cores use the same IMPLEMENTATION DEFINED encoding of the source field. That's not really a property of Neoverse specifically, and I'm not sure what Arm's policy is here going forwards.

We should probably rename that to something like common_data_source_encoding, with a big comment about exactly what it implies.

Agreed.

I went through Neoverse-V2/V3/V4, Cortex-X4, Cortex-X4, Cortex-A720, and Cortex-X925, all of them have the same definition for data source packet format. It makes sense to change name to Neoverse specific to a more general name.

Quoted 3 lines

I would not touch this for now -- someone would have to go audit the TRMs to check that those other cores have the same encoding, and I think it'd be better to do that as a follow-up.

So far, it's fine to not change the file util/arm-spe.c.

Now more and more Arm CPUs support the data source in SPE and share the same data source format. It's not scalable for us to adding every CPU variant into the file util/arm-spe.c.

I would like to expose the PMSIDR_EL1.LDS bit (Data source indicator for sampled load instructions) via the 'cap' folder, and then we can save this info into the perf meta data during record phase.

In the perf report, we can parse the meta data and if the PMSIDR_EL1.LDS bit is set, the tool will parse the data source packet based on the common format.

Quoted 7 lines

Now more and more Arm CPUs support the data source in SPE and share the same data source format. It's not scalable for us to adding every CPU variant into the file util/arm-spe.c.

I would like to expose the PMSIDR_EL1.LDS bit (Data source indicator for sampled load instructions) via the 'cap' folder, and then we can save this info into the perf meta data during record phase.

I'd be happy to expose fields from PMSIDR_EL1.

Quoted 3 lines

In the perf report, we can parse the meta data and if the PMSIDR_EL1.LDS bit is set, the tool will parse the data source packet based on the common format.

I don't believe that's right.

PMSIDR_EL1.LDS indicates that the loaded data source field is implemented, but even when it is implemented, the format is IMPLEMENTATION DEFINED.

Today, Arm Ltd implementations happen to share a format, but that isn't implied by PMSIDR_EL1.LDS, and there's no guarantee that future CPUs will all use the same format.

For the moment we'll have to keep adding to this list.

On 6/4/24 19:55, Mark Rutland wrote:

[...]

Quoted 14 lines

Quoted 7 lines

Now more and more Arm CPUs support the data source in SPE and share the same data source format. It's not scalable for us to adding every CPU variant into the file util/arm-spe.c.

I would like to expose the PMSIDR_EL1.LDS bit (Data source indicator for sampled load instructions) via the 'cap' folder, and then we can save this info into the perf meta data during record phase.

I'd be happy to expose fields from PMSIDR_EL1.

Quoted 3 lines

In the perf report, we can parse the meta data and if the PMSIDR_EL1.LDS bit is set, the tool will parse the data source packet based on the common format.

Quoted 5 lines

I don't believe that's right.

PMSIDR_EL1.LDS indicates that the loaded data source field is implemented, but even when it is implemented, the format is IMPLEMENTATION DEFINED.

Thanks for correction. PMSIDR_EL1.LDS bit is necessary but not sufficient for using the common data source format.

Quoted 5 lines

Today, Arm Ltd implementations happen to share a format, but that isn't implied by PMSIDR_EL1.LDS, and there's no guarantee that future CPUs will all use the same format.

For the moment we'll have to keep adding to this list.

I would like to use an opposite way - we can only maintain CPU variants with special data source format, otherwise, all other CPUs use the common format.

-----Original Message-----
From: Mark Rutland <[email protected]>
Sent: Wednesday, June 5, 2024 4:32 PM
To: Leo Yan <[email protected]>
Cc: Arnaldo Carvalho de Melo <[email protected]>; Besar Wicaksono <[email protected]>; Will Deacon <[email protected]>; Adrian Hunter <[email protected]>; Ian Rogers <[email protected]>; Jiri Olsa <[email protected]>; Kan Liang <[email protected]>; Namhyung Kim <[email protected]>; Linux Kernel Mailing List <linux- [email protected]>; [email protected]; James Clark <[email protected]>
Subject: Re: [RFC/PATCH 1/1] tools headers arm64: Sync arm64's cputype.h with the kernel sources

External email: Use caution opening links or attachments

Quoted 5 lines · Leo Yan

On 6/4/24 19:55, Mark Rutland wrote:

[...]

Quoted 1 line

Quoted 1 line

Now more and more Arm CPUs support the data source in SPE and share

the same

Quoted 27 lines

Quoted 13 lines

Quoted 6 lines

data source format. It's not scalable for us to adding every CPU variant into the file util/arm-spe.c.

I would like to expose the PMSIDR_EL1.LDS bit (Data source indicator for sampled load instructions) via the 'cap' folder, and then we can save this info into the perf meta data during record phase.

I'd be happy to expose fields from PMSIDR_EL1.

Quoted 3 lines

In the perf report, we can parse the meta data and if the PMSIDR_EL1.LDS bit is set, the tool will parse the data source packet based on the common format.

Quoted 5 lines

I don't believe that's right.

PMSIDR_EL1.LDS indicates that the loaded data source field is implemented, but even when it is implemented, the format is IMPLEMENTATION DEFINED.

Thanks for correction. PMSIDR_EL1.LDS bit is necessary but not sufficient for using the common data source format.

Quoted 5 lines

Today, Arm Ltd implementations happen to share a format, but that isn't implied by PMSIDR_EL1.LDS, and there's no guarantee that future CPUs will all use the same format.

For the moment we'll have to keep adding to this list.

Quoted 3 lines

I would like to use an opposite way - we can only maintain CPU variants with special data source format, otherwise, all other CPUs use the common format.

I think that's not a good idea.

Today, Arm Ltd CPUs happen to share *a* common format, but that's likely to change at some point in future, and CPUs from other vendors are likely to use different formats.

Assuming any format by default means that when CPUs with different formats are released, we'll produce incorrect results for those CPU by default, we'll need to update tables to exclude those CPUs, and we'll probably want to backport that exclusion to minimize the risk of users getting incorrect/misleading results.

While the current situation isn't nice, I think the alternative is worse -- it will confuse and anger users.

I think we need to talk with the Arm architects to see if they can define some discovery mechanism for the data source format.

Quoted 5 lines

Quoted 5 lines

Quoted 5 lines

Today, Arm Ltd implementations happen to share a format, but that isn't implied by PMSIDR_EL1.LDS, and there's no guarantee that future CPUs will all use the same format.

For the moment we'll have to keep adding to this list.

I apologize I didn't follow. Do you mean adding new CPU identifier to neoverse_spe[] list is still the way to go for now?

Quoted 15 lines

Quoted 2 lines

I would like to use an opposite way - we can only maintain CPU variants with special data source format, otherwise, all other CPUs use the common format.

I think that's not a good idea.

Today, Arm Ltd CPUs happen to share *a* common format, but that's likely to change at some point in future, and CPUs from other vendors are likely to use different formats.

Assuming any format by default means that when CPUs with different formats are released, we'll produce incorrect results for those CPU by default, we'll need to update tables to exclude those CPUs, and we'll probably want to backport that exclusion to minimize the risk of users getting incorrect/misleading results.

Quoted 5 lines

While the current situation isn't nice, I think the alternative is worse -- it will confuse and anger users.

I think we need to talk with the Arm architects to see if they can define some discovery mechanism for the data source format.

Is there a follow-up on this from Arm?