Skip to contentSkip to conversation

arm64: dts: qcom: x1e80100: enable GICv3 ITS for PCIe

PATCH Applied Johan Hovold 4 participants 6 messages Oct 9, 2024 – Oct 16, 2024

Subsystems (3)
Device tree bindings Arm Qualcomm mailing list Arm Qualcomm support
lore
Share & tools
lore

Johan Hovold

author
#0 lore raw

PATCH v2 1/1 arm64: dts: qcom: x1e80100: enable GICv3 ITS for PCIe

The DWC PCIe controller can be used with its internal MSI controller or with an external one such as the GICv3 Interrupt Translation Service (ITS).

Add the msi-map properties needed to use the GIC ITS. This will also make Linux switch to the ITS implementation, which allows for assigning affinity to individual MSIs. This specifically allows NVMe and Wi-Fi interrupts to be processed on all cores (and not just on CPU0).

Note that using the GIC ITS on x1e80100 will cause Advanced Error Reporting (AER) interrupts to be received on errors unlike when using the internal MSI controller. Consequently, notifications about (correctable) errors may now be logged for errors that previously went unnoticed.

Also note that PCIe5 (and PCIe3) can currently only be used with the internal MSI controller due to a platform (firmware) limitation.

Signed-off-by Johan Hovold <[email protected]>

---

The PCIe Gen4 stability fixes [1] are now in 6.12-rc1 so that we can enable the GIC ITS without being flooded with link error notifications [2].

Johan

[1] https://lore.kernel.org/lkml/[email protected]/
[2] https://lore.kernel.org/lkml/[email protected]/

Changes in v2
- amend commit message with comment about PCIe3 and PCIe5 only supporting the internal MSI controller

 arch/arm64/boot/dts/qcom/x1e80100.dtsi | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)
arch/arm64/boot/dts/qcom/x1e80100.dtsi +4 -2
index 1743fe229ded..4d978fe936e5 100644
@@ -2934,6 +2934,8 @@ pcie6a: pci@1bf8000 {
 			linux,pci-domain = <6>;
 			num-lanes = <4>;
 
+			msi-map = <0x0 &gic_its 0xe0000 0x10000>;
+
 			interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>,

@@ -3183,6 +3185,8 @@ pcie4: pci@1c08000 {
 			linux,pci-domain = <4>;
 			num-lanes = <2>;
 
+			msi-map = <0x0 &gic_its 0xc0000 0x10000>;
+
 			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,

@@ -5773,8 +5777,6 @@ gic_its: msi-controller@17040000 {
 
 				msi-controller;
 				#msi-cells = <1>;
-
-				status = "disabled";
 			};
 		};
Signature · 1 line
2.45.2
Reviewed-by on v2 1/1
#1 lore raw
Quoted 15 lines · Johan Hovold

The DWC PCIe controller can be used with its internal MSI controller or with an external one such as the GICv3 Interrupt Translation Service (ITS).

Add the msi-map properties needed to use the GIC ITS. This will also make Linux switch to the ITS implementation, which allows for assigning affinity to individual MSIs. This specifically allows NVMe and Wi-Fi interrupts to be processed on all cores (and not just on CPU0).

Note that using the GIC ITS on x1e80100 will cause Advanced Error Reporting (AER) interrupts to be received on errors unlike when using the internal MSI controller. Consequently, notifications about (correctable) errors may now be logged for errors that previously went unnoticed.

Quoted 8 lines

Also note that PCIe5 (and PCIe3) can currently only be used with the internal MSI controller due to a platform (firmware) limitation.

Signed-off-by Johan Hovold <[email protected]>

---

The PCIe Gen4 stability fixes [1] are now in 6.12-rc1 so that we can enable the GIC ITS without being flooded with link error notifications [2].

Cc <[email protected]> # Depends on driver stability fixes
Reviewed-by Dmitry Baryshkov <[email protected]>
Quoted 10 lines

Johan

[1] https://lore.kernel.org/lkml/[email protected]/
[2] https://lore.kernel.org/lkml/[email protected]/

Changes in v2
- amend commit message with comment about PCIe3 and PCIe5 only supporting the internal MSI controller

Signature · 2 lines
With best wishes
Dmitry
#2 lore raw
Quoted 19 lines · Dmitry Baryshkov
Quoted 18 lines · Johan Hovold

The DWC PCIe controller can be used with its internal MSI controller or with an external one such as the GICv3 Interrupt Translation Service (ITS).

Add the msi-map properties needed to use the GIC ITS. This will also make Linux switch to the ITS implementation, which allows for assigning affinity to individual MSIs. This specifically allows NVMe and Wi-Fi interrupts to be processed on all cores (and not just on CPU0).

Note that using the GIC ITS on x1e80100 will cause Advanced Error Reporting (AER) interrupts to be received on errors unlike when using the internal MSI controller. Consequently, notifications about (correctable) errors may now be logged for errors that previously went unnoticed.

Also note that PCIe5 (and PCIe3) can currently only be used with the internal MSI controller due to a platform (firmware) limitation.

Quoted 7 lines
Quoted 5 lines
Signed-off-by Johan Hovold <[email protected]>

---

The PCIe Gen4 stability fixes [1] are now in 6.12-rc1 so that we can enable the GIC ITS without being flooded with link error notifications [2].

Cc <[email protected]> # Depends on driver stability fixes

This patch is enabling a new feature, it is not a fix, so Bjorn please do not include the above tag when applying.

Quoted 1 line
Reviewed-by Dmitry Baryshkov <[email protected]>

But thanks for reviewing.

Johan

#3 lore raw
Quoted 24 lines · Johan Hovold
Quoted 22 lines · Dmitry Baryshkov
Quoted 21 lines · Johan Hovold

The DWC PCIe controller can be used with its internal MSI controller or with an external one such as the GICv3 Interrupt Translation Service (ITS).

Add the msi-map properties needed to use the GIC ITS. This will also make Linux switch to the ITS implementation, which allows for assigning affinity to individual MSIs. This specifically allows NVMe and Wi-Fi interrupts to be processed on all cores (and not just on CPU0).

Note that using the GIC ITS on x1e80100 will cause Advanced Error Reporting (AER) interrupts to be received on errors unlike when using the internal MSI controller. Consequently, notifications about (correctable) errors may now be logged for errors that previously went unnoticed.

Also note that PCIe5 (and PCIe3) can currently only be used with the internal MSI controller due to a platform (firmware) limitation.

Signed-off-by Johan Hovold <[email protected]>

---

Quoted 7 lines
Quoted 4 lines
Quoted 2 lines

The PCIe Gen4 stability fixes [1] are now in 6.12-rc1 so that we can enable the GIC ITS without being flooded with link error notifications [2].

Cc <[email protected]> # Depends on driver stability fixes

This patch is enabling a new feature, it is not a fix, so Bjorn please do not include the above tag when applying.

This is for stopping autosel from picking up the patch, not for picking it up. After just helping to revert random patches being picked by autosel I start to like this header.

Quoted 6 lines
Quoted 2 lines
Reviewed-by Dmitry Baryshkov <[email protected]>

But thanks for reviewing.

Johan

Signature · 2 lines
With best wishes
Dmitry
#4 lore raw
Quoted 28 lines · Dmitry Baryshkov
Quoted 27 lines · Johan Hovold
Quoted 25 lines · Dmitry Baryshkov
Quoted 23 lines · Johan Hovold

The DWC PCIe controller can be used with its internal MSI controller or with an external one such as the GICv3 Interrupt Translation Service (ITS).

Add the msi-map properties needed to use the GIC ITS. This will also make Linux switch to the ITS implementation, which allows for assigning affinity to individual MSIs. This specifically allows NVMe and Wi-Fi interrupts to be processed on all cores (and not just on CPU0).

Note that using the GIC ITS on x1e80100 will cause Advanced Error Reporting (AER) interrupts to be received on errors unlike when using the internal MSI controller. Consequently, notifications about (correctable) errors may now be logged for errors that previously went unnoticed.

Also note that PCIe5 (and PCIe3) can currently only be used with the internal MSI controller due to a platform (firmware) limitation.

Signed-off-by Johan Hovold <[email protected]>

---

The PCIe Gen4 stability fixes [1] are now in 6.12-rc1 so that we can enable the GIC ITS without being flooded with link error notifications [2].

Quoted 8 lines
Quoted 4 lines
Quoted 1 line
Cc <[email protected]> # Depends on driver stability fixes

This patch is enabling a new feature, it is not a fix, so Bjorn please do not include the above tag when applying.

This is for stopping autosel from picking up the patch, not for picking it up. After just helping to revert random patches being picked by autosel I start to like this header.

I know what it is, but you should not be adding them to my patches.

Johan

maintainer Applied
#5 lore raw
In reply to Johan Hovold
Quoted 10 lines · Johan Hovold

The DWC PCIe controller can be used with its internal MSI controller or with an external one such as the GICv3 Interrupt Translation Service (ITS).

Add the msi-map properties needed to use the GIC ITS. This will also make Linux switch to the ITS implementation, which allows for assigning affinity to individual MSIs. This specifically allows NVMe and Wi-Fi interrupts to be processed on all cores (and not just on CPU0).

[...]

Applied, thanks!

[1/1] arm64: dts: qcom: x1e80100: enable GICv3 ITS for PCIe

      commit: 9c4cd0aef259d41355f90e0dbb2d3574f3830de9

Best regards,

Signature · 1 line
Bjorn Andersson <[email protected]>