ARM: dts: samsung: Add cache information to the Exynos4412 SoCS

As per Exynos 5422 user manual add missing cache information to the Exynos542x SoC.

- Each Cortex-A7 core has 32 KB of instruction cache and 32 KB of L1 data cache available.
- Each Cortex-A15 core has 32 KB of L1 instruction cache and 32 KB of L1 data cache available.
- The little (A7) cluster has 512 KB of unified L2 cache available.
- The big (A15) cluster has 2 MB of unified L2 cache available.

Features:
- Exynos 5422 support cache coherency interconnect (CCI) bus with L2 cache snooping capability. This hardware automatic L2 cache snooping removes the efforts of synchronizing the contents of the two L2 caches in core switching event.

Signed-off-by Anand Moon <[email protected]>

---
  .../arm/boot/dts/samsung/exynos5422-cpus.dtsi | 74 +++++++++++++++++++
  1 file changed, 74 insertions(+)

arch/arm/boot/dts/samsung/exynos5422-cpus.dtsi +67 -0

index 412a0bb4b988..9b9b2bdfb522 100644
@@ -59,6 +59,13 @@ cpu0: cpu@100 {
  			reg = <0x100>;
  			clocks = <&clock CLK_KFC_CLK>;
  			clock-frequency = <1000000000>;
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
+			next-level-cache = <&L2_a7>;
  			cci-control-port = <&cci_control0>;
  			operating-points-v2 = <&cluster_a7_opp_table>;
  			#cooling-cells = <2>; /* min followed by max */

@@ -72,6 +79,13 @@ cpu1: cpu@101 {
  			reg = <0x101>;
  			clocks = <&clock CLK_KFC_CLK>;
  			clock-frequency = <1000000000>;
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
+			next-level-cache = <&L2_a7>;
  			cci-control-port = <&cci_control0>;
  			operating-points-v2 = <&cluster_a7_opp_table>;
  			#cooling-cells = <2>; /* min followed by max */

@@ -85,6 +99,13 @@ cpu2: cpu@102 {
  			reg = <0x102>;
  			clocks = <&clock CLK_KFC_CLK>;
  			clock-frequency = <1000000000>;
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
+			next-level-cache = <&L2_a7>;
  			cci-control-port = <&cci_control0>;
  			operating-points-v2 = <&cluster_a7_opp_table>;
  			#cooling-cells = <2>; /* min followed by max */

@@ -98,6 +119,13 @@ cpu3: cpu@103 {
  			reg = <0x103>;
  			clocks = <&clock CLK_KFC_CLK>;
  			clock-frequency = <1000000000>;
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
+			next-level-cache = <&L2_a7>;
  			cci-control-port = <&cci_control0>;
  			operating-points-v2 = <&cluster_a7_opp_table>;
  			#cooling-cells = <2>; /* min followed by max */

@@ -111,6 +139,13 @@ cpu4: cpu@0 {
  			reg = <0x0>;
  			clocks = <&clock CLK_ARM_CLK>;
  			clock-frequency = <1800000000>;
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
+			next-level-cache = <&L2_a15>;
  			cci-control-port = <&cci_control1>;
  			operating-points-v2 = <&cluster_a15_opp_table>;
  			#cooling-cells = <2>; /* min followed by max */

@@ -124,6 +159,13 @@ cpu5: cpu@1 {
  			reg = <0x1>;
  			clocks = <&clock CLK_ARM_CLK>;
  			clock-frequency = <1800000000>;
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
+			next-level-cache = <&L2_a15>;
  			cci-control-port = <&cci_control1>;
  			operating-points-v2 = <&cluster_a15_opp_table>;
  			#cooling-cells = <2>; /* min followed by max */

@@ -137,6 +179,13 @@ cpu6: cpu@2 {
  			reg = <0x2>;
  			clocks = <&clock CLK_ARM_CLK>;
  			clock-frequency = <1800000000>;
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
+			next-level-cache = <&L2_a15>;
  			cci-control-port = <&cci_control1>;
  			operating-points-v2 = <&cluster_a15_opp_table>;
  			#cooling-cells = <2>; /* min followed by max */

@@ -150,12 +199,37 @@ cpu7: cpu@3 {
  			reg = <0x3>;
  			clocks = <&clock CLK_ARM_CLK>;
  			clock-frequency = <1800000000>;
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
+			next-level-cache = <&L2_a15>;
  			cci-control-port = <&cci_control1>;
  			operating-points-v2 = <&cluster_a15_opp_table>;
  			#cooling-cells = <2>; /* min followed by max */
  			capacity-dmips-mhz = <1024>;
  			dynamic-power-coefficient = <310>;
  		};
+
+		L2_a7: l2-cache-cluster0 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-unified;
+			cache-size = <0x80000>;	/* L2. 512 KB */
+			cache-line-size = <64>;
+			cache-sets = <512>;
+		};
+
+		L2_a15: l2-cache-cluster1 {

Quoted 16 lines · Anand Moon

As per Exynos 5422 user manual add missing cache information to the Exynos542x SoC.

- Each Cortex-A7 core has 32 KB of instruction cache and 32 KB of L1 data cache available.
- Each Cortex-A15 core has 32 KB of L1 instruction cache and 32 KB of L1 data cache available.
- The little (A7) cluster has 512 KB of unified L2 cache available.
- The big (A15) cluster has 2 MB of unified L2 cache available.

Features:
- Exynos 5422 support cache coherency interconnect (CCI) bus with L2 cache snooping capability. This hardware automatic L2 cache snooping removes the efforts of synchronizing the contents of the two L2 caches in core switching event.

Quoted 1 line

Signed-off-by Anand Moon <[email protected]>

The provided values are not correct. Please refer to commit 5f41f9198f29 ("ARM: 8864/1: Add workaround for I-Cache line size mismatch between CPU cores"), which adds workaround for different l1 icache line size between big and little CPUs. This workaround gets enabled on all Exynos542x/5800 boards.

Quoted 135 lines

---
  .../arm/boot/dts/samsung/exynos5422-cpus.dtsi | 74 +++++++++++++++++++
  1 file changed, 74 insertions(+)

arch/arm/boot/dts/samsung/exynos5422-cpus.dtsi +67 -0

index 412a0bb4b988..9b9b2bdfb522 100644
@@ -59,6 +59,13 @@ cpu0: cpu@100 {
                      reg = <0x100>;
                      clocks = <&clock CLK_KFC_CLK>;
                      clock-frequency = <1000000000>;
+                     d-cache-line-size = <32>;
+                     d-cache-size = <0x8000>;
+                     d-cache-sets = <32>;
+                     i-cache-line-size = <32>;
+                     i-cache-size = <0x8000>;
+                     i-cache-sets = <32>;
+                     next-level-cache = <&L2_a7>;
                      cci-control-port = <&cci_control0>;
                      operating-points-v2 = <&cluster_a7_opp_table>;
                      #cooling-cells = <2>; /* min followed by max */

@@ -72,6 +79,13 @@ cpu1: cpu@101 {
                      reg = <0x101>;
                      clocks = <&clock CLK_KFC_CLK>;
                      clock-frequency = <1000000000>;
+                     d-cache-line-size = <32>;
+                     d-cache-size = <0x8000>;
+                     d-cache-sets = <32>;
+                     i-cache-line-size = <32>;
+                     i-cache-size = <0x8000>;
+                     i-cache-sets = <32>;
+                     next-level-cache = <&L2_a7>;
                      cci-control-port = <&cci_control0>;
                      operating-points-v2 = <&cluster_a7_opp_table>;
                      #cooling-cells = <2>; /* min followed by max */

@@ -85,6 +99,13 @@ cpu2: cpu@102 {
                      reg = <0x102>;
                      clocks = <&clock CLK_KFC_CLK>;
                      clock-frequency = <1000000000>;
+                     d-cache-line-size = <32>;
+                     d-cache-size = <0x8000>;
+                     d-cache-sets = <32>;
+                     i-cache-line-size = <32>;
+                     i-cache-size = <0x8000>;
+                     i-cache-sets = <32>;
+                     next-level-cache = <&L2_a7>;
                      cci-control-port = <&cci_control0>;
                      operating-points-v2 = <&cluster_a7_opp_table>;
                      #cooling-cells = <2>; /* min followed by max */

@@ -98,6 +119,13 @@ cpu3: cpu@103 {
                      reg = <0x103>;
                      clocks = <&clock CLK_KFC_CLK>;
                      clock-frequency = <1000000000>;
+                     d-cache-line-size = <32>;
+                     d-cache-size = <0x8000>;
+                     d-cache-sets = <32>;
+                     i-cache-line-size = <32>;
+                     i-cache-size = <0x8000>;
+                     i-cache-sets = <32>;
+                     next-level-cache = <&L2_a7>;
                      cci-control-port = <&cci_control0>;
                      operating-points-v2 = <&cluster_a7_opp_table>;
                      #cooling-cells = <2>; /* min followed by max */

@@ -111,6 +139,13 @@ cpu4: cpu@0 {
                      reg = <0x0>;
                      clocks = <&clock CLK_ARM_CLK>;
                      clock-frequency = <1800000000>;
+                     d-cache-line-size = <32>;
+                     d-cache-size = <0x8000>;
+                     d-cache-sets = <32>;
+                     i-cache-line-size = <32>;
+                     i-cache-size = <0x8000>;
+                     i-cache-sets = <32>;
+                     next-level-cache = <&L2_a15>;
                      cci-control-port = <&cci_control1>;
                      operating-points-v2 = <&cluster_a15_opp_table>;
                      #cooling-cells = <2>; /* min followed by max */

@@ -124,6 +159,13 @@ cpu5: cpu@1 {
                      reg = <0x1>;
                      clocks = <&clock CLK_ARM_CLK>;
                      clock-frequency = <1800000000>;
+                     d-cache-line-size = <32>;
+                     d-cache-size = <0x8000>;
+                     d-cache-sets = <32>;
+                     i-cache-line-size = <32>;
+                     i-cache-size = <0x8000>;
+                     i-cache-sets = <32>;
+                     next-level-cache = <&L2_a15>;
                      cci-control-port = <&cci_control1>;
                      operating-points-v2 = <&cluster_a15_opp_table>;
                      #cooling-cells = <2>; /* min followed by max */

@@ -137,6 +179,13 @@ cpu6: cpu@2 {
                      reg = <0x2>;
                      clocks = <&clock CLK_ARM_CLK>;
                      clock-frequency = <1800000000>;
+                     d-cache-line-size = <32>;
+                     d-cache-size = <0x8000>;
+                     d-cache-sets = <32>;
+                     i-cache-line-size = <32>;
+                     i-cache-size = <0x8000>;
+                     i-cache-sets = <32>;
+                     next-level-cache = <&L2_a15>;
                      cci-control-port = <&cci_control1>;
                      operating-points-v2 = <&cluster_a15_opp_table>;
                      #cooling-cells = <2>; /* min followed by max */

@@ -150,12 +199,37 @@ cpu7: cpu@3 {
                      reg = <0x3>;
                      clocks = <&clock CLK_ARM_CLK>;
                      clock-frequency = <1800000000>;
+                     d-cache-line-size = <32>;
+                     d-cache-size = <0x8000>;
+                     d-cache-sets = <32>;
+                     i-cache-line-size = <32>;
+                     i-cache-size = <0x8000>;
+                     i-cache-sets = <32>;
+                     next-level-cache = <&L2_a15>;
                      cci-control-port = <&cci_control1>;
                      operating-points-v2 = <&cluster_a15_opp_table>;
                      #cooling-cells = <2>; /* min followed by max */
                      capacity-dmips-mhz = <1024>;
                      dynamic-power-coefficient = <310>;
              };
+
+             L2_a7: l2-cache-cluster0 {
+                     compatible = "cache";
+                     cache-level = <2>;
+                     cache-unified;
+                     cache-size = <0x80000>; /* L2. 512 KB */
+                     cache-line-size = <64>;
+                     cache-sets = <512>;
+             };
+
+             L2_a15: l2-cache-cluster1 {

arch/arm/boot/dts/samsung/exynos5422-cpus.dtsi cpu7: cpu@3 { · line 235

Quoted 10 lines

arch/arm/boot/dts/samsung/exynos5422-cpus.dtsi +7 -0

+                     compatible = "cache";
+                     cache-level = <2>;
+                     cache-unified;
+                     cache-size = <0x200000>; /* L2, 2M */
+                     cache-line-size = <64>;
+                     cache-sets = <512>;
+             };
      };
  };
 

Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland

Hi Marek,

Quoted 22 lines · Marek Szyprowski

Quoted 17 lines · Anand Moon

As per Exynos 5422 user manual add missing cache information to the Exynos542x SoC.

- Each Cortex-A7 core has 32 KB of instruction cache and 32 KB of L1 data cache available.
- Each Cortex-A15 core has 32 KB of L1 instruction cache and 32 KB of L1 data cache available.
- The little (A7) cluster has 512 KB of unified L2 cache available.
- The big (A15) cluster has 2 MB of unified L2 cache available.

Features:
- Exynos 5422 support cache coherency interconnect (CCI) bus with L2 cache snooping capability. This hardware automatic L2 cache snooping removes the efforts of synchronizing the contents of the two L2 caches in core switching event.

Signed-off-by Anand Moon <[email protected]>

Quoted 6 lines

The provided values are not correct. Please refer to commit 5f41f9198f29 ("ARM: 8864/1: Add workaround for I-Cache line size mismatch between CPU cores"), which adds workaround for different l1 icache line size between big and little CPUs. This workaround gets enabled on all Exynos542x/5800 boards.

Ok, I have just referred to the Exynos 5422 user manual for this patch, This patch is just updating the cache size for CPU for big.litle architecture..

Quoted 25 lines · Anand Moon

Hi Marek,

Quoted 22 lines · Marek Szyprowski

Quoted 17 lines · Anand Moon

As per Exynos 5422 user manual add missing cache information to the Exynos542x SoC.

- Each Cortex-A7 core has 32 KB of instruction cache and 32 KB of L1 data cache available.
- Each Cortex-A15 core has 32 KB of L1 instruction cache and 32 KB of L1 data cache available.
- The little (A7) cluster has 512 KB of unified L2 cache available.
- The big (A15) cluster has 2 MB of unified L2 cache available.

Features:
- Exynos 5422 support cache coherency interconnect (CCI) bus with L2 cache snooping capability. This hardware automatic L2 cache snooping removes the efforts of synchronizing the contents of the two L2 caches in core switching event.

Signed-off-by Anand Moon <[email protected]>

Quoted 9 lines

Quoted 6 lines

The provided values are not correct. Please refer to commit 5f41f9198f29 ("ARM: 8864/1: Add workaround for I-Cache line size mismatch between CPU cores"), which adds workaround for different l1 icache line size between big and little CPUs. This workaround gets enabled on all Exynos542x/5800 boards.

Ok, I have just referred to the Exynos 5422 user manual for this patch, This patch is just updating the cache size for CPU for big.litle architecture..

Let me get it right. Marek's comment was that you used wrong values. Marek also provided rationale for this. Now your reply is that you update cache size? Sorry, I fail how you address Marek's comment.

Do not repeat what the patch is doing. We all can see it. Instead respond to the comment with some sort of arguments.

Best regards,
Krzysztof

Hi Krzysztof,

Quoted 37 lines · Krzysztof Kozlowski

Quoted 25 lines · Anand Moon

Hi Marek,

Quoted 22 lines · Marek Szyprowski

Quoted 17 lines · Anand Moon

As per Exynos 5422 user manual add missing cache information to the Exynos542x SoC.

- Each Cortex-A7 core has 32 KB of instruction cache and 32 KB of L1 data cache available.
- Each Cortex-A15 core has 32 KB of L1 instruction cache and 32 KB of L1 data cache available.
- The little (A7) cluster has 512 KB of unified L2 cache available.
- The big (A15) cluster has 2 MB of unified L2 cache available.

Features:
- Exynos 5422 support cache coherency interconnect (CCI) bus with L2 cache snooping capability. This hardware automatic L2 cache snooping removes the efforts of synchronizing the contents of the two L2 caches in core switching event.

Signed-off-by Anand Moon <[email protected]>

Quoted 9 lines

Quoted 6 lines

The provided values are not correct. Please refer to commit 5f41f9198f29 ("ARM: 8864/1: Add workaround for I-Cache line size mismatch between CPU cores"), which adds workaround for different l1 icache line size between big and little CPUs. This workaround gets enabled on all Exynos542x/5800 boards.

Ok, I have just referred to the Exynos 5422 user manual for this patch, This patch is just updating the cache size for CPU for big.litle architecture..

Quoted 7 lines

Let me get it right. Marek's comment was that you used wrong values. Marek also provided rationale for this. Now your reply is that you update cache size? Sorry, I fail how you address Marek's comment.

Do not repeat what the patch is doing. We all can see it. Instead respond to the comment with some sort of arguments.

Ok, If I am not wrong icache_size is hard-coded in the above commit.

(quoted diff) +8 -0

+#ifdef CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND
+.globl icache_size
+       .data
+       .align  2
+icache_size:
+       .long   64
+       .text
+#endif

In the check_cpu_icache_size function, we read the control reg and recalculate the icache_size.
if there mismatch we re-apply the Icache_size,

So dts passed values do not apply over here,

Quoted 59 lines · Anand Moon

Hi Krzysztof,

Quoted 37 lines · Krzysztof Kozlowski

Quoted 25 lines · Anand Moon

Hi Marek,

Quoted 22 lines · Marek Szyprowski

Quoted 17 lines · Anand Moon

As per the Exynos 5422 user manual add missing cache information to the Exynos542x SoC.

- Each Cortex-A7 core has 32 KB of instruction cache and 32 KB of L1 data cache available.
- Each Cortex-A15 core has 32 KB of L1 instruction cache and 32 KB of L1 data cache available.
- The little (A7) cluster has 512 KB of unified L2 cache available.
- The big (A15) cluster has 2 MB of unified L2 cache available.

Features:
- Exynos 5422 support cache coherency interconnect (CCI) bus with L2 cache snooping capability. This hardware automatic L2 cache snooping removes the efforts of synchronizing the contents of the two L2 caches in core switching event.

Signed-off-by Anand Moon <[email protected]>

Quoted 9 lines

Quoted 6 lines

The provided values are not correct. Please refer to commit 5f41f9198f29 ("ARM: 8864/1: Add workaround for I-Cache line size mismatch between CPU cores"), which adds workaround for different l1 icache line size between big and little CPUs. This workaround gets enabled on all Exynos542x/5800 boards.

Ok, I have just referred to the Exynos 5422 user manual for this patch, This patch is just updating the cache size for CPU for big.litle architecture..

Quoted 7 lines

Let me get it right. Marek's comment was that you used wrong values. Marek also provided rationale for this. Now your reply is that you update cache size? Sorry, I fail how you address Marek's comment.

Do not repeat what the patch is doing. We all can see it. Instead respond to the comment with some sort of arguments.

Ok, If I am not wrong icache_size is hard-coded in the above commit.

(quoted diff) +8 -0

+#ifdef CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND
+.globl icache_size
+       .data
+       .align  2
+icache_size:
+       .long   64
+       .text
+#endif

Quoted 5 lines

In the check_cpu_icache_size function, we read the control reg and recalculate the icache_size.
if there mismatch we re-apply the Icache_size,

So dts passed values do not apply over here,

So you provide incorrect values in terms of them being ignored? Then do not provide at all.

Best regards,
Krzysztof

Hi Krzysztof,

Quoted 61 lines · Krzysztof Kozlowski

Quoted 59 lines · Anand Moon

Hi Krzysztof,

Quoted 37 lines · Krzysztof Kozlowski

Quoted 25 lines · Anand Moon

Hi Marek,

Quoted 22 lines · Marek Szyprowski

Quoted 17 lines · Anand Moon

As per the Exynos 5422 user manual add missing cache information to the Exynos542x SoC.

- Each Cortex-A7 core has 32 KB of instruction cache and 32 KB of L1 data cache available.
- Each Cortex-A15 core has 32 KB of L1 instruction cache and 32 KB of L1 data cache available.
- The little (A7) cluster has 512 KB of unified L2 cache available.
- The big (A15) cluster has 2 MB of unified L2 cache available.

Features:
- Exynos 5422 support cache coherency interconnect (CCI) bus with L2 cache snooping capability. This hardware automatic L2 cache snooping removes the efforts of synchronizing the contents of the two L2 caches in core switching event.

Signed-off-by Anand Moon <[email protected]>

Quoted 9 lines

Quoted 6 lines

The provided values are not correct. Please refer to commit 5f41f9198f29 ("ARM: 8864/1: Add workaround for I-Cache line size mismatch between CPU cores"), which adds workaround for different l1 icache line size between big and little CPUs. This workaround gets enabled on all Exynos542x/5800 boards.

Ok, I have just referred to the Exynos 5422 user manual for this patch, This patch is just updating the cache size for CPU for big.litle architecture..

Quoted 7 lines

Let me get it right. Marek's comment was that you used wrong values. Marek also provided rationale for this. Now your reply is that you update cache size? Sorry, I fail how you address Marek's comment.

Do not repeat what the patch is doing. We all can see it. Instead respond to the comment with some sort of arguments.

Ok, If I am not wrong icache_size is hard-coded in the above commit.

(quoted diff) +8 -0

+#ifdef CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND
+.globl icache_size
+       .data
+       .align  2
+icache_size:
+       .long   64
+       .text
+#endif

Quoted 9 lines

Quoted 5 lines

In the check_cpu_icache_size function, we read the control reg and recalculate the icache_size.
if there mismatch we re-apply the Icache_size,

So dts passed values do not apply over here,

So you provide incorrect values in terms of them being ignored? Then do not provide at all.

I will drop the icache and dcache values and just pass the L2_a7 and L2_a15, value
Is this ok for you?

Earlier, I have tried to verify this information in /sys and /proc to verify the changes as ARM does not populate this information.

Quoted 20 lines

Quoted 20 lines

Quoted 20 lines

Quoted 20 lines

Quoted 20 lines

Quoted 20 lines · Anand Moon

Quoted 17 lines

As per the Exynos 5422 user manual add missing cache information to the Exynos542x SoC.

- Each Cortex-A7 core has 32 KB of instruction cache and 32 KB of L1 data cache available.
- Each Cortex-A15 core has 32 KB of L1 instruction cache and 32 KB of L1 data cache available.
- The little (A7) cluster has 512 KB of unified L2 cache available.
- The big (A15) cluster has 2 MB of unified L2 cache available.

Features:
- Exynos 5422 support cache coherency interconnect (CCI) bus with L2 cache snooping capability. This hardware automatic L2 cache snooping removes the efforts of synchronizing the contents of the two L2 caches in core switching event.

Signed-off-by Anand Moon <[email protected]>

Quoted 8 lines

Quoted 8 lines

Quoted 8 lines

Quoted 8 lines

Quoted 8 lines

Quoted 6 lines

The provided values are not correct. Please refer to commit 5f41f9198f29 ("ARM: 8864/1: Add workaround for I-Cache line size mismatch between CPU cores"), which adds workaround for different l1 icache line size between big and little CPUs. This workaround gets enabled on all Exynos542x/5800 boards.

Ok, I have just referred to the Exynos 5422 user manual for this patch, This patch is just updating the cache size for CPU for big.litle architecture..

Here's an article that provides detailed insights into the cache feature.
[0] http://jake.dothome.co.kr/cache4/

The values associated with L1 and L2 caches indicate their respective sizes, as specified in the ARM Technical Reference Manual (TRM) below.

Cortex-A15 L2 cache controller
[0] https://developer.arm.com/documentation/ddi0503/i/programmers-model/programmable-peripherals-and-interfaces/cortex-a15-l2-cache-controller

Cortex-A7 L2 cache controller
[1] https://developer.arm.com/documentation/ddi0503/i/programmers-model/programmable-peripherals-and-interfaces/cortex-a7-l2-cache-controller

These changes help define a fixed cache size, ensuring that active pages are mapped correctly within the expected cache boundaries.

Here is the small test case using perf
Before

$ sudo perf stat -e L1-dcache-loads,L1-dcache-load-misses ./fact

Simulated Cache Miss Time (avg): 4766632 ns
Factorial(10) = 3628800

Performance counter stats for './fact':

            926328      armv7_cortex_a15/L1-dcache-loads/
     <not counted>      armv7_cortex_a7/L1-dcache-loads/
                         (0.00%)
             16510      armv7_cortex_a15/L1-dcache-load-misses/ #
1.78% of all L1-dcache accesses
     <not counted>      armv7_cortex_a7/L1-dcache-load-misses/
                               (0.00%)

       0.008970031 seconds time elapsed

       0.000000000 seconds user
       0.009673000 seconds sys

After

$ sudo perf stat -e L1-dcache-loads,L1-dcache-load-misses ./fact
Simulated Cache Miss Time (avg): 4623272 ns
Factorial(10) = 3628800

Performance counter stats for './fact':

            930570      armv7_cortex_a15/L1-dcache-loads/
     <not counted>      armv7_cortex_a7/L1-dcache-loads/
                         (0.00%)
              4755      armv7_cortex_a15/L1-dcache-load-misses/ #
0.51% of all L1-dcache accesses
     <not counted>      armv7_cortex_a7/L1-dcache-load-misses/
                               (0.00%)

       0.011068250 seconds time elapsed

       0.000000000 seconds user
       0.010793000 seconds sys

Hi Krzysztof, Marek,

Quoted 78 lines · Anand Moon

Hi Krzysztof,

Quoted 61 lines · Krzysztof Kozlowski

Quoted 59 lines · Anand Moon

Hi Krzysztof,

Quoted 37 lines · Krzysztof Kozlowski

Quoted 25 lines · Anand Moon

Hi Marek,

Quoted 22 lines · Marek Szyprowski

Quoted 17 lines · Anand Moon

As per the Exynos 5422 user manual add missing cache information to the Exynos542x SoC.

- Each Cortex-A7 core has 32 KB of instruction cache and 32 KB of L1 data cache available.
- Each Cortex-A15 core has 32 KB of L1 instruction cache and 32 KB of L1 data cache available.
- The little (A7) cluster has 512 KB of unified L2 cache available.
- The big (A15) cluster has 2 MB of unified L2 cache available.

Features:
- Exynos 5422 support cache coherency interconnect (CCI) bus with L2 cache snooping capability. This hardware automatic L2 cache snooping removes the efforts of synchronizing the contents of the two L2 caches in core switching event.

Signed-off-by Anand Moon <[email protected]>

Quoted 9 lines

Quoted 6 lines

The provided values are not correct. Please refer to commit 5f41f9198f29 ("ARM: 8864/1: Add workaround for I-Cache line size mismatch between CPU cores"), which adds workaround for different l1 icache line size between big and little CPUs. This workaround gets enabled on all Exynos542x/5800 boards.

Ok, I have just referred to the Exynos 5422 user manual for this patch, This patch is just updating the cache size for CPU for big.litle architecture..

Quoted 7 lines

Let me get it right. Marek's comment was that you used wrong values. Marek also provided rationale for this. Now your reply is that you update cache size? Sorry, I fail how you address Marek's comment.

Do not repeat what the patch is doing. We all can see it. Instead respond to the comment with some sort of arguments.

Ok, If I am not wrong icache_size is hard-coded in the above commit.

(quoted diff) +8 -0

+#ifdef CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND
+.globl icache_size
+       .data
+       .align  2
+icache_size:
+       .long   64
+       .text
+#endif

Quoted 9 lines

Quoted 5 lines

In the check_cpu_icache_size function, we read the control reg and recalculate the icache_size.
if there mismatch we re-apply the Icache_size,

So dts passed values do not apply over here,

So you provide incorrect values in terms of them being ignored? Then do not provide at all.

I will drop the icache and dcache values and just pass the L2_a7 and L2_a15, value
Is this ok for you?

Quoted 3 lines

Earlier, I have tried to verify this information in /sys and /proc to verify the changes as ARM does not populate this information.

Here's an article that provides detailed insights into the cache feature.
[0] http://jake.dothome.co.kr/cache4/

The values associated with L1 and L2 caches indicate their respective sizes, as specified in the ARM Technical Reference Manual (TRM) below.

Cortex-A15 L2 cache controller
[0] https://developer.arm.com/documentation/ddi0503/i/programmers-model/programmable-peripherals-and-interfaces/cortex-a15-l2-cache-controller

Cortex-A7 L2 cache controller
[1] https://developer.arm.com/documentation/ddi0503/i/programmers-model/programmable-peripherals-and-interfaces/cortex-a7-l2-cache-controller

These changes help define a fixed cache size, ensuring that active pages are mapped correctly within the expected cache boundaries.

Quoted 84 lines · Anand Moon

Hi Krzysztof, Marek,

Quoted 81 lines · Anand Moon

Hi Krzysztof,

Quoted 61 lines · Krzysztof Kozlowski

Quoted 59 lines · Anand Moon

Hi Krzysztof,

Quoted 37 lines · Krzysztof Kozlowski

Quoted 25 lines · Anand Moon

Hi Marek,

Quoted 22 lines · Marek Szyprowski

Quoted 17 lines · Anand Moon

As per the Exynos 5422 user manual add missing cache information to the Exynos542x SoC.

- Each Cortex-A7 core has 32 KB of instruction cache and 32 KB of L1 data cache available.
- Each Cortex-A15 core has 32 KB of L1 instruction cache and 32 KB of L1 data cache available.
- The little (A7) cluster has 512 KB of unified L2 cache available.
- The big (A15) cluster has 2 MB of unified L2 cache available.

Features:
- Exynos 5422 support cache coherency interconnect (CCI) bus with L2 cache snooping capability. This hardware automatic L2 cache snooping removes the efforts of synchronizing the contents of the two L2 caches in core switching event.

Signed-off-by Anand Moon <[email protected]>

Quoted 9 lines

Quoted 6 lines

The provided values are not correct. Please refer to commit 5f41f9198f29 ("ARM: 8864/1: Add workaround for I-Cache line size mismatch between CPU cores"), which adds workaround for different l1 icache line size between big and little CPUs. This workaround gets enabled on all Exynos542x/5800 boards.

Ok, I have just referred to the Exynos 5422 user manual for this patch, This patch is just updating the cache size for CPU for big.litle architecture..

Quoted 7 lines

Let me get it right. Marek's comment was that you used wrong values. Marek also provided rationale for this. Now your reply is that you update cache size? Sorry, I fail how you address Marek's comment.

Do not repeat what the patch is doing. We all can see it. Instead respond to the comment with some sort of arguments.

Ok, If I am not wrong icache_size is hard-coded in the above commit.

(quoted diff) +8 -0

+#ifdef CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND
+.globl icache_size
+       .data
+       .align  2
+icache_size:
+       .long   64
+       .text
+#endif

Quoted 9 lines

Quoted 5 lines

In the check_cpu_icache_size function, we read the control reg and recalculate the icache_size.
if there mismatch we re-apply the Icache_size,

So dts passed values do not apply over here,

So you provide incorrect values in terms of them being ignored? Then do not provide at all.

I will drop the icache and dcache values and just pass the L2_a7 and L2_a15, value
Is this ok for you?

Earlier, I have tried to verify this information in /sys and /proc to verify the changes as ARM does not populate this information.

Quoted 2 lines

Here's an article that provides detailed insights into the cache feature.
[0] http://jake.dothome.co.kr/cache4/

Here is Korean Wikipedia article about Sugar glider:
https://ko.wikipedia.org/wiki/%EC%9C%A0%EB%8C%80%ED%95%98%EB%8A%98%EB%8B%A4%EB%9E%8C%EC%A5%90

I guess we are putting now random references in Korean to our emails.

Quoted 5 lines

The values associated with L1 and L2 caches indicate their respective sizes, as specified in the ARM Technical Reference Manual (TRM) below.

Quoted 8 lines

Cortex-A15 L2 cache controller
[0] https://developer.arm.com/documentation/ddi0503/i/programmers-model/programmable-peripherals-and-interfaces/cortex-a15-l2-cache-controller

Cortex-A7 L2 cache controller
[1] https://developer.arm.com/documentation/ddi0503/i/programmers-model/programmable-peripherals-and-interfaces/cortex-a7-l2-cache-controller

These changes help define a fixed cache size, ensuring that active pages are mapped correctly within the expected cache boundaries.

As with many previous attempts, you do not understand comments and questions and you do not reply to them. This makes conversation pointless.

To prove it:

1. No one asks for performance numbers.
2. You give performance numbers.

I am dropping this patch because you did not address actual comments. I also do not plan to give thorough review to other of your patches, because you wasted a lot of my time in the past and this example here proves you keep wasting.

Best regards,
Krzysztof