Add support for RaspberryPi RP1 PCI device using a DT overlay
Subsystems (8)
Andrea della Porta
maintainerv12 cover Add support for RaspberryPi RP1 PCI device using a DT overlay
*** RESENDING PATCHSET AS V12 SINCE LAST ONE HAS CLOBBERED EMAIL Message-Id ***
RP1 is an MFD chipset that acts as a south-bridge PCIe endpoint sporting a pletora of subdevices (i.e. Ethernet, USB host controller, I2C, PWM, etc.) whose registers are all reachable starting from an offset from the BAR address. The main point here is that while the RP1 as an endpoint itself is discoverable via usual PCI enumeraiton, the devices it contains are not discoverable and must be declared e.g. via the devicetree.
This patchset is an attempt to provide a minimum infrastructure to allow the RP1 chipset to be discovered and perpherals it contains to be added from a devictree overlay loaded during RP1 PCI endpoint enumeration. To ensure compatibility with downstream, a devicetree already comprising the RP1 node is also provided, so it's not strictly necessary to use the dynamically loaded overlay if the devicetree is already fully defined at the origin.
To achieve this modularity, the RP1 node DT definitions are arranged by file inclusion as per following schema (the arrow points to the includer, see also [9]):
rp1-pci.dtso rp1.dtso
^ ^
| |rp1-common.dtsi ----> rp1-nexus.dtsi ----> bcm2712-rpi-5-b.dts
^
|
bcm2712-rpi-5-b-ovl-rp1.dtsFollowup patches should add support for the several peripherals contained in RP1.
This work is based upon dowstream drivers code and the proposal from RH et al. (see [1] and [2]). A similar approach is also pursued in [3].
The patches are ordered as follows:
-PATCHES 1 to 3: add binding schemas for clock, gpio and RP1 peripherals.
They are needed to support the other peripherals, e.g. the ethernet mac depends on a clock generated by RP1 and the phy is reset through the on-board gpio controller.
-PATCH 4 and 5: add clock and gpio device drivers.
-PATCH 6: the devicetree node describing the RP1 chipset.
-PATCH 7: this is the main patch to support RP1 chipset. It can work
either with a fully defined devicetree (i.e. one that already included the rp1 node since boot time) or with a runtime loaded dtb overlay which is linked as binary blob in the driver obj. This duality is useful to comply with both downstream and upstream needs (see [9]). The real dtso is in devicetree folder while the dtso in driver folder is just a placeholder to include the real dtso.
In this way it is possible to check the dtso against dt-bindings. The reason why drivers/misc has been selected as containing folder for this driver can be seen in [6], [7] and [8].
-PATCH 8: add the external clock node (used by RP1) to the main dts.
-PATCH 9: the fully fledged devictree containing also the rp1 node.
This devicetree is functionally similar to the one downstream is using.
-PATCH 10 (OPTIONAL): this patch introduces a new scenario about how
the rp1 node is specified and loaded in DT. On top of the base DT (without rp1 node), the fw loads this overlay and the end result is the same devicetree as in patch 9, which is then passed to the next stage (either the kernel or u-boot/bootloader).
While this patch is not strictly necessary and can therefore be dropped (see [10]), it's not introducing much extra work and maybe can come in handy while debugging.
-PATCH 11: add the relevant kernel CONFIG_ options to defconfig.
-PATCH 12: enable CONFIG_OF_OVERLAY in order for 'make defconfig'
to produce a configuration valid for the RP1 driver. Without this patch, the user has to explicitly enable it since the misc driver depends on OF_OVERLAY.
-PATCH 13: collect all changes for MAINTAINERS file.
This patchset is also a first attempt to be more agnostic wrt hardware description standards such as OF devicetree and ACPI, where 'agnostic' means "using DT in coexistence with ACPI", as been already promoted by e.g. AL (see [4]). Although there's currently no evidence it will also run out of the box on purely ACPI system, it is a first step towards that direction.
Many thanks,
Andrea della Porta
Links:
- [1]: https://lpc.events/event/17/contributions/1421/attachments/1337/2680/LPC2023%20Non-discoverable%20devices%20in%20PCI.pdf
- [2]: https://lore.kernel.org/lkml/[email protected]/t/
- [3]: https://lore.kernel.org/all/[email protected]/#t
- [4]: https://lore.kernel.org/all/[email protected]/
- [5]: https://lore.kernel.org/all/[email protected]/
- [6]: https://lore.kernel.org/all/[email protected]/
- [7]: https://lore.kernel.org/all/[email protected]/
- [8]: https://lore.kernel.org/all/2024081356-mutable-everyday-6f9d@gregkh/
- [9]: https://lore.kernel.org/all/Z87wTfChRC5Ruwc0@apocalypse/
- [10]: https://lore.kernel.org/all/CAMEGJJ0f4YUgdWBhxvQ_dquZHztve9KO7pvQjoDWJ3=zd3cgcg@mail.gmail.com/#t
CHANGES IN V12 VERSUS V9
PATCH RELATED -------------------------------------------------
- Patch 10,11,12: Added: Reviewed-by: Reviewed-by: Florian Fainelli <[email protected]>
- Patches reworked to apply cleanly on broadcom/stblinux branches:
patch 1,2,3,6,8,9,10 -> devicetree/next
patch 11,12 -> defconfig/next
patch 4,5,7 -> drivers/next
patch 13 -> maintainers/next
- Patch 13: new patch gathering all changes for MAINTAINERS
- Patch 7: Added: Acked-by: Greg Kroah-Hartman <[email protected]>
RP1 CLOCK DRIVER ------------------------------------
- Dropped some WARN_ONCE() lines that are basically useless
- rp1_clock_set_parent() now returns EINVAL in case the parent check is failing. As a result, rp1_clock_set_rate_and_parent() has also been adapted to return rp1_clock_set_parent() retcode.
- Return an ERR_PTR from rp1_register_clock() instead of just NULL
- Dropped some unaesthetic blank lines
- Disabled the builtin locking in regmap since we're already dealing with concurrency in the code
- rp1_clk_probe(): dropped dev_err_probe() as redundant due to commit 12a0fd23e870 ("clk: Print an error when clk registration fails")
Andrea della Porta
maintainerPATCH v12 1/13 dt-bindings: clock: Add RaspberryPi RP1 clock bindings
Add device tree bindings for the clock generator found in RP1 multi function device, and relative entries in MAINTAINERS file.
--- .../clock/raspberrypi,rp1-clocks.yaml | 58 ++++++++++++++++++ .../clock/raspberrypi,rp1-clocks.h | 61 +++++++++++++++++++ 2 files changed, 119 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/raspberrypi,rp1-clocks.yaml create mode 100644 include/dt-bindings/clock/raspberrypi,rp1-clocks.h
Documentation/devicetree/bindings/clock/raspberrypi,rp1-clocks.yaml new file +58 -0
@@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/raspberrypi,rp1-clocks.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RaspberryPi RP1 clock generator + +maintainers: + - A. della Porta <[email protected]> + +description: | + The RP1 contains a clock generator designed as three PLLs (CORE, AUDIO, + VIDEO), and each PLL output can be programmed through dividers to generate + the clocks to drive the sub-peripherals embedded inside the chipset. + + Link to datasheet: + https://datasheets.raspberrypi.com/rp1/rp1-peripherals.pdf + +properties: + compatible: + const: raspberrypi,rp1-clocks + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + description: + The available clocks are defined in + include/dt-bindings/clock/raspberrypi,rp1-clocks.h. + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - '#clock-cells' + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/raspberrypi,rp1-clocks.h> + + rp1 { + #address-cells = <2>; + #size-cells = <2>; + + clocks@c040018000 { + compatible = "raspberrypi,rp1-clocks"; + reg = <0xc0 0x40018000 0x0 0x10038>; + #clock-cells = <1>; + clocks = <&clk_rp1_xosc>; + }; + };
include/dt-bindings/clock/raspberrypi,rp1-clocks.h new file +61 -0
61 lines not on this page · raw message
Signature · 1 line
2.35.3
Re: [PATCH v12 01/13] dt-bindings: clock: Add RaspberryPi RP1 clock bindings
From: Florian Fainelli <[email protected]>
Quoted 7 lines · Andrea della Porta
Add device tree bindings for the clock generator found in RP1 multi function device, and relative entries in
MAINTAINERSfile.Signed-off-by Andrea della Porta <[email protected]>Reviewed-by Krzysztof Kozlowski <[email protected]>Reviewed-by Florian Fainelli <[email protected]>---
Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, thanks! --
Florian
Andrea della Porta
maintainerPATCH v12 2/13 dt-bindings: pinctrl: Add RaspberryPi RP1 gpio/pinctrl/pinmux bindings
In reply to Andrea della PortaAdd device tree bindings for the gpio/pin/mux controller that is part of the RP1 multi function device, and relative entries in MAINTAINERS file.
--- .../pinctrl/raspberrypi,rp1-gpio.yaml | 198 ++++++++++++++++++ 1 file changed, 198 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/raspberrypi,rp1-gpio.yaml
Documentation/devicetree/bindings/pinctrl/raspberrypi,rp1-gpio.yaml new file +198 -0
@@ -0,0 +1,198 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/raspberrypi,rp1-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RaspberryPi RP1 GPIO/Pinconf/Pinmux Controller submodule + +maintainers: + - A. della Porta <[email protected]> + +description: + The RP1 chipset is a Multi Function Device containing, among other + sub-peripherals, a gpio/pinconf/mux controller whose 54 pins are grouped + into 3 banks. + It works also as an interrupt controller for those gpios. + +properties: + compatible: + const: raspberrypi,rp1-gpio + + reg: + maxItems: 3 + description: One reg specifier for each one of the 3 pin banks. + + '#gpio-cells': + description: The first cell is the pin number and the second cell is used + to specify the flags (see include/dt-bindings/gpio/gpio.h). + const: 2 + + gpio-controller: true + + gpio-ranges: + maxItems: 1 + + gpio-line-names: + maxItems: 54 + + interrupts: + maxItems: 3 + description: One interrupt specifier for each one of the 3 pin banks. + + '#interrupt-cells': + description: + Specifies the Bank number [0, 1, 2] and Flags as defined in + include/dt-bindings/interrupt-controller/irq.h. + const: 2 + + interrupt-controller: true + +patternProperties: + '-state$': + oneOf: + - $ref: '#/$defs/raspberrypi-rp1-state' + - patternProperties: + '-pins$': + $ref: '#/$defs/raspberrypi-rp1-state' + additionalProperties: false + +$defs: + raspberrypi-rp1-state: + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + description: + Pin controller client devices use pin configuration subnodes (children + and grandchildren) for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: '^gpio([0-9]|[1-4][0-9]|5[0-3])$' + + function: + enum: [ alt0, alt1, alt2, alt3, alt4, gpio, alt6, alt7, alt8, none, + aaud, dcd0, dpi, dsi0_te_ext, dsi1_te_ext, dsr0, dtr0, gpclk0, + gpclk1, gpclk2, gpclk3, gpclk4, gpclk5, i2c0, i2c1, i2c2, i2c3, + i2c4, i2c5, i2c6, i2s0, i2s1, i2s2, ir, mic, pcie_clkreq_n, + pio, proc_rio, pwm0, pwm1, ri0, sd0, sd1, spi0, spi1, spi2, + spi3, spi4, spi5, spi6, spi7, spi8, uart0, uart1, uart2, uart3, + uart4, uart5, vbus0, vbus1, vbus2, vbus3 ] + + description: + Specify the alternative function to be configured for the specified + pins. + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + input-enable: true + input-schmitt-enable: true + output-enable: true + output-high: true + output-low: true + slew-rate: + description: 0 is slow slew rate, 1 is fast slew rate + enum: [ 0, 1 ] + drive-strength: + enum: [ 2, 4, 8, 12 ] + + additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + +required: + - reg + - compatible + - '#gpio-cells' + - gpio-controller + - interrupts + - '#interrupt-cells' + - interrupt-controller + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + rp1 { + #address-cells = <2>; + #size-cells = <2>; + + rp1_gpio: pinctrl@c0400d0000 { + reg = <0xc0 0x400d0000 0x0 0xc000>, + <0xc0 0x400e0000 0x0 0xc000>, + <0xc0 0x400f0000 0x0 0xc000>; + compatible = "raspberrypi,rp1-gpio"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, + <1 IRQ_TYPE_LEVEL_HIGH>, + <2 IRQ_TYPE_LEVEL_HIGH>; + gpio-line-names = + "ID_SDA", // GPIO0 + "ID_SCL", // GPIO1 + "GPIO2", "GPIO3", "GPIO4", "GPIO5", "GPIO6", + "GPIO7", "GPIO8", "GPIO9", "GPIO10", "GPIO11", + "GPIO12", "GPIO13", "GPIO14", "GPIO15", "GPIO16", + "GPIO17", "GPIO18", "GPIO19", "GPIO20", "GPIO21", + "GPIO22", "GPIO23", "GPIO24", "GPIO25", "GPIO26", + "GPIO27", + "PCIE_RP1_WAKE", // GPIO28 + "FAN_TACH", // GPIO29 + "HOST_SDA", // GPIO30 + "HOST_SCL", // GPIO31 + "ETH_RST_N", // GPIO32 + "", // GPIO33 + "CD0_IO0_MICCLK", // GPIO34 + "CD0_IO0_MICDAT0", // GPIO35 + "RP1_PCIE_CLKREQ_N", // GPIO36 + "", // GPIO37 + "CD0_SDA", // GPIO38 + "CD0_SCL", // GPIO39 + "CD1_SDA", // GPIO40 + "CD1_SCL", // GPIO41 + "USB_VBUS_EN", // GPIO42 + "USB_OC_N", // GPIO43 + "RP1_STAT_LED", // GPIO44 + "FAN_PWM", // GPIO45 + "CD1_IO0_MICCLK", // GPIO46 + "2712_WAKE", // GPIO47 + "CD1_IO1_MICDAT1", // GPIO48 + "EN_MAX_USB_CUR", // GPIO49 + "", // GPIO50 + "", // GPIO51 + "", // GPIO52 + ""; // GPIO53 + + rp1-i2s0-default-state { + function = "i2s0"; + pins = "gpio18", "gpio19", "gpio20", "gpio21"; + bias-disable; + }; + + rp1-uart0-default-state { + txd-pins { + function = "uart0"; + pins = "gpio14"; + bias-disable; + }; + + rxd-pins { + function = "uart0"; + pins = "gpio15"; + bias-pull-up; + }; + }; + }; + };
Signature · 1 line
2.35.3
Re: [PATCH v12 02/13] dt-bindings: pinctrl: Add RaspberryPi RP1 gpio/pinctrl/pinmux bindings
From: Florian Fainelli <[email protected]>
Quoted 8 lines · Andrea della Porta
Add device tree bindings for the gpio/pin/mux controller that is part of the RP1 multi function device, and relative entries in
MAINTAINERSfile.Signed-off-by Andrea della Porta <[email protected]>Reviewed-by Krzysztof Kozlowski <[email protected]>Reviewed-by Linus Walleij <[email protected]>Reviewed-by Florian Fainelli <[email protected]>---
Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, thanks! --
Florian
Andrea della Porta
maintainerPATCH v12 3/13 dt-bindings: misc: Add device specific bindings for RaspberryPi RP1
In reply to Andrea della PortaThe RP1 is a MFD that exposes its peripherals through PCI BARs. This schema is intended as minimal support for the clock generator and gpio controller peripherals which are accessible through BAR1.
--- .../devicetree/bindings/misc/pci1de4,1.yaml | 137 ++++++++++++++++++ 1 file changed, 137 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/pci1de4,1.yaml
Documentation/devicetree/bindings/misc/pci1de4,1.yaml new file +137 -0
@@ -0,0 +1,137 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/pci1de4,1.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RaspberryPi RP1 MFD PCI device + +maintainers: + - A. della Porta <[email protected]> + +description: + The RaspberryPi RP1 is a PCI multi function device containing + peripherals ranging from Ethernet to USB controller, I2C, SPI + and others. + The peripherals are accessed by addressing the PCI BAR1 region. + +allOf: + - $ref: /schemas/pci/pci-ep-bus.yaml + +properties: + compatible: + additionalItems: true + maxItems: 3 + items: + - const: pci1de4,1 + + '#interrupt-cells': + const: 2 + description: | + Specifies respectively the interrupt number and flags as defined + in include/dt-bindings/interrupt-controller/irq.h. + Since all interrupts are active high, only IRQ_TYPE_LEVEL_HIGH + and IRQ_TYPE_EDGE_RISING can be specified as type flags. + The supported values for the interrupt number are: + - IO BANK0: 0 + - IO BANK1: 1 + - IO BANK2: 2 + - AUDIO IN: 3 + - AUDIO OUT: 4 + - PWM0: 5 + - ETH: 6 + - I2C0: 7 + - I2C1: 8 + - I2C2: 9 + - I2C3: 10 + - I2C4: 11 + - I2C5: 12 + - I2C6: 13 + - I2S0: 14 + - I2S1: 15 + - I2S2: 16 + - SDIO0: 17 + - SDIO1: 18 + - SPI0: 19 + - SPI1: 20 + - SPI2: 21 + - SPI3: 22 + - SPI4: 23 + - SPI5: 24 + - UART0: 25 + - TIMER0: 26 + - TIMER1: 27 + - TIMER2: 28 + - TIMER3: 29 + - USB HOST0: 30 + - USB HOST0-0: 31 + - USB HOST0-1: 32 + - USB HOST0-2: 33 + - USB HOST0-3: 34 + - USB HOST1: 35 + - USB HOST1-0: 36 + - USB HOST1-1: 37 + - USB HOST1-2: 38 + - USB HOST1-3: 39 + - DMA: 40 + - PWM1: 41 + - UART1: 42 + - UART2: 43 + - UART3: 44 + - UART4: 45 + - UART5: 46 + - MIPI0: 47 + - MIPI1: 48 + - VIDEO OUT: 49 + - PIO0: 50 + - PIO1: 51 + - ADC FIFO: 52 + - PCIE OUT: 53 + - SPI6: 54 + - SPI7: 55 + - SPI8: 56 + - PROC MISC: 57 + - SYSCFG: 58 + - CLOCKS DEFAULT: 59 + - VBUSCTRL: 60 + + interrupt-controller: true + +unevaluatedProperties: false + +required: + - compatible + - '#interrupt-cells' + - interrupt-controller + - pci-ep-bus@1 + +examples: + - | + pci { + #address-cells = <3>; + #size-cells = <2>; + + rp1@0,0 { + compatible = "pci1de4,1"; + ranges = <0x01 0x00 0x00000000 0x82010000 0x00 0x00 0x00 0x400000>; + #address-cells = <3>; + #size-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + pci_ep_bus: pci-ep-bus@1 { + compatible = "simple-bus"; + ranges = <0x00 0x40000000 0x01 0x00 0x00000000 0x00 0x00400000>; + dma-ranges = <0x10 0x00000000 0x43000000 0x10 0x00000000 0x10 0x00000000>; + #address-cells = <2>; + #size-cells = <2>; + + rp1_clocks: clocks@40018000 { + compatible = "raspberrypi,rp1-clocks"; + reg = <0x00 0x40018000 0x0 0x10038>; + #clock-cells = <1>; + clocks = <&clk_rp1_xosc>; + }; + }; + }; + };
Signature · 1 line
2.35.3
Re: [PATCH v12 03/13] dt-bindings: misc: Add device specific bindings for RaspberryPi RP1
From: Florian Fainelli <[email protected]>
Quoted 8 lines · Andrea della Porta
The RP1 is a MFD that exposes its peripherals through PCI BARs. This schema is intended as minimal support for the clock generator and gpio controller peripherals which are accessible through BAR1.
Signed-off-by Andrea della Porta <[email protected]>Reviewed-by Rob Herring (Arm) <[email protected]>Reviewed-by Florian Fainelli <[email protected]>---
Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, thanks! --
Florian
Andrea della Porta
maintainerPATCH v12 4/13 clk: rp1: Add support for clocks provided by RP1
In reply to Andrea della PortaRaspberryPi RP1 is an MFD providing, among other peripherals, several clock generators and PLLs that drives the sub-peripherals. Add the driver to support the clock providers.
--- drivers/clk/Kconfig | 9 + drivers/clk/Makefile | 1 + drivers/clk/clk-rp1.c | 1494 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 1504 insertions(+) create mode 100644 drivers/clk/clk-rp1.c
drivers/clk/Kconfig +9 -0
@@ -88,6 +88,15 @@ config COMMON_CLK_RK808 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each. Clkout1 is always on, Clkout2 can off by control register. +config COMMON_CLK_RP1 + tristate "Raspberry Pi RP1-based clock support" + depends on MISC_RP1 || COMPILE_TEST + default MISC_RP1 + help + Enable common clock framework support for Raspberry Pi RP1. + This multi-function device has 3 main PLLs and several clock + generators to drive the internal sub-peripherals. + config COMMON_CLK_HI655X tristate "Clock driver for Hi655x" if EXPERT depends on (MFD_HI655X_PMIC || COMPILE_TEST)
drivers/clk/Makefile +1 -0
@@ -84,6 +84,7 @@ obj-$(CONFIG_CLK_LS1028A_PLLDIG) += clk-plldig.o obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o obj-$(CONFIG_CLK_QORIQ) += clk-qoriq.o obj-$(CONFIG_COMMON_CLK_RK808) += clk-rk808.o +obj-$(CONFIG_COMMON_CLK_RP1) += clk-rp1.o obj-$(CONFIG_COMMON_CLK_HI655X) += clk-hi655x.o obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o obj-$(CONFIG_COMMON_CLK_SCMI) += clk-scmi.o
drivers/clk/clk-rp1.c new file +1494 -0
1,494 lines not on this page · raw message
Signature · 1 line
2.35.3
Re: [PATCH v12 04/13] clk: rp1: Add support for clocks provided by RP1
From: Florian Fainelli <[email protected]>
Quoted 6 lines · Andrea della Porta
RaspberryPi RP1 is an MFD providing, among other peripherals, several clock generators and PLLs that drives the sub-peripherals. Add the driver to support the clock providers.
Signed-off-by Andrea della Porta <[email protected]>---
Applied to https://github.com/Broadcom/stblinux/commits/drivers/next, thanks! --
Florian
Andrea della Porta
maintainerPATCH v12 5/13 pinctrl: rp1: Implement RaspberryPi RP1 gpio support
In reply to Andrea della PortaThe RP1 is an MFD supporting a gpio controller and /pinmux/pinctrl. Add minimum support for the gpio only portion. The driver is in pinctrl folder since upcoming patches will add the pinmux/pinctrl support where the gpio part can be seen as an addition.
--- drivers/pinctrl/Kconfig | 11 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-rp1.c | 790 ++++++++++++++++++++++++++++++++++ 3 files changed, 802 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-rp1.c
drivers/pinctrl/Kconfig +11 -0
@@ -626,6 +626,17 @@ config PINCTRL_MLXBF3 each pin. This driver can also be built as a module called pinctrl-mlxbf3. +config PINCTRL_RP1 + tristate "Pinctrl driver for RP1" + depends on MISC_RP1 + default MISC_RP1 + select PINMUX + select PINCONF + select GENERIC_PINCONF + help + Enable the gpio and pinctrl/mux driver for RaspberryPi RP1 + multi function device. + source "drivers/pinctrl/actions/Kconfig" source "drivers/pinctrl/aspeed/Kconfig" source "drivers/pinctrl/bcm/Kconfig"
drivers/pinctrl/Makefile +1 -0
@@ -49,6 +49,7 @@ obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o +obj-$(CONFIG_PINCTRL_RP1) += pinctrl-rp1.o obj-$(CONFIG_PINCTRL_SCMI) += pinctrl-scmi.o obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o
drivers/pinctrl/pinctrl-rp1.c new file +790 -0
790 lines not on this page · raw message
Signature · 1 line
2.35.3
Re: [PATCH v12 05/13] pinctrl: rp1: Implement RaspberryPi RP1 gpio support
From: Florian Fainelli <[email protected]>
Quoted 9 lines · Andrea della Porta
The RP1 is an MFD supporting a gpio controller and /pinmux/pinctrl. Add minimum support for the gpio only portion. The driver is in pinctrl folder since upcoming patches will add the pinmux/pinctrl support where the gpio part can be seen as an addition.
Signed-off-by Andrea della Porta <[email protected]>Reviewed-by Linus Walleij <[email protected]>Reviewed-by Stefan Wahren <[email protected]>---
Applied to https://github.com/Broadcom/stblinux/commits/drivers/next, thanks! --
Florian
Andrea della Porta
maintainerPATCH v12 6/13 arm64: dts: rp1: Add support for RaspberryPi's RP1 device
In reply to Andrea della PortaRaspberryPi RP1 is a multi function PCI endpoint device that exposes several subperipherals via PCI BAR.
Add a dtb overlay that will be compiled into a binary blob and linked in the RP1 driver.
This overlay offers just minimal support to represent the RP1 device itself, the sub-peripherals will be added by future patches.
--- arch/arm64/boot/dts/broadcom/rp1-common.dtsi | 42 ++++++++++++++++++++ arch/arm64/boot/dts/broadcom/rp1-nexus.dtsi | 14 +++++++ 2 files changed, 56 insertions(+) create mode 100644 arch/arm64/boot/dts/broadcom/rp1-common.dtsi create mode 100644 arch/arm64/boot/dts/broadcom/rp1-nexus.dtsi
arch/arm64/boot/dts/broadcom/rp1-common.dtsi new file +42 -0
@@ -0,0 +1,42 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/clock/raspberrypi,rp1-clocks.h> + +pci_ep_bus: pci-ep-bus@1 { + compatible = "simple-bus"; + ranges = <0x00 0x40000000 0x01 0x00 0x00000000 0x00 0x00400000>; + dma-ranges = <0x10 0x00000000 0x43000000 0x10 0x00000000 0x10 0x00000000>; + #address-cells = <2>; + #size-cells = <2>; + + rp1_clocks: clocks@40018000 { + compatible = "raspberrypi,rp1-clocks"; + reg = <0x00 0x40018000 0x0 0x10038>; + #clock-cells = <1>; + clocks = <&clk_rp1_xosc>; + assigned-clocks = <&rp1_clocks RP1_PLL_SYS_CORE>, + <&rp1_clocks RP1_PLL_SYS>, + <&rp1_clocks RP1_PLL_SYS_SEC>, + <&rp1_clocks RP1_CLK_SYS>; + assigned-clock-rates = <1000000000>, // RP1_PLL_SYS_CORE + <200000000>, // RP1_PLL_SYS + <125000000>, // RP1_PLL_SYS_SEC + <200000000>; // RP1_CLK_SYS + }; + + rp1_gpio: pinctrl@400d0000 { + compatible = "raspberrypi,rp1-gpio"; + reg = <0x00 0x400d0000 0x0 0xc000>, + <0x00 0x400e0000 0x0 0xc000>, + <0x00 0x400f0000 0x0 0xc000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, + <1 IRQ_TYPE_LEVEL_HIGH>, + <2 IRQ_TYPE_LEVEL_HIGH>; + }; +};
arch/arm64/boot/dts/broadcom/rp1-nexus.dtsi new file +14 -0
@@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +rp1_nexus { + compatible = "pci1de4,1"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01 0x00 0x00000000 + 0x02000000 0x00 0x00000000 + 0x0 0x400000>; + interrupt-controller; + #interrupt-cells = <2>; + + #include "rp1-common.dtsi" +};
Signature · 1 line
2.35.3
Re: [PATCH v12 06/13] arm64: dts: rp1: Add support for RaspberryPi's RP1 device
From: Florian Fainelli <[email protected]>
Quoted 6 lines · Andrea della Porta
RaspberryPi RP1 is a multi function PCI endpoint device that exposes several subperipherals via PCI BAR.
Add a dtb overlay that will be compiled into a binary blob and linked in the RP1 driver.
Quoted 7 lines
This overlay offers just minimal support to represent the RP1 device itself, the sub-peripherals will be added by future patches.
Signed-off-by Andrea della Porta <[email protected]>Reviewed-by Florian Fainelli <[email protected]>---
Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, thanks! --
Florian
Andrea della Porta
maintainerPATCH v12 7/13 misc: rp1: RaspberryPi RP1 misc driver
In reply to Andrea della PortaThe RaspberryPi RP1 is a PCI multi function device containing peripherals ranging from Ethernet to USB controller, I2C, SPI and others.
Implement a bare minimum driver to operate the RP1, leveraging actual OF based driver implementations for the on-board peripherals by loading a devicetree overlay during driver probe if the RP1 node is not already present in the DT.
The peripherals are accessed by mapping MMIO registers starting from PCI BAR1 region.
With the overlay approach we can achieve more generic and agnostic approach to managing this chipset, being that it is a PCI endpoint and could possibly be reused in other hw implementations. The presented approach is also used by Bootlin's Microchip LAN966x patchset (see link) as well, for a similar chipset.
In this case, the inclusion tree for the DT overlay is as follow (the arrow points to the includer):
rp1-pci.dtso <---- rp1-common.dtsi
On the other hand, to ensure compatibility with downstream, this driver can also work with a DT already comprising the RP1 node, so the dynamically loaded overlay will not be used if the DT is already fully defined.
The reason why this driver is contained in drivers/misc has been paved by Bootlin's LAN966X driver, which first used the overlay approach to implement non discoverable peripherals behind a PCI bus. For RP1, the same arguments apply: it's not used as an SoC since the driver code is not running on-chip and is not like an MFD since it does not really need all the MFD infrastructure (shared regs, etc.). So, for this particular use, misc has been proposed and deemed as a good choice. For further details about that please check the links.
This driver is heavily based on downstream code from RaspberryPi Foundation, and the original author is Phil Elwell.
--- drivers/misc/Kconfig | 1 + drivers/misc/Makefile | 1 + drivers/misc/rp1/Kconfig | 20 ++ drivers/misc/rp1/Makefile | 3 + drivers/misc/rp1/rp1-pci.dtso | 25 +++ drivers/misc/rp1/rp1_pci.c | 333 ++++++++++++++++++++++++++++++++++ drivers/pci/quirks.c | 1 + include/linux/pci_ids.h | 3 + 8 files changed, 387 insertions(+) create mode 100644 drivers/misc/rp1/Kconfig create mode 100644 drivers/misc/rp1/Makefile create mode 100644 drivers/misc/rp1/rp1-pci.dtso create mode 100644 drivers/misc/rp1/rp1_pci.c
drivers/misc/Kconfig +1 -0
@@ -648,4 +648,5 @@ source "drivers/misc/uacce/Kconfig" source "drivers/misc/pvpanic/Kconfig" source "drivers/misc/mchp_pci1xxxx/Kconfig" source "drivers/misc/keba/Kconfig" +source "drivers/misc/rp1/Kconfig" endmenu
drivers/misc/Makefile +1 -0
@@ -74,3 +74,4 @@ lan966x-pci-objs := lan966x_pci.o lan966x-pci-objs += lan966x_pci.dtbo.o obj-$(CONFIG_MCHP_LAN966X_PCI) += lan966x-pci.o obj-y += keba/ +obj-$(CONFIG_MISC_RP1) += rp1/
drivers/misc/rp1/Kconfig new file +20 -0
@@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# RaspberryPi RP1 misc device +# + +config MISC_RP1 + tristate "RaspberryPi RP1 misc device" + depends on OF_IRQ && OF_OVERLAY && PCI_MSI && PCI_QUIRKS + select PCI_DYNAMIC_OF_NODES + help + Support the RP1 peripheral chip found on Raspberry Pi 5 board. + + This device supports several sub-devices including e.g. Ethernet + controller, USB controller, I2C, SPI and UART. + + The driver is responsible for enabling the DT node once the PCIe + endpoint has been configured, and handling interrupts. + + This driver uses an overlay to load other drivers to support for + RP1 internal sub-devices.
drivers/misc/rp1/Makefile new file +3 -0
@@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_MISC_RP1) += rp1-pci.o +rp1-pci-objs := rp1_pci.o rp1-pci.dtbo.o
drivers/misc/rp1/rp1-pci.dtso new file +25 -0
@@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/* + * The dts overlay is included from the dts directory so + * it can be possible to check it with CHECK_DTBS while + * also compile it from the driver source directory. + */ + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target-path=""; + __overlay__ { + compatible = "pci1de4,1"; + #address-cells = <3>; + #size-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + #include "arm64/broadcom/rp1-common.dtsi" + }; + }; +};
drivers/misc/rp1/rp1_pci.c new file +333 -0
333 lines not on this page · raw message
drivers/pci/quirks.c +1 -0
@@ -6284,6 +6284,7 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node);DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_XILINX ,0x5021 , of_pci_make_dev_node);DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_REDHAT ,0x0005 , of_pci_make_dev_node);DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_EFAR ,0x9660 , of_pci_make_dev_node); +DECLARE_PCI_FIXUP_FINAL (PCI_VENDOR_ID_RPI ,PCI_DEVICE_ID_RPI_RP1_C0 , of_pci_make_dev_node);/* * Devices known to require a longer delay before first config space access
include/linux/pci_ids.h +3 -0
@@ -2624,6 +2624,9 @@#define PCI_VENDOR_ID_TEKRAM 0x1de1#define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29 +#define PCI_VENDOR_ID_RPI 0x1de4 +#define PCI_DEVICE_ID_RPI_RP1_C0 0x0001 +#define PCI_VENDOR_ID_ALIBABA 0x1ded#define PCI_VENDOR_ID_CXL 0x1e98
Signature · 1 line
2.35.3
Re: [PATCH v12 07/13] misc: rp1: RaspberryPi RP1 misc driver
From: Florian Fainelli <[email protected]>
Quoted 45 lines · Andrea della Porta
The RaspberryPi RP1 is a PCI multi function device containing peripherals ranging from Ethernet to USB controller, I2C, SPI and others.
Implement a bare minimum driver to operate the RP1, leveraging actual OF based driver implementations for the on-board peripherals by loading a devicetree overlay during driver probe if the RP1 node is not already present in the DT.
The peripherals are accessed by mapping MMIO registers starting from PCI BAR1 region.
With the overlay approach we can achieve more generic and agnostic approach to managing this chipset, being that it is a PCI endpoint and could possibly be reused in other hw implementations. The presented approach is also used by Bootlin's Microchip LAN966x patchset (see link) as well, for a similar chipset.
In this case, the inclusion tree for the DT overlay is as follow (the arrow points to the includer):rp1-pci.dtso <----
rp1-common.dtsiOn the other hand, to ensure compatibility with downstream, this driver can also work with a DT already comprising the RP1 node, so the dynamically loaded overlay will not be used if the DT is already fully defined.
The reason why this driver is contained in
drivers/mischas been paved by Bootlin's LAN966X driver, which first used the overlay approach to implement non discoverable peripherals behind a PCI bus. For RP1, the same arguments apply: it's not used as an SoC since the driver code is not running on-chip and is not like an MFD since it does not really need all the MFD infrastructure (shared regs, etc.). So, for this particular use, misc has been proposed and deemed as a good choice. For further details about that please check the links.This driver is heavily based on downstream code from RaspberryPi Foundation, and the original author is Phil Elwell.
Quoted 4 lines
Signed-off-by Andrea della Porta <[email protected]>---
Applied to https://github.com/Broadcom/stblinux/commits/drivers/next, thanks! --
Florian
Andrea della Porta
maintainerPATCH v12 8/13 arm64: dts: bcm2712: Add external clock for RP1 chipset on Rpi5
In reply to Andrea della PortaThe RP1 found on Raspberry Pi 5 board needs an external crystal at 50MHz. Add clk_rp1_xosc node to provide that.
--- arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts | 7 +++++++ 1 file changed, 7 insertions(+)
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts +7 -0
@@ -16,6 +16,13 @@ chosen: chosen { stdout-path = "serial10:115200n8"; }; + clk_rp1_xosc: clock-50000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "rp1-xosc"; + clock-frequency = <50000000>; + }; + /* Will be filled by the bootloader */ memory@0 { device_type = "memory";
Signature · 1 line
2.35.3
Re: [PATCH v12 08/13] arm64: dts: bcm2712: Add external clock for RP1 chipset on Rpi5
From: Florian Fainelli <[email protected]>
Quoted 6 lines · Andrea della Porta
The RP1 found on Raspberry Pi 5 board needs an external crystal at 50MHz. Add
clk_rp1_xoscnode to provide that.Signed-off-by Andrea della Porta <[email protected]>Reviewed-by Florian Fainelli <[email protected]>---
Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, thanks! --
Florian
Andrea della Porta
maintainerPATCH v12 9/13 arm64: dts: broadcom: Add board DTS for Rpi5 which includes RP1 node
In reply to Andrea della PortaAdd the fully populated DTS for RaspberryPi 5 which includes the RP1 node definition. The inclusion tree is as follow (the arrow points to the includer):
rp1-common.dtsi ----> rp1-nexus.dtsi ----> bcm2712-rpi-5-b.dts
^
|
bcm2712-rpi-5-b-ovl-rp1.dtsThis is designed to maximize the compatibility with downstream DT while ensuring that a fully defined DT (one which includes the RP1 node as opposed to load it from overlay at runtime) is present since early boot stage.
Since the preferred board DT is the fully populated one, name it bcm2712-rpi-5-b.dts and move the previous one into bcm2712-rpi-5-b-ovl-rp1.dts.
--- arch/arm64/boot/dts/broadcom/Makefile | 1 + .../dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts | 121 ++++++++++++++++++ .../boot/dts/broadcom/bcm2712-rpi-5-b.dts | 118 ++--------------- 3 files changed, 133 insertions(+), 107 deletions(-) create mode 100644 arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts
arch/arm64/boot/dts/broadcom/Makefile +1 -0
@@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-400.dtb \ bcm2711-rpi-4-b.dtb \ bcm2711-rpi-cm4-io.dtb \ bcm2712-rpi-5-b.dtb \ + bcm2712-rpi-5-b-ovl-rp1.dtb \ bcm2712-d-rpi-5-b.dtb \ bcm2837-rpi-2-b.dtb \ bcm2837-rpi-3-a-plus.dtb \
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts new file +121 -0
121 lines not on this page · raw message
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts +11 -107
124 lines not on this page · raw message
Signature · 1 line
2.35.3
Re: [PATCH v12 09/13] arm64: dts: broadcom: Add board DTS for Rpi5 which includes RP1 node
From: Florian Fainelli <[email protected]>
Quoted 14 lines · Andrea della Porta
Add the fully populated DTS for RaspberryPi 5 which includes the RP1 node definition. The inclusion tree is as follow (the arrow points to the includer):
rp1-common.dtsi---->rp1-nexus.dtsi---->bcm2712-rpi-5-b.dts^ | bcm2712-rpi-5-b-ovl-rp1.dtsThis is designed to maximize the compatibility with downstream DT while ensuring that a fully defined DT (one which includes the RP1 node as opposed to load it from overlay at runtime) is present since early boot stage.
Quoted 6 lines
Since the preferred board DT is the fully populated one, name it
bcm2712-rpi-5-b.dtsand move the previous one intobcm2712-rpi-5-b-ovl-rp1.dts.Signed-off-by Andrea della Porta <[email protected]>---
Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, thanks! --
Florian
Andrea della Porta
maintainerPATCH v12 10/13 arm64: dts: broadcom: Add overlay for RP1 device
In reply to Andrea della PortaDefine the RP1 node in an overlay. The inclusion tree is as follow (the arrow points to the includer):
rp1.dtso
^
|rp1-common.dtsi ----> rp1-nexus.dtsi
--- arch/arm64/boot/dts/broadcom/Makefile | 3 ++- arch/arm64/boot/dts/broadcom/rp1.dtso | 11 +++++++++++ 2 files changed, 13 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/broadcom/rp1.dtso
arch/arm64/boot/dts/broadcom/Makefile +2 -1
@@ -14,7 +14,8 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-400.dtb \ bcm2837-rpi-3-b.dtb \ bcm2837-rpi-3-b-plus.dtb \ bcm2837-rpi-cm3-io3.dtb \ - bcm2837-rpi-zero-2-w.dtb + bcm2837-rpi-zero-2-w.dtb \ + rp1.dtbo subdir-y += bcmbca subdir-y += northstar2
arch/arm64/boot/dts/broadcom/rp1.dtso new file +11 -0
@@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; +/plugin/; + +&pcie2 { + #address-cells = <3>; + #size-cells = <2>; + + #include "rp1-nexus.dtsi" +};
Signature · 1 line
2.35.3
Re: [PATCH v12 10/13] arm64: dts: broadcom: Add overlay for RP1 device
From: Florian Fainelli <[email protected]>
Quoted 11 lines · Andrea della Porta
Define the RP1 node in an overlay. The inclusion tree is as follow (the arrow points to the includer):
rp1.dtso ^ |
rp1-common.dtsi---->rp1-nexus.dtsiSigned-off-by Andrea della Porta <[email protected]>Reviewed-by Florian Fainelli <[email protected]>---
Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, thanks! --
Florian
Andrea della Porta
maintainerPATCH v12 11/13 arm64: defconfig: Enable RP1 misc/clock/gpio drivers
In reply to Andrea della PortaSelect the RP1 drivers needed to operate the PCI endpoint containing several peripherals such as Ethernet and USB Controller. This chip is present on RaspberryPi 5.
--- arch/arm64/configs/defconfig | 3 +++ 1 file changed, 3 insertions(+)
arch/arm64/configs/defconfig +3 -0
@@ -620,6 +620,7 @@ CONFIG_PINCTRL_QCS615=y CONFIG_PINCTRL_QCS8300=y CONFIG_PINCTRL_QDF2XXX=y CONFIG_PINCTRL_QDU1000=y +CONFIG_PINCTRL_RP1=m CONFIG_PINCTRL_SA8775P=y CONFIG_PINCTRL_SC7180=y CONFIG_PINCTRL_SC7280=y
@@ -702,6 +703,7 @@ CONFIG_SENSORS_RASPBERRYPI_HWMON=m CONFIG_SENSORS_SL28CPLD=m CONFIG_SENSORS_INA2XX=m CONFIG_SENSORS_INA3221=m +CONFIG_MISC_RP1=m CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y CONFIG_CPU_THERMAL=y CONFIG_DEVFREQ_THERMAL=y
@@ -1299,6 +1301,7 @@ CONFIG_COMMON_CLK_CS2000_CP=y CONFIG_COMMON_CLK_FSL_SAI=y CONFIG_COMMON_CLK_S2MPS11=y CONFIG_COMMON_CLK_PWM=y +CONFIG_COMMON_CLK_RP1=m CONFIG_COMMON_CLK_RS9_PCIE=y CONFIG_COMMON_CLK_VC3=y CONFIG_COMMON_CLK_VC5=y
Signature · 1 line
2.35.3
Re: [PATCH v12 11/13] arm64: defconfig: Enable RP1 misc/clock/gpio drivers
From: Florian Fainelli <[email protected]>
Quoted 8 lines · Andrea della Porta
Select the RP1 drivers needed to operate the PCI endpoint containing several peripherals such as Ethernet and USB Controller. This chip is present on RaspberryPi 5.
Signed-off-by Andrea della Porta <[email protected]>Reviewed-by Stefan Wahren <[email protected]>Reviewed-by Florian Fainelli <[email protected]>---
Applied to https://github.com/Broadcom/stblinux/commits/defconfig-arm64/next, thanks! --
Florian
Andrea della Porta
maintainerPATCH v12 12/13 arm64: defconfig: Enable OF_OVERLAY option
In reply to Andrea della PortaThe RP1 driver uses the infrastructure enabled by OF_OVERLAY config option. Enable that option in defconfig in order to produce a kernel usable on RaspberryPi5 avoiding to enable it separately.
--- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+)
arch/arm64/configs/defconfig +1 -0
@@ -1659,6 +1659,7 @@ CONFIG_FPGA_BRIDGE=m CONFIG_ALTERA_FREEZE_BRIDGE=m CONFIG_FPGA_REGION=m CONFIG_OF_FPGA_REGION=m +CONFIG_OF_OVERLAY=y CONFIG_TEE=y CONFIG_OPTEE=y CONFIG_MUX_GPIO=m
Signature · 1 line
2.35.3
Re: [PATCH v12 12/13] arm64: defconfig: Enable OF_OVERLAY option
From: Florian Fainelli <[email protected]>
Quoted 8 lines · Andrea della Porta
The RP1 driver uses the infrastructure enabled by
OF_OVERLAYconfig option. Enable that option in defconfig in order to produce a kernel usable on RaspberryPi5 avoiding to enable it separately.Signed-off-by Andrea della Porta <[email protected]>Reviewed-by Stefan Wahren <[email protected]>Reviewed-by Florian Fainelli <[email protected]>---
Applied to https://github.com/Broadcom/stblinux/commits/defconfig-arm64/next, thanks! --
Florian
Andrea della Porta
maintainerPATCH v12 13/13 MAINTAINERS: add Raspberry Pi RP1 section
In reply to Andrea della PortaRaspberry Pi RP1 is a southbridge PCIe device which embeds several peripherals.
Add a new section to cover the main RP1 driver, DTS and specific subperipherals (such as clock and pinconf/pinmux/gpio controller).
--- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+)
MAINTAINERS +8 -0
@@ -20197,6 +20197,14 @@ S: Maintained F: Documentation/devicetree/bindings/media/raspberrypi,rp1-cfe.yaml F: drivers/media/platform/raspberrypi/rp1-cfe/ +RASPBERRY PI RP1 PCI DRIVER +M: Andrea della Porta <[email protected]> +S: Maintained +F: arch/arm64/boot/dts/broadcom/rp1*.dts* +F: drivers/clk/clk-rp1.c +F: drivers/misc/rp1/ +F: drivers/pinctrl/pinctrl-rp1.c + RC-CORE / LIRC FRAMEWORK M: Sean Young <[email protected]> L: [email protected]
Signature · 1 line
2.35.3
Re: [PATCH v12 13/13] MAINTAINERS: add Raspberry Pi RP1 section
From: Florian Fainelli <[email protected]>
Quoted 7 lines · Andrea della Porta
Raspberry Pi RP1 is a southbridge PCIe device which embeds several peripherals.
Add a new section to cover the main RP1 driver, DTS and specific subperipherals (such as clock and pinconf/pinmux/gpio controller).Signed-off-by Andrea della Porta <[email protected]>---
Applied to https://github.com/Broadcom/stblinux/commits/maintainers/next, thanks! --
Florian
Quoted 2 lines · Andrea della Porta
*** RESENDING PATCHSET AS V12 SINCE LAST ONE HAS CLOBBERED EMAIL Message-Id ***
Can you slow down please? It's merge window and you keep sending the same big patchset third time today.
Best regards,
Krzysztof
Andrea della Porta
maintainerHi Krzysztof,
Quoted 5 lines · Krzysztof Kozlowski
Quoted 2 lines · Andrea della Porta
*** RESENDING PATCHSET AS V12 SINCE LAST ONE HAS CLOBBERED EMAIL Message-Id ***
Can you slow down please? It's merge window and you keep sending the same big patchset third time today.
Sorry for that, I was sending it so Florian can pick it up for this merge window, and I had some trouble with formatting. Hopefully this was the last one.
Regards,
Andrea
Quoted 3 lines
Best regards,
Krzysztof
Arnd Bergmann
maintainerQuoted 4 lines · Andrea della Porta
Hi Krzysztof,
Quoted 1 line · Krzysztof Kozlowski
On 29/05/2025 15:50, Andrea della Porta wrote:
Quoted 8 lines
Quoted 4 lines
Quoted 2 lines
*** RESENDING PATCHSET AS V12 SINCE LAST ONE HAS CLOBBERED EMAIL Message-Id ***
Can you slow down please? It's merge window and you keep sending the same big patchset third time today.
Sorry for that, I was sending it so Florian can pick it up for this merge window, and I had some trouble with formatting. Hopefully this was the last one.
That's not how the merge window works, you missed 6.16 long ago:
Florian sent his pull requests for 6.16 in early may, see
https://lore.kernel.org/linux-arm-kernel/[email protected]/
and he needed time to test the contents before sending them to me.
If the driver is ready to be merged now, Florian can pick it up after -rc1 is out, and then include it in the 6.17 pull requests so I can include them in the next merge window.
Arnd
Florian Fainelli
maintainerQuoted 16 lines · Arnd Bergmann
Quoted 4 lines · Andrea della Porta
Hi Krzysztof,
Quoted 1 line · Krzysztof Kozlowski
On 29/05/2025 15:50, Andrea della Porta wrote:
Quoted 8 lines
Quoted 4 lines
Quoted 2 lines
*** RESENDING PATCHSET AS V12 SINCE LAST ONE HAS CLOBBERED EMAIL Message-Id ***
Can you slow down please? It's merge window and you keep sending the same big patchset third time today.
Sorry for that, I was sending it so Florian can pick it up for this merge window, and I had some trouble with formatting. Hopefully this was the last one.
That's not how the merge window works, you missed 6.16 long ago:
Quoted 8 lines
Florian sent his pull requests for 6.16 in early may, see
https://lore.kernel.org/linux-arm-kernel/[email protected]/and he needed time to test the contents before sending them to me.
If the driver is ready to be merged now, Florian can pick it up after -rc1 is out, and then include it in the 6.17 pull requests so I can include them in the next merge window.
I have applied all of the patches in the respective branch as we had discussed with Andrea and also merged all of the branches into my "next" branch so we can give this some proper soak testing. Once 6.16-rc1 is available, all those branches (devicetree/next, defconfig-arm64/next, drivers/next, etc.) will be rebased against that tag such that the patches that are already included will be dropped, and only this patch set plus what I have accumulated will be applied on top (if that makes sense).
As Arnd says though, this is too late for 6.16 so this would be included in 6.17. Andrea, thank you very much for your persistence working on this patch series, and sorry that the request to merge those patches came in during a time where I was away. The good news is that I am not doing that again anytime soon.
Thank you!
Signature · 1 line
Florian
Andrea della Porta
maintainerHi Florian,
Quoted 34 lines · Florian Fainelli
Quoted 16 lines · Arnd Bergmann
Quoted 4 lines · Andrea della Porta
Hi Krzysztof,
Quoted 1 line · Krzysztof Kozlowski
On 29/05/2025 15:50, Andrea della Porta wrote:
Quoted 8 lines
Quoted 4 lines
Quoted 2 lines
*** RESENDING PATCHSET AS V12 SINCE LAST ONE HAS CLOBBERED EMAIL Message-Id ***
Can you slow down please? It's merge window and you keep sending the same big patchset third time today.
Sorry for that, I was sending it so Florian can pick it up for this merge window, and I had some trouble with formatting. Hopefully this was the last one.
That's not how the merge window works, you missed 6.16 long ago:
Quoted 8 lines
Florian sent his pull requests for 6.16 in early may, see
https://lore.kernel.org/linux-arm-kernel/[email protected]/and he needed time to test the contents before sending them to me.
If the driver is ready to be merged now, Florian can pick it up after -rc1 is out, and then include it in the 6.17 pull requests so I can include them in the next merge window.
I have applied all of the patches in the respective branch as we had discussed with Andrea and also merged all of the branches into my "next" branch so we can give this some proper soak testing. Once 6.16-rc1 is available, all those branches (devicetree/next, defconfig-arm64/next,
drivers/next, etc.) will be rebased against that tag such that the patches that are already included will be dropped, and only this patch set plus what I have accumulated will be applied on top (if that makes sense).
Quoted 5 lines
As Arnd says though, this is too late for 6.16 so this would be included in 6.17. Andrea, thank you very much for your persistence working on this patch series, and sorry that the request to merge those patches came in during a time where I was away. The good news is that I am not doing that again anytime soon.
It was a pleasure, and many thanks for your patience too.
Andrea
Quoted 4 lines
Thank you!
Signature · 1 line
Florian
Florian Fainelli
maintainerQuoted 37 lines · Andrea della Porta
Hi Florian,
Quoted 34 lines · Florian Fainelli
Quoted 16 lines · Arnd Bergmann
Quoted 4 lines · Andrea della Porta
Hi Krzysztof,
Quoted 1 line · Krzysztof Kozlowski
On 29/05/2025 15:50, Andrea della Porta wrote:
Quoted 8 lines
Quoted 4 lines
Quoted 2 lines
*** RESENDING PATCHSET AS V12 SINCE LAST ONE HAS CLOBBERED EMAIL Message-Id ***
Can you slow down please? It's merge window and you keep sending the same big patchset third time today.
Sorry for that, I was sending it so Florian can pick it up for this merge window, and I had some trouble with formatting. Hopefully this was the last one.
That's not how the merge window works, you missed 6.16 long ago:
Quoted 8 lines
Florian sent his pull requests for 6.16 in early may, see
https://lore.kernel.org/linux-arm-kernel/[email protected]/and he needed time to test the contents before sending them to me.
If the driver is ready to be merged now, Florian can pick it up after -rc1 is out, and then include it in the 6.17 pull requests so I can include them in the next merge window.
I have applied all of the patches in the respective branch as we had discussed with Andrea and also merged all of the branches into my "next" branch so we can give this some proper soak testing. Once 6.16-rc1 is available, all those branches (devicetree/next, defconfig-arm64/next,
drivers/next, etc.) will be rebased against that tag such that the patches that are already included will be dropped, and only this patch set plus what I have accumulated will be applied on top (if that makes sense).
Quoted 7 lines
Quoted 5 lines
As Arnd says though, this is too late for 6.16 so this would be included in 6.17. Andrea, thank you very much for your persistence working on this patch series, and sorry that the request to merge those patches came in during a time where I was away. The good news is that I am not doing that again anytime soon.
It was a pleasure, and many thanks for your patience too.
As a heads up, the kernel robot reported a build failure for devicetree/next due to the missing pcie1 label, I have moved the DT patches from devicetree/next to devicetree-arm64/next where Stanimir's patches adding 2712 PCIe are already present.
Thanks!
Signature · 1 line
Florian