iio: adc: Add support for AD4170 series of ADCs
Subsystems (5)
Marcelo Schmitt
maintainerv7 cover iio: adc: Add support for AD4170 series of ADCs
Hello,
AD4170 support v7 comes after testing the driver with even more variations of channel setups. Signal offset and amplification can be tricky to grasp at times.
Thank you to all reviewers of previous versions. This intends to comply with all comments and suggestions to v6.
Same amount of patches than v6.
Patch 1 adds device tree documentation for the parts.
Patch 2 adds basic device support.
Patch 3 adds support for calibration scale.
Patch 4 adds support for calibration bias.
Patch 5 adds sinc5+avg to filter_type_available IIO ABI documentation. Patch 6 adds support for sample frequency along with filter type configuration. Patch 7 adds support for buffered ADC reading.
Patch 8 adds clock provider support
Patch 9 adds GPIO controller support.
Patch 10 adds internal temperature sensor support.
Patch 11 adds support for external RTD and bridge circuit sensors. Patch 12 adds timestamp channel
Change log v6 -> v7
[Generic changes]
- Renamed dt-doc and driver from ad4170 to ad4170-4. This will hopefully be more future proof since there is precedent of different devices with names ending with and without -N (e.g. AD7091R and AD7091R-5, AD7768 and AD7768-1).
[Device tree changes]
- Dropped leftover/unneeded list of valid reference-buffer values.
- Set vbias at AIN8 in example. The vbias is expected to be set on the IN- pin.
[Basic driver patch]
- Refactored ad4170_parse_adc_channel_type() to use fwnode_property_present() so to return errors early if required properties are not present.
- Use spi_write_then_read() to skip dealing with DMA safe buffers in slow data paths.
- Minor tweaks to comments such as 'handle options ...' -> 'handle PGA options ...'.
[sinc5+avg ABI patch]
- Fixed IIO ABI documentation by specifying the correct filter enabled with sinc5+avg.
[Digital filter and sample frequency config patch]
- Now reading SPS table within filter type switch to ensure in bounds array access.
- Squeezed info_mask_separate additions to reduce change diff.
[Buffer support patch]
- Dropped extra assignment of st->trig->dev.parent.
[GPIO controller patch]
- Used local device pointer (replaced &st->spi->dev with dev) in ad4170_parse_firmware().
[External sensor patch]
- adi,vbias was previously set per channel in ad4170 dt-binding but it is set per device in adi,ad4130.yaml. Fixed ad4170 parsing of adi,vbias. The dt-binding had been updated to the established use of adi,vbias in v4.
Link to v6: https://lore.kernel.org/linux-iio/[email protected]/
Link to v5: https://lore.kernel.org/linux-iio/[email protected]/
Link to v4: https://lore.kernel.org/linux-iio/[email protected]/
Link to v3: https://lore.kernel.org/linux-iio/[email protected]/
Link to v2: https://lore.kernel.org/linux-iio/[email protected]/
Link to v1: https://lore.kernel.org/linux-iio/[email protected]/
Ana-Maria Cusco (1):
iio: adc: Add basic support for AD4170-4
Marcelo Schmitt (11):
dt-bindings: iio: adc: Add AD4170
iio: adc: ad4170-4: Add support for calibration gain
iio: adc: ad4170-4: Add support for calibration bias
Documentation: ABI: IIO: Add sinc5+avg to the filter_type_available
list
iio: adc: ad4170-4: Add digital filter and sample frequency config
support
iio: adc: ad4170-4: Add support for buffered data capture
iio: adc: ad4170-4: Add clock provider support
iio: adc: ad4170-4: Add GPIO controller support
iio: adc: ad4170-4: Add support for internal temperature sensor
iio: adc: ad4170-4: Add support for weigh scale and RTD sensors
iio: adc: ad4170-4: Add timestamp channel
Documentation/ABI/testing/sysfs-bus-iio | 1 + .../bindings/iio/adc/adi,ad4170-4.yaml | 555 +++ MAINTAINERS | 8 + drivers/iio/adc/Kconfig | 16 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/ad4170-4.c | 3020 +++++++++++++++++ 6 files changed, 3601 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/adi,ad4170-4.yaml create mode 100644 drivers/iio/adc/ad4170-4.c
base-commit: 42498420746a4db923f03d048a0ebc9bd2371f56
Signature · 1 line
2.47.2
Marcelo Schmitt
maintainerPATCH v7 1/12 dt-bindings: iio: adc: Add AD4170
Add device tree documentation for AD4170 and similar sigma-delta ADCs. The AD4170 is a 24-bit, multichannel, sigma-delta ADC.
---
Change log v6 -> v7
- Renamed dt-doc from ad4170 to ad4170-4. This will hopefully be more future proof since there is precedent of different devices with names ending with and without -N (e.g. AD7091R and AD7091R-5, AD7768 and AD7768-1).
- Dropped leftover/unneeded list of valid reference-buffer values.
- Set vbias at AIN8 in example. The vbias is expected to be set on the IN- pin.
.../bindings/iio/adc/adi,ad4170-4.yaml | 555 ++++++++++++++++++ MAINTAINERS | 7 + 2 files changed, 562 insertions(+) create mode 100644 Documentation/devicetree/bindings/iio/adc/adi,ad4170-4.yaml
Documentation/devicetree/bindings/iio/adc/adi,ad4170-4.yaml new file +555 -0
@@ -0,0 +1,555 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,ad4170-4.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD4170-4 and similar Analog to Digital Converters + +maintainers: + - Marcelo Schmitt <[email protected]> + +description: | + Analog Devices AD4170-4 series of Sigma-delta Analog to Digital Converters. + Specifications can be found at: + https://www.analog.com/media/en/technical-documentation/data-sheets/ad4170-4.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/ad4190-4.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/ad4195-4.pdf + +$ref: /schemas/spi/spi-peripheral-props.yaml# + +$defs: + reference-buffer: + description: | + Enable precharge buffer, full buffer, or skip reference buffering of + the positive/negative voltage reference. Because the output impedance + of the source driving the voltage reference inputs may be dynamic, + resistive/capacitive combinations of those inputs can cause DC gain + errors if the reference inputs go unbuffered into the ADC. Enable + reference buffering if the provided reference source has dynamic high + impedance output. Note the absolute voltage allowed on REFINn+ and REFINn- + inputs is from AVSS - 50 mV to AVDD + 50 mV when the reference buffers are + disabled but narrows to AVSS to AVDD when reference buffering is enabled + or in precharge mode. + $ref: /schemas/types.yaml#/definitions/string + enum: [ precharge, full, disabled ] + default: full + +properties: + compatible: + enum: + - adi,ad4170-4 + - adi,ad4190-4 + - adi,ad4195-4 + + avss-supply: + description: + Reference voltage supply for AVSS. A −2.625V minimum and 0V maximum supply + that powers the chip. If not provided, AVSS is assumed to be at system + ground (0V). + + avdd-supply: + description: + A supply of 4.75V to 5.25V relative to AVSS that powers the chip (AVDD). + + iovdd-supply: + description: 1.7V to 5.25V reference supply to the serial interface (IOVDD). + + refin1p-supply: + description: REFIN+ supply that can be used as reference for conversion. + + refin1n-supply: + description: REFIN- supply that can be used as reference for conversion. + + refin2p-supply: + description: REFIN2+ supply that can be used as reference for conversion. + + refin2n-supply: + description: REFIN2- supply that can be used as reference for conversion. + + spi-cpol: true + + spi-cpha: true + + interrupts: + description: + Interrupt for signaling the completion of conversion results. The data + ready signal (RDY) used as interrupt is by default provided on the SDO + pin. Alternatively, it can be provided on the DIG_AUX1 pin in which case + the chip disables the RDY function on SDO. Thus, there can be only one + data ready interrupt enabled at a time. + + interrupt-names: + description: + Specify which pin should be configured as Data Ready interrupt. + enum: + - sdo + - dig_aux1 + + clocks: + maxItems: 1 + description: + Optional external clock source. Can specify either an external clock or + external crystal. + + clock-names: + enum: + - ext-clk + - xtal + default: ext-clk + + '#clock-cells': + const: 0 + + clock-output-names: + maxItems: 1 + + gpio-controller: true + + "#gpio-cells": + const: 2 + description: | + The first cell is for the GPIO number: 0 to 3. + The second cell takes standard GPIO flags. + + ldac-gpios: + description: + GPIO connected to DIG_AUX2 pin to be used as LDAC toggle to control the + transfer of data from the DAC_INPUT_A register to the DAC. + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + adi,vbias-pins: + description: Analog inputs to apply a voltage bias of (AVDD − AVSS) / 2 to. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 9 + items: + minimum: 0 + maximum: 8 + +allOf: + # Some devices don't have integrated DAC + - if: + properties: + compatible: + contains: + enum: + - adi,ad4190-4 + - adi,ad4195-4 + then: + properties: + ldac-gpios: false + + # Require to specify the interrupt pin when using interrupts + - if: + required: + - interrupts + then: + required: + - interrupt-names + + # If an external clock is set, the internal clock cannot go out and vice versa + - oneOf: + - required: [clocks] + properties: + '#clock-cells': false + - required: ['#clock-cells'] + properties: + clocks: false + +required: + - compatible + - reg + - avdd-supply + - iovdd-supply + - spi-cpol + - spi-cpha + +unevaluatedProperties: false + +patternProperties: + "^channel@[0-9a-f]$": + $ref: /schemas/iio/adc/adc.yaml# + unevaluatedProperties: false + description: + Represents the external channels which are connected to the ADC. + + properties: + reg: + description: + The channel number. + minimum: 0 + maximum: 15 + + diff-channels: + description: | + This property is used for defining the inputs of a differential + voltage channel. The first value is the positive input and the second + value is the negative input of the channel. + + Besides the analog input pins AIN0 to AIN8, there are special inputs + that can be selected with the following values: + 17: Internal temperature sensor + 18: (AVDD-AVSS)/5 + 19: (IOVDD-DGND)/5 + 20: DAC output + 21: ALDO + 22: DLDO + 23: AVSS + 24: DGND + 25: REFIN+ + 26: REFIN- + 27: REFIN2+ + 28: REFIN2- + 29: REFOUT + For the internal temperature sensor, use the input number for both + inputs (i.e. diff-channels = <17 17>). + items: + enum: [0, 1, 2, 3, 4, 5, 6, 7, 8, 17, 18, 19, 20, 21, 22, 23, 24, 25, + 26, 27, 28, 29] + + adi,reference-select: + description: | + Select the reference source to use when converting on the + specific channel. Valid values are: + 0: REFIN+/REFIN- + 1: REFIN2+/REFIN2− + 2: REFOUT/AVSS (internal reference) + 3: AVDD/AVSS + If not specified, REFOUT/AVSS is used. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + default: 1 + + adi,positive-reference-buffer: + $ref: '#/$defs/reference-buffer' + + adi,negative-reference-buffer: + $ref: '#/$defs/reference-buffer' + + adi,sensor-type: + description: + The AD4170-4 and similar designs have features to aid interfacing with + load cell weigh scale, RTD, and thermocouple sensors. Each of those + sensor types requires either distinct wiring configuration or + external circuitry for proper sensor operation and can use different + ADC chip functionality on their setups. A key characteristic of those + external sensors is that they must be excited either by voltage supply + or by ADC chip excitation signals. The sensor can then be read through + a pair of analog inputs. This property specifies which particular + sensor type is connected to the ADC so it can be properly setup and + handled. Omit this property for conventional (not weigh scale, RTD, or + thermocouple) ADC channel setups. + $ref: /schemas/types.yaml#/definitions/string + enum: [ weighscale, rtd, thermocouple ] + + adi,excitation-pin-0: + description: + Analog input to apply excitation current to while the channel + is active. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 20 + default: 0 + + adi,excitation-pin-1: + description: + Analog input to apply excitation current to while the channel + is active. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 20 + default: 0 + + adi,excitation-pin-2: + description: + Analog input to apply excitation current to while the channel + is active. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 20 + default: 0 + + adi,excitation-pin-3: + description: + Analog input to apply excitation current to while the channel + is active. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 20 + default: 0 + + adi,excitation-current-0-microamp: + description: + Excitation current in microamperes to be applied to pin specified in + adi,excitation-pin-0 while this channel is active. + enum: [0, 10, 50, 100, 250, 500, 1000, 1500] + default: 0 + + adi,excitation-current-1-microamp: + description: + Excitation current in microamperes to be applied to pin specified in + adi,excitation-pin-1 while this channel is active. + enum: [0, 10, 50, 100, 250, 500, 1000, 1500] + default: 0 + + adi,excitation-current-2-microamp: + description: + Excitation current in microamperes to be applied to pin specified in + adi,excitation-pin-2 while this channel is active. + enum: [0, 10, 50, 100, 250, 500, 1000, 1500] + default: 0 + + adi,excitation-current-3-microamp: + description: + Excitation current in microamperes to be applied to pin specified in + adi,excitation-pin-3 while this channel is active. + enum: [0, 10, 50, 100, 250, 500, 1000, 1500] + default: 0 + + adi,excitation-ac: + type: boolean + description: + Whether the external sensor has to be AC or DC excited. When omitted, + it is DC excited. + + allOf: + - oneOf: + - required: [single-channel, common-mode-channel] + properties: + diff-channels: false + - required: [diff-channels] + properties: + single-channel: false + common-mode-channel: false + # Usual ADC channels don't need external circuitry excitation. + - if: + not: + required: + - adi,sensor-type + then: + properties: + adi,excitation-pin-0: false + adi,excitation-pin-1: false + adi,excitation-pin-2: false + adi,excitation-pin-3: false + adi,excitation-current-0-microamp: false + adi,excitation-current-1-microamp: false + adi,excitation-current-2-microamp: false + adi,excitation-current-3-microamp: false + adi,excitation-ac: false + # Weigh scale bridge AC excited with one pair of predefined signals. + - if: + allOf: + - properties: + adi,sensor-type: + contains: + const: weighscale + - required: + - adi,excitation-ac + - adi,excitation-pin-2 + - adi,excitation-pin-3 + - not: + required: + - adi,excitation-current-2-microamp + - adi,excitation-current-3-microamp + then: + properties: + adi,excitation-pin-2: + const: 19 + adi,excitation-pin-3: + const: 20 + # Weigh scale bridge AC excited with two pairs of predefined signals. + - if: + allOf: + - properties: + adi,sensor-type: + contains: + const: weighscale + - required: + - adi,excitation-ac + - adi,excitation-pin-0 + - adi,excitation-pin-1 + - adi,excitation-pin-2 + - adi,excitation-pin-3 + - not: + required: + - adi,excitation-current-0-microamp + - adi,excitation-current-1-microamp + - adi,excitation-current-2-microamp + - adi,excitation-current-3-microamp + then: + properties: + adi,excitation-pin-0: + const: 17 + adi,excitation-pin-1: + const: 18 + adi,excitation-pin-2: + const: 19 + adi,excitation-pin-3: + const: 20 + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + spi { + #address-cells = <1>; + #size-cells = <0>; + + adc@0 { + compatible = "adi,ad4170-4"; + reg = <0>; + spi-max-frequency = <20000000>; + spi-cpol; + spi-cpha; + avdd-supply = <&avdd>; + iovdd-supply = <&iovdd>; + clocks = <&clk>; + clock-names = "xtal"; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "dig_aux1"; + adi,vbias-pins = <8>; + #address-cells = <1>; + #size-cells = <0>; + + // Sample AIN0 with respect to DGND throughout AVDD/DGND input range + // Pseudo-differential unipolar + channel@0 { + reg = <0>; + single-channel = <0>; + common-mode-channel = <24>; + adi,reference-select = <3>; + }; + // Weigh scale sensor + channel@1 { + reg = <1>; + bipolar; + diff-channels = <1 2>; + adi,reference-select = <0>; + adi,positive-reference-buffer = "precharge"; + adi,negative-reference-buffer = "precharge"; + adi,sensor-type = "weighscale"; + adi,excitation-pin-2 = <19>; + adi,excitation-pin-3 = <20>; + adi,excitation-ac; + }; + // RTD sensor + channel@2 { + reg = <2>; + bipolar; + diff-channels = <3 4>; + adi,reference-select = <0>; + adi,sensor-type = "rtd"; + adi,excitation-pin-0 = <5>; + adi,excitation-pin-1 = <6>; + adi,excitation-current-0-microamp = <500>; + adi,excitation-current-1-microamp = <500>; + adi,excitation-ac; + }; + // Thermocouple sensor + channel@3 { + reg = <3>; + bipolar; + diff-channels = <7 8>; + adi,reference-select = <0>; + adi,sensor-type = "thermocouple"; + adi,excitation-pin-0 = <18>; + adi,excitation-current-0-microamp = <500>; + }; + }; + }; + - | + #include <dt-bindings/interrupt-controller/irq.h> + spi { + #address-cells = <1>; + #size-cells = <0>; + + adc@0 { + compatible = "adi,ad4170-4"; + reg = <0>; + spi-max-frequency = <20000000>; + spi-cpol; + spi-cpha; + avdd-supply = <&avdd>; + iovdd-supply = <&iovdd>; + #clock-cells = <0>; + clock-output-names = "ad4170-clk16mhz"; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "dig_aux1"; + #address-cells = <1>; + #size-cells = <0>; + + // Sample AIN0 with respect to AIN1 throughout AVDD/AVSS input range + // Differential bipolar. If AVSS < 0V, differential true bipolar + channel@0 { + reg = <0>; + bipolar; + diff-channels = <0 1>; + adi,reference-select = <3>; + }; + // Sample AIN2 with respect to DGND throughout AVDD/DGND input range + // Pseudo-differential unipolar + channel@1 { + reg = <1>; + single-channel = <2>; + common-mode-channel = <24>; + adi,reference-select = <3>; + }; + // Sample AIN3 with respect to 2.5V throughout AVDD/AVSS input range + // Pseudo-differential bipolar + channel@2 { + reg = <2>; + bipolar; + single-channel = <3>; + common-mode-channel = <29>; + adi,reference-select = <3>; + }; + // Sample AIN4 with respect to DGND throughout AVDD/AVSS input range + // Pseudo-differential bipolar + channel@3 { + reg = <3>; + bipolar; + single-channel = <4>; + common-mode-channel = <24>; + adi,reference-select = <3>; + }; + // Sample AIN5 with respect to 2.5V throughout AVDD/AVSS input range + // Pseudo-differential unipolar (AD4170-4 datasheet page 46 example) + channel@4 { + reg = <4>; + single-channel = <5>; + common-mode-channel = <29>; + adi,reference-select = <3>; + }; + // Sample AIN6 with respect to 2.5V throughout REFIN+/REFIN- input range + // Pseudo-differential bipolar + channel@5 { + reg = <5>; + bipolar; + single-channel = <6>; + common-mode-channel = <29>; + adi,reference-select = <0>; + }; + // Weigh scale sensor + channel@6 { + reg = <6>; + bipolar; + diff-channels = <7 8>; + adi,reference-select = <0>; + adi,sensor-type = "weighscale"; + adi,excitation-pin-0 = <17>; + adi,excitation-pin-1 = <18>; + adi,excitation-pin-2 = <19>; + adi,excitation-pin-3 = <20>; + adi,excitation-ac; + }; + }; + }; +... +
MAINTAINERS +7 -0
@@ -1392,6 +1392,13 @@ F: Documentation/ABI/testing/sysfs-bus-iio-adc-ad4130 F: Documentation/devicetree/bindings/iio/adc/adi,ad4130.yaml F: drivers/iio/adc/ad4130.c +ANALOG DEVICES INC AD4170-4 DRIVER +M: Marcelo Schmitt <[email protected]> +L: [email protected] +S: Supported +W: https://ez.analog.com/linux-software-drivers +F: Documentation/devicetree/bindings/iio/adc/adi,ad4170-4.yaml + ANALOG DEVICES INC AD4695 DRIVER M: Michael Hennerich <[email protected]> M: Nuno Sá <[email protected]>
Signature · 1 line
2.47.2
Jonathan Cameron
maintainerRe: [PATCH v7 01/12] dt-bindings: iio: adc: Add AD4170
Quoted 5 lines · On Mon, 30 Jun 2025 10:57:59 -0300 Marcelo Schmitt…
Add device tree documentation for AD4170 and similar sigma-delta ADCs. The AD4170 is a 24-bit, multichannel, sigma-delta ADC.
Acked-by Conor Dooley <[email protected]>Signed-off-by Marcelo Schmitt <[email protected]>
Very small tweak whilst applying. There is a bonus blank line at the end of the file that I removed. Git moans about it otherwise.
Documentation/devicetree/bindings/iio/adc/adi,ad4170-4.yaml line 555
Quoted 3 lines
Documentation/devicetree/bindings/iio/adc/adi,ad4170-4.yaml new file +3
-0+ }; +... +
This one.
Marcelo Schmitt
maintainerPATCH v7 2/12 iio: adc: Add basic support for AD4170-4
In reply to Marcelo SchmittFrom: Ana-Maria Cusco <[email protected]>
The AD4170-4 is a multichannel, low noise, 24-bit precision sigma-delta analog to digital converter. The AD4170-4 design offers a flexible data acquisition solution with crosspoint multiplexed analog inputs, configurable ADC voltage reference inputs, ultra-low noise integrated PGA, digital filtering, wide range of configurable output data rates, internal oscillator and temperature sensor, four GPIOs, and integrated features for interfacing with load cell weigh scales, RTD, and thermocouple sensors.
Add basic support for the AD4170-4 ADC with the following features:
- Single-shot read.
- Analog front end PGA configuration.
- Differential and pseudo-differential input configuration.
---
Change log v6 -> v7
- Renamed from ad4170 to ad4170-4. This will hopefully be more future proof since there is precedent of different devices with names ending with and without -N (e.g. AD7091R and AD7091R-5, AD7768 and AD7768-1).
- Refactored ad4170_parse_adc_channel_type() to use fwnode_property_present() so to return errors early if required properties are not present.
- Use spi_write_then_read() to skip dealing with DMA safe buffers in slow data paths.
- Minor tweaks to comments such as 'handle options ...' -> 'handle PGA options ...'.
MAINTAINERS | 1 + drivers/iio/adc/Kconfig | 12 + drivers/iio/adc/Makefile | 1 + drivers/iio/adc/ad4170-4.c | 1556 ++++++++++++++++++++++++++++++++++++ 4 files changed, 1570 insertions(+) create mode 100644 drivers/iio/adc/ad4170-4.c
MAINTAINERS +1 -0
@@ -1398,6 +1398,7 @@ L: [email protected] S: Supported W: https://ez.analog.com/linux-software-drivers F: Documentation/devicetree/bindings/iio/adc/adi,ad4170-4.yaml +F: drivers/iio/adc/ad4170-4.c ANALOG DEVICES INC AD4695 DRIVER M: Michael Hennerich <[email protected]>
drivers/iio/adc/Kconfig +12 -0
@@ -84,6 +84,18 @@ config AD4130 To compile this driver as a module, choose M here: the module will be called ad4130. + +config AD4170_4 + tristate "Analog Device AD4170-4 ADC Driver" + depends on SPI + select REGMAP_SPI + help + Say yes here to build support for Analog Devices AD4170-4 SPI analog + to digital converters (ADC). + + To compile this driver as a module, choose M here: the module will be + called ad4170-4. + config AD4695 tristate "Analog Device AD4695 ADC Driver" depends on SPI
drivers/iio/adc/Makefile +1 -0
@@ -12,6 +12,7 @@ obj-$(CONFIG_AD4000) += ad4000.o obj-$(CONFIG_AD4030) += ad4030.o obj-$(CONFIG_AD4080) += ad4080.o obj-$(CONFIG_AD4130) += ad4130.o +obj-$(CONFIG_AD4170_4) += ad4170-4.o obj-$(CONFIG_AD4695) += ad4695.o obj-$(CONFIG_AD4851) += ad4851.o obj-$(CONFIG_AD7091R) += ad7091r-base.o
drivers/iio/adc/ad4170-4.c new file +1556 -0
1,556 lines not on this page · raw message
Signature · 1 line
2.47.2
Marcelo Schmitt
maintainerPATCH v7 3/12 iio: adc: ad4170-4: Add support for calibration gain
In reply to Marcelo SchmittAdd support for ADC calibration gain configuration.
---
No changes since v5.
drivers/iio/adc/ad4170-4.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)
drivers/iio/adc/ad4170-4.c +20 -0
@@ -623,6 +623,7 @@ static const struct iio_chan_spec ad4170_channel_template = { .differential = 1, .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE) | + BIT(IIO_CHAN_INFO_CALIBSCALE) | BIT(IIO_CHAN_INFO_OFFSET), .info_mask_separate_available = BIT(IIO_CHAN_INFO_SCALE), .scan_type = {
@@ -940,6 +941,9 @@ static int ad4170_read_raw(struct iio_dev *indio_dev, pga =FIELD_GET (AD4170_AFE_PGA_GAIN_MSK , setup->afe); *val = chan_info->offset_tbl[pga];return IIO_VAL_INT ; +case IIO_CHAN_INFO_CALIBSCALE : + *val = setup->gain; +return IIO_VAL_INT ;default :return -EINVAL ; }
@@ -1054,6 +1058,18 @@ static int ad4170_set_pga(struct ad4170_state *st,return ad4170_write_channel_setup (st, chan->address, false); } +static int ad4170_set_calib_gain (struct ad4170_state *st, +struct iio_chan_spec const *chan,int val) +{ +struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address]; +struct ad4170_setup *setup = &chan_info->setup; + +guard (mutex)(&st->lock); + setup->gain = val; + +return ad4170_write_channel_setup (st, chan->address, false); +} +static int __ad4170_write_raw (struct iio_dev *indio_dev,struct iio_chan_spec const *chan,int val,int val2,long info)
@@ -1063,6 +1079,8 @@ static int __ad4170_write_raw(struct iio_dev *indio_dev,switch (info) {case IIO_CHAN_INFO_SCALE :return ad4170_set_pga (st, chan, val, val2); +case IIO_CHAN_INFO_CALIBSCALE : +return ad4170_set_calib_gain (st, chan, val);default :return -EINVAL ; }
@@ -1089,6 +1107,8 @@ static int ad4170_write_raw_get_fmt(struct iio_dev *indio_dev,switch (info) {case IIO_CHAN_INFO_SCALE :return IIO_VAL_INT_PLUS_NANO ; +case IIO_CHAN_INFO_CALIBSCALE : +return IIO_VAL_INT ;default :return -EINVAL ; }
Signature · 1 line
2.47.2
Marcelo Schmitt
maintainerPATCH v7 4/12 iio: adc: ad4170-4: Add support for calibration bias
In reply to Marcelo SchmittAdd support for ADC calibration bias/offset configuration.
---
No changes since v5.
drivers/iio/adc/ad4170-4.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)
drivers/iio/adc/ad4170-4.c +19 -0
@@ -623,6 +623,7 @@ static const struct iio_chan_spec ad4170_channel_template = { .differential = 1, .info_mask_separate =BIT (IIO_CHAN_INFO_RAW ) |BIT (IIO_CHAN_INFO_SCALE ) | +BIT (IIO_CHAN_INFO_CALIBBIAS ) |BIT (IIO_CHAN_INFO_CALIBSCALE ) | BIT(IIO_CHAN_INFO_OFFSET), .info_mask_separate_available = BIT(IIO_CHAN_INFO_SCALE),
@@ -941,6 +942,9 @@ static int ad4170_read_raw(struct iio_dev *indio_dev, pga =FIELD_GET (AD4170_AFE_PGA_GAIN_MSK , setup->afe); *val = chan_info->offset_tbl[pga];return IIO_VAL_INT ; +case IIO_CHAN_INFO_CALIBBIAS : + *val = setup->offset; +return IIO_VAL_INT ;case IIO_CHAN_INFO_CALIBSCALE : *val = setup->gain;return IIO_VAL_INT ;
@@ -1058,6 +1062,18 @@ static int ad4170_set_pga(struct ad4170_state *st,return ad4170_write_channel_setup (st, chan->address, false); } +static int ad4170_set_calib_offset (struct ad4170_state *st, +struct iio_chan_spec const *chan,int val) +{ +struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address]; +struct ad4170_setup *setup = &chan_info->setup; + +guard (mutex)(&st->lock); + setup->offset = val; + +return ad4170_write_channel_setup (st, chan->address, false); +} +static int ad4170_set_calib_gain (struct ad4170_state *st,struct iio_chan_spec const *chan,int val) {
@@ -1079,6 +1095,8 @@ static int __ad4170_write_raw(struct iio_dev *indio_dev,switch (info) {case IIO_CHAN_INFO_SCALE :return ad4170_set_pga (st, chan, val, val2); +case IIO_CHAN_INFO_CALIBBIAS : +return ad4170_set_calib_offset (st, chan, val);case IIO_CHAN_INFO_CALIBSCALE :return ad4170_set_calib_gain (st, chan, val);default :
@@ -1107,6 +1125,7 @@ static int ad4170_write_raw_get_fmt(struct iio_dev *indio_dev,switch (info) {case IIO_CHAN_INFO_SCALE :return IIO_VAL_INT_PLUS_NANO ; +case IIO_CHAN_INFO_CALIBBIAS :case IIO_CHAN_INFO_CALIBSCALE :return IIO_VAL_INT ;default :
Signature · 1 line
2.47.2
Marcelo Schmitt
maintainerPATCH v7 5/12 Documentation: ABI: IIO: Add sinc5+avg to the filter_type_available list
In reply to Marcelo SchmittAdd the sinc5+avg filter type to the list of possible values for the filter_type_available attribute.
The sinc5+avg filter type is handled by the ad4170 driver.
---
Change log v6 -> v7
- Fixed IIO ABI documentation by specifying the correct filter enabled with sinc5+avg.
Documentation/ABI/testing/sysfs-bus-iio | 1 + 1 file changed, 1 insertion(+)
Documentation/ABI/testing/sysfs-bus-iio +1 -0
@@ -2321,6 +2321,7 @@ Description: * "sinc3+pf3" - Sinc3 + device specific Post Filter 3. * "sinc3+pf4" - Sinc3 + device specific Post Filter 4. * "sinc5+pf1" - Sinc5 + device specific Post Filter 1. + * "sinc5+avg" - Sinc5 + averaging by 4. * "wideband" - filter with wideband low ripple passband and sharp transition band.
Signature · 1 line
2.47.2
Marcelo Schmitt
maintainerPATCH v7 6/12 iio: adc: ad4170-4: Add digital filter and sample frequency config support
In reply to Marcelo SchmittAdd support for sinc3, sinc5, and averaged sinc5 digital filters along with sample frequency configuration.
---
Change log v6 -> v7
- Now reading SPS table within filter type switch to ensure in bounds array access.
- Squeezed info_mask_separate additions to reduce change diff.
drivers/iio/adc/ad4170-4.c | 263 ++++++++++++++++++++++++++++++++++++- 1 file changed, 261 insertions(+), 2 deletions(-)
drivers/iio/adc/ad4170-4.c +261 -2
@@ -20,6 +20,7 @@#include <linux/interrupt.h> #include <linux/irq.h> #include <linux/math64.h> +#include <linux/minmax.h> #include <linux/module.h> #include <linux/property.h> #include <linux/regmap.h>
@@ -90,6 +91,9 @@#define AD4170_AFE_BIPOLAR_MSK BIT(4)#define AD4170_AFE_PGA_GAIN_MSK GENMASK(3, 0) +/* AD4170_FILTER_REG */ +#define AD4170_FILTER_FILTER_TYPE_MSK GENMASK(3, 0) +/* AD4170 register constants */ /* AD4170_CHAN_MAP_REG constants */
@@ -115,6 +119,11 @@#define AD4170_ADC_CTRL_MODE_SINGLE 0x4#define AD4170_ADC_CTRL_MODE_IDLE 0x7 +/* AD4170_FILTER_REG constants */ +#define AD4170_FILTER_FILTER_TYPE_SINC5_AVG 0x0 +#define AD4170_FILTER_FILTER_TYPE_SINC5 0x4 +#define AD4170_FILTER_FILTER_TYPE_SINC3 0x6 +/* Device properties and auxiliary constants */ #define AD4170_NUM_ANALOG_PINS 9
@@ -124,6 +133,7 @@#define AD4170_INVALID_SETUP 9#define AD4170_SPI_INST_PHASE_LEN 2#define AD4170_SPI_MAX_XFER_LEN 6 +#define AD4170_DEFAULT_SAMP_RATE (125 * HZ_PER_KHZ)#define AD4170_INT_REF_2_5V 2500000
@@ -132,6 +142,12 @@#define AD4170_NUM_PGA_OPTIONS 10 +/* Digital filter properties */ +#define AD4170_SINC3_MIN_FS 4 +#define AD4170_SINC3_MAX_FS 65532 +#define AD4170_SINC5_MIN_FS 1 +#define AD4170_SINC5_MAX_FS 256 +#define AD4170_GAIN_REG_DEFAULT 0x555555static const unsigned int ad4170_reg_size[] = {
@@ -192,6 +208,12 @@ enum ad4170_ref_select { AD4170_REF_AVDD, }; +enum ad4170_filter_type { +AD4170_SINC5_AVG , +AD4170_SINC5 , +AD4170_SINC3 , +}; +enum ad4170_regulator {AD4170_AVDD_SUP ,AD4170_AVSS_SUP ,
@@ -213,6 +235,18 @@ static const char * const ad4170_int_pin_names[] = { [AD4170_INT_PIN_DIG_AUX1] = "dig_aux1", }; +static const unsigned int ad4170_sinc3_filt_fs_tbl[] = { +4 ,8 ,12 ,16 ,20 ,40 ,48 ,80 ,/* 0 - 7 */ +100 ,256 ,500 ,1000 ,5000 ,8332 ,10000 ,25000 ,/* 8 - 15 */ +50000 ,65532 ,/* 16 - 17 */ +}; + +#define AD4170_MAX_FS_TBL_SIZE ARRAY_SIZE(ad4170_sinc3_filt_fs_tbl) + +static const unsigned int ad4170_sinc5_filt_fs_tbl[] = { +1 ,2 ,4 ,8 ,12 ,16 ,20 ,40 ,48 ,80 ,100 ,256 , +}; +struct ad4170_chip_info {const char *name; };
@@ -270,6 +304,12 @@ struct ad4170_chan_info {bool enabled; }; +static const char *const ad4170_filt_names[] = { + [AD4170_SINC5_AVG ] ="sinc5+avg" , + [AD4170_SINC5 ] ="sinc5" , + [AD4170_SINC3 ] ="sinc3" , +}; +struct ad4170_state {struct mutex lock;/* Protect read-modify-write and multi write sequences */ int vrefs_uv[AD4170_MAX_SUP ];
@@ -279,6 +319,7 @@ struct ad4170_state {struct ad4170_chan_info chan_infos[AD4170_MAX_CHANNELS ];struct spi_device *spi;struct regmap *regmap; +int sps_tbl[ARRAY_SIZE (ad4170_filt_names)][AD4170_MAX_FS_TBL_SIZE ][2 ];struct completion completion;unsigned int pins_fn[AD4170_NUM_ANALOG_PINS ];u32 int_pin_sel;
@@ -289,6 +330,38 @@ struct ad4170_state {u8 rx_buf[4 ]__aligned(IIO_DMA_MINALIGN) ; }; +static void ad4170_fill_sps_tbl (struct ad4170_state *st) +{ +unsigned int tmp0, tmp1, i; + +/* +* The ODR can be calculated the same way for sinc5+avg, sinc5, and +* sinc3 filter types with the exception that sinc5 filter has a +* narrowed range of allowed FILTER_FS values. +*/ +for (i =0 ; i <ARRAY_SIZE (ad4170_sinc3_filt_fs_tbl); i++) { + tmp0 =div_u64_rem (st->mclk_hz,32 * ad4170_sinc3_filt_fs_tbl[i], + &tmp1); + tmp1 =mult_frac (tmp1,MICRO ,32 * ad4170_sinc3_filt_fs_tbl[i]); +/* Fill sinc5+avg filter SPS table */ + st->sps_tbl[AD4170_SINC5_AVG ][i][0 ] = tmp0;/* Integer part */ + st->sps_tbl[AD4170_SINC5_AVG ][i][1 ] = tmp1;/* Fractional part */ + +/* Fill sinc3 filter SPS table */ + st->sps_tbl[AD4170_SINC3 ][i][0 ] = tmp0;/* Integer part */ + st->sps_tbl[AD4170_SINC3 ][i][1 ] = tmp1;/* Fractional part */ + } +/* Sinc5 filter ODR doesn't use all FILTER_FS bits */ +for (i =0 ; i <ARRAY_SIZE (ad4170_sinc5_filt_fs_tbl); i++) { + tmp0 =div_u64_rem (st->mclk_hz,32 * ad4170_sinc5_filt_fs_tbl[i], + &tmp1); + tmp1 =mult_frac (tmp1,MICRO ,32 * ad4170_sinc5_filt_fs_tbl[i]); +/* Fill sinc5 filter SPS table */ + st->sps_tbl[AD4170_SINC5 ][i][0 ] = tmp0;/* Integer part */ + st->sps_tbl[AD4170_SINC5 ][i][1 ] = tmp1;/* Fractional part */ + } +} +static int ad4170_debugfs_reg_access (struct iio_dev *indio_dev,unsigned int reg,unsigned int writeval,unsigned int *readval)
@@ -617,6 +690,100 @@ static int ad4170_set_channel_enable(struct ad4170_state *st,return 0 ; } +static int __ad4170_get_filter_type (unsigned int filter) +{ +u16 f_conf =FIELD_GET (AD4170_FILTER_FILTER_TYPE_MSK , filter); + +switch (f_conf) { +case AD4170_FILTER_FILTER_TYPE_SINC5_AVG : +return AD4170_SINC5_AVG ; +case AD4170_FILTER_FILTER_TYPE_SINC5 : +return AD4170_SINC5 ; +case AD4170_FILTER_FILTER_TYPE_SINC3 : +return AD4170_SINC3 ; +default : +return -EINVAL ; + } +} + +static int ad4170_set_filter_type (struct iio_dev *indio_dev, +struct iio_chan_spec const *chan, +unsigned int val) +{ +struct ad4170_state *st =iio_priv (indio_dev); +struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address]; +struct ad4170_setup *setup = &chan_info->setup; +unsigned int filter_type_conf; +int ret; + +switch (val) { +case AD4170_SINC5_AVG : + filter_type_conf =AD4170_FILTER_FILTER_TYPE_SINC5_AVG ; +break ; +case AD4170_SINC5 : + filter_type_conf =AD4170_FILTER_FILTER_TYPE_SINC5 ; +break ; +case AD4170_SINC3 : + filter_type_conf =AD4170_FILTER_FILTER_TYPE_SINC3 ; +break ; +default : +return -EINVAL ; + } + +/* +* The filters provide the same ODR for a given filter_fs value but +* there are different minimum and maximum filter_fs limits for each +* filter. The filter_fs value will be adjusted if the current filter_fs +* is out of the limits of the just requested filter. Since the +* filter_fs value affects the ODR (sampling_frequency), changing the +* filter may lead to a change in the sampling frequency. +*/ + scoped_guard(mutex, &st->lock) { +if (!iio_device_claim_direct (indio_dev)) +return -EBUSY ; + +if (val ==AD4170_SINC5_AVG || val ==AD4170_SINC3 ) + setup->filter_fs =clamp (val,AD4170_SINC3_MIN_FS , +AD4170_SINC3_MAX_FS ); +else + setup->filter_fs =clamp (val,AD4170_SINC5_MIN_FS , +AD4170_SINC5_MAX_FS ); + + setup->filter &= ~AD4170_FILTER_FILTER_TYPE_MSK ; + setup->filter |=FIELD_PREP (AD4170_FILTER_FILTER_TYPE_MSK , + filter_type_conf); + + ret =ad4170_write_channel_setup (st, chan->address, false); +iio_device_release_direct (indio_dev); + } + +return ret; +} + +static int ad4170_get_filter_type (struct iio_dev *indio_dev, +struct iio_chan_spec const *chan) +{ +struct ad4170_state *st =iio_priv (indio_dev); +struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address]; +struct ad4170_setup *setup = &chan_info->setup; + +return __ad4170_get_filter_type (setup->filter); +} + +static const struct iio_enum ad4170_filter_type_enum = { + .items = ad4170_filt_names, + .num_items =ARRAY_SIZE (ad4170_filt_names), + .get = ad4170_get_filter_type, + .set = ad4170_set_filter_type, +}; + +static const struct iio_chan_spec_ext_info ad4170_filter_type_ext_info[] = { +IIO_ENUM ("filter_type" ,IIO_SEPARATE , &ad4170_filter_type_enum), +IIO_ENUM_AVAILABLE ("filter_type" ,IIO_SHARED_BY_TYPE , + &ad4170_filter_type_enum), + { } +}; +static const struct iio_chan_spec ad4170_channel_template = { .type =IIO_VOLTAGE , .indexed =1 ,
@@ -625,8 +792,11 @@ static const struct iio_chan_spec ad4170_channel_template = {BIT (IIO_CHAN_INFO_SCALE ) |BIT (IIO_CHAN_INFO_CALIBBIAS ) |BIT (IIO_CHAN_INFO_CALIBSCALE ) | +BIT (IIO_CHAN_INFO_SAMP_FREQ ) | BIT(IIO_CHAN_INFO_OFFSET), - .info_mask_separate_available = BIT(IIO_CHAN_INFO_SCALE), + .info_mask_separate_available =BIT (IIO_CHAN_INFO_SCALE ) | + BIT(IIO_CHAN_INFO_SAMP_FREQ), + .ext_info = ad4170_filter_type_ext_info, .scan_type = { .realbits = 24, .storagebits = 32,
@@ -921,7 +1091,8 @@ static int ad4170_read_raw(struct iio_dev *indio_dev,struct ad4170_state *st =iio_priv (indio_dev);struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address];struct ad4170_setup *setup = &chan_info->setup; -unsigned int pga; +enum ad4170_filter_type f_type; +unsigned int pga, fs_idx;int ret;guard (mutex)(&st->lock);
@@ -942,6 +1113,27 @@ static int ad4170_read_raw(struct iio_dev *indio_dev, pga =FIELD_GET (AD4170_AFE_PGA_GAIN_MSK , setup->afe); *val = chan_info->offset_tbl[pga];return IIO_VAL_INT ; +case IIO_CHAN_INFO_SAMP_FREQ : + f_type =__ad4170_get_filter_type (setup->filter); +switch (f_type) { +case AD4170_SINC5_AVG : +case AD4170_SINC3 : + fs_idx =find_closest (setup->filter_fs, + ad4170_sinc3_filt_fs_tbl, +ARRAY_SIZE (ad4170_sinc3_filt_fs_tbl)); + *val = st->sps_tbl[f_type][fs_idx][0 ]; + *val2 = st->sps_tbl[f_type][fs_idx][1 ]; +return IIO_VAL_INT_PLUS_MICRO ; +case AD4170_SINC5 : + fs_idx =find_closest (setup->filter_fs, + ad4170_sinc5_filt_fs_tbl, +ARRAY_SIZE (ad4170_sinc5_filt_fs_tbl)); + *val = st->sps_tbl[f_type][fs_idx][0 ]; + *val2 = st->sps_tbl[f_type][fs_idx][1 ]; +return IIO_VAL_INT_PLUS_MICRO ; +default : +return -EINVAL ; + }case IIO_CHAN_INFO_CALIBBIAS : *val = setup->offset;return IIO_VAL_INT ;
@@ -1027,6 +1219,7 @@ static int ad4170_read_avail(struct iio_dev *indio_dev, {struct ad4170_state *st =iio_priv (indio_dev);struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address]; +enum ad4170_filter_type f_type;switch (info) {case IIO_CHAN_INFO_SCALE :
@@ -1034,6 +1227,24 @@ static int ad4170_read_avail(struct iio_dev *indio_dev, *length =ARRAY_SIZE (chan_info->scale_tbl) *2 ; *type =IIO_VAL_INT_PLUS_NANO ;return IIO_AVAIL_LIST ; +case IIO_CHAN_INFO_SAMP_FREQ : + *type =IIO_VAL_INT_PLUS_MICRO ; + f_type =ad4170_get_filter_type (indio_dev, chan); +switch (f_type) { +case AD4170_SINC5_AVG : +case AD4170_SINC3 : +/* Read sps_tbl here to ensure in bounds array access */ + *vals = (int *)st->sps_tbl[f_type]; + *length =ARRAY_SIZE (ad4170_sinc3_filt_fs_tbl) *2 ; +return IIO_AVAIL_LIST ; +case AD4170_SINC5 : +/* Read sps_tbl here to ensure in bounds array access */ + *vals = (int *)st->sps_tbl[f_type]; + *length =ARRAY_SIZE (ad4170_sinc5_filt_fs_tbl) *2 ; +return IIO_AVAIL_LIST ; +default : +return -EINVAL ; + }default :return -EINVAL ; }
@@ -1062,6 +1273,42 @@ static int ad4170_set_pga(struct ad4170_state *st,return ad4170_write_channel_setup (st, chan->address, false); } +static int ad4170_set_channel_freq (struct ad4170_state *st, +struct iio_chan_spec const *chan,int val, +int val2) +{ +struct ad4170_chan_info *chan_info = &st->chan_infos[chan->address]; +struct ad4170_setup *setup = &chan_info->setup; +enum ad4170_filter_type f_type =__ad4170_get_filter_type (setup->filter); +unsigned int filt_fs_tbl_size, i; + +switch (f_type) { +case AD4170_SINC5_AVG : +case AD4170_SINC3 : + filt_fs_tbl_size =ARRAY_SIZE (ad4170_sinc3_filt_fs_tbl); +break ; +case AD4170_SINC5 : + filt_fs_tbl_size =ARRAY_SIZE (ad4170_sinc5_filt_fs_tbl); +break ; + } + +for (i =0 ; i < filt_fs_tbl_size; i++) { +if (st->sps_tbl[f_type][i][0 ] == val && + st->sps_tbl[f_type][i][1 ] == val2) +break ; + } +if (i == filt_fs_tbl_size) +return -EINVAL ; + +guard (mutex)(&st->lock); +if (f_type ==AD4170_SINC5 ) + setup->filter_fs = ad4170_sinc5_filt_fs_tbl[i]; +else + setup->filter_fs = ad4170_sinc3_filt_fs_tbl[i]; + +return ad4170_write_channel_setup (st, chan->address, false); +} +static int ad4170_set_calib_offset (struct ad4170_state *st,struct iio_chan_spec const *chan,int val) {
@@ -1095,6 +1342,8 @@ static int __ad4170_write_raw(struct iio_dev *indio_dev,switch (info) {case IIO_CHAN_INFO_SCALE :return ad4170_set_pga (st, chan, val, val2); +case IIO_CHAN_INFO_SAMP_FREQ : +return ad4170_set_channel_freq (st, chan, val, val2);case IIO_CHAN_INFO_CALIBBIAS :return ad4170_set_calib_offset (st, chan, val);case IIO_CHAN_INFO_CALIBSCALE :
@@ -1125,6 +1374,8 @@ static int ad4170_write_raw_get_fmt(struct iio_dev *indio_dev,switch (info) {case IIO_CHAN_INFO_SCALE :return IIO_VAL_INT_PLUS_NANO ; +case IIO_CHAN_INFO_SAMP_FREQ : +return IIO_VAL_INT_PLUS_MICRO ;case IIO_CHAN_INFO_CALIBBIAS :case IIO_CHAN_INFO_CALIBSCALE :return IIO_VAL_INT ;
@@ -1370,6 +1621,8 @@ static int ad4170_initial_config(struct iio_dev *indio_dev)unsigned int i;int ret; +ad4170_fill_sps_tbl (st); + ret = regmap_update_bits(st->regmap, AD4170_ADC_CTRL_REG, AD4170_ADC_CTRL_MODE_MSK, FIELD_PREP(AD4170_ADC_CTRL_MODE_MSK,
@@ -1402,6 +1655,12 @@ static int ad4170_initial_config(struct iio_dev *indio_dev)return dev_err_probe (dev, ret,"Failed to write CHAN_MAP_REG\n" ); + ret =ad4170_set_channel_freq (st, chan, +AD4170_DEFAULT_SAMP_RATE ,0 ); +if (ret) +return dev_err_probe (dev, ret, +"Failed to set channel freq\n" ); + ret =ad4170_fill_scale_tbl (indio_dev, chan);if (ret) return dev_err_probe(dev, ret,
Signature · 1 line
2.47.2
Marcelo Schmitt
maintainerPATCH v7 7/12 iio: adc: ad4170-4: Add support for buffered data capture
In reply to Marcelo SchmittExtend the AD4170-4 driver to allow buffered data capture in continuous read mode. In continuous read mode, the chip skips the instruction phase and outputs just ADC sample data, enabling faster sample rates to be reached. The internal channel sequencer always starts sampling from channel 0 and channel 0 must be enabled if more than one channel is selected for data capture. The scan mask validation callback checks if the aforementioned condition is met.
---
Change log v6 -> v7
- Dropped extra assignment of st->trig->dev.parent.
drivers/iio/adc/Kconfig | 2 + drivers/iio/adc/ad4170-4.c | 216 ++++++++++++++++++++++++++++++++++++- 2 files changed, 217 insertions(+), 1 deletion(-)
drivers/iio/adc/Kconfig +2 -0
@@ -89,6 +89,8 @@ config AD4170_4 tristate "Analog Device AD4170-4 ADC Driver" depends on SPI select REGMAP_SPI + select IIO_BUFFER + select IIO_TRIGGERED_BUFFER help Say yes here to build support for Analog Devices AD4170-4 SPI analog to digital converters (ADC).
drivers/iio/adc/ad4170-4.c +215 -1
308 lines not on this page · raw message
Signature · 1 line
2.47.2
Marcelo Schmitt
maintainerPATCH v7 8/12 iio: adc: ad4170-4: Add clock provider support
In reply to Marcelo SchmittThe AD4170-4 chip can use an externally supplied clock at the XTAL2 pin, or an external crystal connected to the XTAL1 and XTAL2 pins. Alternatively, the AD4170-4 can provide its 16 MHz internal clock at the XTAL2 pin. In addition, the chip has a programmable clock divider that allows dividing the external or internal clock frequency, however, control for that is not provided in this patch. Extend the AD4170-4 driver so it effectively uses the provided external clock, if any, or supplies its own clock as a clock provider.
---
No changes since v6.
drivers/iio/adc/Kconfig | 1 + drivers/iio/adc/ad4170-4.c | 147 ++++++++++++++++++++++++++++++++++++- 2 files changed, 147 insertions(+), 1 deletion(-)
drivers/iio/adc/Kconfig +1 -0
@@ -91,6 +91,7 @@ config AD4170_4 select REGMAP_SPI select IIO_BUFFER select IIO_TRIGGERED_BUFFER + depends on COMMON_CLK help Say yes here to build support for Analog Devices AD4170-4 SPI analog to digital converters (ADC).
drivers/iio/adc/ad4170-4.c +146 -1
207 lines not on this page · raw message
Signature · 1 line
2.47.2
Marcelo Schmitt
maintainerPATCH v7 9/12 iio: adc: ad4170-4: Add GPIO controller support
In reply to Marcelo SchmittThe AD4170-4 has four multifunctional pins that can be used as GPIOs. The GPIO functionality can be accessed when the AD4170-4 chip is not busy performing continuous data capture or handling any other register read/write request. Also, the AD4170-4 does not provide any interrupt based on GPIO pin states so AD4170-4 GPIOs can't be used as interrupt sources.
Implement gpio_chip callbacks to make AD4170-4 GPIO pins controllable through the gpiochip interface.
---
Change log v6 -> v7
- Used local device pointer (replaced &st->spi->dev with dev) in ad4170_parse_firmware().
drivers/iio/adc/Kconfig | 1 + drivers/iio/adc/ad4170-4.c | 224 ++++++++++++++++++++++++++++++++++++- 2 files changed, 224 insertions(+), 1 deletion(-)
drivers/iio/adc/Kconfig +1 -0
@@ -92,6 +92,7 @@ config AD4170_4 select IIO_BUFFER select IIO_TRIGGERED_BUFFER depends on COMMON_CLK + depends on GPIOLIB help Say yes here to build support for Analog Devices AD4170-4 SPI analog to digital converters (ADC).
drivers/iio/adc/ad4170-4.c +223 -1
282 lines not on this page · raw message
Signature · 1 line
2.47.2
Marcelo Schmitt
maintainerPATCH v7 10/12 iio: adc: ad4170-4: Add support for internal temperature sensor
In reply to Marcelo SchmittThe AD4170-4 has an internal temperature sensor that can be read using the ADC. Whenever possible, configure an IIO channel to provide the chip's temperature.
---
No changes since v3.
drivers/iio/adc/ad4170-4.c | 72 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 69 insertions(+), 3 deletions(-)
drivers/iio/adc/ad4170-4.c +69 -3
@@ -870,6 +870,27 @@ static const struct iio_chan_spec ad4170_channel_template = { }, }; +static const struct iio_chan_spec ad4170_temp_channel_template = { + .type =IIO_TEMP , + .indexed =0 , + .channel =17 , + .channel2 =17 , + .info_mask_separate =BIT (IIO_CHAN_INFO_RAW ) | +BIT (IIO_CHAN_INFO_SCALE ) | +BIT (IIO_CHAN_INFO_OFFSET ) | +BIT (IIO_CHAN_INFO_CALIBSCALE ) | +BIT (IIO_CHAN_INFO_CALIBBIAS ) | +BIT (IIO_CHAN_INFO_SAMP_FREQ ), + .info_mask_separate_available =BIT (IIO_CHAN_INFO_SAMP_FREQ ), + .scan_type = { + .sign ='s' , + .realbits =24 , + .storagebits =32 , + .shift =8 , + .endianness =IIO_BE , + }, +}; +/* * Receives the number of a multiplexed AD4170 input (ain_n), and stores the * voltage (in µV) of the specified input into ain_voltage. If the input number
@@ -1172,9 +1193,27 @@ static int ad4170_read_raw(struct iio_dev *indio_dev,return ret;case IIO_CHAN_INFO_SCALE : pga =FIELD_GET (AD4170_AFE_PGA_GAIN_MSK , setup->afe); - *val = chan_info->scale_tbl[pga][0 ]; - *val2 = chan_info->scale_tbl[pga][1 ]; -return IIO_VAL_INT_PLUS_NANO ; +switch (chan->type) { +case IIO_VOLTAGE : + *val = chan_info->scale_tbl[pga][0 ]; + *val2 = chan_info->scale_tbl[pga][1 ]; +return IIO_VAL_INT_PLUS_NANO ; + +case IIO_TEMP : +/* +* The scale_tbl converts output codes to mV units so +* multiply by MILLI to make the factor convert to µV. +* Then, apply the temperature sensor change sensitivity +* of 477 μV/K. Finally, multiply the result by MILLI +* again to comply with milli degrees Celsius IIO ABI. +*/ + *val =0 ; + *val2 =DIV_ROUND_CLOSEST (chan_info->scale_tbl[pga][1 ] *MILLI ,477 ) * +MILLI ; +return IIO_VAL_INT_PLUS_NANO ; +default : +return -EINVAL ; + }case IIO_CHAN_INFO_OFFSET : pga =FIELD_GET (AD4170_AFE_PGA_GAIN_MSK , setup->afe); *val = chan_info->offset_tbl[pga];
@@ -1842,6 +1881,9 @@ static int ad4170_parse_channels(struct iio_dev *indio_dev)if (num_channels >AD4170_MAX_CHANNELS )return dev_err_probe (dev, -EINVAL ,"Too many channels\n" ); +/* Add one for temperature */ + num_channels =min (num_channels +1 ,AD4170_MAX_CHANNELS ); + chan_num =0 ;device_for_each_child_node_scoped (dev, child) { ret =ad4170_parse_channel_node (indio_dev, child, chan_num++);
@@ -1849,6 +1891,30 @@ static int ad4170_parse_channels(struct iio_dev *indio_dev)return ret; } +/* +* Add internal temperature sensor channel if the maximum number of +* channels has not been reached. +*/ +if (num_channels <AD4170_MAX_CHANNELS ) { +struct ad4170_setup *setup = &st->chan_infos[chan_num].setup; + + st->chans[chan_num] = ad4170_temp_channel_template; + st->chans[chan_num].address = chan_num; + st->chans[chan_num].scan_index = chan_num; + + st->chan_infos[chan_num].setup_num =AD4170_INVALID_SETUP ; + st->chan_infos[chan_num].initialized = true; + + setup->afe |=FIELD_PREP (AD4170_AFE_REF_SELECT_MSK , +AD4170_REF_AVDD ); + + ret =ad4170_get_input_range (st, &st->chans[chan_num], chan_num, +AD4170_REF_AVDD ); +if (ret <0 ) +return dev_err_probe (dev, ret,"Invalid input config\n" ); + + st->chan_infos[chan_num].input_range_uv = ret; + } indio_dev->num_channels = num_channels; indio_dev->channels = st->chans;
Signature · 1 line
2.47.2
Marcelo Schmitt
maintainerPATCH v7 11/12 iio: adc: ad4170-4: Add support for weigh scale and RTD sensors
In reply to Marcelo SchmittThe AD4170-4 design has features to aid interfacing with weigh scale and RTD sensors that are expected to be setup with external circuitry for proper sensor operation. A key characteristic of those sensors is that the circuit they are in must be excited with a pair of signals. The external circuit can be excited either by voltage supply or by AD4170-4 excitation signals. The sensor can then be read through a different pair of lines that are connected to AD4170-4 ADC.
Configure AD4170-4 to handle external circuit sensors.
---
Change log v6 -> v7
- adi,vbias was previously set per channel in ad4170 dt-binding but it is set per device in adi,ad4130.yaml. Fixed ad4170 parsing of adi,vbias. The dt-binding had been updated to the established use of adi,vbias in v4.
drivers/iio/adc/ad4170-4.c | 514 ++++++++++++++++++++++++++++++++++++- 1 file changed, 510 insertions(+), 4 deletions(-)
drivers/iio/adc/ad4170-4.c +510 -4
@@ -69,6 +69,8 @@#define AD4170_FILTER_FS_REG (x) (0xC7 + 14 * (x))#define AD4170_OFFSET_REG (x) (0xCA + 14 * (x))#define AD4170_GAIN_REG (x) (0xCD + 14 * (x)) +#define AD4170_V_BIAS_REG 0x135 +#define AD4170_CURRENT_SRC_REG (x) (0x139 + 2 * (x))#define AD4170_GPIO_MODE_REG 0x191#define AD4170_GPIO_OUTPUT_REG 0x193#define AD4170_GPIO_INPUT_REG 0x195
@@ -100,6 +102,10 @@#define AD4170_CHAN_MAP_AINP_MSK GENMASK(12, 8)#define AD4170_CHAN_MAP_AINM_MSK GENMASK(4, 0) +/* AD4170_MISC_REG */ +#define AD4170_MISC_CHOP_IEXC_MSK GENMASK(15, 14) +#define AD4170_MISC_CHOP_ADC_MSK GENMASK(9, 8) +/* AD4170_AFE_REG */ #define AD4170_AFE_REF_BUF_M_MSK GENMASK(11, 10)#define AD4170_AFE_REF_BUF_P_MSK GENMASK(9, 8)
@@ -110,12 +116,19 @@/* AD4170_FILTER_REG */ #define AD4170_FILTER_FILTER_TYPE_MSK GENMASK(3, 0) +/* AD4170_CURRENT_SRC_REG */ +#define AD4170_CURRENT_SRC_I_OUT_PIN_MSK GENMASK(12, 8) +#define AD4170_CURRENT_SRC_I_OUT_VAL_MSK GENMASK(2, 0) +/* AD4170_GPIO_MODE_REG */ #define AD4170_GPIO_MODE_GPIO0_MSK GENMASK(1, 0)#define AD4170_GPIO_MODE_GPIO1_MSK GENMASK(3, 2)#define AD4170_GPIO_MODE_GPIO2_MSK GENMASK(5, 4)#define AD4170_GPIO_MODE_GPIO3_MSK GENMASK(7, 6) +/* AD4170_GPIO_OUTPUT_REG */ +#define AD4170_GPIO_OUTPUT_GPIO_MSK (x) BIT(x) +/* AD4170 register constants */ /* AD4170_CLOCK_CTRL_REG constants */
@@ -139,6 +152,11 @@#define AD4170_CHAN_MAP_REFIN2_N 28#define AD4170_CHAN_MAP_REFOUT 29 +/* AD4170_MISC_REG constants */ +#define AD4170_MISC_CHOP_IEXC_PAIR1 0x1 +#define AD4170_MISC_CHOP_IEXC_PAIR2 0x2 +#define AD4170_MISC_CHOP_IEXC_BOTH 0x3 +/* AD4170_PIN_MUXING_REG constants */ #define AD4170_PIN_MUXING_DIG_AUX1_DISABLED 0x0#define AD4170_PIN_MUXING_DIG_AUX1_RDY 0x1
@@ -156,6 +174,10 @@#define AD4170_FILTER_FILTER_TYPE_SINC5 0x4#define AD4170_FILTER_FILTER_TYPE_SINC3 0x6 +/* AD4170_CURRENT_SRC_REG constants */ +#define AD4170_CURRENT_SRC_I_OUT_PIN_AIN (x) (x) +#define AD4170_CURRENT_SRC_I_OUT_PIN_GPIO (x) ((x) + 17) +/* AD4170_GPIO_MODE_REG constants */ #define AD4170_GPIO_MODE_GPIO_INPUT 1#define AD4170_GPIO_MODE_GPIO_OUTPUT 2
@@ -170,6 +192,7 @@#define AD4170_INVALID_SETUP 9#define AD4170_SPI_INST_PHASE_LEN 2#define AD4170_SPI_MAX_XFER_LEN 6 +#define AD4170_NUM_CURRENT_SRC 4#define AD4170_DEFAULT_SAMP_RATE (125 * HZ_PER_KHZ)#define AD4170_INT_REF_2_5V 2500000
@@ -191,8 +214,19 @@#define AD4170_ADC_CTRL_CONT_READ_EXIT 0xA5 +/* Analog pin functions */ +#define AD4170_PIN_UNASSIGNED 0x00 +#define AD4170_PIN_ANALOG_IN 0x01 +#define AD4170_PIN_CURRENT_OUT 0x02 +#define AD4170_PIN_VBIAS 0x04 +/* GPIO pin functions */ #define AD4170_GPIO_UNASSIGNED 0x00 +#define AD4170_GPIO_AC_EXCITATION 0x02 +#define AD4170_GPIO_OUTPUT 0x04 + +/* Current source */ +#define AD4170_CURRENT_SRC_DISABLED 0xFFstatic const unsigned int ad4170_reg_size[] = { [AD4170_CONFIG_A_REG ] =1 ,
@@ -231,6 +265,8 @@ static const unsigned int ad4170_reg_size[] = { [AD4170_OFFSET_REG(5) ... AD4170_GAIN_REG(5)] = 3, [AD4170_OFFSET_REG(6) ... AD4170_GAIN_REG(6)] = 3, [AD4170_OFFSET_REG(7) ... AD4170_GAIN_REG(7)] = 3, + [AD4170_V_BIAS_REG ] =2 , + [AD4170_CURRENT_SRC_REG(0) ... AD4170_CURRENT_SRC_REG(3)] = 2, [AD4170_GPIO_MODE_REG] = 2, [AD4170_GPIO_OUTPUT_REG] = 2, [AD4170_GPIO_INPUT_REG] = 2,
@@ -300,6 +336,41 @@ static const unsigned int ad4170_sinc5_filt_fs_tbl[] = { 1, 2, 4, 8, 12, 16, 20, 40, 48, 80, 100, 256, }; +static const unsigned int ad4170_iout_pin_tbl[] = { +AD4170_CURRENT_SRC_I_OUT_PIN_AIN (0 ), +AD4170_CURRENT_SRC_I_OUT_PIN_AIN (1 ), +AD4170_CURRENT_SRC_I_OUT_PIN_AIN (2 ), +AD4170_CURRENT_SRC_I_OUT_PIN_AIN (3 ), +AD4170_CURRENT_SRC_I_OUT_PIN_AIN (4 ), +AD4170_CURRENT_SRC_I_OUT_PIN_AIN (5 ), +AD4170_CURRENT_SRC_I_OUT_PIN_AIN (6 ), +AD4170_CURRENT_SRC_I_OUT_PIN_AIN (7 ), +AD4170_CURRENT_SRC_I_OUT_PIN_AIN (8 ), +AD4170_CURRENT_SRC_I_OUT_PIN_GPIO (0 ), +AD4170_CURRENT_SRC_I_OUT_PIN_GPIO (1 ), +AD4170_CURRENT_SRC_I_OUT_PIN_GPIO (2 ), +AD4170_CURRENT_SRC_I_OUT_PIN_GPIO (3 ), +}; + +static const unsigned int ad4170_iout_current_ua_tbl[] = { +0 ,10 ,50 ,100 ,250 ,500 ,1000 ,1500 , +}; + +enum ad4170_sensor_enum { +AD4170_ADC_SENSOR =0 , +AD4170_WEIGH_SCALE_SENSOR =1 , +AD4170_RTD_SENSOR =2 , +AD4170_THERMOCOUPLE_SENSOR =3 , +}; + +/* maps adi,sensor-type property value to enum */ +static const char *const ad4170_sensor_type[] = { + [AD4170_ADC_SENSOR ] ="adc" , + [AD4170_WEIGH_SCALE_SENSOR ] ="weighscale" , + [AD4170_RTD_SENSOR ] ="rtd" , + [AD4170_THERMOCOUPLE_SENSOR ] ="thermocouple" , +}; +struct ad4170_chip_info {const char *name; };
@@ -384,6 +455,7 @@ struct ad4170_state {struct gpio_chip gpiochip;unsigned int clock_ctrl;int gpio_fn[AD4170_NUM_GPIO_PINS ]; +unsigned int cur_src_pins[AD4170_NUM_CURRENT_SRC ];/* * DMA (thus cache coherency maintenance) requires the transfer buffers * to live in their own cache lines.
@@ -905,6 +977,19 @@ static int ad4170_get_ain_voltage_uv(struct ad4170_state *st, int ain_n,int v_diff; *ain_voltage =0 ; +/* +* The voltage bias (vbias) sets the common-mode voltage of the channel +* to (AVDD + AVSS)/2. If provided, AVSS supply provides the magnitude +* (absolute value) of the negative voltage supplied to the AVSS pin. +* So, we do AVDD - AVSS to compute the DC voltage generated by the bias +* voltage generator. +*/ +if (st->pins_fn[ain_n] &AD4170_PIN_VBIAS ) { +int v_diff = st->vrefs_uv[AD4170_AVDD_SUP ] - st->vrefs_uv[AD4170_AVSS_SUP ]; + *ain_voltage = v_diff /2 ; +return 0 ; + } +if (ain_n <=AD4170_CHAN_MAP_TEMP_SENSOR )return 0 ;
@@ -959,6 +1044,19 @@ static int ad4170_get_ain_voltage_uv(struct ad4170_state *st, int ain_n, } } +static int ad4170_validate_analog_input (struct ad4170_state *st,int pin) +{ +if (pin <=AD4170_MAX_ANALOG_PINS ) { +if (st->pins_fn[pin] &AD4170_PIN_CURRENT_OUT ) +return dev_err_probe (&st->spi->dev, -EINVAL , +"Pin %d already used with fn %u.\n" , + pin, st->pins_fn[pin]); + + st->pins_fn[pin] |=AD4170_PIN_ANALOG_IN ; + } +return 0 ; +} +static int ad4170_validate_channel_input (struct ad4170_state *st,int pin,bool com) {/* Check common-mode input pin is mapped to a special input. */
@@ -973,7 +1071,7 @@ static int ad4170_validate_channel_input(struct ad4170_state *st, int pin, bool"Invalid analog input pin number. %d\n" , pin); -return 0 ; +return ad4170_validate_analog_input (st, pin); }/*
@@ -1716,6 +1814,370 @@ static int ad4170_gpio_init(struct iio_dev *indio_dev)return devm_gpiochip_add_data (&st->spi->dev, &st->gpiochip, indio_dev); } +static int ad4170_validate_excitation_pin (struct ad4170_state *st,u32 pin) +{ +struct device *dev = &st->spi->dev; +unsigned int i; + +/* Check the pin number is valid */ +for (i =0 ; i <ARRAY_SIZE (ad4170_iout_pin_tbl); i++) +if (ad4170_iout_pin_tbl[i] == pin) +break ; + +if (i ==ARRAY_SIZE (ad4170_iout_pin_tbl)) +return dev_err_probe (dev, -EINVAL , +"Invalid excitation pin: %u\n" , + pin); + +/* Check the pin is available */ +if (pin <=AD4170_MAX_ANALOG_PINS ) { +if (st->pins_fn[pin] !=AD4170_PIN_UNASSIGNED ) +return dev_err_probe (dev, -EINVAL , +"Pin %u already used with fn %u\n" , + pin, st->pins_fn[pin]); + + st->pins_fn[pin] |=AD4170_PIN_CURRENT_OUT ; + }else { +unsigned int gpio = pin -AD4170_CURRENT_SRC_I_OUT_PIN_GPIO (0 ); + +if (st->gpio_fn[gpio] !=AD4170_GPIO_UNASSIGNED ) +return dev_err_probe (dev, -EINVAL , +"GPIO %u already used with fn %u\n" , + gpio, st->gpio_fn[gpio]); + + st->gpio_fn[gpio] |=AD4170_GPIO_AC_EXCITATION ; + } + +return 0 ; +} + +static int ad4170_validate_excitation_pins (struct ad4170_state *st, +u32 *exc_pins,int num_exc_pins) +{ +unsigned int i; +int ret; + +for (i =0 ; i < num_exc_pins; i++) { + ret =ad4170_validate_excitation_pin (st, exc_pins[i]); +if (ret) +return ret; + } +return 0 ; +} + +static const char *const ad4170_i_out_pin_dt_props[] = { +"adi,excitation-pin-0" , +"adi,excitation-pin-1" , +"adi,excitation-pin-2" , +"adi,excitation-pin-3" , +}; + +static const char *const ad4170_i_out_val_dt_props[] = { +"adi,excitation-current-0-microamp" , +"adi,excitation-current-1-microamp" , +"adi,excitation-current-2-microamp" , +"adi,excitation-current-3-microamp" , +}; + +/* +* Parses firmware data describing output current source setup. There are 4 +* excitation currents (IOUT0 to IOUT3) that can be configured independently. +* Excitation currents are added if they are output on the same pin. +*/ +static int ad4170_parse_exc_current (struct ad4170_state *st, +struct fwnode_handle *child, +unsigned int *exc_pins, +unsigned int *exc_curs, +unsigned int *num_exc_pins) +{ +struct device *dev = &st->spi->dev; +unsigned int num_pins, i, j; +u32 pin, val; +int ret; + + num_pins =0 ; +for (i =0 ; i <AD4170_NUM_CURRENT_SRC ; i++) { +/* Parse excitation current output pin properties. */ + pin =AD4170_CURRENT_SRC_I_OUT_PIN_AIN (0 ); + ret =fwnode_property_read_u32 (child, ad4170_i_out_pin_dt_props[i], + &pin); +if (ret) +continue ; + + exc_pins[num_pins] = pin; + +/* Parse excitation current value properties. */ + val = ad4170_iout_current_ua_tbl[0 ]; +fwnode_property_read_u32 (child, + ad4170_i_out_val_dt_props[i], &val); + +for (j =0 ; j <ARRAY_SIZE (ad4170_iout_current_ua_tbl); j++) +if (ad4170_iout_current_ua_tbl[j] == val) +break ; + +if (j ==ARRAY_SIZE (ad4170_iout_current_ua_tbl)) +return dev_err_probe (dev, -EINVAL ,"Invalid %s: %uuA\n" , + ad4170_i_out_val_dt_props[i], val); + + exc_curs[num_pins] = j; + num_pins++; + } + *num_exc_pins = num_pins; + +return 0 ; +} + +static int ad4170_setup_current_src (struct ad4170_state *st, +struct fwnode_handle *child, +struct ad4170_setup *setup,u32 *exc_pins, +unsigned int *exc_curs,int num_exc_pins, +bool ac_excited) +{ +unsigned int exc_cur_pair, i, j; +int ret; + +for (i =0 ; i < num_exc_pins; i++) { +unsigned int exc_cur = exc_curs[i]; +unsigned int pin = exc_pins[i]; +unsigned int current_src =0 ; + +for (j =0 ; j <AD4170_NUM_CURRENT_SRC ; j++) +if (st->cur_src_pins[j] ==AD4170_CURRENT_SRC_DISABLED ) +break ; + +if (j ==AD4170_NUM_CURRENT_SRC ) +return dev_err_probe (&st->spi->dev, -EINVAL , +"Too many excitation current sources\n" ); + + current_src |=FIELD_PREP (AD4170_CURRENT_SRC_I_OUT_PIN_MSK , pin); + current_src |=FIELD_PREP (AD4170_CURRENT_SRC_I_OUT_VAL_MSK , exc_cur); + st->cur_src_pins[j] = pin; + ret =regmap_write (st->regmap,AD4170_CURRENT_SRC_REG (j), + current_src); +if (ret) +return ret; + } + +if (!ac_excited) +return 0 ; + +if (num_exc_pins <2 ) +return dev_err_probe (&st->spi->dev, -EINVAL , +"Current chopping requested but only one pin provided: %u\n" , + exc_pins[0 ]); + +/* +* Two use cases to handle here: +* - 2 pairs of excitation currents; +* - 1 pair of excitation currents. +*/ +if (num_exc_pins ==4 ) { +for (i =0 ; i <AD4170_NUM_CURRENT_SRC ; i++) +if (st->cur_src_pins[i] != exc_pins[i]) +return dev_err_probe (&st->spi->dev, -EINVAL , +"Unable to use 4 exc pins\n" ); + }else { +/* +* Excitation current chopping is configured in pairs. Current +* sources IOUT0 and IOUT1 form pair 1, IOUT2 and IOUT3 make up +* pair 2. So, if current chopping was requested, check if the +* first end of the first pair of excitation currents is +* available. Try the next pair if IOUT0 has already been +* configured for another channel. +*/ + i = st->cur_src_pins[0 ] == exc_pins[0 ] ?0 :2 ; + +if (st->cur_src_pins[i] != exc_pins[0 ] || + st->cur_src_pins[i +1 ] != exc_pins[1 ]) +return dev_err_probe (&st->spi->dev, -EINVAL , +"Failed to setup current chopping\n" ); + + st->cur_src_pins[i] = exc_pins[0 ]; + st->cur_src_pins[i +1 ] = exc_pins[1 ]; + +if (i ==0 ) + exc_cur_pair =AD4170_MISC_CHOP_IEXC_PAIR1 ; +else + exc_cur_pair =AD4170_MISC_CHOP_IEXC_PAIR2 ; + } + +/* +* Configure excitation current chopping. +* Chop both pairs if using four excitation pins. +*/ + setup->misc |=FIELD_PREP (AD4170_MISC_CHOP_IEXC_MSK , + num_exc_pins ==2 ? + exc_cur_pair : +AD4170_MISC_CHOP_IEXC_BOTH ); + +return 0 ; +} + +static int ad4170_setup_bridge (struct ad4170_state *st, +struct fwnode_handle *child, +struct ad4170_setup *setup,u32 *exc_pins, +unsigned int *exc_curs,int num_exc_pins, +bool ac_excited) +{ +unsigned long gpio_mask; +unsigned int i; +int ret; + +/* +* If a specific current is provided through +* adi,excitation-current-n-microamp, set excitation pins provided +* through adi,excitation-pin-n to excite the bridge circuit. +*/ +for (i =0 ; i < num_exc_pins; i++) +if (exc_curs[i] >0 ) +return ad4170_setup_current_src (st, child, setup, exc_pins, + exc_curs, num_exc_pins, + ac_excited); + +/* +* Else, use predefined ACX1, ACX1 negated, ACX2, ACX2 negated signals +* to AC excite the bridge. Those signals are output on GPIO2, GPIO0, +* GPIO3, and GPIO1, respectively. If only two pins are specified for AC +* excitation, use ACX1 and ACX2 (GPIO2 and GPIO3). +* +* Also, to avoid any short-circuit condition when more than one channel +* is enabled, set GPIO2 and GPIO0 high, and set GPIO1 and GPIO3 low to +* DC excite the bridge whenever a channel without AC excitation is +* selected. That is needed because GPIO pins are controlled by the next +* highest priority GPIO function when a channel doesn't enable AC +* excitation. See datasheet Figure 113 Weigh Scale (AC Excitation) for +* the reference circuit diagram. +*/ +if (num_exc_pins ==2 ) { + setup->misc |=FIELD_PREP (AD4170_MISC_CHOP_ADC_MSK ,0x3 ); + + gpio_mask =AD4170_GPIO_MODE_GPIO3_MSK |AD4170_GPIO_MODE_GPIO2_MSK ; + ret =regmap_update_bits (st->regmap,AD4170_GPIO_MODE_REG , gpio_mask, +FIELD_PREP (AD4170_GPIO_MODE_GPIO3_MSK , +AD4170_GPIO_MODE_GPIO_OUTPUT ) | +FIELD_PREP (AD4170_GPIO_MODE_GPIO2_MSK , +AD4170_GPIO_MODE_GPIO_OUTPUT )); +if (ret) +return ret; + +/* +* Set GPIO2 high and GPIO3 low to DC excite the bridge when +* a different channel is selected. +*/ + gpio_mask =AD4170_GPIO_OUTPUT_GPIO_MSK (3 ) | +AD4170_GPIO_OUTPUT_GPIO_MSK (2 ); + ret =regmap_update_bits (st->regmap,AD4170_GPIO_OUTPUT_REG , gpio_mask, +FIELD_PREP (AD4170_GPIO_OUTPUT_GPIO_MSK (3 ),0 ) | +FIELD_PREP (AD4170_GPIO_OUTPUT_GPIO_MSK (2 ),1 )); +if (ret) +return ret; + + st->gpio_fn[3 ] |=AD4170_GPIO_OUTPUT ; + st->gpio_fn[2 ] |=AD4170_GPIO_OUTPUT ; + }else { + setup->misc |=FIELD_PREP (AD4170_MISC_CHOP_ADC_MSK ,0x2 ); + + gpio_mask =AD4170_GPIO_MODE_GPIO3_MSK |AD4170_GPIO_MODE_GPIO2_MSK | +AD4170_GPIO_MODE_GPIO1_MSK |AD4170_GPIO_MODE_GPIO0_MSK ; + ret =regmap_update_bits (st->regmap,AD4170_GPIO_MODE_REG , gpio_mask, +FIELD_PREP (AD4170_GPIO_MODE_GPIO3_MSK , +AD4170_GPIO_MODE_GPIO_OUTPUT ) | +FIELD_PREP (AD4170_GPIO_MODE_GPIO2_MSK , +AD4170_GPIO_MODE_GPIO_OUTPUT ) | +FIELD_PREP (AD4170_GPIO_MODE_GPIO1_MSK , +AD4170_GPIO_MODE_GPIO_OUTPUT ) | +FIELD_PREP (AD4170_GPIO_MODE_GPIO0_MSK , +AD4170_GPIO_MODE_GPIO_OUTPUT )); +if (ret) +return ret; + +/* +* Set GPIO2 and GPIO0 high, and set GPIO1 and GPIO3 low to DC +* excite the bridge when a different channel is selected. +*/ + gpio_mask =AD4170_GPIO_OUTPUT_GPIO_MSK (3 ) | +AD4170_GPIO_OUTPUT_GPIO_MSK (2 ) | +AD4170_GPIO_OUTPUT_GPIO_MSK (1 ) | +AD4170_GPIO_OUTPUT_GPIO_MSK (0 ); + ret =regmap_update_bits (st->regmap,AD4170_GPIO_OUTPUT_REG , gpio_mask, +FIELD_PREP (AD4170_GPIO_OUTPUT_GPIO_MSK (3 ),0 ) | +FIELD_PREP (AD4170_GPIO_OUTPUT_GPIO_MSK (2 ),1 ) | +FIELD_PREP (AD4170_GPIO_OUTPUT_GPIO_MSK (1 ),0 ) | +FIELD_PREP (AD4170_GPIO_OUTPUT_GPIO_MSK (0 ),1 )); +if (ret) +return ret; + + st->gpio_fn[3 ] |=AD4170_GPIO_OUTPUT ; + st->gpio_fn[2 ] |=AD4170_GPIO_OUTPUT ; + st->gpio_fn[1 ] |=AD4170_GPIO_OUTPUT ; + st->gpio_fn[0 ] |=AD4170_GPIO_OUTPUT ; + } + +return 0 ; +} + +static int ad4170_setup_rtd (struct ad4170_state *st, +struct fwnode_handle *child, +struct ad4170_setup *setup,u32 *exc_pins, +unsigned int *exc_curs,int num_exc_pins,bool ac_excited) +{ +return ad4170_setup_current_src (st, child, setup, exc_pins, + exc_curs, num_exc_pins, ac_excited); +} + +static int ad4170_parse_external_sensor (struct ad4170_state *st, +struct fwnode_handle *child, +struct ad4170_setup *setup, +struct iio_chan_spec *chan,u8 s_type) +{ +unsigned int num_exc_pins, reg_val; +struct device *dev = &st->spi->dev; +u32 pins[2 ], exc_pins[4 ], exc_curs[4 ]; +bool ac_excited; +int ret; + + ret =fwnode_property_read_u32_array (child,"diff-channels" , pins, +ARRAY_SIZE (pins)); +if (ret) +return dev_err_probe (dev, ret, +"Failed to read sensor diff-channels\n" ); + + chan->differential = true; + chan->channel = pins[0 ]; + chan->channel2 = pins[1 ]; + + ret =ad4170_parse_exc_current (st, child, exc_pins, exc_curs, &num_exc_pins); +if (ret) +return ret; + +/* The external sensor may not need excitation from the ADC chip. */ +if (num_exc_pins ==0 ) +return 0 ; + + ret =ad4170_validate_excitation_pins (st, exc_pins, num_exc_pins); +if (ret) +return ret; + + ac_excited =fwnode_property_read_bool (child,"adi,excitation-ac" ); + +if (s_type ==AD4170_THERMOCOUPLE_SENSOR ) { +if (st->pins_fn[chan->channel2] &AD4170_PIN_VBIAS ) { + reg_val =BIT (chan->channel2); + ret =regmap_write (st->regmap,AD4170_V_BIAS_REG , reg_val); +if (ret) +dev_err_probe (dev, ret,"Failed to set vbias\n" ); + } + } +if (s_type ==AD4170_WEIGH_SCALE_SENSOR ) + ret =ad4170_setup_bridge (st, child, setup, exc_pins, exc_curs, + num_exc_pins, ac_excited); +else + ret =ad4170_setup_rtd (st, child, setup, exc_pins, exc_curs, + num_exc_pins, ac_excited); + +return ret; +} +static int ad4170_parse_reference (struct ad4170_state *st,struct fwnode_handle *child,struct ad4170_setup *setup)
@@ -1817,6 +2279,7 @@ static int ad4170_parse_channel_node(struct iio_dev *indio_dev,struct ad4170_setup *setup;struct iio_chan_spec *chan;unsigned int ref_select; +unsigned int s_type;unsigned int ch_reg;bool bipolar;int ret;
@@ -1844,10 +2307,28 @@ static int ad4170_parse_channel_node(struct iio_dev *indio_dev,if (ret)return ret; - ret =ad4170_parse_adc_channel_type (dev, child, chan); -if (ret) -return ret; + ret =fwnode_property_match_property_string (child,"adi,sensor-type" , + ad4170_sensor_type, +ARRAY_SIZE (ad4170_sensor_type)); + +/* Default to conventional ADC channel if sensor type not present */ + s_type = ret <0 ?AD4170_ADC_SENSOR : ret; +switch (s_type) { +case AD4170_ADC_SENSOR : + ret =ad4170_parse_adc_channel_type (dev, child, chan); +if (ret) +return ret; + +break ; +case AD4170_WEIGH_SCALE_SENSOR : +case AD4170_THERMOCOUPLE_SENSOR : +case AD4170_RTD_SENSOR : + ret =ad4170_parse_external_sensor (st, child, setup, chan, s_type); +if (ret) +return ret; +break ; + } bipolar =fwnode_property_read_bool (child,"bipolar" ); setup->afe |=FIELD_PREP (AD4170_AFE_BIPOLAR_MSK , bipolar);if (bipolar)
@@ -2041,9 +2522,12 @@ static int ad4170_clock_select(struct iio_dev *indio_dev)static int ad4170_parse_firmware (struct iio_dev *indio_dev) { +unsigned int vbias_pins[AD4170_MAX_ANALOG_PINS ];struct ad4170_state *st =iio_priv (indio_dev);struct device *dev = &st->spi->dev; +unsigned int num_vbias_pins;int reg_data, ret; +unsigned int i; ret =ad4170_clock_select (indio_dev);if (ret)
@@ -2053,6 +2537,9 @@ static int ad4170_parse_firmware(struct iio_dev *indio_dev)if (ret)return ret; +for (i =0 ; i <AD4170_NUM_CURRENT_SRC ; i++) + st->cur_src_pins[i] =AD4170_CURRENT_SRC_DISABLED ; +/* On power on, device defaults to using SDO pin for data ready signal */ st->int_pin_sel =AD4170_INT_PIN_SDO ; ret = device_property_match_property_string(dev, "interrupt-names",
@@ -2071,6 +2558,25 @@ static int ad4170_parse_firmware(struct iio_dev *indio_dev)if (ret)return ret; + ret =device_property_count_u32 (dev,"adi,vbias-pins" ); +if (ret >0 ) { +if (ret >AD4170_MAX_ANALOG_PINS ) +return dev_err_probe (dev, -EINVAL , +"Too many vbias pins %u\n" , ret); + + num_vbias_pins = ret; + + ret =device_property_read_u32_array (dev,"adi,vbias-pins" , + vbias_pins, + num_vbias_pins); +if (ret) +return dev_err_probe (dev, ret, +"Failed to read vbias pins\n" ); + +for (i =0 ; i < num_vbias_pins; i++) + st->pins_fn[vbias_pins[i]] |=AD4170_PIN_VBIAS ; + } + ret =ad4170_parse_channels (indio_dev);if (ret)return ret;
Signature · 1 line
2.47.2
Marcelo Schmitt
maintainerPATCH v7 12/12 iio: adc: ad4170-4: Add timestamp channel
In reply to Marcelo SchmittAdd timestamp channel allowing to record the moment at which ADC samples are captured in buffered read mode.
---
No changes since v5.
drivers/iio/adc/ad4170-4.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-)
drivers/iio/adc/ad4170-4.c +17 -4
@@ -187,6 +187,7 @@#define AD4170_NUM_ANALOG_PINS 9#define AD4170_NUM_GPIO_PINS 4#define AD4170_MAX_CHANNELS 16 +#define AD4170_MAX_IIO_CHANNELS (AD4170_MAX_CHANNELS + 1)#define AD4170_MAX_ANALOG_PINS 8#define AD4170_MAX_SETUPS 8#define AD4170_INVALID_SETUP 9
@@ -439,7 +440,7 @@ struct ad4170_state {int vrefs_uv[AD4170_MAX_SUP ];u32 mclk_hz;struct ad4170_setup_info setup_infos[AD4170_MAX_SETUPS ]; -struct iio_chan_spec chans[AD4170_MAX_CHANNELS ]; +struct iio_chan_spec chans[AD4170_MAX_IIO_CHANNELS ];struct ad4170_chan_info chan_infos[AD4170_MAX_CHANNELS ];struct spi_device *spi;struct regmap *regmap;
@@ -456,6 +457,7 @@ struct ad4170_state {unsigned int clock_ctrl;int gpio_fn[AD4170_NUM_GPIO_PINS ];unsigned int cur_src_pins[AD4170_NUM_CURRENT_SRC ]; +unsigned int num_adc_chans;/* * DMA (thus cache coherency maintenance) requires the transfer buffers * to live in their own cache lines.
@@ -2395,7 +2397,16 @@ static int ad4170_parse_channels(struct iio_dev *indio_dev)return dev_err_probe (dev, ret,"Invalid input config\n" ); st->chan_infos[chan_num].input_range_uv = ret; + chan_num++; } + st->num_adc_chans = chan_num; + +/* Add timestamp channel */ +struct iio_chan_spec ts_chan =IIO_CHAN_SOFT_TIMESTAMP (chan_num); + + st->chans[chan_num] = ts_chan; + num_channels = num_channels +1 ; + indio_dev->num_channels = num_channels; indio_dev->channels = st->chans;
@@ -2608,7 +2619,7 @@ static int ad4170_initial_config(struct iio_dev *indio_dev)return dev_err_probe (dev, ret,"Failed to set ADC mode to idle\n" ); -for (i =0 ; i < indio_dev->num_channels; i++) { +for (i =0 ; i < st->num_adc_chans; i++) {struct ad4170_chan_info *chan_info;struct iio_chan_spec const *chan;struct ad4170_setup *setup;
@@ -2733,7 +2744,7 @@ static int ad4170_buffer_predisable(struct iio_dev *indio_dev)* is done after buffer disable. Disable all channels so only requested * channels will be read. */ -for (i =0 ; i < indio_dev->num_channels; i++) { +for (i =0 ; i < st->num_adc_chans; i++) { ret =ad4170_set_channel_enable (st, i, false);if (ret)return ret;
@@ -2785,7 +2796,9 @@ static irqreturn_t ad4170_trigger_handler(int irq, void *p)memcpy (&st->bounce_buffer[i++], st->rx_buf,ARRAY_SIZE (st->rx_buf)); } -iio_push_to_buffers (indio_dev, st->bounce_buffer); +iio_push_to_buffers_with_ts (indio_dev, st->bounce_buffer, +sizeof (st->bounce_buffer), +iio_get_time_ns (indio_dev)); err_out:iio_trigger_notify_done (indio_dev->trig);return IRQ_HANDLED ;
Signature · 1 line
2.47.2
Quoted 9 lines · Marcelo Schmitt
Hello,
AD4170 support v7 comes after testing the driver with even more variations of channel setups. Signal offset and amplification can be tricky to grasp at times.
Thank you to all reviewers of previous versions. This intends to comply with all comments and suggestions to v6.
Same amount of patches than v6.
...
Quoted 1 line
6 files changed, 3601 insertions(+)
This is weird. At least patches 11 & 12 have '-' lines...
Signature · 2 lines
With Best Regards, Andy Shevchenko
Quoted 9 lines · Andy Shevchenko
Quoted 8 lines · Marcelo Schmitt
Hello,
AD4170 support v7 comes after testing the driver with even more variations of channel setups. Signal offset and amplification can be tricky to grasp at times.
Thank you to all reviewers of previous versions. This intends to comply with all comments and suggestions to v6.
Quoted 8 lines
Quoted 1 line
Same amount of patches than v6.
...
Quoted 1 line
6 files changed, 3601 insertions(+)This is weird. At least patches 11 & 12 have '-' lines...
Yeah, sorry about that. These ADCs are fancy such that the base driver is about 1500 LoCs due to channel setup handling and support for multiple combinations of voltage references and channel setups.
About the '-' lines, I will rework ad4170_parse_channel_node() on earlier patches to avoid 3 line removals in patch 11. Patch 12 is only makes sense after patch 7 and I think it would lead to '-' lines if coming before patch 10 since both increment the number of IIO channels. Anyway, I'll see how to further reduce the number of lines being removed.
Best regards,
Marcelo
Quoted 5 lines
Signature · 2 lines
With Best Regards, Andy Shevchenko
Quoted 2 lines · Marcelo Schmitt
Quoted 1 line · Andy Shevchenko
On Mon, Jun 30, 2025 at 10:57:32AM -0300, Marcelo Schmitt wrote:
...
Quoted 8 lines
Quoted 4 lines
Quoted 1 line
6 files changed, 3601 insertions(+)This is weird. At least patches 11 & 12 have '-' lines...
Yeah, sorry about that. These ADCs are fancy such that the base driver is about 1500 LoCs due to channel setup handling and support for multiple combinations of voltage references and channel setups.
Quoted 5 lines
About the '-' lines, I will rework
ad4170_parse_channel_node()on earlier patches to avoid 3 line removals in patch 11. Patch 12 is only makes sense after patch 7 and I think it would lead to '-' lines if coming before patch 10 since both increment the number of IIO channels. Anyway, I'll see how to further reduce the number of lines being removed.
My point is that the above statistics is mangled and I don't know how I can trust the contents of this series if it already lied about that.
Signature · 2 lines
With Best Regards, Andy Shevchenko
Quoted 14 lines · Andy Shevchenko
Quoted 2 lines · Marcelo Schmitt
Quoted 1 line · Andy Shevchenko
On Mon, Jun 30, 2025 at 10:57:32AM -0300, Marcelo Schmitt wrote:
...
Quoted 8 lines
Quoted 4 lines
Quoted 1 line
6 files changed, 3601 insertions(+)This is weird. At least patches 11 & 12 have '-' lines...
Yeah, sorry about that. These ADCs are fancy such that the base driver is about 1500 LoCs due to channel setup handling and support for multiple combinations of voltage references and channel setups.
Quoted 8 lines
Quoted 5 lines
About the '-' lines, I will rework
ad4170_parse_channel_node()on earlier patches to avoid 3 line removals in patch 11. Patch 12 is only makes sense after patch 7 and I think it would lead to '-' lines if coming before patch 10 since both increment the number of IIO channels. Anyway, I'll see how to further reduce the number of lines being removed.My point is that the above statistics is mangled and I don't know how I can trust the contents of this series if it already lied about that.
Looks like git format-patch summarizes the changes from all patches when printing the statistics to the cover letter. Also, git format-patch doc [1] says the 'changes' dirstat option (default behavior) doesn't count rearranged lines as much as other changes. There are cover letters of other patch sets where the number of '-' lines don't match the sum of lines removed by each patch. [2] and [3] are examples of that.
[1]: https://git-scm.com/docs/git-format-patch
[2]: https://lore.kernel.org/linux-iio/20250630-losd-3-inv-icm42600-add-wom-support-v6-0-5bb0c84800d9@tdk.com/
[3]: https://lore.kernel.org/linux-iio/20250627-iio-adc-ad7173-add-spi-offload-support-v2-0-f49c55599113@baylibre.com/
This set doesn't remove stuff that existed prior to it so I think it makes sense the cover letter to show that lines are only being added.
I'll send v8 with the change I mentioned earlier. Unless patches 11 and 12 already look good the way they are in v7.
Best regards,
Marcelo
Quoted 4 lines · Marcelo Schmitt
Quoted 3 lines · Andy Shevchenko
Quoted 2 lines · Marcelo Schmitt
Quoted 1 line · Andy Shevchenko
On Mon, Jun 30, 2025 at 10:57:32AM -0300, Marcelo Schmitt wrote:
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Quoted 14 lines
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Quoted 4 lines
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6 files changed, 3601 insertions(+)This is weird. At least patches 11 & 12 have '-' lines...
Yeah, sorry about that. These ADCs are fancy such that the base driver is about 1500 LoCs due to channel setup handling and support for multiple combinations of voltage references and channel setups.
About the '-' lines, I will rework
ad4170_parse_channel_node()on earlier patches to avoid 3 line removals in patch 11. Patch 12 is only makes sense after patch 7 and I think it would lead to '-' lines if coming before patch 10 since both increment the number of IIO channels. Anyway, I'll see how to further reduce the number of lines being removed.
Quoted 7 lines
Quoted 2 lines
My point is that the above statistics is mangled and I don't know how I can trust the contents of this series if it already lied about that.
Looks like git format-patch summarizes the changes from all patches when printing the statistics to the cover letter. Also, git format-patch doc [1] says the 'changes' dirstat option (default behavior) doesn't count rearranged lines as much as other changes.
TIL. Thanks for pointing that out.
Quoted 3 lines
There are cover letters of other
patch sets where the number of '-' lines don't match the sum of lines removed by each patch. [2] and [3] are examples of that.
That's different I believe due to the diff algorithm in use (btw, do you use histogramm?).
Quoted 9 lines
[1]: https://git-scm.com/docs/git-format-patch
[2]: https://lore.kernel.org/linux-iio/20250630-losd-3-inv-icm42600-add-wom-support-v6-0-5bb0c84800d9@tdk.com/
[3]: https://lore.kernel.org/linux-iio/20250627-iio-adc-ad7173-add-spi-offload-support-v2-0-f49c55599113@baylibre.com/This set doesn't remove stuff that existed prior to it so I think it makes sense the cover letter to show that lines are only being added.
I'll send v8 with the change I mentioned earlier. Unless patches 11 and 12 already look good the way they are in v7.
Signature · 2 lines
With Best Regards, Andy Shevchenko
Quoted 30 lines · Andy Shevchenko
Quoted 4 lines · Marcelo Schmitt
Quoted 3 lines · Andy Shevchenko
Quoted 2 lines · Marcelo Schmitt
Quoted 1 line · Andy Shevchenko
On Mon, Jun 30, 2025 at 10:57:32AM -0300, Marcelo Schmitt wrote:
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Quoted 1 line
6 files changed, 3601 insertions(+)This is weird. At least patches 11 & 12 have '-' lines...
Yeah, sorry about that. These ADCs are fancy such that the base driver is about 1500 LoCs due to channel setup handling and support for multiple combinations of voltage references and channel setups.
About the '-' lines, I will rework
ad4170_parse_channel_node()on earlier patches to avoid 3 line removals in patch 11. Patch 12 is only makes sense after patch 7 and I think it would lead to '-' lines if coming before patch 10 since both increment the number of IIO channels. Anyway, I'll see how to further reduce the number of lines being removed.Quoted 7 lines
Quoted 2 lines
My point is that the above statistics is mangled and I don't know how I can trust the contents of this series if it already lied about that.
Looks like git format-patch summarizes the changes from all patches when printing the statistics to the cover letter. Also, git format-patch doc [1] says the 'changes' dirstat option (default behavior) doesn't count rearranged lines as much as other changes.
Quoted 8 lines
TIL. Thanks for pointing that out.
Quoted 3 lines
There are cover letters of other
patch sets where the number of '-' lines don't match the sum of lines removed by each patch. [2] and [3] are examples of that.That's different I believe due to the diff algorithm in use (btw, do you use histogramm?).
Nope, I was using the default diff algorithm to generate the patches. I tried the --histogram option today but didn't notice any difference. Maybe default and histogram output the same result for the ad4170 set. I'll send v8 using histogram alg. Nevertheless, is there any preferred alg for generating patches (so I can use what's best on next patch sets)?
Thanks,
Marcelo
Jonathan Cameron
maintainerQuoted 37 lines · On Thu, 3 Jul 2025 17:24:07 -0300 Marcelo Schmitt <[email protected]>…
Quoted 36 lines · Andy Shevchenko
Quoted 4 lines · Marcelo Schmitt
Quoted 3 lines · Andy Shevchenko
Quoted 2 lines · Marcelo Schmitt
Quoted 1 line · Andy Shevchenko
On Mon, Jun 30, 2025 at 10:57:32AM -0300, Marcelo Schmitt wrote:
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6 files changed, 3601 insertions(+)This is weird. At least patches 11 & 12 have '-' lines...
Yeah, sorry about that. These ADCs are fancy such that the base driver is about 1500 LoCs due to channel setup handling and support for multiple combinations of voltage references and channel setups.
About the '-' lines, I will rework
ad4170_parse_channel_node()on earlier patches to avoid 3 line removals in patch 11. Patch 12 is only makes sense after patch 7 and I think it would lead to '-' lines if coming before patch 10 since both increment the number of IIO channels. Anyway, I'll see how to further reduce the number of lines being removed.Quoted 7 lines
Quoted 2 lines
My point is that the above statistics is mangled and I don't know how I can trust the contents of this series if it already lied about that.
Looks like git format-patch summarizes the changes from all patches when printing the statistics to the cover letter. Also, git format-patch doc [1] says the 'changes' dirstat option (default behavior) doesn't count rearranged lines as much as other changes.
TIL. Thanks for pointing that out.
Quoted 3 lines
There are cover letters of other
patch sets where the number of '-' lines don't match the sum of lines removed by each patch. [2] and [3] are examples of that.
Quoted 8 lines
Quoted 2 lines
That's different I believe due to the diff algorithm in use (btw, do you use histogramm?).
Nope, I was using the default diff algorithm to generate the patches. I tried the --histogram option today but didn't notice any difference. Maybe default and histogram output the same result for the ad4170 set. I'll send v8 using histogram alg. Nevertheless, is there any preferred alg for generating patches (so I can use what's best on next patch sets)?
Given the size and complexity of this driver, I've applied it to the testing branch of iio.git to get some extra build coverage. Last minute reviews still welcome but I may ask for patches on top depending on what they affect.
Hence applied to the togreg branch of iio.git and pushed out as testing for 0-day to take a poke at them.
Thanks,
Jonathan
Quoted 4 lines
Thanks,
Marcelo