riscv: dts: thead: add more th1520 isa extension support

PATCH Applied Han Gao 2 participants 12 messages Sep 18, 2025 – Oct 18, 2025

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Device tree bindings RISC-V RISC-V T-Head SoC support

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Han Gao

author

2025-09-18 20:45 UTC #0 lore raw

v2 cover riscv: dts: thead: add more th1520 isa extension support

Add xtheadvector & ziccrse & zfh for th1520

Updated the commit message for the patchset

Thanks,
Han

---
v1: https://lore.kernel.org/all/[email protected]/

Han Gao (3):
riscv: dts: thead: add xtheadvector to the th1520 devicetree
riscv: dts: thead: add ziccrse for th1520
riscv: dts: thead: add zfh for th1520

 arch/riscv/boot/dts/thead/th1520.dtsi | 28 +++++++++++++++++++--------
 1 file changed, 20 insertions(+), 8 deletions(-)

Signature · 1 line

2.47.3

Han Gao

author

2025-09-18 20:45 UTC #1 lore raw

PATCH v2 1/3 riscv: dts: thead: add xtheadvector to the th1520 devicetree

The th1520 support xtheadvector [1] so it can be included in the devicetree. Also include vlenb for the cpu. And set vlenb=16 [2].

This can be tested by passing the "mitigations=off" kernel parameter.

Link https://lore.kernel.org/linux-riscv/[email protected]/ [1] open here

Link https://lore.kernel.org/linux-riscv/aCO44SAoS2kIP61r@ghost/ [2] open here

Signed-off-by Han Gao <[email protected]>

---
 arch/riscv/boot/dts/thead/th1520.dtsi | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

arch/riscv/boot/dts/thead/th1520.dtsi +8 -4

index 42724bf7e90e..59d1927764a6 100644
@@ -25,7 +25,8 @@ c910_0: cpu@0 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
-					       "zifencei", "zihpm";
+					       "zifencei", "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <0>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -49,7 +50,8 @@ c910_1: cpu@1 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
-					       "zifencei", "zihpm";
+					       "zifencei", "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <1>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -73,7 +75,8 @@ c910_2: cpu@2 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
-					       "zifencei", "zihpm";
+					       "zifencei", "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <2>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

@@ -97,7 +100,8 @@ c910_3: cpu@3 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
-					       "zifencei", "zihpm";
+					       "zifencei", "zihpm", "xtheadvector";
+			thead,vlenb = <16>;
 			reg = <3>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;

Signature · 1 line

2.47.3

Drew Fustini

maintainer Reviewed-by on v2 1/3

2025-09-20 23:12 UTC #2 lore raw

Re: [PATCH v2 1/3] riscv: dts: thead: add xtheadvector to the th1520 devicetree

Quoted 9 lines · Han Gao

The th1520 support xtheadvector [1] so it can be included in the devicetree. Also include vlenb for the cpu. And set vlenb=16 [2].
This can be tested by passing the "mitigations=off" kernel parameter.
Link https://lore.kernel.org/linux-riscv/[email protected]/ [1] open here
Link https://lore.kernel.org/linux-riscv/aCO44SAoS2kIP61r@ghost/ [2] open here
Signed-off-by Han Gao <[email protected]>

Reviewed-by Drew Fustini <[email protected]>

Thanks,
Drew

Drew Fustini

maintainer Reviewed-by on v2 1/3

2025-10-03 01:35 UTC #3 lore raw

Re: [PATCH v2 1/3] riscv: dts: thead: add xtheadvector to the th1520 devicetree

In reply to Han Gao

Quoted 9 lines · Han Gao

The th1520 support xtheadvector [1] so it can be included in the devicetree. Also include vlenb for the cpu. And set vlenb=16 [2].
This can be tested by passing the "mitigations=off" kernel parameter.
Link https://lore.kernel.org/linux-riscv/[email protected]/ [1] open here
Link https://lore.kernel.org/linux-riscv/aCO44SAoS2kIP61r@ghost/ [2] open here
Signed-off-by Han Gao <[email protected]>

Reviewed-by Drew Fustini <[email protected]>

Han Gao

author

2025-09-18 20:45 UTC #4 lore raw

PATCH v2 2/3 riscv: dts: thead: add ziccrse for th1520

In reply to Han Gao

Existing rv64 hardware conforms to the rva20 profile.

Ziccrse is an additional extension required by the rva20 profile, so th1520 has this extension.

Signed-off-by Han Gao <[email protected]>

---
 arch/riscv/boot/dts/thead/th1520.dtsi | 24 ++++++++++++++++--------
 1 file changed, 16 insertions(+), 8 deletions(-)

arch/riscv/boot/dts/thead/th1520.dtsi +16 -8

index 59d1927764a6..7f07688aa964 100644
@@ -24,8 +24,10 @@ c910_0: cpu@0 {
 			device_type = "cpu";
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
-			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
-					       "zifencei", "zihpm", "xtheadvector";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <0>;
 			i-cache-block-size = <64>;

@@ -49,8 +51,10 @@ c910_1: cpu@1 {
 			device_type = "cpu";
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
-			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
-					       "zifencei", "zihpm", "xtheadvector";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <1>;
 			i-cache-block-size = <64>;

@@ -74,8 +78,10 @@ c910_2: cpu@2 {
 			device_type = "cpu";
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
-			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
-					       "zifencei", "zihpm", "xtheadvector";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <2>;
 			i-cache-block-size = <64>;

@@ -99,8 +105,10 @@ c910_3: cpu@3 {
 			device_type = "cpu";
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
-			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
-					       "zifencei", "zihpm", "xtheadvector";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
+					       "ziccrse", "zicntr", "zicsr",
+					       "zifencei", "zihpm",
+					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <3>;
 			i-cache-block-size = <64>;

Signature · 1 line

2.47.3

Drew Fustini

maintainer Reviewed-by on v2 2/3

2025-09-20 23:12 UTC #5 lore raw

Re: [PATCH v2 2/3] riscv: dts: thead: add ziccrse for th1520

Quoted 6 lines · Han Gao

Existing rv64 hardware conforms to the rva20 profile.
Ziccrse is an additional extension required by the rva20 profile, so th1520 has this extension.
Signed-off-by Han Gao <[email protected]>

Reviewed-by Drew Fustini <[email protected]>

Thanks,
Drew

Drew Fustini

maintainer Reviewed-by on v2 2/3

2025-10-03 01:35 UTC #6 lore raw

Re: [PATCH v2 2/3] riscv: dts: thead: add ziccrse for th1520

In reply to Han Gao

Quoted 6 lines · Han Gao

Existing rv64 hardware conforms to the rva20 profile.
Ziccrse is an additional extension required by the rva20 profile, so th1520 has this extension.
Signed-off-by Han Gao <[email protected]>

Reviewed-by Drew Fustini <[email protected]>

Han Gao

author

2025-09-18 20:45 UTC #7 lore raw

PATCH v2 3/3 riscv: dts: thead: add zfh for th1520

In reply to Han Gao

th1520 support Zfh ISA extension.
It supports the same RISC-V extensions as SG2042.

commit cb074bed1186 ("riscv: dts: sophgo: add zfh for sg2042")

Signed-off-by Han Gao <[email protected]>

---
 arch/riscv/boot/dts/thead/th1520.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

arch/riscv/boot/dts/thead/th1520.dtsi +4 -4

index 7f07688aa964..2075bb969c2f 100644
@@ -26,7 +26,7 @@ c910_0: cpu@0 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <0>;

@@ -53,7 +53,7 @@ c910_1: cpu@1 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <1>;

@@ -80,7 +80,7 @@ c910_2: cpu@2 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <2>;

@@ -107,7 +107,7 @@ c910_3: cpu@3 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "ziccrse", "zicntr", "zicsr",
-					       "zifencei", "zihpm",
+					       "zifencei", "zihpm", "zfh",
 					       "xtheadvector";
 			thead,vlenb = <16>;
 			reg = <3>;

Signature · 1 line

2.47.3

Drew Fustini

maintainer Reviewed-by on v2 3/3

2025-09-20 23:40 UTC #8 lore raw

Re: [PATCH v2 3/3] riscv: dts: thead: add zfh for th1520

Quoted 6 lines · Han Gao

th1520 support Zfh ISA extension.
It supports the same RISC-V extensions as SG2042.
commit cb074bed1186 ("riscv: dts: sophgo: add zfh for sg2042")
Signed-off-by Han Gao <[email protected]>

Reviewed-by Drew Fustini <[email protected]>

Thanks,
Drew

Drew Fustini

maintainer Reviewed-by on v2 3/3

2025-10-03 01:36 UTC #9 lore raw

Re: [PATCH v2 3/3] riscv: dts: thead: add zfh for th1520

In reply to Han Gao

Quoted 6 lines · Han Gao

th1520 support Zfh ISA extension.
It supports the same RISC-V extensions as SG2042.
commit cb074bed1186 ("riscv: dts: sophgo: add zfh for sg2042")
Signed-off-by Han Gao <[email protected]>

Reviewed-by Drew Fustini <[email protected]>

Drew Fustini

maintainer

2025-10-03 21:13 UTC #10 lore raw

In reply to Han Gao

Quoted 10 lines · Han Gao

Add xtheadvector & ziccrse & zfh for th1520
Updated the commit message for the patchset
Thanks,
Han
---
v1: https://lore.kernel.org/all/[email protected]/

Quoted 11 lines

Han Gao (3):
riscv: dts: thead: add xtheadvector to the th1520 devicetree
riscv: dts: thead: add ziccrse for th1520
riscv: dts: thead: add zfh for th1520
 arch/riscv/boot/dts/thead/th1520.dtsi | 28 +++++++++++++++++++--------
 1 file changed, 20 insertions(+), 8 deletions(-)
Signature · 1 line
2.47.3

I'll apply this to thead-dt-for-next once 6.18-rc1 is out and I can update the next branch to that.

Thanks,
Drew

Drew Fustini

maintainer Applied

2025-10-18 04:26 UTC #11 lore raw

In reply to Han Gao

Quoted 10 lines · Han Gao

Add xtheadvector & ziccrse & zfh for th1520
Updated the commit message for the patchset
Thanks,
Han
---
v1: https://lore.kernel.org/all/[email protected]/

Quoted 11 lines

Han Gao (3):
riscv: dts: thead: add xtheadvector to the th1520 devicetree
riscv: dts: thead: add ziccrse for th1520
riscv: dts: thead: add zfh for th1520
 arch/riscv/boot/dts/thead/th1520.dtsi | 28 +++++++++++++++++++--------
 1 file changed, 20 insertions(+), 8 deletions(-)
Signature · 1 line
2.47.3

Applied to thead-dt-for-next, thanks!

[1/3] riscv: dts: thead: add xtheadvector to the th1520 devicetree

      commit aef6dc006696c20ccc58c4c0235a14e7b4b317a0
[2/3] riscv: dts: thead: add ziccrse for th1520
      commit bcc3b9c5de5e2a03ede1a8133c05255927d744d6
[3/3] riscv: dts: thead: add zfh for th1520
      commit fac4be7b3d49ae7e32d8ae523343d7fe790772f9

-Drew