media: imx-mipi-csis: Cleanups and debugging improvements

The CSIS driver uses register macro names that do not match the reference manual of the i.MX7[DS] and i.MX8M[MNP] SoCs in which the CSIS is integrated. Rename them to match the documentation, making the code easier to read alongside the reference manuals.

One of the misnamed register fields is MIPI_CSIS_INT_SRC_ERR_UNKNOWN, which led to the corresponding event being logged as "Unknown Error". The correct register field name is MIPI_CSIS_INT_SRC_ERR_ID, documented as "Unknown ID error". Update the event description accordingly.

While at it, also replace a few *_OFFSET macros with parametric macros for consistency, and add the missing MIPI_CSIS_ISP_RESOL_VRESOL and MIPI_CSIS_ISP_RESOL_HRESOL register field macros.

No functional change intended.

Signed-off-by Laurent Pinchart <[email protected]>

---
Changes since v2:

- Drop MIPI_CSIS_CMN_CTRL_INTERLEAVE_MODE_NONE
- Restore usage of BIT() for MIPI_CSIS_CMN_CTRL_INTERLEAVE_MODE_DT

---
 drivers/media/platform/nxp/imx-mipi-csis.c | 68 +++++++++++-----------
 1 file changed, 35 insertions(+), 33 deletions(-)

drivers/media/platform/nxp/imx-mipi-csis.c +35 -34

index 894d12fef519..ce889c436cb1 100644
@@ -55,13 +55,12 @@
 /* CSIS common control */
 #define MIPI_CSIS_CMN_CTRL			0x04
 #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW	BIT(16)
-#define MIPI_CSIS_CMN_CTRL_INTER_MODE		BIT(10)
+#define MIPI_CSIS_CMN_CTRL_INTERLEAVE_MODE_DT	BIT(10)
+#define MIPI_CSIS_CMN_CTRL_LANE_NUMBER(n)	((n) << 8)
+#define MIPI_CSIS_CMN_CTRL_LANE_NUMBER_MASK	(3 << 8)
 #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL	BIT(2)
-#define MIPI_CSIS_CMN_CTRL_RESET		BIT(1)
-#define MIPI_CSIS_CMN_CTRL_ENABLE		BIT(0)
-
-#define MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET	8
-#define MIPI_CSIS_CMN_CTRL_LANE_NR_MASK		(3 << 8)
+#define MIPI_CSIS_CMN_CTRL_SW_RESET		BIT(1)
+#define MIPI_CSIS_CMN_CTRL_CSI_EN		BIT(0)
 
 /* CSIS clock control */
 #define MIPI_CSIS_CLK_CTRL			0x08

@@ -87,7 +86,7 @@
 #define MIPI_CSIS_INT_MSK_ERR_WRONG_CFG		BIT(3)
 #define MIPI_CSIS_INT_MSK_ERR_ECC		BIT(2)
 #define MIPI_CSIS_INT_MSK_ERR_CRC		BIT(1)
-#define MIPI_CSIS_INT_MSK_ERR_UNKNOWN		BIT(0)
+#define MIPI_CSIS_INT_MSK_ERR_ID		BIT(0)
 
 /* CSIS Interrupt source */
 #define MIPI_CSIS_INT_SRC			0x14

@@ -107,7 +106,7 @@
 #define MIPI_CSIS_INT_SRC_ERR_WRONG_CFG		BIT(3)
 #define MIPI_CSIS_INT_SRC_ERR_ECC		BIT(2)
 #define MIPI_CSIS_INT_SRC_ERR_CRC		BIT(1)
-#define MIPI_CSIS_INT_SRC_ERR_UNKNOWN		BIT(0)
+#define MIPI_CSIS_INT_SRC_ERR_ID		BIT(0)
 #define MIPI_CSIS_INT_SRC_ERRORS		0xfffff
 
 /* D-PHY status control */

@@ -123,8 +122,8 @@
 #define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE_MASK	GENMASK(31, 24)
 #define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(n)	((n) << 22)
 #define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE_MASK	GENMASK(23, 22)
-#define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_CLK	BIT(6)
-#define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_DAT	BIT(5)
+#define MIPI_CSIS_DPHY_CMN_CTRL_S_DPDN_SWAP_CLK	BIT(6)
+#define MIPI_CSIS_DPHY_CMN_CTRL_S_DPDN_SWAP_DAT	BIT(5)
 #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_DAT	BIT(1)
 #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_CLK	BIT(0)
 #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE		(0x1f << 0)

@@ -179,21 +178,23 @@
 #define MIPI_CSIS_ISPCFG_PIXEL_MODE_SINGLE	(0 << 12)
 #define MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL	(1 << 12)
 #define MIPI_CSIS_ISPCFG_PIXEL_MODE_QUAD	(2 << 12)	/* i.MX8M[MNP] only */
-#define MIPI_CSIS_ISPCFG_PIXEL_MASK		(3 << 12)
-#define MIPI_CSIS_ISPCFG_ALIGN_32BIT		BIT(11)
-#define MIPI_CSIS_ISPCFG_FMT(fmt)		((fmt) << 2)
-#define MIPI_CSIS_ISPCFG_FMT_MASK		(0x3f << 2)
+#define MIPI_CSIS_ISPCFG_PIXEL_MODE_MASK	(3 << 12)
+#define MIPI_CSIS_ISPCFG_PARALLEL		BIT(11)
+#define MIPI_CSIS_ISPCFG_DATAFORMAT(fmt)	((fmt) << 2)
+#define MIPI_CSIS_ISPCFG_DATAFORMAT_MASK	(0x3f << 2)
 
 /* ISP Image Resolution register */
 #define MIPI_CSIS_ISP_RESOL_CH(n)		(0x44 + (n) * 0x10)
+#define MIPI_CSIS_ISP_RESOL_VRESOL(n)		((n) << 16)
+#define MIPI_CSIS_ISP_RESOL_HRESOL(n)		((n) << 0)
 #define CSIS_MAX_PIX_WIDTH			0xffff
 #define CSIS_MAX_PIX_HEIGHT			0xffff
 
 /* ISP SYNC register */
 #define MIPI_CSIS_ISP_SYNC_CH(n)		(0x48 + (n) * 0x10)
-#define MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET	18
-#define MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET	12
-#define MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET	0
+#define MIPI_CSIS_ISP_SYNC_HSYNC_LINTV(n)	((n) << 18)
+#define MIPI_CSIS_ISP_SYNC_VSYNC_SINTV(n)	((n) << 12)
+#define MIPI_CSIS_ISP_SYNC_VSYNC_EINTV(n)	((n) << 0)
 
 /* ISP shadow registers */
 #define MIPI_CSIS_SDW_CONFIG_CH(n)		(0x80 + (n) * 0x10)

@@ -246,7 +247,7 @@ static const struct mipi_csis_event mipi_csis_events[] = {
 	{ false, MIPI_CSIS_INT_SRC_ERR_WRONG_CFG,	"Wrong Configuration Error" },
 	{ false, MIPI_CSIS_INT_SRC_ERR_ECC,		"ECC Error" },
 	{ false, MIPI_CSIS_INT_SRC_ERR_CRC,		"CRC Error" },
-	{ false, MIPI_CSIS_INT_SRC_ERR_UNKNOWN,		"Unknown Error" },
+	{ false, MIPI_CSIS_INT_SRC_ERR_ID,		"Unknown ID Error" },
 	{ true, MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT,	"Data Type Not Supported" },
 	{ true, MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE,	"Data Type Ignored" },
 	{ true, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE,	"Frame Size Error" },

@@ -517,7 +518,7 @@ static void mipi_csis_sw_reset(struct mipi_csis_device *csis)
 	u32 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
 
 	mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL,
-			val | MIPI_CSIS_CMN_CTRL_RESET);
+			val | MIPI_CSIS_CMN_CTRL_SW_RESET);
 	usleep_range(10, 20);
 }
 

@@ -527,9 +528,9 @@ static void mipi_csis_system_enable(struct mipi_csis_device *csis, int on)
 
 	val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
 	if (on)
-		val |= MIPI_CSIS_CMN_CTRL_ENABLE;
+		val |= MIPI_CSIS_CMN_CTRL_CSI_EN;
 	else
-		val &= ~MIPI_CSIS_CMN_CTRL_ENABLE;
+		val &= ~MIPI_CSIS_CMN_CTRL_CSI_EN;
 	mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, val);
 
 	val = mipi_csis_read(csis, MIPI_CSIS_DPHY_CMN_CTRL);

@@ -549,8 +550,8 @@ static void __mipi_csis_set_format(struct mipi_csis_device *csis,
 
 	/* Color format */
 	val = mipi_csis_read(csis, MIPI_CSIS_ISP_CONFIG_CH(0));
-	val &= ~(MIPI_CSIS_ISPCFG_ALIGN_32BIT | MIPI_CSIS_ISPCFG_FMT_MASK
-		| MIPI_CSIS_ISPCFG_PIXEL_MASK);
+	val &= ~(MIPI_CSIS_ISPCFG_PARALLEL | MIPI_CSIS_ISPCFG_PIXEL_MODE_MASK |
+		 MIPI_CSIS_ISPCFG_DATAFORMAT_MASK);
 
 	/*
 	 * YUV 4:2:2 can be transferred with 8 or 16 bits per clock sample

@@ -568,12 +569,13 @@ static void __mipi_csis_set_format(struct mipi_csis_device *csis,
 	if (csis_fmt->data_type == MIPI_CSI2_DT_YUV422_8B)
 		val |= MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL;
 
-	val |= MIPI_CSIS_ISPCFG_FMT(csis_fmt->data_type);
+	val |= MIPI_CSIS_ISPCFG_DATAFORMAT(csis_fmt->data_type);
 	mipi_csis_write(csis, MIPI_CSIS_ISP_CONFIG_CH(0), val);
 
 	/* Pixel resolution */
-	val = format->width | (format->height << 16);
-	mipi_csis_write(csis, MIPI_CSIS_ISP_RESOL_CH(0), val);
+	mipi_csis_write(csis, MIPI_CSIS_ISP_RESOL_CH(0),
+			MIPI_CSIS_ISP_RESOL_VRESOL(format->height) |
+			MIPI_CSIS_ISP_RESOL_HRESOL(format->width));
 }
 
 static int mipi_csis_calculate_params(struct mipi_csis_device *csis,

@@ -633,10 +635,10 @@ static void mipi_csis_set_params(struct mipi_csis_device *csis,
 	u32 val;
 
 	val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
-	val &= ~MIPI_CSIS_CMN_CTRL_LANE_NR_MASK;
-	val |= (lanes - 1) << MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET;
+	val &= ~MIPI_CSIS_CMN_CTRL_LANE_NUMBER_MASK;
+	val |= MIPI_CSIS_CMN_CTRL_LANE_NUMBER(lanes - 1);
 	if (csis->info->version == MIPI_CSIS_V3_3)
-		val |= MIPI_CSIS_CMN_CTRL_INTER_MODE;
+		val |= MIPI_CSIS_CMN_CTRL_INTERLEAVE_MODE_DT;
 	mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, val);
 
 	__mipi_csis_set_format(csis, format, csis_fmt);

@@ -645,10 +647,10 @@ static void mipi_csis_set_params(struct mipi_csis_device *csis,
 			MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(csis->hs_settle) |
 			MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(csis->clk_settle));
 
-	val = (0 << MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET)
-	    | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET)
-	    | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET);
-	mipi_csis_write(csis, MIPI_CSIS_ISP_SYNC_CH(0), val);
+	mipi_csis_write(csis, MIPI_CSIS_ISP_SYNC_CH(0),
+			MIPI_CSIS_ISP_SYNC_HSYNC_LINTV(0) |
+			MIPI_CSIS_ISP_SYNC_VSYNC_SINTV(0) |
+			MIPI_CSIS_ISP_SYNC_VSYNC_EINTV(0));
 
 	val = mipi_csis_read(csis, MIPI_CSIS_CLK_CTRL);
 	val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC;
--

Regards,

Laurent Pinchart

Multiple register field mask macros use GENMASK, while other define the mask value manually. Standardize on GENMASK everywhere, as well as on the _MASK suffix to name the macros. This improves consistency and helps with readability.

No functional change is intended.

Signed-off-by Laurent Pinchart <[email protected]>

---
 drivers/media/platform/nxp/imx-mipi-csis.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

drivers/media/platform/nxp/imx-mipi-csis.c +0 -0

index ce889c436cb1..50f6f4468f7b 100644
@@ -57,7 +57,7 @@

drivers/media/platform/nxp/imx-mipi-csis.c +0 -1

 	mipi_csis_write(csis, MIPI_CSIS_CLK_CTRL, val);
 
 	mipi_csis_write(csis, MIPI_CSIS_DPHY_BCTRL_L,
--

Regards,

Laurent Pinchart

Quoted 17 lines · Laurent Pinchart

Multiple register field mask macros use GENMASK, while other define the mask value manually. Standardize on GENMASK everywhere, as well as on the _MASK suffix to name the macros. This improves consistency and helps with readability.

No functional change is intended.

Signed-off-by Laurent Pinchart <[email protected]>

---
 drivers/media/platform/nxp/imx-mipi-csis.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

drivers/media/platform/nxp/imx-mipi-csis.c +0 -0

index ce889c436cb1..50f6f4468f7b 100644
@@ -57,7 +57,7 @@

...

Quoted 1 line

drivers/media/platform/nxp/imx-mipi-csis.c static void mipi_csis_set_params(struct mipi_csis_device *csis, · line 658

Quoted 8 lines

/* ISP Image Resolution register */
#define MIPI_CSIS_ISP_RESOL_CH(n) (0x44 + (n) * 0x10)

drivers/media/platform/nxp/imx-mipi-csis.c +1 -1

@@ -655,7 +655,7 @@ static void mipi_csis_set_params(struct mipi_csis_device *csis,
 	val = mipi_csis_read(csis, MIPI_CSIS_CLK_CTRL);
 	val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC;
 	val |= MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(15);
-	val &= ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK;
+	val &= ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MASK;

nit: if need create new verison, I suggest add "change MSK to MASK" informaiton at commit message.

Reviewed-by Frank Li <[email protected]>

Quoted 3 lines

drivers/media/platform/nxp/imx-mipi-csis.c +0 -0

 	mipi_csis_write(csis, MIPI_CSIS_CLK_CTRL, val);
 
 	mipi_csis_write(csis, MIPI_CSIS_DPHY_BCTRL_L,

Hi Frank,

Quoted 21 lines · Frank Li

Quoted 17 lines · Laurent Pinchart

Multiple register field mask macros use GENMASK, while other define the mask value manually. Standardize on GENMASK everywhere, as well as on the _MASK suffix to name the macros. This improves consistency and helps with readability.

No functional change is intended.

Signed-off-by Laurent Pinchart <[email protected]>

---
 drivers/media/platform/nxp/imx-mipi-csis.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

drivers/media/platform/nxp/imx-mipi-csis.c +0 -0

index ce889c436cb1..50f6f4468f7b 100644
@@ -57,7 +57,7 @@

...

Quoted 1 line

Quoted 11 lines

drivers/media/platform/nxp/imx-mipi-csis.c static void mipi_csis_set_params(struct mipi_csis_device *csis, · line 658

Quoted 8 lines

/* ISP Image Resolution register */
#define MIPI_CSIS_ISP_RESOL_CH(n) (0x44 + (n) * 0x10)

drivers/media/platform/nxp/imx-mipi-csis.c +1 -1

@@ -655,7 +655,7 @@ static void mipi_csis_set_params(struct mipi_csis_device *csis,
 	val = mipi_csis_read(csis, MIPI_CSIS_CLK_CTRL);
 	val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC;
 	val |= MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(15);
-	val &= ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK;
+	val &= ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MASK;

nit: if need create new verison, I suggest add "change MSK to MASK" informaiton at commit message.

The information is there already, the commit message already states "Standardize [...] on the _MASK suffix to name the macros".

Quoted 6 lines

Reviewed-by Frank Li <[email protected]>

Quoted 3 lines

drivers/media/platform/nxp/imx-mipi-csis.c +0 -0

 	mipi_csis_write(csis, MIPI_CSIS_CLK_CTRL, val);
 
 	mipi_csis_write(csis, MIPI_CSIS_DPHY_BCTRL_L,

--
Regards,

Laurent Pinchart

Some CSIS instances feature more than one output channel. Update register macros accordingly, parse the number of channels from the device tree, and update register dumps and event counters to log per-channel data.

Support for routing virtual channels and data types to output channels through the subdev internal routing API will come later.

Signed-off-by Laurent Pinchart <[email protected]>

---
Changes since v1:

- Update more per-channel registers
- Update commit message

---
 drivers/media/platform/nxp/imx-mipi-csis.c | 239 +++++++++++++--------
 1 file changed, 152 insertions(+), 87 deletions(-)

drivers/media/platform/nxp/imx-mipi-csis.c +80 -52

index e1588990beda..ee8e541dcb1d 100644
@@ -54,7 +54,7 @@
 
 /* CSIS common control */
 #define MIPI_CSIS_CMN_CTRL                     0x04
-#define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW       BIT(16)
+#define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW(n)    BIT((n) + 16)
 #define MIPI_CSIS_CMN_CTRL_INTERLEAVE_MODE_DT  BIT(10)
 #define MIPI_CSIS_CMN_CTRL_LANE_NUMBER(n)      ((n) << 8)
 #define MIPI_CSIS_CMN_CTRL_LANE_NUMBER_MASK    GENMASK(9, 8)

@@ -64,12 +64,9 @@
 
 /* CSIS clock control */
 #define MIPI_CSIS_CLK_CTRL                     0x08
-#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH3(x)        ((x) << 28)
-#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH2(x)        ((x) << 24)
-#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH1(x)        ((x) << 20)
-#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(x)        ((x) << 16)
+#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL(n, x) ((x) << ((n) * 4 + 16))
 #define MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MASK     GENMASK(7, 4)
-#define MIPI_CSIS_CLK_CTRL_WCLK_SRC            BIT(0)
+#define MIPI_CSIS_CLK_CTRL_WCLK_SRC(n)         BIT(n)
 
 /* CSIS Interrupt mask */
 #define MIPI_CSIS_INT_MSK                      0x10

@@ -97,12 +94,12 @@
 #define MIPI_CSIS_INT_SRC_ODD_AFTER            BIT(28)
 #define MIPI_CSIS_INT_SRC_ODD                  (0x3 << 28)
 #define MIPI_CSIS_INT_SRC_NON_IMAGE_DATA       (0xf << 28)
-#define MIPI_CSIS_INT_SRC_FRAME_START          BIT(24)
-#define MIPI_CSIS_INT_SRC_FRAME_END            BIT(20)
+#define MIPI_CSIS_INT_SRC_FRAME_START(n)       BIT((n) + 24)
+#define MIPI_CSIS_INT_SRC_FRAME_END(n)         BIT((n) + 20)
 #define MIPI_CSIS_INT_SRC_ERR_SOT_HS(n)                BIT((n) + 16)
-#define MIPI_CSIS_INT_SRC_ERR_LOST_FS          BIT(12)
-#define MIPI_CSIS_INT_SRC_ERR_LOST_FE          BIT(8)
-#define MIPI_CSIS_INT_SRC_ERR_OVER             BIT(4)
+#define MIPI_CSIS_INT_SRC_ERR_LOST_FS(n)       BIT((n) + 12)
+#define MIPI_CSIS_INT_SRC_ERR_LOST_FE(n)       BIT((n) + 8)
+#define MIPI_CSIS_INT_SRC_ERR_OVER(n)          BIT((n) + 4)
 #define MIPI_CSIS_INT_SRC_ERR_WRONG_CFG                BIT(3)
 #define MIPI_CSIS_INT_SRC_ERR_ECC              BIT(2)
 #define MIPI_CSIS_INT_SRC_ERR_CRC              BIT(1)

@@ -204,23 +201,23 @@
 /* Debug control register */
 #define MIPI_CSIS_DBG_CTRL                     0xc0
 #define MIPI_CSIS_DBG_INTR_MSK                 0xc4
-#define MIPI_CSIS_DBG_INTR_MSK_DT_NOT_SUPPORT  BIT(25)
-#define MIPI_CSIS_DBG_INTR_MSK_DT_IGNORE       BIT(24)
-#define MIPI_CSIS_DBG_INTR_MSK_ERR_FRAME_SIZE  BIT(20)
-#define MIPI_CSIS_DBG_INTR_MSK_TRUNCATED_FRAME BIT(16)
-#define MIPI_CSIS_DBG_INTR_MSK_EARLY_FE                BIT(12)
-#define MIPI_CSIS_DBG_INTR_MSK_EARLY_FS                BIT(8)
-#define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_FALL  BIT(4)
-#define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_RISE  BIT(0)
+#define MIPI_CSIS_DBG_INTR_MSK_DT_NOT_SUPPORT          BIT(25)
+#define MIPI_CSIS_DBG_INTR_MSK_DT_IGNORE               BIT(24)
+#define MIPI_CSIS_DBG_INTR_MSK_ERR_FRAME_SIZE(n)       BIT((n) + 20)
+#define MIPI_CSIS_DBG_INTR_MSK_TRUNCATED_FRAME(n)      BIT((n) + 16)
+#define MIPI_CSIS_DBG_INTR_MSK_EARLY_FE(n)             BIT((n) + 12)
+#define MIPI_CSIS_DBG_INTR_MSK_EARLY_FS(n)             BIT((n) + 8)
+#define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_FALL(n)       BIT((n) + 4)
+#define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_RISE(n)       BIT((n) + 0)
 #define MIPI_CSIS_DBG_INTR_SRC                 0xc8
-#define MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT  BIT(25)
-#define MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE       BIT(24)
-#define MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE  BIT(20)
-#define MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME BIT(16)
-#define MIPI_CSIS_DBG_INTR_SRC_EARLY_FE                BIT(12)
-#define MIPI_CSIS_DBG_INTR_SRC_EARLY_FS                BIT(8)
-#define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL  BIT(4)
-#define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE  BIT(0)
+#define MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT          BIT(25)
+#define MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE               BIT(24)
+#define MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE(n)       BIT((n) + 20)
+#define MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME(n)      BIT((n) + 16)
+#define MIPI_CSIS_DBG_INTR_SRC_EARLY_FE(n)             BIT((n) + 12)
+#define MIPI_CSIS_DBG_INTR_SRC_EARLY_FS(n)             BIT((n) + 8)
+#define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL(n)       BIT((n) + 4)
+#define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE(n)       BIT((n) + 0)
 
 #define MIPI_CSIS_FRAME_COUNTER_CH(n)          (0x0100 + (n) * 4)
 

@@ -229,8 +226,11 @@
 #define MIPI_CSIS_PKTDATA_EVEN                 0x3000
 #define MIPI_CSIS_PKTDATA_SIZE                 SZ_4K
 
+#define MIPI_CSIS_MAX_CHANNELS                 4
+
 struct mipi_csis_event {
        bool debug;
+       unsigned int channel;
        u32 mask;
        const char * const name;
        unsigned int counter;

@@ -238,36 +238,70 @@ struct mipi_csis_event {
 
 static const struct mipi_csis_event mipi_csis_events[] = {
        /* Errors */
-       { false, MIPI_CSIS_INT_SRC_ERR_SOT_HS(0),       "SOT 0 Error" },
-       { false, MIPI_CSIS_INT_SRC_ERR_SOT_HS(1),       "SOT 1 Error" },
-       { false, MIPI_CSIS_INT_SRC_ERR_SOT_HS(2),       "SOT 2 Error" },
-       { false, MIPI_CSIS_INT_SRC_ERR_SOT_HS(3),       "SOT 3 Error" },
-       { false, MIPI_CSIS_INT_SRC_ERR_LOST_FS,         "Lost Frame Start Error" },
-       { false, MIPI_CSIS_INT_SRC_ERR_LOST_FE,         "Lost Frame End Error" },
-       { false, MIPI_CSIS_INT_SRC_ERR_OVER,            "FIFO Overflow Error" },
-       { false, MIPI_CSIS_INT_SRC_ERR_WRONG_CFG,       "Wrong Configuration Error" },
-       { false, MIPI_CSIS_INT_SRC_ERR_ECC,             "ECC Error" },
-       { false, MIPI_CSIS_INT_SRC_ERR_CRC,             "CRC Error" },
-       { false, MIPI_CSIS_INT_SRC_ERR_ID,              "Unknown ID Error" },
-       { true, MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT,  "Data Type Not Supported" },
-       { true, MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE,       "Data Type Ignored" },
-       { true, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE,  "Frame Size Error" },
-       { true, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME, "Truncated Frame" },
-       { true, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE,        "Early Frame End" },
-       { true, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS,        "Early Frame Start" },
+       { false, 0, MIPI_CSIS_INT_SRC_ERR_SOT_HS(0),            "SOT 0 Error" },
+       { false, 0, MIPI_CSIS_INT_SRC_ERR_SOT_HS(1),            "SOT 1 Error" },
+       { false, 0, MIPI_CSIS_INT_SRC_ERR_SOT_HS(2),            "SOT 2 Error" },
+       { false, 0, MIPI_CSIS_INT_SRC_ERR_SOT_HS(3),            "SOT 3 Error" },
+       { false, 0, MIPI_CSIS_INT_SRC_ERR_LOST_FS(0),           "Lost Frame Start Error 0" },
+       { false, 1, MIPI_CSIS_INT_SRC_ERR_LOST_FS(1),           "Lost Frame Start Error 1" },
+       { false, 2, MIPI_CSIS_INT_SRC_ERR_LOST_FS(2),           "Lost Frame Start Error 2" },
+       { false, 3, MIPI_CSIS_INT_SRC_ERR_LOST_FS(3),           "Lost Frame Start Error 3" },
+       { false, 0, MIPI_CSIS_INT_SRC_ERR_LOST_FE(0),           "Lost Frame End Error 0" },
+       { false, 1, MIPI_CSIS_INT_SRC_ERR_LOST_FE(1),           "Lost Frame End Error 1" },
+       { false, 2, MIPI_CSIS_INT_SRC_ERR_LOST_FE(2),           "Lost Frame End Error 2" },
+       { false, 3, MIPI_CSIS_INT_SRC_ERR_LOST_FE(3),           "Lost Frame End Error 3" },
+       { false, 0, MIPI_CSIS_INT_SRC_ERR_OVER(0),              "FIFO Overflow Error 0" },
+       { false, 1, MIPI_CSIS_INT_SRC_ERR_OVER(1),              "FIFO Overflow Error 1" },
+       { false, 2, MIPI_CSIS_INT_SRC_ERR_OVER(2),              "FIFO Overflow Error 2" },
+       { false, 3, MIPI_CSIS_INT_SRC_ERR_OVER(3),              "FIFO Overflow Error 3" },
+       { false, 0, MIPI_CSIS_INT_SRC_ERR_WRONG_CFG,            "Wrong Configuration Error" },
+       { false, 0, MIPI_CSIS_INT_SRC_ERR_ECC,                  "ECC Error" },
+       { false, 0, MIPI_CSIS_INT_SRC_ERR_CRC,                  "CRC Error" },
+       { false, 0, MIPI_CSIS_INT_SRC_ERR_ID,                   "Unknown ID Error" },
+       { true, 0, MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT,       "Data Type Not Supported" },
+       { true, 0, MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE,            "Data Type Ignored" },
+       { true, 0, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE(0),    "Frame Size Error 0" },
+       { true, 1, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE(1),    "Frame Size Error 1" },
+       { true, 2, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE(2),    "Frame Size Error 2" },
+       { true, 3, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE(3),    "Frame Size Error 3" },
+       { true, 0, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME(0),   "Truncated Frame 0" },
+       { true, 1, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME(1),   "Truncated Frame 1" },
+       { true, 2, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME(2),   "Truncated Frame 2" },
+       { true, 3, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME(3),   "Truncated Frame 3" },
+       { true, 0, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE(0),          "Early Frame End 0" },
+       { true, 1, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE(1),          "Early Frame End 1" },
+       { true, 2, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE(2),          "Early Frame End 2" },
+       { true, 3, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE(3),          "Early Frame End 3" },
+       { true, 0, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS(0),          "Early Frame Start 0" },
+       { true, 1, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS(1),          "Early Frame Start 1" },
+       { true, 2, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS(2),          "Early Frame Start 2" },
+       { true, 3, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS(3),          "Early Frame Start 3" },
        /* Non-image data receive events */
-       { false, MIPI_CSIS_INT_SRC_EVEN_BEFORE,         "Non-image data before even frame" },
-       { false, MIPI_CSIS_INT_SRC_EVEN_AFTER,          "Non-image data after even frame" },
-       { false, MIPI_CSIS_INT_SRC_ODD_BEFORE,          "Non-image data before odd frame" },
-       { false, MIPI_CSIS_INT_SRC_ODD_AFTER,           "Non-image data after odd frame" },
+       { false, 0, MIPI_CSIS_INT_SRC_EVEN_BEFORE,              "Non-image data before even frame" },
+       { false, 0, MIPI_CSIS_INT_SRC_EVEN_AFTER,               "Non-image data after even frame" },
+       { false, 0, MIPI_CSIS_INT_SRC_ODD_BEFORE,               "Non-image data before odd frame" },
+       { false, 0, MIPI_CSIS_INT_SRC_ODD_AFTER,                "Non-image data after odd frame" },
        /* Frame start/end */
-       { false, MIPI_CSIS_INT_SRC_FRAME_START,         "Frame Start" },
-       { false, MIPI_CSIS_INT_SRC_FRAME_END,           "Frame End" },
-       { true, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL,  "VSYNC Falling Edge" },
-       { true, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE,  "VSYNC Rising Edge" },
+       { false, 0, MIPI_CSIS_INT_SRC_FRAME_START(0),           "Frame Start 0" },
+       { false, 1, MIPI_CSIS_INT_SRC_FRAME_START(1),           "Frame Start 1" },
+       { false, 2, MIPI_CSIS_INT_SRC_FRAME_START(2),           "Frame Start 2" },
+       { false, 3, MIPI_CSIS_INT_SRC_FRAME_START(3),           "Frame Start 3" },
+       { false, 0, MIPI_CSIS_INT_SRC_FRAME_END(0),             "Frame End 0" },
+       { false, 1, MIPI_CSIS_INT_SRC_FRAME_END(1),             "Frame End 1" },
+       { false, 2, MIPI_CSIS_INT_SRC_FRAME_END(2),             "Frame End 2" },
+       { false, 3, MIPI_CSIS_INT_SRC_FRAME_END(3),             "Frame End 3" },
+       { true, 0, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL(0),    "VSYNC Falling Edge 0" },
+       { true, 1, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL(1),    "VSYNC Falling Edge 1" },
+       { true, 2, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL(2),    "VSYNC Falling Edge 2" },

drivers/media/platform/nxp/imx-mipi-csis.c +65 -34

 enum mipi_csis_clk {
        MIPI_CSIS_CLK_PCLK,

@@ -299,7 +333,9 @@ struct mipi_csis_device {
        struct clk_bulk_data *clks;
        struct reset_control *mrst;
        struct regulator *mipi_phy_regulator;
+
        const struct mipi_csis_info *info;
+       unsigned int num_channels;
 
        struct v4l2_subdev sd;
        struct media_pad pads[CSIS_PADS_NUM];

@@ -654,8 +690,8 @@ static void mipi_csis_set_params(struct mipi_csis_device *csis,
                        MIPI_CSIS_ISP_SYNC_VSYNC_EINTV(0));
 
        val = mipi_csis_read(csis, MIPI_CSIS_CLK_CTRL);
-       val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC;
-       val |= MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(15);
+       val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC(0);
+       val |= MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL(0, 15);
        val &= ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MASK;
        mipi_csis_write(csis, MIPI_CSIS_CLK_CTRL, val);
 

@@ -672,7 +708,7 @@ static void mipi_csis_set_params(struct mipi_csis_device *csis,
        /* Update the shadow register. */
        val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
        mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL,
-                       val | MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW |
+                       val | MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW(0) |
                        MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL);
 }
 

@@ -763,16 +799,19 @@ static irqreturn_t mipi_csis_irq_handler(int irq, void *dev_id)
 
        /* Update the event/error counters */
        if ((status & MIPI_CSIS_INT_SRC_ERRORS) || csis->debug.enable) {
-               for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) {
+               for (i = 0; i < ARRAY_SIZE(csis->events); i++) {
                        struct mipi_csis_event *event = &csis->events[i];
 
+                       if (event->channel >= csis->num_channels)
+                               continue;
+
                        if ((!event->debug && (status & event->mask)) ||
                            (event->debug && (dbg_status & event->mask)))
                                event->counter++;
                }
        }
 
-       if (status & MIPI_CSIS_INT_SRC_FRAME_START)
+       if (status & MIPI_CSIS_INT_SRC_FRAME_START(0))
                mipi_csis_queue_event_sof(csis);
 
        spin_unlock_irqrestore(&csis->slock, flags);

@@ -849,7 +888,7 @@ static void mipi_csis_clear_counters(struct mipi_csis_device *csis)
 static void mipi_csis_log_counters(struct mipi_csis_device *csis, bool non_errors)
 {
        unsigned int num_events = non_errors ? MIPI_CSIS_NUM_EVENTS
-                               : MIPI_CSIS_NUM_EVENTS - 8;
+                               : MIPI_CSIS_NUM_ERROR_EVENTS;
        unsigned int counters[MIPI_CSIS_NUM_EVENTS];
        unsigned long flags;
        unsigned int i;

@@ -860,45 +899,67 @@ static void mipi_csis_log_counters(struct mipi_csis_device *csis, bool non_error
        spin_unlock_irqrestore(&csis->slock, flags);
 
        for (i = 0; i < num_events; ++i) {
+               const struct mipi_csis_event *event = &csis->events[i];
+
+               if (event->channel >= csis->num_channels)
+                       continue;
+
                if (counters[i] > 0 || csis->debug.enable)
                        dev_info(csis->dev, "%s events: %d\n",
-                                csis->events[i].name,
-                                counters[i]);
+                                event->name, counters[i]);
        }
 }
 
+struct mipi_csis_reg_info {
+       u32 addr;
+       unsigned int offset;
+       const char * const name;
+};
+
+static void mipi_csis_dump_channel_reg(struct mipi_csis_device *csis,
+                                      const struct mipi_csis_reg_info *reg,
+                                      unsigned int channel)
+{
+       dev_info(csis->dev, "%16s%u: 0x%08x\n", reg->name, channel,
+                mipi_csis_read(csis, reg->addr + channel * reg->offset));
+}
+
 static int mipi_csis_dump_regs(struct mipi_csis_device *csis)
 {
-       static const struct {
-               u32 offset;
-               const char * const name;
-       } registers[] = {
-               { MIPI_CSIS_CMN_CTRL, "CMN_CTRL" },
-               { MIPI_CSIS_CLK_CTRL, "CLK_CTRL" },
-               { MIPI_CSIS_INT_MSK, "INT_MSK" },
-               { MIPI_CSIS_DPHY_STATUS, "DPHY_STATUS" },
-               { MIPI_CSIS_DPHY_CMN_CTRL, "DPHY_CMN_CTRL" },
-               { MIPI_CSIS_DPHY_SCTRL_L, "DPHY_SCTRL_L" },
-               { MIPI_CSIS_DPHY_SCTRL_H, "DPHY_SCTRL_H" },
-               { MIPI_CSIS_ISP_CONFIG_CH(0), "ISP_CONFIG_CH0" },
-               { MIPI_CSIS_ISP_RESOL_CH(0), "ISP_RESOL_CH0" },
-               { MIPI_CSIS_SDW_CONFIG_CH(0), "SDW_CONFIG_CH0" },
-               { MIPI_CSIS_SDW_RESOL_CH(0), "SDW_RESOL_CH0" },
-               { MIPI_CSIS_DBG_CTRL, "DBG_CTRL" },
-               { MIPI_CSIS_FRAME_COUNTER_CH(0), "FRAME_COUNTER_CH0" },
+       static const struct mipi_csis_reg_info common_registers[] = {
+               { MIPI_CSIS_CMN_CTRL, 0, "CMN_CTRL" },
+               { MIPI_CSIS_CLK_CTRL, 0, "CLK_CTRL" },
+               { MIPI_CSIS_INT_MSK, 0, "INT_MSK" },
+               { MIPI_CSIS_DPHY_STATUS, 0, "DPHY_STATUS" },
+               { MIPI_CSIS_DPHY_CMN_CTRL, 0, "DPHY_CMN_CTRL" },
+               { MIPI_CSIS_DPHY_SCTRL_L, 0, "DPHY_SCTRL_L" },
+               { MIPI_CSIS_DPHY_SCTRL_H, 0, "DPHY_SCTRL_H" },
+               { MIPI_CSIS_DBG_CTRL, 0, "DBG_CTRL" },
+       };
+       static const struct mipi_csis_reg_info channel_registers[] = {
+               { MIPI_CSIS_ISP_CONFIG_CH(0), 0x10, "ISP_CONFIG_CH" },
+               { MIPI_CSIS_ISP_RESOL_CH(0), 0x10, "ISP_RESOL_CH" },
+               { MIPI_CSIS_SDW_CONFIG_CH(0), 0x10, "SDW_CONFIG_CH" },
+               { MIPI_CSIS_SDW_RESOL_CH(0), 0x10, "SDW_RESOL_CH" },
+               { MIPI_CSIS_FRAME_COUNTER_CH(0), 4, "FRAME_COUNTER_CH" },
        };
-
-       unsigned int i;
-       u32 cfg;
 
        if (!pm_runtime_get_if_in_use(csis->dev))
                return 0;
 
        dev_info(csis->dev, "--- REGISTERS ---\n");
 
-       for (i = 0; i < ARRAY_SIZE(registers); i++) {
-               cfg = mipi_csis_read(csis, registers[i].offset);
-               dev_info(csis->dev, "%17s: 0x%08x\n", registers[i].name, cfg);
+       for (unsigned int i = 0; i < ARRAY_SIZE(common_registers); i++) {
+               const struct mipi_csis_reg_info *reg = &common_registers[i];
+
+               dev_info(csis->dev, "%17s: 0x%08x\n", reg->name,
+                        mipi_csis_read(csis, reg->addr));
+       }
+
+       for (unsigned int chan = 0; chan < csis->num_channels; chan++) {
+               for (unsigned int i = 0; i < ARRAY_SIZE(channel_registers); ++i)
+                       mipi_csis_dump_channel_reg(csis, &channel_registers[i],
+                                                  chan);
        }
 
        pm_runtime_put(csis->dev);

@@ -1421,6 +1482,12 @@ static int mipi_csis_parse_dt(struct mipi_csis_device *csis)
 
        of_property_read_u32(node, "clock-frequency", &csis->clk_frequency);
 
+       csis->num_channels = 1;
+       of_property_read_u32(node, "fsl,num-channels", &csis->num_channels);
+       if (csis->num_channels < 1 || csis->num_channels > MIPI_CSIS_MAX_CHANNELS)
+               return dev_err_probe(csis->dev, -EINVAL,
+                                    "Invalid fsl,num-channels value\n");
+
        return 0;
 }
 

@@ -1444,10 +1511,8 @@ static int mipi_csis_probe(struct platform_device *pdev)
 
        /* Parse DT properties. */
        ret = mipi_csis_parse_dt(csis);
-       if (ret < 0) {
-               dev_err(dev, "Failed to parse device tree: %d\n", ret);
+       if (ret < 0)
                return ret;
-       }
 
        /* Acquire resources. */
        csis->regs = devm_platform_ioremap_resource(pdev, 0);

Signature · 3 lines

Regards,

Laurent Pinchart

Quoting Laurent Pinchart (2025-08-22 02:27:32)

Quoted 207 lines

Some CSIS instances feature more than one output channel. Update register macros accordingly, parse the number of channels from the device tree, and update register dumps and event counters to log per-channel data.

Support for routing virtual channels and data types to output channels through the subdev internal routing API will come later.

Signed-off-by Laurent Pinchart <[email protected]>

---
Changes since v1:

- Update more per-channel registers
- Update commit message

---
 drivers/media/platform/nxp/imx-mipi-csis.c | 239 +++++++++++++--------
 1 file changed, 152 insertions(+), 87 deletions(-)

drivers/media/platform/nxp/imx-mipi-csis.c +85 -52

index e1588990beda..ee8e541dcb1d 100644
@@ -54,7 +54,7 @@
 
 /* CSIS common control */
 #define MIPI_CSIS_CMN_CTRL                     0x04
-#define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW       BIT(16)
+#define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW(n)    BIT((n) + 16)
 #define MIPI_CSIS_CMN_CTRL_INTERLEAVE_MODE_DT  BIT(10)
 #define MIPI_CSIS_CMN_CTRL_LANE_NUMBER(n)      ((n) << 8)
 #define MIPI_CSIS_CMN_CTRL_LANE_NUMBER_MASK    GENMASK(9, 8)

@@ -64,12 +64,9 @@
 
 /* CSIS clock control */
 #define MIPI_CSIS_CLK_CTRL                     0x08
-#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH3(x)        ((x) << 28)
-#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH2(x)        ((x) << 24)
-#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH1(x)        ((x) << 20)
-#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(x)        ((x) << 16)
+#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL(n, x) ((x) << ((n) * 4 + 16))
 #define MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MASK     GENMASK(7, 4)
-#define MIPI_CSIS_CLK_CTRL_WCLK_SRC            BIT(0)
+#define MIPI_CSIS_CLK_CTRL_WCLK_SRC(n)         BIT(n)
 
 /* CSIS Interrupt mask */
 #define MIPI_CSIS_INT_MSK                      0x10

@@ -97,12 +94,12 @@
 #define MIPI_CSIS_INT_SRC_ODD_AFTER            BIT(28)
 #define MIPI_CSIS_INT_SRC_ODD                  (0x3 << 28)
 #define MIPI_CSIS_INT_SRC_NON_IMAGE_DATA       (0xf << 28)
-#define MIPI_CSIS_INT_SRC_FRAME_START          BIT(24)
-#define MIPI_CSIS_INT_SRC_FRAME_END            BIT(20)
+#define MIPI_CSIS_INT_SRC_FRAME_START(n)       BIT((n) + 24)
+#define MIPI_CSIS_INT_SRC_FRAME_END(n)         BIT((n) + 20)
 #define MIPI_CSIS_INT_SRC_ERR_SOT_HS(n)                BIT((n) + 16)
-#define MIPI_CSIS_INT_SRC_ERR_LOST_FS          BIT(12)
-#define MIPI_CSIS_INT_SRC_ERR_LOST_FE          BIT(8)
-#define MIPI_CSIS_INT_SRC_ERR_OVER             BIT(4)
+#define MIPI_CSIS_INT_SRC_ERR_LOST_FS(n)       BIT((n) + 12)
+#define MIPI_CSIS_INT_SRC_ERR_LOST_FE(n)       BIT((n) + 8)
+#define MIPI_CSIS_INT_SRC_ERR_OVER(n)          BIT((n) + 4)
 #define MIPI_CSIS_INT_SRC_ERR_WRONG_CFG                BIT(3)
 #define MIPI_CSIS_INT_SRC_ERR_ECC              BIT(2)
 #define MIPI_CSIS_INT_SRC_ERR_CRC              BIT(1)

@@ -204,23 +201,23 @@
 /* Debug control register */
 #define MIPI_CSIS_DBG_CTRL                     0xc0
 #define MIPI_CSIS_DBG_INTR_MSK                 0xc4
-#define MIPI_CSIS_DBG_INTR_MSK_DT_NOT_SUPPORT  BIT(25)
-#define MIPI_CSIS_DBG_INTR_MSK_DT_IGNORE       BIT(24)
-#define MIPI_CSIS_DBG_INTR_MSK_ERR_FRAME_SIZE  BIT(20)
-#define MIPI_CSIS_DBG_INTR_MSK_TRUNCATED_FRAME BIT(16)
-#define MIPI_CSIS_DBG_INTR_MSK_EARLY_FE                BIT(12)
-#define MIPI_CSIS_DBG_INTR_MSK_EARLY_FS                BIT(8)
-#define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_FALL  BIT(4)
-#define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_RISE  BIT(0)
+#define MIPI_CSIS_DBG_INTR_MSK_DT_NOT_SUPPORT          BIT(25)
+#define MIPI_CSIS_DBG_INTR_MSK_DT_IGNORE               BIT(24)
+#define MIPI_CSIS_DBG_INTR_MSK_ERR_FRAME_SIZE(n)       BIT((n) + 20)
+#define MIPI_CSIS_DBG_INTR_MSK_TRUNCATED_FRAME(n)      BIT((n) + 16)
+#define MIPI_CSIS_DBG_INTR_MSK_EARLY_FE(n)             BIT((n) + 12)
+#define MIPI_CSIS_DBG_INTR_MSK_EARLY_FS(n)             BIT((n) + 8)
+#define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_FALL(n)       BIT((n) + 4)
+#define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_RISE(n)       BIT((n) + 0)
 #define MIPI_CSIS_DBG_INTR_SRC                 0xc8
-#define MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT  BIT(25)
-#define MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE       BIT(24)
-#define MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE  BIT(20)
-#define MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME BIT(16)
-#define MIPI_CSIS_DBG_INTR_SRC_EARLY_FE                BIT(12)
-#define MIPI_CSIS_DBG_INTR_SRC_EARLY_FS                BIT(8)
-#define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL  BIT(4)
-#define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE  BIT(0)
+#define MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT          BIT(25)
+#define MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE               BIT(24)
+#define MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE(n)       BIT((n) + 20)
+#define MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME(n)      BIT((n) + 16)
+#define MIPI_CSIS_DBG_INTR_SRC_EARLY_FE(n)             BIT((n) + 12)
+#define MIPI_CSIS_DBG_INTR_SRC_EARLY_FS(n)             BIT((n) + 8)
+#define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL(n)       BIT((n) + 4)
+#define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE(n)       BIT((n) + 0)
 
 #define MIPI_CSIS_FRAME_COUNTER_CH(n)          (0x0100 + (n) * 4)
 

@@ -229,8 +226,11 @@
 #define MIPI_CSIS_PKTDATA_EVEN                 0x3000
 #define MIPI_CSIS_PKTDATA_SIZE                 SZ_4K
 
+#define MIPI_CSIS_MAX_CHANNELS                 4
+
 struct mipi_csis_event {
        bool debug;
+       unsigned int channel;
        u32 mask;
        const char * const name;
        unsigned int counter;

@@ -238,36 +238,70 @@ struct mipi_csis_event {
 
 static const struct mipi_csis_event mipi_csis_events[] = {
        /* Errors */
-       { false, MIPI_CSIS_INT_SRC_ERR_SOT_HS(0),       "SOT 0 Error" },
-       { false, MIPI_CSIS_INT_SRC_ERR_SOT_HS(1),       "SOT 1 Error" },
-       { false, MIPI_CSIS_INT_SRC_ERR_SOT_HS(2),       "SOT 2 Error" },
-       { false, MIPI_CSIS_INT_SRC_ERR_SOT_HS(3),       "SOT 3 Error" },
-       { false, MIPI_CSIS_INT_SRC_ERR_LOST_FS,         "Lost Frame Start Error" },
-       { false, MIPI_CSIS_INT_SRC_ERR_LOST_FE,         "Lost Frame End Error" },
-       { false, MIPI_CSIS_INT_SRC_ERR_OVER,            "FIFO Overflow Error" },
-       { false, MIPI_CSIS_INT_SRC_ERR_WRONG_CFG,       "Wrong Configuration Error" },
-       { false, MIPI_CSIS_INT_SRC_ERR_ECC,             "ECC Error" },
-       { false, MIPI_CSIS_INT_SRC_ERR_CRC,             "CRC Error" },
-       { false, MIPI_CSIS_INT_SRC_ERR_ID,              "Unknown ID Error" },
-       { true, MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT,  "Data Type Not Supported" },
-       { true, MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE,       "Data Type Ignored" },
-       { true, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE,  "Frame Size Error" },
-       { true, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME, "Truncated Frame" },
-       { true, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE,        "Early Frame End" },
-       { true, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS,        "Early Frame Start" },
+       { false, 0, MIPI_CSIS_INT_SRC_ERR_SOT_HS(0),            "SOT 0 Error" },
+       { false, 0, MIPI_CSIS_INT_SRC_ERR_SOT_HS(1),            "SOT 1 Error" },
+       { false, 0, MIPI_CSIS_INT_SRC_ERR_SOT_HS(2),            "SOT 2 Error" },
+       { false, 0, MIPI_CSIS_INT_SRC_ERR_SOT_HS(3),            "SOT 3 Error" },
+       { false, 0, MIPI_CSIS_INT_SRC_ERR_LOST_FS(0),           "Lost Frame Start Error 0" },
+       { false, 1, MIPI_CSIS_INT_SRC_ERR_LOST_FS(1),           "Lost Frame Start Error 1" },
+       { false, 2, MIPI_CSIS_INT_SRC_ERR_LOST_FS(2),           "Lost Frame Start Error 2" },
+       { false, 3, MIPI_CSIS_INT_SRC_ERR_LOST_FS(3),           "Lost Frame Start Error 3" },
+       { false, 0, MIPI_CSIS_INT_SRC_ERR_LOST_FE(0),           "Lost Frame End Error 0" },
+       { false, 1, MIPI_CSIS_INT_SRC_ERR_LOST_FE(1),           "Lost Frame End Error 1" },
+       { false, 2, MIPI_CSIS_INT_SRC_ERR_LOST_FE(2),           "Lost Frame End Error 2" },
+       { false, 3, MIPI_CSIS_INT_SRC_ERR_LOST_FE(3),           "Lost Frame End Error 3" },
+       { false, 0, MIPI_CSIS_INT_SRC_ERR_OVER(0),              "FIFO Overflow Error 0" },
+       { false, 1, MIPI_CSIS_INT_SRC_ERR_OVER(1),              "FIFO Overflow Error 1" },
+       { false, 2, MIPI_CSIS_INT_SRC_ERR_OVER(2),              "FIFO Overflow Error 2" },
+       { false, 3, MIPI_CSIS_INT_SRC_ERR_OVER(3),              "FIFO Overflow Error 3" },
+       { false, 0, MIPI_CSIS_INT_SRC_ERR_WRONG_CFG,            "Wrong Configuration Error" },
+       { false, 0, MIPI_CSIS_INT_SRC_ERR_ECC,                  "ECC Error" },
+       { false, 0, MIPI_CSIS_INT_SRC_ERR_CRC,                  "CRC Error" },
+       { false, 0, MIPI_CSIS_INT_SRC_ERR_ID,                   "Unknown ID Error" },
+       { true, 0, MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT,       "Data Type Not Supported" },
+       { true, 0, MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE,            "Data Type Ignored" },
+       { true, 0, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE(0),    "Frame Size Error 0" },
+       { true, 1, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE(1),    "Frame Size Error 1" },
+       { true, 2, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE(2),    "Frame Size Error 2" },
+       { true, 3, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE(3),    "Frame Size Error 3" },
+       { true, 0, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME(0),   "Truncated Frame 0" },
+       { true, 1, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME(1),   "Truncated Frame 1" },
+       { true, 2, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME(2),   "Truncated Frame 2" },
+       { true, 3, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME(3),   "Truncated Frame 3" },
+       { true, 0, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE(0),          "Early Frame End 0" },
+       { true, 1, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE(1),          "Early Frame End 1" },
+       { true, 2, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE(2),          "Early Frame End 2" },
+       { true, 3, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE(3),          "Early Frame End 3" },
+       { true, 0, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS(0),          "Early Frame Start 0" },
+       { true, 1, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS(1),          "Early Frame Start 1" },
+       { true, 2, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS(2),          "Early Frame Start 2" },
+       { true, 3, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS(3),          "Early Frame Start 3" },
        /* Non-image data receive events */
-       { false, MIPI_CSIS_INT_SRC_EVEN_BEFORE,         "Non-image data before even frame" },
-       { false, MIPI_CSIS_INT_SRC_EVEN_AFTER,          "Non-image data after even frame" },
-       { false, MIPI_CSIS_INT_SRC_ODD_BEFORE,          "Non-image data before odd frame" },
-       { false, MIPI_CSIS_INT_SRC_ODD_AFTER,           "Non-image data after odd frame" },
+       { false, 0, MIPI_CSIS_INT_SRC_EVEN_BEFORE,              "Non-image data before even frame" },
+       { false, 0, MIPI_CSIS_INT_SRC_EVEN_AFTER,               "Non-image data after even frame" },
+       { false, 0, MIPI_CSIS_INT_SRC_ODD_BEFORE,               "Non-image data before odd frame" },
+       { false, 0, MIPI_CSIS_INT_SRC_ODD_AFTER,                "Non-image data after odd frame" },
        /* Frame start/end */
-       { false, MIPI_CSIS_INT_SRC_FRAME_START,         "Frame Start" },
-       { false, MIPI_CSIS_INT_SRC_FRAME_END,           "Frame End" },
-       { true, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL,  "VSYNC Falling Edge" },
-       { true, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE,  "VSYNC Rising Edge" },
+       { false, 0, MIPI_CSIS_INT_SRC_FRAME_START(0),           "Frame Start 0" },
+       { false, 1, MIPI_CSIS_INT_SRC_FRAME_START(1),           "Frame Start 1" },
+       { false, 2, MIPI_CSIS_INT_SRC_FRAME_START(2),           "Frame Start 2" },
+       { false, 3, MIPI_CSIS_INT_SRC_FRAME_START(3),           "Frame Start 3" },
+       { false, 0, MIPI_CSIS_INT_SRC_FRAME_END(0),             "Frame End 0" },
+       { false, 1, MIPI_CSIS_INT_SRC_FRAME_END(1),             "Frame End 1" },
+       { false, 2, MIPI_CSIS_INT_SRC_FRAME_END(2),             "Frame End 2" },
+       { false, 3, MIPI_CSIS_INT_SRC_FRAME_END(3),             "Frame End 3" },
+       { true, 0, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL(0),    "VSYNC Falling Edge 0" },
+       { true, 1, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL(1),    "VSYNC Falling Edge 1" },
+       { true, 2, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL(2),    "VSYNC Falling Edge 2" },
+       { true, 3, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL(3),    "VSYNC Falling Edge 3" },
+       { true, 0, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE(0),    "VSYNC Rising Edge 0" },
+       { true, 1, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE(1),    "VSYNC Rising Edge 1" },
+       { true, 2, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE(2),    "VSYNC Rising Edge 2" },
+       { true, 3, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE(3),    "VSYNC Rising Edge 3" },
 };
 

drivers/media/platform/nxp/imx-mipi-csis.c struct mipi_csis_event { · line 304

Quoted 3 lines

drivers/media/platform/nxp/imx-mipi-csis.c +2 -1

-#define MIPI_CSIS_NUM_EVENTS ARRAY_SIZE(mipi_csis_events)
+#define MIPI_CSIS_NUM_EVENTS           ARRAY_SIZE(mipi_csis_events)
+#define MIPI_CSIS_NUM_ERROR_EVENTS     (MIPI_CSIS_NUM_EVENTS - 20)

Why is that (MIPI_CSIS_NUM_EVENTS - 20)? Should that just be 20?

The rest looks fine to me.

Quoted 182 lines

drivers/media/platform/nxp/imx-mipi-csis.c +65 -34

 enum mipi_csis_clk {
        MIPI_CSIS_CLK_PCLK,

@@ -299,7 +333,9 @@ struct mipi_csis_device {
        struct clk_bulk_data *clks;
        struct reset_control *mrst;
        struct regulator *mipi_phy_regulator;
+
        const struct mipi_csis_info *info;
+       unsigned int num_channels;
 
        struct v4l2_subdev sd;
        struct media_pad pads[CSIS_PADS_NUM];

@@ -654,8 +690,8 @@ static void mipi_csis_set_params(struct mipi_csis_device *csis,
                        MIPI_CSIS_ISP_SYNC_VSYNC_EINTV(0));
 
        val = mipi_csis_read(csis, MIPI_CSIS_CLK_CTRL);
-       val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC;
-       val |= MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(15);
+       val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC(0);
+       val |= MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL(0, 15);
        val &= ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MASK;
        mipi_csis_write(csis, MIPI_CSIS_CLK_CTRL, val);
 

@@ -672,7 +708,7 @@ static void mipi_csis_set_params(struct mipi_csis_device *csis,
        /* Update the shadow register. */
        val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
        mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL,
-                       val | MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW |
+                       val | MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW(0) |
                        MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL);
 }
 

@@ -763,16 +799,19 @@ static irqreturn_t mipi_csis_irq_handler(int irq, void *dev_id)
 
        /* Update the event/error counters */
        if ((status & MIPI_CSIS_INT_SRC_ERRORS) || csis->debug.enable) {
-               for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) {
+               for (i = 0; i < ARRAY_SIZE(csis->events); i++) {
                        struct mipi_csis_event *event = &csis->events[i];
 
+                       if (event->channel >= csis->num_channels)
+                               continue;
+
                        if ((!event->debug && (status & event->mask)) ||
                            (event->debug && (dbg_status & event->mask)))
                                event->counter++;
                }
        }
 
-       if (status & MIPI_CSIS_INT_SRC_FRAME_START)
+       if (status & MIPI_CSIS_INT_SRC_FRAME_START(0))
                mipi_csis_queue_event_sof(csis);
 
        spin_unlock_irqrestore(&csis->slock, flags);

@@ -849,7 +888,7 @@ static void mipi_csis_clear_counters(struct mipi_csis_device *csis)
 static void mipi_csis_log_counters(struct mipi_csis_device *csis, bool non_errors)
 {
        unsigned int num_events = non_errors ? MIPI_CSIS_NUM_EVENTS
-                               : MIPI_CSIS_NUM_EVENTS - 8;
+                               : MIPI_CSIS_NUM_ERROR_EVENTS;
        unsigned int counters[MIPI_CSIS_NUM_EVENTS];
        unsigned long flags;
        unsigned int i;

@@ -860,45 +899,67 @@ static void mipi_csis_log_counters(struct mipi_csis_device *csis, bool non_error
        spin_unlock_irqrestore(&csis->slock, flags);
 
        for (i = 0; i < num_events; ++i) {
+               const struct mipi_csis_event *event = &csis->events[i];
+
+               if (event->channel >= csis->num_channels)
+                       continue;
+
                if (counters[i] > 0 || csis->debug.enable)
                        dev_info(csis->dev, "%s events: %d\n",
-                                csis->events[i].name,
-                                counters[i]);
+                                event->name, counters[i]);
        }
 }
 
+struct mipi_csis_reg_info {
+       u32 addr;
+       unsigned int offset;
+       const char * const name;
+};
+
+static void mipi_csis_dump_channel_reg(struct mipi_csis_device *csis,
+                                      const struct mipi_csis_reg_info *reg,
+                                      unsigned int channel)
+{
+       dev_info(csis->dev, "%16s%u: 0x%08x\n", reg->name, channel,
+                mipi_csis_read(csis, reg->addr + channel * reg->offset));
+}
+
 static int mipi_csis_dump_regs(struct mipi_csis_device *csis)
 {
-       static const struct {
-               u32 offset;
-               const char * const name;
-       } registers[] = {
-               { MIPI_CSIS_CMN_CTRL, "CMN_CTRL" },
-               { MIPI_CSIS_CLK_CTRL, "CLK_CTRL" },
-               { MIPI_CSIS_INT_MSK, "INT_MSK" },
-               { MIPI_CSIS_DPHY_STATUS, "DPHY_STATUS" },
-               { MIPI_CSIS_DPHY_CMN_CTRL, "DPHY_CMN_CTRL" },
-               { MIPI_CSIS_DPHY_SCTRL_L, "DPHY_SCTRL_L" },
-               { MIPI_CSIS_DPHY_SCTRL_H, "DPHY_SCTRL_H" },
-               { MIPI_CSIS_ISP_CONFIG_CH(0), "ISP_CONFIG_CH0" },
-               { MIPI_CSIS_ISP_RESOL_CH(0), "ISP_RESOL_CH0" },
-               { MIPI_CSIS_SDW_CONFIG_CH(0), "SDW_CONFIG_CH0" },
-               { MIPI_CSIS_SDW_RESOL_CH(0), "SDW_RESOL_CH0" },
-               { MIPI_CSIS_DBG_CTRL, "DBG_CTRL" },
-               { MIPI_CSIS_FRAME_COUNTER_CH(0), "FRAME_COUNTER_CH0" },
+       static const struct mipi_csis_reg_info common_registers[] = {
+               { MIPI_CSIS_CMN_CTRL, 0, "CMN_CTRL" },
+               { MIPI_CSIS_CLK_CTRL, 0, "CLK_CTRL" },
+               { MIPI_CSIS_INT_MSK, 0, "INT_MSK" },
+               { MIPI_CSIS_DPHY_STATUS, 0, "DPHY_STATUS" },
+               { MIPI_CSIS_DPHY_CMN_CTRL, 0, "DPHY_CMN_CTRL" },
+               { MIPI_CSIS_DPHY_SCTRL_L, 0, "DPHY_SCTRL_L" },
+               { MIPI_CSIS_DPHY_SCTRL_H, 0, "DPHY_SCTRL_H" },
+               { MIPI_CSIS_DBG_CTRL, 0, "DBG_CTRL" },
+       };
+       static const struct mipi_csis_reg_info channel_registers[] = {
+               { MIPI_CSIS_ISP_CONFIG_CH(0), 0x10, "ISP_CONFIG_CH" },
+               { MIPI_CSIS_ISP_RESOL_CH(0), 0x10, "ISP_RESOL_CH" },
+               { MIPI_CSIS_SDW_CONFIG_CH(0), 0x10, "SDW_CONFIG_CH" },
+               { MIPI_CSIS_SDW_RESOL_CH(0), 0x10, "SDW_RESOL_CH" },
+               { MIPI_CSIS_FRAME_COUNTER_CH(0), 4, "FRAME_COUNTER_CH" },
        };
-
-       unsigned int i;
-       u32 cfg;
 
        if (!pm_runtime_get_if_in_use(csis->dev))
                return 0;
 
        dev_info(csis->dev, "--- REGISTERS ---\n");
 
-       for (i = 0; i < ARRAY_SIZE(registers); i++) {
-               cfg = mipi_csis_read(csis, registers[i].offset);
-               dev_info(csis->dev, "%17s: 0x%08x\n", registers[i].name, cfg);
+       for (unsigned int i = 0; i < ARRAY_SIZE(common_registers); i++) {
+               const struct mipi_csis_reg_info *reg = &common_registers[i];
+
+               dev_info(csis->dev, "%17s: 0x%08x\n", reg->name,
+                        mipi_csis_read(csis, reg->addr));
+       }
+
+       for (unsigned int chan = 0; chan < csis->num_channels; chan++) {
+               for (unsigned int i = 0; i < ARRAY_SIZE(channel_registers); ++i)
+                       mipi_csis_dump_channel_reg(csis, &channel_registers[i],
+                                                  chan);
        }
 
        pm_runtime_put(csis->dev);

@@ -1421,6 +1482,12 @@ static int mipi_csis_parse_dt(struct mipi_csis_device *csis)
 
        of_property_read_u32(node, "clock-frequency", &csis->clk_frequency);
 
+       csis->num_channels = 1;
+       of_property_read_u32(node, "fsl,num-channels", &csis->num_channels);
+       if (csis->num_channels < 1 || csis->num_channels > MIPI_CSIS_MAX_CHANNELS)
+               return dev_err_probe(csis->dev, -EINVAL,
+                                    "Invalid fsl,num-channels value\n");
+
        return 0;
 }
 

@@ -1444,10 +1511,8 @@ static int mipi_csis_probe(struct platform_device *pdev)
 
        /* Parse DT properties. */
        ret = mipi_csis_parse_dt(csis);
-       if (ret < 0) {
-               dev_err(dev, "Failed to parse device tree: %d\n", ret);
+       if (ret < 0)
                return ret;
-       }
 
        /* Acquire resources. */
        csis->regs = devm_platform_ioremap_resource(pdev, 0);

Quoted 208 lines

Quoting Laurent Pinchart (2025-08-22 02:27:32)

Quoted 207 lines

Some CSIS instances feature more than one output channel. Update register macros accordingly, parse the number of channels from the device tree, and update register dumps and event counters to log per-channel data.

Support for routing virtual channels and data types to output channels through the subdev internal routing API will come later.

Signed-off-by Laurent Pinchart <[email protected]>

---
Changes since v1:

- Update more per-channel registers
- Update commit message

---
 drivers/media/platform/nxp/imx-mipi-csis.c | 239 +++++++++++++--------
 1 file changed, 152 insertions(+), 87 deletions(-)

drivers/media/platform/nxp/imx-mipi-csis.c +85 -52

index e1588990beda..ee8e541dcb1d 100644
@@ -54,7 +54,7 @@
 
 /* CSIS common control */
 #define MIPI_CSIS_CMN_CTRL                     0x04
-#define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW       BIT(16)
+#define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW(n)    BIT((n) + 16)
 #define MIPI_CSIS_CMN_CTRL_INTERLEAVE_MODE_DT  BIT(10)
 #define MIPI_CSIS_CMN_CTRL_LANE_NUMBER(n)      ((n) << 8)
 #define MIPI_CSIS_CMN_CTRL_LANE_NUMBER_MASK    GENMASK(9, 8)

@@ -64,12 +64,9 @@
 
 /* CSIS clock control */
 #define MIPI_CSIS_CLK_CTRL                     0x08
-#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH3(x)        ((x) << 28)
-#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH2(x)        ((x) << 24)
-#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH1(x)        ((x) << 20)
-#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(x)        ((x) << 16)
+#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL(n, x) ((x) << ((n) * 4 + 16))
 #define MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MASK     GENMASK(7, 4)
-#define MIPI_CSIS_CLK_CTRL_WCLK_SRC            BIT(0)
+#define MIPI_CSIS_CLK_CTRL_WCLK_SRC(n)         BIT(n)
 
 /* CSIS Interrupt mask */
 #define MIPI_CSIS_INT_MSK                      0x10

@@ -97,12 +94,12 @@
 #define MIPI_CSIS_INT_SRC_ODD_AFTER            BIT(28)
 #define MIPI_CSIS_INT_SRC_ODD                  (0x3 << 28)
 #define MIPI_CSIS_INT_SRC_NON_IMAGE_DATA       (0xf << 28)
-#define MIPI_CSIS_INT_SRC_FRAME_START          BIT(24)
-#define MIPI_CSIS_INT_SRC_FRAME_END            BIT(20)
+#define MIPI_CSIS_INT_SRC_FRAME_START(n)       BIT((n) + 24)
+#define MIPI_CSIS_INT_SRC_FRAME_END(n)         BIT((n) + 20)
 #define MIPI_CSIS_INT_SRC_ERR_SOT_HS(n)                BIT((n) + 16)
-#define MIPI_CSIS_INT_SRC_ERR_LOST_FS          BIT(12)
-#define MIPI_CSIS_INT_SRC_ERR_LOST_FE          BIT(8)
-#define MIPI_CSIS_INT_SRC_ERR_OVER             BIT(4)
+#define MIPI_CSIS_INT_SRC_ERR_LOST_FS(n)       BIT((n) + 12)
+#define MIPI_CSIS_INT_SRC_ERR_LOST_FE(n)       BIT((n) + 8)
+#define MIPI_CSIS_INT_SRC_ERR_OVER(n)          BIT((n) + 4)
 #define MIPI_CSIS_INT_SRC_ERR_WRONG_CFG                BIT(3)
 #define MIPI_CSIS_INT_SRC_ERR_ECC              BIT(2)
 #define MIPI_CSIS_INT_SRC_ERR_CRC              BIT(1)

@@ -204,23 +201,23 @@
 /* Debug control register */
 #define MIPI_CSIS_DBG_CTRL                     0xc0
 #define MIPI_CSIS_DBG_INTR_MSK                 0xc4
-#define MIPI_CSIS_DBG_INTR_MSK_DT_NOT_SUPPORT  BIT(25)
-#define MIPI_CSIS_DBG_INTR_MSK_DT_IGNORE       BIT(24)
-#define MIPI_CSIS_DBG_INTR_MSK_ERR_FRAME_SIZE  BIT(20)
-#define MIPI_CSIS_DBG_INTR_MSK_TRUNCATED_FRAME BIT(16)
-#define MIPI_CSIS_DBG_INTR_MSK_EARLY_FE                BIT(12)
-#define MIPI_CSIS_DBG_INTR_MSK_EARLY_FS                BIT(8)
-#define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_FALL  BIT(4)
-#define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_RISE  BIT(0)
+#define MIPI_CSIS_DBG_INTR_MSK_DT_NOT_SUPPORT          BIT(25)
+#define MIPI_CSIS_DBG_INTR_MSK_DT_IGNORE               BIT(24)
+#define MIPI_CSIS_DBG_INTR_MSK_ERR_FRAME_SIZE(n)       BIT((n) + 20)
+#define MIPI_CSIS_DBG_INTR_MSK_TRUNCATED_FRAME(n)      BIT((n) + 16)
+#define MIPI_CSIS_DBG_INTR_MSK_EARLY_FE(n)             BIT((n) + 12)
+#define MIPI_CSIS_DBG_INTR_MSK_EARLY_FS(n)             BIT((n) + 8)
+#define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_FALL(n)       BIT((n) + 4)
+#define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_RISE(n)       BIT((n) + 0)
 #define MIPI_CSIS_DBG_INTR_SRC                 0xc8
-#define MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT  BIT(25)
-#define MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE       BIT(24)
-#define MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE  BIT(20)
-#define MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME BIT(16)
-#define MIPI_CSIS_DBG_INTR_SRC_EARLY_FE                BIT(12)
-#define MIPI_CSIS_DBG_INTR_SRC_EARLY_FS                BIT(8)
-#define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL  BIT(4)
-#define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE  BIT(0)
+#define MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT          BIT(25)
+#define MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE               BIT(24)
+#define MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE(n)       BIT((n) + 20)
+#define MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME(n)      BIT((n) + 16)
+#define MIPI_CSIS_DBG_INTR_SRC_EARLY_FE(n)             BIT((n) + 12)
+#define MIPI_CSIS_DBG_INTR_SRC_EARLY_FS(n)             BIT((n) + 8)
+#define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL(n)       BIT((n) + 4)
+#define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE(n)       BIT((n) + 0)
 
 #define MIPI_CSIS_FRAME_COUNTER_CH(n)          (0x0100 + (n) * 4)
 

@@ -229,8 +226,11 @@
 #define MIPI_CSIS_PKTDATA_EVEN                 0x3000
 #define MIPI_CSIS_PKTDATA_SIZE                 SZ_4K
 
+#define MIPI_CSIS_MAX_CHANNELS                 4
+
 struct mipi_csis_event {
        bool debug;
+       unsigned int channel;
        u32 mask;
        const char * const name;
        unsigned int counter;

@@ -238,36 +238,70 @@ struct mipi_csis_event {
 
 static const struct mipi_csis_event mipi_csis_events[] = {
        /* Errors */
-       { false, MIPI_CSIS_INT_SRC_ERR_SOT_HS(0),       "SOT 0 Error" },
-       { false, MIPI_CSIS_INT_SRC_ERR_SOT_HS(1),       "SOT 1 Error" },
-       { false, MIPI_CSIS_INT_SRC_ERR_SOT_HS(2),       "SOT 2 Error" },
-       { false, MIPI_CSIS_INT_SRC_ERR_SOT_HS(3),       "SOT 3 Error" },
-       { false, MIPI_CSIS_INT_SRC_ERR_LOST_FS,         "Lost Frame Start Error" },
-       { false, MIPI_CSIS_INT_SRC_ERR_LOST_FE,         "Lost Frame End Error" },
-       { false, MIPI_CSIS_INT_SRC_ERR_OVER,            "FIFO Overflow Error" },
-       { false, MIPI_CSIS_INT_SRC_ERR_WRONG_CFG,       "Wrong Configuration Error" },
-       { false, MIPI_CSIS_INT_SRC_ERR_ECC,             "ECC Error" },
-       { false, MIPI_CSIS_INT_SRC_ERR_CRC,             "CRC Error" },
-       { false, MIPI_CSIS_INT_SRC_ERR_ID,              "Unknown ID Error" },
-       { true, MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT,  "Data Type Not Supported" },
-       { true, MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE,       "Data Type Ignored" },
-       { true, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE,  "Frame Size Error" },
-       { true, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME, "Truncated Frame" },
-       { true, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE,        "Early Frame End" },
-       { true, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS,        "Early Frame Start" },
+       { false, 0, MIPI_CSIS_INT_SRC_ERR_SOT_HS(0),            "SOT 0 Error" },
+       { false, 0, MIPI_CSIS_INT_SRC_ERR_SOT_HS(1),            "SOT 1 Error" },
+       { false, 0, MIPI_CSIS_INT_SRC_ERR_SOT_HS(2),            "SOT 2 Error" },
+       { false, 0, MIPI_CSIS_INT_SRC_ERR_SOT_HS(3),            "SOT 3 Error" },
+       { false, 0, MIPI_CSIS_INT_SRC_ERR_LOST_FS(0),           "Lost Frame Start Error 0" },
+       { false, 1, MIPI_CSIS_INT_SRC_ERR_LOST_FS(1),           "Lost Frame Start Error 1" },
+       { false, 2, MIPI_CSIS_INT_SRC_ERR_LOST_FS(2),           "Lost Frame Start Error 2" },
+       { false, 3, MIPI_CSIS_INT_SRC_ERR_LOST_FS(3),           "Lost Frame Start Error 3" },
+       { false, 0, MIPI_CSIS_INT_SRC_ERR_LOST_FE(0),           "Lost Frame End Error 0" },
+       { false, 1, MIPI_CSIS_INT_SRC_ERR_LOST_FE(1),           "Lost Frame End Error 1" },
+       { false, 2, MIPI_CSIS_INT_SRC_ERR_LOST_FE(2),           "Lost Frame End Error 2" },
+       { false, 3, MIPI_CSIS_INT_SRC_ERR_LOST_FE(3),           "Lost Frame End Error 3" },
+       { false, 0, MIPI_CSIS_INT_SRC_ERR_OVER(0),              "FIFO Overflow Error 0" },
+       { false, 1, MIPI_CSIS_INT_SRC_ERR_OVER(1),              "FIFO Overflow Error 1" },
+       { false, 2, MIPI_CSIS_INT_SRC_ERR_OVER(2),              "FIFO Overflow Error 2" },
+       { false, 3, MIPI_CSIS_INT_SRC_ERR_OVER(3),              "FIFO Overflow Error 3" },
+       { false, 0, MIPI_CSIS_INT_SRC_ERR_WRONG_CFG,            "Wrong Configuration Error" },
+       { false, 0, MIPI_CSIS_INT_SRC_ERR_ECC,                  "ECC Error" },
+       { false, 0, MIPI_CSIS_INT_SRC_ERR_CRC,                  "CRC Error" },
+       { false, 0, MIPI_CSIS_INT_SRC_ERR_ID,                   "Unknown ID Error" },
+       { true, 0, MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT,       "Data Type Not Supported" },
+       { true, 0, MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE,            "Data Type Ignored" },
+       { true, 0, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE(0),    "Frame Size Error 0" },
+       { true, 1, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE(1),    "Frame Size Error 1" },
+       { true, 2, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE(2),    "Frame Size Error 2" },
+       { true, 3, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE(3),    "Frame Size Error 3" },
+       { true, 0, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME(0),   "Truncated Frame 0" },
+       { true, 1, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME(1),   "Truncated Frame 1" },
+       { true, 2, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME(2),   "Truncated Frame 2" },
+       { true, 3, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME(3),   "Truncated Frame 3" },
+       { true, 0, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE(0),          "Early Frame End 0" },
+       { true, 1, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE(1),          "Early Frame End 1" },
+       { true, 2, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE(2),          "Early Frame End 2" },
+       { true, 3, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE(3),          "Early Frame End 3" },
+       { true, 0, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS(0),          "Early Frame Start 0" },
+       { true, 1, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS(1),          "Early Frame Start 1" },
+       { true, 2, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS(2),          "Early Frame Start 2" },
+       { true, 3, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS(3),          "Early Frame Start 3" },
        /* Non-image data receive events */
-       { false, MIPI_CSIS_INT_SRC_EVEN_BEFORE,         "Non-image data before even frame" },
-       { false, MIPI_CSIS_INT_SRC_EVEN_AFTER,          "Non-image data after even frame" },
-       { false, MIPI_CSIS_INT_SRC_ODD_BEFORE,          "Non-image data before odd frame" },
-       { false, MIPI_CSIS_INT_SRC_ODD_AFTER,           "Non-image data after odd frame" },
+       { false, 0, MIPI_CSIS_INT_SRC_EVEN_BEFORE,              "Non-image data before even frame" },
+       { false, 0, MIPI_CSIS_INT_SRC_EVEN_AFTER,               "Non-image data after even frame" },
+       { false, 0, MIPI_CSIS_INT_SRC_ODD_BEFORE,               "Non-image data before odd frame" },
+       { false, 0, MIPI_CSIS_INT_SRC_ODD_AFTER,                "Non-image data after odd frame" },
        /* Frame start/end */
-       { false, MIPI_CSIS_INT_SRC_FRAME_START,         "Frame Start" },
-       { false, MIPI_CSIS_INT_SRC_FRAME_END,           "Frame End" },
-       { true, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL,  "VSYNC Falling Edge" },
-       { true, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE,  "VSYNC Rising Edge" },
+       { false, 0, MIPI_CSIS_INT_SRC_FRAME_START(0),           "Frame Start 0" },
+       { false, 1, MIPI_CSIS_INT_SRC_FRAME_START(1),           "Frame Start 1" },
+       { false, 2, MIPI_CSIS_INT_SRC_FRAME_START(2),           "Frame Start 2" },
+       { false, 3, MIPI_CSIS_INT_SRC_FRAME_START(3),           "Frame Start 3" },
+       { false, 0, MIPI_CSIS_INT_SRC_FRAME_END(0),             "Frame End 0" },
+       { false, 1, MIPI_CSIS_INT_SRC_FRAME_END(1),             "Frame End 1" },
+       { false, 2, MIPI_CSIS_INT_SRC_FRAME_END(2),             "Frame End 2" },
+       { false, 3, MIPI_CSIS_INT_SRC_FRAME_END(3),             "Frame End 3" },
+       { true, 0, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL(0),    "VSYNC Falling Edge 0" },
+       { true, 1, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL(1),    "VSYNC Falling Edge 1" },
+       { true, 2, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL(2),    "VSYNC Falling Edge 2" },
+       { true, 3, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL(3),    "VSYNC Falling Edge 3" },
+       { true, 0, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE(0),    "VSYNC Rising Edge 0" },
+       { true, 1, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE(1),    "VSYNC Rising Edge 1" },
+       { true, 2, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE(2),    "VSYNC Rising Edge 2" },
+       { true, 3, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE(3),    "VSYNC Rising Edge 3" },
 };
 

Quoted 5 lines

drivers/media/platform/nxp/imx-mipi-csis.c struct mipi_csis_event { · line 304

Quoted 3 lines

drivers/media/platform/nxp/imx-mipi-csis.c +2 -1

-#define MIPI_CSIS_NUM_EVENTS ARRAY_SIZE(mipi_csis_events)
+#define MIPI_CSIS_NUM_EVENTS           ARRAY_SIZE(mipi_csis_events)
+#define MIPI_CSIS_NUM_ERROR_EVENTS     (MIPI_CSIS_NUM_EVENTS - 20)

Why is that (MIPI_CSIS_NUM_EVENTS - 20)? Should that just be 20?

That would then be 38. I don't have a preference.

Quoted 185 lines

The rest looks fine to me.

Quoted 182 lines

drivers/media/platform/nxp/imx-mipi-csis.c +65 -34

 enum mipi_csis_clk {
        MIPI_CSIS_CLK_PCLK,

@@ -299,7 +333,9 @@ struct mipi_csis_device {
        struct clk_bulk_data *clks;
        struct reset_control *mrst;
        struct regulator *mipi_phy_regulator;
+
        const struct mipi_csis_info *info;
+       unsigned int num_channels;
 
        struct v4l2_subdev sd;
        struct media_pad pads[CSIS_PADS_NUM];

@@ -654,8 +690,8 @@ static void mipi_csis_set_params(struct mipi_csis_device *csis,
                        MIPI_CSIS_ISP_SYNC_VSYNC_EINTV(0));
 
        val = mipi_csis_read(csis, MIPI_CSIS_CLK_CTRL);
-       val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC;
-       val |= MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(15);
+       val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC(0);
+       val |= MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL(0, 15);
        val &= ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MASK;
        mipi_csis_write(csis, MIPI_CSIS_CLK_CTRL, val);
 

@@ -672,7 +708,7 @@ static void mipi_csis_set_params(struct mipi_csis_device *csis,
        /* Update the shadow register. */
        val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
        mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL,
-                       val | MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW |
+                       val | MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW(0) |
                        MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL);
 }
 

@@ -763,16 +799,19 @@ static irqreturn_t mipi_csis_irq_handler(int irq, void *dev_id)
 
        /* Update the event/error counters */
        if ((status & MIPI_CSIS_INT_SRC_ERRORS) || csis->debug.enable) {
-               for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) {
+               for (i = 0; i < ARRAY_SIZE(csis->events); i++) {
                        struct mipi_csis_event *event = &csis->events[i];
 
+                       if (event->channel >= csis->num_channels)
+                               continue;
+
                        if ((!event->debug && (status & event->mask)) ||
                            (event->debug && (dbg_status & event->mask)))
                                event->counter++;
                }
        }
 
-       if (status & MIPI_CSIS_INT_SRC_FRAME_START)
+       if (status & MIPI_CSIS_INT_SRC_FRAME_START(0))
                mipi_csis_queue_event_sof(csis);
 
        spin_unlock_irqrestore(&csis->slock, flags);

@@ -849,7 +888,7 @@ static void mipi_csis_clear_counters(struct mipi_csis_device *csis)
 static void mipi_csis_log_counters(struct mipi_csis_device *csis, bool non_errors)
 {
        unsigned int num_events = non_errors ? MIPI_CSIS_NUM_EVENTS
-                               : MIPI_CSIS_NUM_EVENTS - 8;
+                               : MIPI_CSIS_NUM_ERROR_EVENTS;
        unsigned int counters[MIPI_CSIS_NUM_EVENTS];
        unsigned long flags;
        unsigned int i;

@@ -860,45 +899,67 @@ static void mipi_csis_log_counters(struct mipi_csis_device *csis, bool non_error
        spin_unlock_irqrestore(&csis->slock, flags);
 
        for (i = 0; i < num_events; ++i) {
+               const struct mipi_csis_event *event = &csis->events[i];
+
+               if (event->channel >= csis->num_channels)
+                       continue;
+
                if (counters[i] > 0 || csis->debug.enable)
                        dev_info(csis->dev, "%s events: %d\n",
-                                csis->events[i].name,
-                                counters[i]);
+                                event->name, counters[i]);
        }
 }
 
+struct mipi_csis_reg_info {
+       u32 addr;
+       unsigned int offset;
+       const char * const name;
+};
+
+static void mipi_csis_dump_channel_reg(struct mipi_csis_device *csis,
+                                      const struct mipi_csis_reg_info *reg,
+                                      unsigned int channel)
+{
+       dev_info(csis->dev, "%16s%u: 0x%08x\n", reg->name, channel,
+                mipi_csis_read(csis, reg->addr + channel * reg->offset));
+}
+
 static int mipi_csis_dump_regs(struct mipi_csis_device *csis)
 {
-       static const struct {
-               u32 offset;
-               const char * const name;
-       } registers[] = {
-               { MIPI_CSIS_CMN_CTRL, "CMN_CTRL" },
-               { MIPI_CSIS_CLK_CTRL, "CLK_CTRL" },
-               { MIPI_CSIS_INT_MSK, "INT_MSK" },
-               { MIPI_CSIS_DPHY_STATUS, "DPHY_STATUS" },
-               { MIPI_CSIS_DPHY_CMN_CTRL, "DPHY_CMN_CTRL" },
-               { MIPI_CSIS_DPHY_SCTRL_L, "DPHY_SCTRL_L" },
-               { MIPI_CSIS_DPHY_SCTRL_H, "DPHY_SCTRL_H" },
-               { MIPI_CSIS_ISP_CONFIG_CH(0), "ISP_CONFIG_CH0" },
-               { MIPI_CSIS_ISP_RESOL_CH(0), "ISP_RESOL_CH0" },
-               { MIPI_CSIS_SDW_CONFIG_CH(0), "SDW_CONFIG_CH0" },
-               { MIPI_CSIS_SDW_RESOL_CH(0), "SDW_RESOL_CH0" },
-               { MIPI_CSIS_DBG_CTRL, "DBG_CTRL" },
-               { MIPI_CSIS_FRAME_COUNTER_CH(0), "FRAME_COUNTER_CH0" },
+       static const struct mipi_csis_reg_info common_registers[] = {
+               { MIPI_CSIS_CMN_CTRL, 0, "CMN_CTRL" },
+               { MIPI_CSIS_CLK_CTRL, 0, "CLK_CTRL" },
+               { MIPI_CSIS_INT_MSK, 0, "INT_MSK" },
+               { MIPI_CSIS_DPHY_STATUS, 0, "DPHY_STATUS" },
+               { MIPI_CSIS_DPHY_CMN_CTRL, 0, "DPHY_CMN_CTRL" },
+               { MIPI_CSIS_DPHY_SCTRL_L, 0, "DPHY_SCTRL_L" },
+               { MIPI_CSIS_DPHY_SCTRL_H, 0, "DPHY_SCTRL_H" },
+               { MIPI_CSIS_DBG_CTRL, 0, "DBG_CTRL" },
+       };
+       static const struct mipi_csis_reg_info channel_registers[] = {
+               { MIPI_CSIS_ISP_CONFIG_CH(0), 0x10, "ISP_CONFIG_CH" },
+               { MIPI_CSIS_ISP_RESOL_CH(0), 0x10, "ISP_RESOL_CH" },
+               { MIPI_CSIS_SDW_CONFIG_CH(0), 0x10, "SDW_CONFIG_CH" },
+               { MIPI_CSIS_SDW_RESOL_CH(0), 0x10, "SDW_RESOL_CH" },
+               { MIPI_CSIS_FRAME_COUNTER_CH(0), 4, "FRAME_COUNTER_CH" },
        };
-
-       unsigned int i;
-       u32 cfg;
 
        if (!pm_runtime_get_if_in_use(csis->dev))
                return 0;
 
        dev_info(csis->dev, "--- REGISTERS ---\n");
 
-       for (i = 0; i < ARRAY_SIZE(registers); i++) {
-               cfg = mipi_csis_read(csis, registers[i].offset);
-               dev_info(csis->dev, "%17s: 0x%08x\n", registers[i].name, cfg);
+       for (unsigned int i = 0; i < ARRAY_SIZE(common_registers); i++) {
+               const struct mipi_csis_reg_info *reg = &common_registers[i];
+
+               dev_info(csis->dev, "%17s: 0x%08x\n", reg->name,
+                        mipi_csis_read(csis, reg->addr));
+       }
+
+       for (unsigned int chan = 0; chan < csis->num_channels; chan++) {
+               for (unsigned int i = 0; i < ARRAY_SIZE(channel_registers); ++i)
+                       mipi_csis_dump_channel_reg(csis, &channel_registers[i],
+                                                  chan);
        }
 
        pm_runtime_put(csis->dev);

@@ -1421,6 +1482,12 @@ static int mipi_csis_parse_dt(struct mipi_csis_device *csis)
 
        of_property_read_u32(node, "clock-frequency", &csis->clk_frequency);
 
+       csis->num_channels = 1;
+       of_property_read_u32(node, "fsl,num-channels", &csis->num_channels);
+       if (csis->num_channels < 1 || csis->num_channels > MIPI_CSIS_MAX_CHANNELS)
+               return dev_err_probe(csis->dev, -EINVAL,
+                                    "Invalid fsl,num-channels value\n");
+
        return 0;
 }
 

@@ -1444,10 +1511,8 @@ static int mipi_csis_probe(struct platform_device *pdev)
 
        /* Parse DT properties. */
        ret = mipi_csis_parse_dt(csis);
-       if (ret < 0) {
-               dev_err(dev, "Failed to parse device tree: %d\n", ret);
+       if (ret < 0)
                return ret;
-       }
 
        /* Acquire resources. */
        csis->regs = devm_platform_ioremap_resource(pdev, 0);

Signature · 3 lines

Regards,

Laurent Pinchart

Some CSIS instances feature more than one output channel. Update register macros accordingly, parse the number of channels from the device tree, and update register dumps and event counters to log per-channel data.

Support for routing virtual channels and data types to output channels through the subdev internal routing API will come later.

Signed-off-by Laurent Pinchart <[email protected]>

---
Changes since v1:

- Update more per-channel registers
- Update commit message

---
 drivers/media/platform/nxp/imx-mipi-csis.c | 239 +++++++++++++--------
 1 file changed, 152 insertions(+), 87 deletions(-)

drivers/media/platform/nxp/imx-mipi-csis.c +3 -0

+		return dev_err_probe(csis->dev, -EINVAL,
+				     "Invalid fsl,num-channels value\n");
+
 	return 0;
 }

drivers/media/platform/nxp/imx-mipi-csis.c +0 -1

 	/* Acquire resources. */
 	csis->regs = devm_platform_ioremap_resource(pdev, 0);
--

Regards,

Laurent Pinchart

Quoted 17 lines · Laurent Pinchart

Some CSIS instances feature more than one output channel. Update register macros accordingly, parse the number of channels from the device tree, and update register dumps and event counters to log per-channel data.

Support for routing virtual channels and data types to output channels through the subdev internal routing API will come later.

Signed-off-by Laurent Pinchart <[email protected]>

---
Changes since v1:

- Update more per-channel registers
- Update commit message

---
 drivers/media/platform/nxp/imx-mipi-csis.c | 239 +++++++++++++--------
 1 file changed, 152 insertions(+), 87 deletions(-)

...

Quoted 8 lines

drivers/media/platform/nxp/imx-mipi-csis.c +3 -0

+		return dev_err_probe(csis->dev, -EINVAL,
+				     "Invalid fsl,num-channels value\n");
+
 	return 0;
 }

@@ -1444,10 +1511,8 @@ static int mipi_csis_probe(struct platform_device *pdev)
 

drivers/media/platform/nxp/imx-mipi-csis.c static int mipi_csis_probe(struct platform_device *pdev) · line 1450

Quoted 7 lines

drivers/media/platform/nxp/imx-mipi-csis.c +1 -3

 	/* Parse DT properties. */
 	ret = mipi_csis_parse_dt(csis);
-	if (ret < 0) {
-		dev_err(dev, "Failed to parse device tree: %d\n", ret);
+	if (ret < 0)
 		return ret;
-	}

I think this change is not belong to this patch.

Quoted 3 lines

drivers/media/platform/nxp/imx-mipi-csis.c +0 -0

 	/* Acquire resources. */
 	csis->regs = devm_platform_ioremap_resource(pdev, 0);

The CSI-2 receivers in the i.MX8MP have 3 output channels. Specify this in the device tree, to enable support for more than one channel.

Signed-off-by Laurent Pinchart <[email protected]>

Reviewed-by Frank Li <[email protected]>

---
 arch/arm64/boot/dts/freescale/imx8mp.dtsi | 2 ++
 1 file changed, 2 insertions(+)

arch/arm64/boot/dts/freescale/imx8mp.dtsi +2 -0

index bb24dba7338e..1e52840078df 100644
@@ -1764,6 +1764,7 @@ mipi_csi_0: csi@32e40000 {
 				assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_250M>,
 							 <&clk IMX8MP_CLK_24M>;
 				power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>;
+				fsl,num-channels = <3>;
 				status = "disabled";
 
 				ports {

@@ -1799,6 +1800,7 @@ mipi_csi_1: csi@32e50000 {
 				assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_250M>,
 							 <&clk IMX8MP_CLK_24M>;
 				power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>;
+				fsl,num-channels = <3>;
 				status = "disabled";
 
 				ports {

The CSI-2 receivers in the i.MX8MP have 3 output channels. Specify this in the device tree, to enable support for more than one channel.

Signed-off-by Laurent Pinchart <[email protected]>

Reviewed-by Frank Li <[email protected]>