arm64: dts: freescale: imx8mn-var-som: Align SOM and Symphony DTSs
Subsystems (2)
v2 cover arm64: dts: freescale: imx8mn-var-som: Align SOM and Symphony DTSs
This series aligns the i.MX8MN VAR-SOM and VAR-SOM Symphony device trees with the latest hardware revisions.
As the i.MX8MN device tree hierarchy closely mirrors the i.MX8MM one, this series applies the same alignment already accepted for the i.MX8MM platform, ensuring a consistent hardware description across both families.
The update consolidates the device tree descriptions to better reflect the actual hardware partitioning between the SOM and the carrier board. Nodes describing peripherals physically present on the SOM are kept in the SOM dtsi, while carrier-specific components are described in the corresponding carrier dts.
The changes were tested on the latest VAR-SOM and Symphony hardware revision.
v1->v2:
- Update all the carrier boards and not only the symphony
- Fixed commit message for eth
- Fixed I3C to I2C3 in codec commit message
Stefano Radaelli (15):
arm64: dts: freescale: imx8mn-var-som: Move UART4 description to
Symphony
arm64: dts: freescale: imx8mn-var-som: move uSD support to carrier
boards
arm64: dts: freescale: imx8mn-var-som: Align fsl,pins tables
arm64: dts: freescale: imx8mn-var-som: Update FEC support with
MaxLinear PHY
arm64: dts: freescale: imx8mn-var-som: Add support for WM8904 audio
codec
arm64: dts: freescale: imx8mn-var-som: Add MCP251xFD CAN controller
arm64: dts: freescale: imx8mn-var-som: Rework WiFi/BT and add legacy
dts
arm64: dts: freescale: imx8mn-var-som: drop duplicate USB OTG node
arm64: dts: freescale: imx8mn-var-som: enable FlexSPI interface
arm64: dts: imx8mn-var-som-symphony: Add TPM2 support
arm64: dts: imx8mn-var-som-symphony: Enable I2C4
arm64: dts: imx8mn-var-som-symphony: add wakeup sources
arm64: dts: imx8mn-var-som-symphony: keep RGB_SEL low
arm64: dts: imx8mn-var-som-symphony: enable PWM1
arm64: dts: imx8mn-var-som-symphony: Disable internal RTC
arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx8mn-rve-gateway.dts | 48 ++- .../imx8mn-var-som-symphony-legacy.dts | 19 + .../dts/freescale/imx8mn-var-som-symphony.dts | 162 +++++++- .../imx8mn-var-som-wifi-brcm-legacy.dtsi | 19 + .../imx8mn-var-som-wifi-bt-iw61x.dtsi | 46 +++ .../boot/dts/freescale/imx8mn-var-som.dtsi | 366 ++++++++++-------- 7 files changed, 500 insertions(+), 161 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony-legacy.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-var-som-wifi-brcm-legacy.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-var-som-wifi-bt-iw61x.dtsi
base-commit: d0c222c2e2ce577d801bdf129dc6c078f29e22df
Signature · 1 line
2.47.3
PATCH v2 1/15 arm64: dts: freescale: imx8mn-var-som: Move UART4 description to Symphony
From: Stefano Radaelli <[email protected]>
The VAR-SOM-MX8MN module does not provide an onboard debug console. UART4 is routed and exposed only on the Symphony carrier board, while custom carrier designs may choose to expose a different UART.
Move the UART4 node from the SOM device tree to the imx8mn-var-som-symphony.dts, keeping the SOM dtsi limited to hardware present on the module itself.
---v1->v2:
-
.../dts/freescale/imx8mn-var-som-symphony.dts | 18 ++++++++++++++++++ .../boot/dts/freescale/imx8mn-var-som.dtsi | 18 ------------------ 2 files changed, 18 insertions(+), 18 deletions(-)
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +18 -0
@@ -15,6 +15,10 @@ / { model = "Variscite VAR-SOM-MX8MN Symphony evaluation board"; compatible = "variscite,var-som-mx8mn-symphony", "variscite,var-som-mx8mn", "fsl,imx8mn"; + chosen { + stdout-path = &uart4; + }; + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { compatible = "regulator-fixed"; pinctrl-names = "default";
@@ -171,6 +175,13 @@ &uart3 { status = "okay"; }; +/* Console */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + &usbotg1 { dr_mode = "otg"; hnp-disable;
@@ -234,4 +245,11 @@ MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 >; }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 + MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 + >; + }; };
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +0 -18
@@ -11,10 +11,6 @@ / { model = "Variscite VAR-SOM-MX8MN module"; compatible = "variscite,var-som-mx8mn", "fsl,imx8mn"; - chosen { - stdout-path = &uart4; - }; - memory@40000000 { device_type = "memory"; reg = <0x0 0x40000000 0 0x40000000>;
@@ -274,13 +270,6 @@ &uart2 { status = "okay"; }; -/* Console */ -&uart4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - &usbotg1 { dr_mode = "otg"; usb-role-switch;
@@ -432,13 +421,6 @@ MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 >; }; - pinctrl_uart4: uart4grp { - fsl,pins = < - MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140 - MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140 - >; - }; - pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
Signature · 1 line
2.47.3
Re: [PATCH v2 01/15] arm64: dts: freescale: imx8mn-var-som: Move UART4 description to Symphony
Quoted 11 lines · Stefano Radaelli
From: Stefano Radaelli <[email protected]>
The VAR-SOM-MX8MN module does not provide an onboard debug console. UART4 is routed and exposed only on the Symphony carrier board, while custom carrier designs may choose to expose a different UART.
Move the UART4 node from the SOM device tree to the
imx8mn-var-som-symphony.dts, keeping the SOM dtsi limited to hardware present on the module itself.Signed-off-by Stefano Radaelli <[email protected]>
PATCH v2 2/15 arm64: dts: freescale: imx8mn-var-som: move uSD support to carrier boards
In reply to Stefano RadaelliFrom: Stefano Radaelli <[email protected]>
The VAR-SOM-MX8MN module does not provide an onboard SD card slot. USDHC2 is routed to the SD card slot on the carrier boards.
Move the USDHC2 node and pinctrl configuration from the SOM device tree to imx8mn-var-som-symphony.dts and imx8mn-rve-gateway.dts, keeping the SOM dtsi limited to hardware present on the module itself.
Add the required off-on-delay-us property for the USDHC2 regulator on the Symphony carrier board.
---v1->v2:
- Update all the carrier boards and not only the symphony
.../boot/dts/freescale/imx8mn-rve-gateway.dts | 47 ++++++++++++++- .../dts/freescale/imx8mn-var-som-symphony.dts | 57 +++++++++++++++++++ .../boot/dts/freescale/imx8mn-var-som.dtsi | 56 ------------------ 3 files changed, 102 insertions(+), 58 deletions(-)
arch/arm64/boot/dts/freescale/imx8mn-rve-gateway.dts +45 -2
@@ -207,8 +207,16 @@ &usbotg1 { /* SD interface on expansion connector. */ &usdhc2 { - vmmc-supply = <®_3p3v>; + assigned-clocks = <&clk IMX8MN_CLK_USDHC2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; cd-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + bus-width = <4>; + vmmc-supply = <®_3p3v>; + status = "okay"; }; &iomuxc {
@@ -276,10 +284,45 @@ MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x00000156 /* B */ >; }; - /* Override Card Detect function GPIO value (GPIO1_IO10) from SOM: */ pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x41 >; }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; };
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +57 -0
73 lines not on this page · raw message
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +0 -56
68 lines not on this page · raw message
Signature · 1 line
2.47.3
Re: [PATCH v2 02/15] arm64: dts: freescale: imx8mn-var-som: move uSD support to carrier boards
Quoted 5 lines · Stefano Radaelli
From: Stefano Radaelli <[email protected]>
The VAR-SOM-MX8MN module does not provide an onboard SD card slot. USDHC2 is routed to the SD card slot on the carrier boards.
Quoted 8 lines
Move the USDHC2 node and pinctrl configuration from the SOM device tree to
imx8mn-var-som-symphony.dtsandimx8mn-rve-gateway.dts, keeping the SOM dtsi limited to hardware present on the module itself.Add the required off-on-delay-us property for the USDHC2 regulator on the Symphony carrier board.
Signed-off-by Stefano Radaelli <[email protected]>
PATCH v2 3/15 arm64: dts: freescale: imx8mn-var-som: Align fsl,pins tables
In reply to Stefano RadaelliFrom: Stefano Radaelli <[email protected]>
Reformat the fsl,pins tables in the i.MX8MN VAR-SOM device tree to use consistent column alignment across all pinctrl groups.
Align the entries to match the formatting already used in the pinctrl_fec1 group, which contains the longest pin definitions, for improved readability and consistency.
No functional changes intended.
---v1->v2:
-
.../boot/dts/freescale/imx8mn-var-som.dtsi | 126 +++++++++--------- 1 file changed, 63 insertions(+), 63 deletions(-)
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +63 -63
@@ -368,129 +368,129 @@ MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x120 pinctrl_i2c1: i2c1grp { fsl,pins = < - MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 >; }; pinctrl_i2c3: i2c3grp { fsl,pins = < - MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 >; }; pinctrl_pmic: pmicirqgrp { fsl,pins = < - MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x141 + MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x141 >; }; pinctrl_reg_eth_phy: regethphygrp { fsl,pins = < - MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41 + MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41 >; }; pinctrl_restouch: restouchgrp { fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 + MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 >; }; pinctrl_uart2: uart2grp { fsl,pins = < - MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 - MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 - MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 - MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 + MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 + MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 + MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 + MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 >; }; pinctrl_usdhc1: usdhc1grp { fsl,pins = < - MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 - MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 - MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 - MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 - MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 - MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 >; }; pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { fsl,pins = < - MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 - MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 - MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 - MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 - MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 - MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 >; }; pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { fsl,pins = < - MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 - MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 - MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 - MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 - MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 - MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 >; }; pinctrl_usdhc3: usdhc3grp { fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 >; }; pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 >; }; pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { fsl,pins = < - MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 >; }; pinctrl_wdog: wdoggrp { fsl,pins = < - MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 + MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 >; }; };
Signature · 1 line
2.47.3
PATCH v2 4/15 arm64: dts: freescale: imx8mn-var-som: Update FEC support with MaxLinear PHY
In reply to Stefano RadaelliFrom: Stefano Radaelli <[email protected]>
Update the FEC Ethernet controller on the i.MX8MN VAR-SOM to match the latest SOM hardware revision using the integrated MaxLinear MXL86110 PHY.
Add the PHY VDDIO supply regulator and adjust reset timings.
The PHY LED signals originate on the SOM, but the actual LEDs are part of the carrier implementation (RJ45 connector). Move the LED configuration to the Symphony carrier device tree, matching the evaluation board LED wiring.
Wake-on-LAN via magic packet is not supported at the VAR-SOM level and is therefore not enabled in the SOM device tree nor in the official evaluation carrier board configuration (symphony).
Designs requiring WoL support may enable it in their own carrier-specific device trees if properly integrated at the hardware level.
---v1->v2:
- Fixed commit message
.../dts/freescale/imx8mn-var-som-symphony.dts | 20 ++++++++++++++++++- .../boot/dts/freescale/imx8mn-var-som.dtsi | 20 ++++++++++--------- 2 files changed, 30 insertions(+), 10 deletions(-)
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +19 -1
@@ -8,6 +8,7 @@ /dts-v1/; +#include <dt-bindings/leds/common.h> #include <dt-bindings/usb/pd.h> #include "imx8mn-var-som.dtsi"
@@ -74,7 +75,24 @@ reg_per_3v3: regulator-peripheral-3v3 { }; ðphy { - reset-gpios = <&pca9534 5 GPIO_ACTIVE_HIGH>; + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = <LED_COLOR_ID_YELLOW>; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + + led@1 { + reg = <1>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + }; }; &i2c2 {
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +11 -9
@@ -35,6 +35,13 @@ reg_3v3_fixed: regulator-3v3-fixed { regulator-max-microvolt = <3300000>; regulator-always-on; }; + + reg_phy_vddio: regulator-phy-vddio { + compatible = "regulator-fixed"; + regulator-name = "vddio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; }; &A53_0 {
@@ -96,24 +103,19 @@ &fec1 { phy-mode = "rgmii"; phy-handle = <ðphy>; phy-supply = <®_eth_phy>; - fsl,magic-packet; status = "okay"; mdio { #address-cells = <1>; #size-cells = <0>; - ethphy: ethernet-phy@4 { /* AR8033 or ADIN1300 */ + ethphy: ethernet-phy@4 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <4>; reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; - /* - * Deassert delay: - * ADIN1300 requires 5ms. - * AR8033 requires 1ms. - */ - reset-deassert-us = <20000>; + reset-deassert-us = <100000>; + vddio-supply = <®_phy_vddio>; }; }; };
@@ -342,7 +344,7 @@ MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x159 + MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 >; };
Signature · 1 line
2.47.3
Re: [PATCH v2 04/15] arm64: dts: freescale: imx8mn-var-som: Update FEC support with MaxLinear PHY
Quoted 12 lines · Stefano Radaelli
From: Stefano Radaelli <[email protected]>
Update the FEC Ethernet controller on the i.MX8MN VAR-SOM to match the latest SOM hardware revision using the integrated MaxLinear MXL86110 PHY.
Add the PHY VDDIO supply regulator and adjust reset timings.
The PHY LED signals originate on the SOM, but the actual LEDs are part of the carrier implementation (RJ45 connector). Move the LED configuration to the Symphony carrier device tree, matching the evaluation board LED wiring.
Quoted 7 lines
Wake-on-LAN via magic packet is not supported at the VAR-SOM level and is therefore not enabled in the SOM device tree nor in the official evaluation carrier board configuration (symphony).
Designs requiring WoL support may enable it in their own carrier-specific device trees if properly integrated at the hardware level.Signed-off-by Stefano Radaelli <[email protected]>
Re: [PATCH v2 04/15] arm64: dts: freescale: imx8mn-var-som: Update FEC support with MaxLinear PHY
In reply to Stefano RadaelliQuoted 40 lines · Stefano Radaelli
From: Stefano Radaelli <[email protected]>
Update the FEC Ethernet controller on the i.MX8MN VAR-SOM to match the latest SOM hardware revision using the integrated MaxLinear MXL86110 PHY.
Add the PHY VDDIO supply regulator and adjust reset timings.
The PHY LED signals originate on the SOM, but the actual LEDs are part of the carrier implementation (RJ45 connector). Move the LED configuration to the Symphony carrier device tree, matching the evaluation board LED wiring.
Wake-on-LAN via magic packet is not supported at the VAR-SOM level and is therefore not enabled in the SOM device tree nor in the official evaluation carrier board configuration (symphony).
Designs requiring WoL support may enable it in their own carrier-specific device trees if properly integrated at the hardware level.Signed-off-by Stefano Radaelli <[email protected]>---
v1->v2:
- Fixed commit message.../dts/freescale/imx8mn-var-som-symphony.dts | 20 ++++++++++++++++++- .../boot/dts/freescale/imx8mn-var-som.dtsi | 20 ++++++++++--------- 2 files changed, 30 insertions(+), 10 deletions(-)arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +1
-0@@ -8,6 +8,7 @@ /dts-v1/; +#include <dt-bindings/leds/common.h> #include <dt-bindings/usb/pd.h> #include "imx8mn-var-som.dtsi"
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts reg_per_3v3: regulator-peripheral-3v3 { · line 77
Quoted 4 lines
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +0
-1@@ -74,7 +75,24 @@ reg_per_3v3: regulator-peripheral-3v3 { }; ðphy { - reset-gpios = <&pca9534 5 GPIO_ACTIVE_HIGH>;
why remove this reset-gpios?
Frank
Quoted 80 lines
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +18
-0+ leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = <LED_COLOR_ID_YELLOW>; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + + led@1 { + reg = <1>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + }; }; &i2c2 {arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +11
-10@@ -35,6 +35,13 @@ reg_3v3_fixed: regulator-3v3-fixed { regulator-max-microvolt = <3300000>; regulator-always-on; }; + + reg_phy_vddio: regulator-phy-vddio { + compatible = "regulator-fixed"; + regulator-name = "vddio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; }; &A53_0 {@@ -96,24 +103,19 @@ &fec1 { phy-mode = "rgmii"; phy-handle = <ðphy>; phy-supply = <®_eth_phy>; - fsl,magic-packet; status = "okay"; mdio { #address-cells = <1>; #size-cells = <0>; - ethphy: ethernet-phy@4 { /* AR8033 or ADIN1300 */ + ethphy: ethernet-phy@4 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <4>; reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; - /* - * Deassert delay: - * ADIN1300 requires 5ms. - * AR8033 requires 1ms. - */ - reset-deassert-us = <20000>; + reset-deassert-us = <100000>; + vddio-supply = <®_phy_vddio>; }; }; };@@ -342,7 +344,7 @@ MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x159 + MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 >; }; --2.47.3
PATCH v2 5/15 arm64: dts: freescale: imx8mn-var-som: Add support for WM8904 audio codec
In reply to Stefano RadaelliFrom: Stefano Radaelli <[email protected]>
The VAR-SOM-MX8MN can integrate the WM8904, a high-performance ultra-low-power stereo codec optimized for portable audio applications.
Add the WM8904 device to the appropriate I2C bus, enable the SAI peripheral, and introduce the sound node to expose the sound card to the system.
Add I2C3 recovery gpio properties.
---v1->v2:
- Fixed I3C to I2C3 in commit message
.../boot/dts/freescale/imx8mn-var-som.dtsi | 98 ++++++++++++++++++- 1 file changed, 95 insertions(+), 3 deletions(-)
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +95 -3
@@ -16,6 +16,14 @@ memory@40000000 { reg = <0x0 0x40000000 0 0x40000000>; }; + reg_audio_supply: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "wm8904-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + reg_eth_phy: regulator-eth-phy { compatible = "regulator-fixed"; pinctrl-names = "default";
@@ -42,6 +50,34 @@ reg_phy_vddio: regulator-phy-vddio { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "wm8904-audio"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "IN1L", "Microphone Jack", + "IN1R", "Microphone Jack"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&wm8904>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai5>; + }; + }; }; &A53_0 {
@@ -246,18 +282,55 @@ eeprom_som: eeprom@52 { &i2c3 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; - /* TODO: configure audio, as of now just put a placeholder */ wm8904: codec@1a { compatible = "wlf,wm8904"; reg = <0x1a>; - status = "disabled"; + #sound-dai-cells = <0>; + clocks = <&clk IMX8MN_CLK_SAI5_ROOT>; + clock-names = "mclk"; + AVDD-supply = <&ldo5_reg>; + CPVDD-supply = <&ldo5_reg>; + DBVDD-supply = <®_audio_supply>; + DCVDD-supply = <&ldo5_reg>; + MICVDD-supply = <&ldo5_reg>; + wlf,drc-cfg-names = "default", "peaklimiter", "tradition", + "soft", "music"; + /* + * Config registers per name, respectively: + * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 + * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 + * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1 + * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1 + * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1 + */ + wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, + /bits/ 16 <0x04af 0x324b 0x0010 0x0408>, + /bits/ 16 <0x04af 0x324b 0x0028 0x0704>, + /bits/ 16 <0x04af 0x324b 0x0018 0x078c>, + /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; + /* GPIO1 = DMIC_CLK, don't touch others */ + wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; }; }; +&sai5 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + assigned-clocks = <&clk IMX8MN_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <1536000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; };
@@ -375,6 +448,13 @@ MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 >; }; + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 + MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
@@ -400,6 +480,18 @@ MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 >; }; + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MN_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 + MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 + MX8MN_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 + MX8MN_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 + MX8MN_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6 + MX8MN_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 + MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
Signature · 1 line
2.47.3
[email protected]
AI reviewRe: [PATCH v2 05/15] arm64: dts: freescale: imx8mn-var-som: Add support for WM8904 audio codec
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Medium] The `simple-audio-card,routing` property maps `Microphone Jack` to `IN1L` and `IN1R` but omits…
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The simple-audio-card,routing property maps Microphone Jack to IN1L and IN1R but omits the connection to the MICBIAS supply, which will leave standard electret microphones unpowered. --
commit 78e4da0f71f2e53ae4312cbe5ceecb0f6f2345db
Author: Stefano Radaelli <[email protected]>
arm64: dts: freescale: imx8mn-var-som: Add support for WM8904 audio codec
This commit adds support for the WM8904 audio codec on the VAR-SOM-MX8MN board. It configures the device on the I2C bus, enables the SAI peripheral, and adds a simple-audio-card sound node to expose the sound card to the system.
Quoted 4 lines
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +0
-0
[ ... ]
Quoted 9 lines
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +5
-0@@ -42,6 +50,34 @@ reg_phy_vddio: regulator-phy-vddio { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s";
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi reg_phy_vddio: regulator-phy-vddio { · line 67
Quoted 10 lines
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +10
-0+ simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "wm8904-audio"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "IN1L", "Microphone Jack", + "IN1R", "Microphone Jack";
[Severity: Medium]
Will standard electret microphones remain unpowered with this routing?
The routing maps "Microphone Jack" to "IN1L" and "IN1R", but omits a link to the "MICBIAS" supply (e.g., "Microphone Jack", "MICBIAS"). Because "MICBIAS" is defined as a DAPM supply widget in the codec driver, DAPM will not enable it unless it has an explicit routing link connecting it to the active audio path. This could leave the microphone without its required bias voltage when recording.
Quoted 8 lines
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +8
-0+ simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&wm8904>; + };
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=5
Re: [PATCH v2 05/15] arm64: dts: freescale: imx8mn-var-som: Add support for WM8904 audio codec
Quoted 42 lines · On Mon, Jul 06, 2026 at 10:09:47AM +0000, [email protected] wrote:
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Thesimple-audio-card,routingproperty mapsMicrophone JacktoIN1LandIN1Rbut omits the connection to theMICBIASsupply, which will leave standard electret microphones unpowered. --commit
78e4da0f71f2e53ae4312cbe5ceecb0f6f2345db
Author: Stefano Radaelli <[email protected]>arm64: dts: freescale: imx8mn-var-som: Add support for WM8904 audio codec
This commit adds support for the WM8904 audio codec on the VAR-SOM-MX8MN board. It configures the device on the I2C bus, enables the SAI peripheral, and adds a simple-audio-card sound node to expose the sound card to the system.
Quoted 4 lines
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +0
-0[ ... ]
Quoted 9 lines
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +5
-0@@ -42,6 +50,34 @@ reg_phy_vddio: regulator-phy-vddio { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s";arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi reg_phy_vddio: regulator-phy-vddio { · line 67
Quoted 10 lines
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +10
-0+ simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "wm8904-audio"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "IN1L", "Microphone Jack", + "IN1R", "Microphone Jack";[Severity: Medium]
Will standard electret microphones remain unpowered with this routing?
Quoted 6 lines
The routing maps "Microphone Jack" to "IN1L" and "IN1R", but omits a link to the "MICBIAS" supply (e.g., "Microphone Jack", "MICBIAS"). Because "MICBIAS" is defined as a DAPM supply widget in the codec driver, DAPM will not enable it unless it has an explicit routing link connecting it to the active audio path. This could leave the microphone without its required bias voltage when recording.
Is this true?
Frank
Quoted 12 lines
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi reg_phy_vddio: regulator-phy-vddio { · line 75
Quoted 9 lines
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +8
-0+ simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&wm8904>; + };--
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=5
Re: [PATCH v2 05/15] arm64: dts: freescale: imx8mn-var-som: Add support for WM8904 audio codec
Hi Frank,
Quoted 50 lines · Frank Li
Quoted 42 lines · On Mon, Jul 06, 2026 at 10:09:47AM +0000, [email protected] wrote:
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Thesimple-audio-card,routingproperty mapsMicrophone JacktoIN1LandIN1Rbut omits the connection to theMICBIASsupply, which will leave standard electret microphones unpowered. --commit
78e4da0f71f2e53ae4312cbe5ceecb0f6f2345db
Author: Stefano Radaelli <[email protected]>arm64: dts: freescale: imx8mn-var-som: Add support for WM8904 audio codec
This commit adds support for the WM8904 audio codec on the VAR-SOM-MX8MN board. It configures the device on the I2C bus, enables the SAI peripheral, and adds a simple-audio-card sound node to expose the sound card to the system.
Quoted 4 lines
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +0
-0[ ... ]
Quoted 9 lines
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +5
-0@@ -42,6 +50,34 @@ reg_phy_vddio: regulator-phy-vddio { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s";arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi reg_phy_vddio: regulator-phy-vddio { · line 67
Quoted 10 lines
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +10
-0+ simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "wm8904-audio"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "IN1L", "Microphone Jack", + "IN1R", "Microphone Jack";[Severity: Medium]
Will standard electret microphones remain unpowered with this routing?Quoted 6 lines
The routing maps "Microphone Jack" to "IN1L" and "IN1R", but omits a link to the "MICBIAS" supply (e.g., "Microphone Jack", "MICBIAS"). Because "MICBIAS" is defined as a DAPM supply widget in the codec driver, DAPM will not enable it unless it has an explicit routing link connecting it to the active audio path. This could leave the microphone without its required bias voltage when recording.
Quoted 4 lines
Is this true?
Frank
Thanks for pointing this out.
This audio routing is not new for this board. It follows the same WM8904 routing that we have been using on our other platforms for quite some time, and we are not aware of any reported issues related to the analogue microphone path.
If adding an explicit route to MICBIAS is indeed required by the codec driver, then this would not be specific to this board but would potentially apply to all of our WM8904-based platforms.
I'd prefer not to introduce this functional change as part of this DTS alignment series without validating it across all affected platforms. If needed, we can investigate the MICBIAS routing separately and submit a dedicated fix covering all WM8904-based boards.
Thanks,
Stefano
Re: [PATCH v2 05/15] arm64: dts: freescale: imx8mn-var-som: Add support for WM8904 audio codec
Quoted 65 lines · Stefano Radaelli
Hi Frank,
Quoted 50 lines · Frank Li
Quoted 42 lines · On Mon, Jul 06, 2026 at 10:09:47AM +0000, [email protected] wrote:
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Thesimple-audio-card,routingproperty mapsMicrophone JacktoIN1LandIN1Rbut omits the connection to theMICBIASsupply, which will leave standard electret microphones unpowered. --commit
78e4da0f71f2e53ae4312cbe5ceecb0f6f2345db
Author: Stefano Radaelli <[email protected]>arm64: dts: freescale: imx8mn-var-som: Add support for WM8904 audio codec
This commit adds support for the WM8904 audio codec on the VAR-SOM-MX8MN board. It configures the device on the I2C bus, enables the SAI peripheral, and adds a simple-audio-card sound node to expose the sound card to the system.
Quoted 4 lines
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +0
-0[ ... ]
Quoted 9 lines
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +5
-0@@ -42,6 +50,34 @@ reg_phy_vddio: regulator-phy-vddio { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s";arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi reg_phy_vddio: regulator-phy-vddio { · line 67
Quoted 10 lines
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +10
-0+ simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "wm8904-audio"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "IN1L", "Microphone Jack", + "IN1R", "Microphone Jack";[Severity: Medium]
Will standard electret microphones remain unpowered with this routing?Quoted 6 lines
The routing maps "Microphone Jack" to "IN1L" and "IN1R", but omits a link to the "MICBIAS" supply (e.g., "Microphone Jack", "MICBIAS"). Because "MICBIAS" is defined as a DAPM supply widget in the codec driver, DAPM will not enable it unless it has an explicit routing link connecting it to the active audio path. This could leave the microphone without its required bias voltage when recording.
Quoted 4 lines
Is this true?
Frank
Thanks for pointing this out.
This audio routing is not new for this board. It follows the same WM8904 routing that we have been using on our other platforms for quite some time, and we are not aware of any reported issues related to the analogue microphone path.
Quoted 8 lines
If adding an explicit route to MICBIAS is indeed required by the codec driver, then this would not be specific to this board but would potentially apply to all of our WM8904-based platforms.
I'd prefer not to introduce this functional change as part of this DTS alignment series without validating it across all affected platforms. If needed, we can investigate the MICBIAS routing separately and submit a dedicated fix covering all WM8904-based boards.
Okay, thanks.
Frank
Quoted 3 lines
Thanks,
Stefano
Re: [PATCH v2 05/15] arm64: dts: freescale: imx8mn-var-som: Add support for WM8904 audio codec
Hi Frank,
Quoted 12 lines · Frank Li
Quoted 12 lines
Thanks for pointing this out.
This audio routing is not new for this board. It follows the same WM8904 routing that we have been using on our other platforms for quite some time, and we are not aware of any reported issues related to the analogue microphone path.
If adding an explicit route to MICBIAS is indeed required by the codec driver, then this would not be specific to this board but would potentially apply to all of our WM8904-based platforms.
Quoted 12 lines
Quoted 4 lines
I'd prefer not to introduce this functional change as part of this DTS alignment series without validating it across all affected platforms. If needed, we can investigate the MICBIAS routing separately and submit a dedicated fix covering all WM8904-based boards.
Okay, thanks.
Frank
Quoted 3 lines
Thanks,
Stefano
Hi Frank,
Just for my understanding, is this patch series going to be applied or are there any further changes you would like me to make?
Thank you,
Best Regards,
Stefano
PATCH v2 6/15 arm64: dts: freescale: imx8mn-var-som: Add MCP251xFD CAN controller
In reply to Stefano RadaelliFrom: Stefano Radaelli <[email protected]>
Add support for the Microchip MCP251xFD CAN-FD controller connected to the SPI bus on the i.MX8MN VAR-SOM.
The controller uses a 40 MHz external oscillator and requires an interrupt line and a dedicated RX interrupt GPIO.
Add the fixed clock, the MCP251xFD device node with the required properties, and the corresponding pinctrl configuration.
---v1->v2:
-
.../boot/dts/freescale/imx8mn-var-som.dtsi | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+)
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +27 -0
@@ -11,6 +11,13 @@ / { model = "Variscite VAR-SOM-MX8MN module"; compatible = "variscite,var-som-mx8mn", "fsl,imx8mn"; + clk40m: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + clock-output-names = "can_osc"; + }; + memory@40000000 { device_type = "memory"; reg = <0x0 0x40000000 0 0x40000000>;
@@ -130,6 +137,19 @@ touchscreen@0 { ti,keep-vref-on; wakeup-source; }; + + /* CAN controller */ + can0: can@1 { + compatible = "microchip,mcp251xfd"; + reg = <1>; + clocks = <&clk40m>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can>; + interrupt-parent = <&gpio1>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <20000000>; + microchip,rx-int-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + }; }; &fec1 {
@@ -391,6 +411,13 @@ &wdog1 { }; &iomuxc { + pinctrl_can: cangrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x1c0 + MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x16 + >; + }; + pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13
Signature · 1 line
2.47.3
Re: [PATCH v2 06/15] arm64: dts: freescale: imx8mn-var-som: Add MCP251xFD CAN controller
Quoted 5 lines · Stefano Radaelli
From: Stefano Radaelli <[email protected]>
Add support for the Microchip MCP251xFD CAN-FD controller connected to the SPI bus on the i.MX8MN VAR-SOM.
Quoted 8 lines
The controller uses a 40 MHz external oscillator and requires an interrupt line and a dedicated RX interrupt GPIO.
Add the fixed clock, the MCP251xFD device node with the required properties, and the corresponding pinctrl configuration.
Signed-off-by Stefano Radaelli <[email protected]>---
PATCH v2 7/15 arm64: dts: freescale: imx8mn-var-som: Rework WiFi/BT and add legacy dts
In reply to Stefano RadaelliFrom: Stefano Radaelli <[email protected]>
The VAR-SOM-MX8MN currently integrates the NXP IW61x wireless module, providing WiFi over SDIO and Bluetooth over UART.
Move the wireless module configuration out of the base imx8mn-var-som.dtsi and provide dedicated variant includes. The IW61x configuration is moved to imx8mn-var-som-wifi-bt-iw61x.dtsi and used by the Symphony evaluation board device tree.
A separate imx8mn-var-som-wifi-brcm-legacy.dtsi include is added to keep the configuration for the legacy Broadcom SDIO WiFi module used on earlier SOM revisions.
To preserve compatibility with older SOM revisions, add a separate imx8mn-var-som-symphony-legacy.dtb, which disables the IW61x setup and applies the Broadcom-specific configuration.
The Broadcom-based SOM revision is no longer in production, but support is kept for existing users.
This keeps the VAR-SOM-MX8MN support aligned with the existing VAR-SOM-MX8MM implementation.
---v1->v2:
-
arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx8mn-rve-gateway.dts | 1 + .../imx8mn-var-som-symphony-legacy.dts | 19 ++++++++ .../dts/freescale/imx8mn-var-som-symphony.dts | 1 + .../imx8mn-var-som-wifi-brcm-legacy.dtsi | 19 ++++++++ .../imx8mn-var-som-wifi-bt-iw61x.dtsi | 46 +++++++++++++++++++ .../boot/dts/freescale/imx8mn-var-som.dtsi | 8 ---- 7 files changed, 87 insertions(+), 8 deletions(-) create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony-legacy.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-var-som-wifi-brcm-legacy.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-var-som-wifi-bt-iw61x.dtsi
arch/arm64/boot/dts/freescale/Makefile +1 -0
@@ -206,6 +206,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-solidsense-n8-compact.dtb DTC_FLAGS_imx8mn-solidsense-n8-compact += -@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony-legacy.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb imx8mn-vhip4-evalboard-v1-overlay-ksz8794-dtbs := imx8mn-vhip4-evalboard-v1.dtb \
arch/arm64/boot/dts/freescale/imx8mn-rve-gateway.dts +1 -0
@@ -7,6 +7,7 @@ #include <dt-bindings/usb/pd.h> #include "imx8mn-var-som.dtsi" +#include "imx8mn-var-som-wifi-brcm-legacy.dtsi" / { model = "RVE gateway";
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony-legacy.dts new file +19 -0
@@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2026 Variscite Ltd. + */ + +#include "imx8mn-var-som-symphony.dts" +#include "imx8mn-var-som-wifi-brcm-legacy.dtsi" + +&bluetooth_iw61x { + status = "disabled"; +}; + +&iw61x_pwrseq { + status = "disabled"; +}; + +&usdhc1 { + /delete-property/ mmc-pwrseq; +};
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +1 -0
@@ -11,6 +11,7 @@ #include <dt-bindings/leds/common.h> #include <dt-bindings/usb/pd.h> #include "imx8mn-var-som.dtsi" +#include "imx8mn-var-som-wifi-bt-iw61x.dtsi" / { model = "Variscite VAR-SOM-MX8MN Symphony evaluation board";
arch/arm64/boot/dts/freescale/imx8mn-var-som-wifi-brcm-legacy.dtsi new file +19 -0
@@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2026 Variscite Ltd. + */ + +/* WIFI */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + #address-cells = <1>; + #size-cells = <0>; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +};
arch/arm64/boot/dts/freescale/imx8mn-var-som-wifi-bt-iw61x.dtsi new file +46 -0
46 lines not on this page · raw message
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +0 -8
@@ -371,10 +371,7 @@ &usbotg1 { status = "okay"; }; -/* WIFI */ &usdhc1 { - #address-cells = <1>; - #size-cells = <0>; pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
@@ -383,11 +380,6 @@ &usdhc1 { non-removable; keep-power-in-suspend; status = "okay"; - - brcmf: wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - }; }; /* eMMC */
Signature · 1 line
2.47.3
[email protected]
AI reviewRe: [PATCH v2 07/15] arm64: dts: freescale: imx8mn-var-som: Rework WiFi/BT and add legacy dts
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [High] The legacy Symphony device tree (`imx8mn-var-som-symphony-legacy.dts`) fails to revert the `uart2`…
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The legacy Symphony device tree (imx8mn-var-som-symphony-legacy.dts) fails to revert the uart2 pinctrl configuration, permanently claiming the Bluetooth enable GPIO and breaking legacy Bluetooth initialization. --
commit 31b3d797e663552df95cdacb42e55c6c3a65c79e
Author: Stefano Radaelli <[email protected]>
arm64: dts: freescale: imx8mn-var-som: Rework WiFi/BT and add legacy dts
This moves the IW61x wireless module configuration out of the base imx8mn-var-som.dtsi into dedicated variant includes. It also adds a legacy device tree to support older SOM revisions with Broadcom WiFi.
[ ... ]
Quoted 7 lines
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony-legacy.dts new file +1
-0@@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony-legacy.dts line 11
Quoted 10 lines
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony-legacy.dts new file +10
-0+/* + * Copyright 2026 Variscite Ltd. + */ + +#include "imx8mn-var-som-symphony.dts" +#include "imx8mn-var-som-wifi-brcm-legacy.dtsi" + +&bluetooth_iw61x { + status = "disabled"; +};
[Severity: High]
Will this leave the pinctrl_bt group claimed by uart2?
Since this legacy device tree includes imx8mn-var-som-symphony.dts (which includes the new IW61x setup), uart2 is initially configured with:
&uart2 {
pinctrl-0 = <&pinctrl_uart2>, <&pinctrl_bt>;
...
}Disabling bluetooth_iw61x here leaves the pinctrl-0 property on uart2 unchanged. Because the i.MX pinctrl driver uses strict pinmux claiming, wouldn't this permanently claim the BT enable GPIO (GPIO2_IO6) and prevent legacy userspace scripts or drivers from exporting or toggling it?
Does uart2 need an override here to drop pinctrl_bt?
Quoted 4 lines
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony-legacy.dts new file +4
-0+ +&iw61x_pwrseq { + status = "disabled"; +};
[ ... ]
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=7
PATCH v2 8/15 arm64: dts: freescale: imx8mn-var-som: drop duplicate USB OTG node
In reply to Stefano RadaelliFrom: Stefano Radaelli <[email protected]>
The VAR-SOM-MX8MN module does not provide an onboard USB connector.
The complete USB OTG description, including the Type-C role switch configuration, is already provided by the Symphony carrier board device tree. Remove the duplicate USB OTG node from the SOM dtsi to avoid describing the same hardware in two places.
---v1->v2:
-
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi | 6 ------ 1 file changed, 6 deletions(-)
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +0 -6
@@ -365,12 +365,6 @@ &uart2 { status = "okay"; }; -&usbotg1 { - dr_mode = "otg"; - usb-role-switch; - status = "okay"; -}; - &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>;
Signature · 1 line
2.47.3
Re: [PATCH v2 08/15] arm64: dts: freescale: imx8mn-var-som: drop duplicate USB OTG node
Quoted 11 lines · Stefano Radaelli
From: Stefano Radaelli <[email protected]>
The VAR-SOM-MX8MN module does not provide an onboard USB connector.
The complete USB OTG description, including the Type-C role switch configuration, is already provided by the Symphony carrier board device tree. Remove the duplicate USB OTG node from the SOM dtsi to avoid describing the same hardware in two places.
Signed-off-by Stefano Radaelli <[email protected]>---
PATCH v2 9/15 arm64: dts: freescale: imx8mn-var-som: enable FlexSPI interface
In reply to Stefano RadaelliFrom: Stefano Radaelli <[email protected]>
Enable the FlexSPI controller on the VAR-SOM-MX8MN and add the corresponding pin multiplexing configuration.
---v1->v2:
-
.../boot/dts/freescale/imx8mn-var-som.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +17 -0
@@ -176,6 +176,12 @@ ethphy: ethernet-phy@4 { }; }; +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default";
@@ -454,6 +460,17 @@ MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x120 >; }; + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4 + MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84 + MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84 + MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84 + MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84 + MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
Signature · 1 line
2.47.3
[email protected]
AI reviewRe: [PATCH v2 09/15] arm64: dts: freescale: imx8mn-var-som: enable FlexSPI interface
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Low] The FlexSPI controller is unconditionally enabled in the SOM dtsi but lacks a child node for the…
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The FlexSPI controller is unconditionally enabled in the SOM dtsi but lacks a child node for the connected SPI flash device. --
commit 636db0e489f17ce6e70d2d0ddbe2135a87fefaff
Author: Stefano Radaelli <[email protected]>
arm64: dts: freescale: imx8mn-var-som: enable FlexSPI interface
This commit enables the FlexSPI controller on the VAR-SOM-MX8MN and adds the corresponding pin multiplexing configuration.
Quoted 4 lines
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +0
-0
[ ... ]
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi ethphy: ethernet-phy@4 { · line 183
Quoted 9 lines
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +5
-0@@ -176,6 +176,12 @@ ethphy: ethernet-phy@4 { }; }; +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; +};
[Severity: Low]
Is it intentional to enable the FlexSPI controller unconditionally in the SOM dtsi without defining a child node for a connected SPI flash device?
Quoted 3 lines
arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +1
-0+ &i2c1 { clock-frequency = <400000>;
[ ... ]
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=9
PATCH v2 10/15 arm64: dts: imx8mn-var-som-symphony: Add TPM2 support
In reply to Stefano RadaelliFrom: Stefano Radaelli <[email protected]>
Add support for the TPM2 device on the VAR-SOM Symphony carrier board.
The ST33K TPM2 is connected over I2C, and A PCA6408 GPIO expander is used to control the reset signal required to release the TPM from reset.
Add the PCA6408 GPIO expander and the ST33K TPM2 device node.
---v1->v2:
-
.../boot/dts/freescale/imx8mn-var-som-symphony.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +14 -0
@@ -160,6 +160,20 @@ typec1_dr_sw: endpoint { }; &i2c3 { + pca6408: gpio@21 { + compatible = "nxp,pcal6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + + st33ktpm2xi2c: tpm@2e { + compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; + reg = <0x2e>; + label = "tpm"; + reset-gpios = <&pca6408 4 GPIO_ACTIVE_LOW>; + }; + /* Capacitive touch controller */ ft5x06_ts: touchscreen@38 { compatible = "edt,edt-ft5406";
Signature · 1 line
2.47.3
[email protected]
AI reviewRe: [PATCH v2 10/15] arm64: dts: imx8mn-var-som-symphony: Add TPM2 support
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Medium] The device tree specifies `reset-gpios` for the TPM device, but the kernel lacks support to…
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The device tree specifies reset-gpios for the TPM device, but the kernel lacks support to drive this GPIO, potentially leaving the TPM stuck in reset. --
commit 5bd051d2688db25353ab678262b0998bf9810906
Author: Stefano Radaelli <[email protected]>
arm64: dts: imx8mn-var-som-symphony: Add TPM2 support
This commit adds support for the ST33K TPM2 device on the VAR-SOM Symphony carrier board over I2C. It also adds the PCA6408 GPIO expander node used to control the TPM reset signal.
Quoted 4 lines
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +0
-0
[ ... ]
Quoted 6 lines
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +2
-0@@ -160,6 +160,20 @@ typec1_dr_sw: endpoint { }; &i2c3 { + pca6408: gpio@21 { + compatible = "nxp,pcal6408";
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts typec1_dr_sw: endpoint { · line 174
Quoted 10 lines
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +10
-0+ reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + + st33ktpm2xi2c: tpm@2e { + compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c"; + reg = <0x2e>; + label = "tpm"; + reset-gpios = <&pca6408 4 GPIO_ACTIVE_LOW>;
[Severity: Medium]
Will the kernel actually use this reset-gpios property to release the TPM?
The commit message states the PCA6408 is used to control the reset signal to release the TPM from reset. However, neither the tpm_tis_i2c driver nor the TPM core appear to parse the reset-gpios property or request a reset GPIO. There is also no gpio-hog configured in the pca6408 node to force the pin state.
Does this setup rely entirely on the bootloader initializing the PCA6408 and leaving the GPIO driven to the correct state?
If the system goes through a suspend/resume sequence or if the PCA6408 defaults back to an input state, could the TPM become stuck in reset and fail to probe?
Quoted 1 line
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +1
-0+ };
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=10
PATCH v2 11/15 arm64: dts: imx8mn-var-som-symphony: Enable I2C4
In reply to Stefano RadaelliFrom: Stefano Radaelli <[email protected]>
Enable I2C4 on the Symphony carrier and add pinctrl configuration, including GPIO-based bus recovery support.
---v1->v2:
-
.../dts/freescale/imx8mn-var-som-symphony.dts | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+)
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +24 -0
@@ -195,6 +195,16 @@ rtc@68 { }; }; +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + /* Header */ &uart1 { pinctrl-names = "default";
@@ -262,6 +272,20 @@ MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 >; }; + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 0x1c3 + MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x1c3 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 + MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + >; + }; + pinctrl_pca9534: pca9534grp { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x16
Signature · 1 line
2.47.3
Re: [PATCH v2 11/15] arm64: dts: imx8mn-var-som-symphony: Enable I2C4
Quoted 6 lines · Stefano Radaelli
From: Stefano Radaelli <[email protected]>
Enable I2C4 on the Symphony carrier and add pinctrl configuration, including GPIO-based bus recovery support.
Signed-off-by Stefano Radaelli <[email protected]>
PATCH v2 12/15 arm64: dts: imx8mn-var-som-symphony: add wakeup sources
In reply to Stefano RadaelliFrom: Stefano Radaelli <[email protected]>
Mark the Symphony carrier board GPIO keys and capacitive touchscreen as wakeup sources.
---v1->v2:
-
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts | 4 ++++ 1 file changed, 4 insertions(+)
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +4 -0
@@ -40,18 +40,21 @@ key-back { label = "Back"; gpios = <&pca9534 1 GPIO_ACTIVE_LOW>; linux,code = <KEY_BACK>; + wakeup-source; }; key-home { label = "Home"; gpios = <&pca9534 2 GPIO_ACTIVE_LOW>; linux,code = <KEY_HOME>; + wakeup-source; }; key-menu { label = "Menu"; gpios = <&pca9534 3 GPIO_ACTIVE_LOW>; linux,code = <KEY_MENU>; + wakeup-source; }; };
@@ -187,6 +190,7 @@ ft5x06_ts: touchscreen@38 { touchscreen-size-y = <480>; touchscreen-inverted-x; touchscreen-inverted-y; + wakeup-source; }; rtc@68 {
Signature · 1 line
2.47.3
Re: [PATCH v2 12/15] arm64: dts: imx8mn-var-som-symphony: add wakeup sources
Quoted 6 lines · Stefano Radaelli
From: Stefano Radaelli <[email protected]>
Mark the Symphony carrier board GPIO keys and capacitive touchscreen as wakeup sources.
Signed-off-by Stefano Radaelli <[email protected]>
PATCH v2 13/15 arm64: dts: imx8mn-var-som-symphony: keep RGB_SEL low
In reply to Stefano RadaelliFrom: Stefano Radaelli <[email protected]>
Keep the RGB_SEL line driven low on the Symphony carrier board.
This avoids leaving the line floating and ensures the board remains in the expected display configuration.
---v1->v2:
-
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts | 8 ++++++++ 1 file changed, 8 insertions(+)
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +8 -0
@@ -168,6 +168,14 @@ pca6408: gpio@21 { reg = <0x21>; gpio-controller; #gpio-cells = <2>; + + /* RGB_SEL */ + lvds-brg-enable-hog { + gpio-hog; + gpios = <7 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "rgb_sel"; + }; }; st33ktpm2xi2c: tpm@2e {
Signature · 1 line
2.47.3
Re: [PATCH v2 13/15] arm64: dts: imx8mn-var-som-symphony: keep RGB_SEL low
Quoted 8 lines · Stefano Radaelli
From: Stefano Radaelli <[email protected]>
Keep the
RGB_SELline driven low on the Symphony carrier board.This avoids leaving the line floating and ensures the board remains in the expected display configuration.
Signed-off-by Stefano Radaelli <[email protected]>
PATCH v2 14/15 arm64: dts: imx8mn-var-som-symphony: enable PWM1
In reply to Stefano RadaelliFrom: Stefano Radaelli <[email protected]>
Enable PWM1 on the Symphony carrier board and add the corresponding pinctrl configuration.
---v1->v2:
-
.../boot/dts/freescale/imx8mn-var-som-symphony.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+)
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +12 -0
@@ -217,6 +217,12 @@ &i2c4 { status = "okay"; }; +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + /* Header */ &uart1 { pinctrl-names = "default";
@@ -310,6 +316,12 @@ MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x16 >; }; + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MN_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x06 + >; + }; + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x41
Signature · 1 line
2.47.3
Re: [PATCH v2 14/15] arm64: dts: imx8mn-var-som-symphony: enable PWM1
Quoted 6 lines · Stefano Radaelli
From: Stefano Radaelli <[email protected]>
Enable PWM1 on the Symphony carrier board and add the corresponding pinctrl configuration.
Signed-off-by Stefano Radaelli <[email protected]>
PATCH v2 15/15 arm64: dts: imx8mn-var-som-symphony: Disable internal RTC
In reply to Stefano RadaelliFrom: Stefano Radaelli <[email protected]>
Disable the internal SNVS RTC on the Symphony carrier board and use the external DS1337 RTC instead.
---v1->v2:
-
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts | 4 ++++ 1 file changed, 4 insertions(+)
arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +4 -0
@@ -223,6 +223,10 @@ &pwm1 { status = "okay"; }; +&snvs_rtc { + status = "disabled"; +}; + /* Header */ &uart1 { pinctrl-names = "default";
Signature · 1 line
2.47.3
Re: [PATCH v2 15/15] arm64: dts: imx8mn-var-som-symphony: Disable internal RTC
Quoted 6 lines · Stefano Radaelli
From: Stefano Radaelli <[email protected]>
Disable the internal SNVS RTC on the Symphony carrier board and use the external DS1337 RTC instead.
Signed-off-by Stefano Radaelli <[email protected]>
[email protected]
AppliedFrom: Frank Li <[email protected]>
Quoted 9 lines · Stefano Radaelli
This series aligns the i.MX8MN VAR-SOM and VAR-SOM Symphony device trees with the latest hardware revisions.
As the i.MX8MN device tree hierarchy closely mirrors the i.MX8MM one, this series applies the same alignment already accepted for the i.MX8MM platform, ensuring a consistent hardware description across both families.
[...]
Applied, thanks!
[01/15] arm64: dts: freescale: imx8mn-var-som: Move UART4 description to Symphony
commit: 259bd77e9f635e058c045a880427570e534c8737
[02/15] arm64: dts: freescale: imx8mn-var-som: move uSD support to carrier boards
commit: bc5217a4e354ebe0a2f52d2188ef952fd630defc
[03/15] arm64: dts: freescale: imx8mn-var-som: Align fsl,pins tables
commit: 763a267bc2ccf637bd0f35492ca1e6ab6c9dc13b
[04/15] arm64: dts: freescale: imx8mn-var-som: Update FEC support with MaxLinear PHY
commit: a6c8d4f9c2db6254681d78ec93f5bd944a0cf89d
[05/15] arm64: dts: freescale: imx8mn-var-som: Add support for WM8904 audio codec
commit: ed99c5c5c5e88f31ed8de6eff9c3da2ca188d947
[06/15] arm64: dts: freescale: imx8mn-var-som: Add MCP251xFD CAN controller
commit: 42a066c24cc673b4317acb382597c0a3230b9f6f
[07/15] arm64: dts: freescale: imx8mn-var-som: Rework WiFi/BT and add legacy dts
commit: 040bf14c102570fee953fc2124737a988c3fb6a6
[08/15] arm64: dts: freescale: imx8mn-var-som: drop duplicate USB OTG node
commit: 0504e4d12fd3c3b5062b49086ce17a2743c60658
[09/15] arm64: dts: freescale: imx8mn-var-som: enable FlexSPI interface
commit: 5580a6278c5ce77a8492d76571929321894934f3
[10/15] arm64: dts: imx8mn-var-som-symphony: Add TPM2 support
commit: 8576126c7ccf632c8edeeb69f57f17ee5e125de5
[11/15] arm64: dts: imx8mn-var-som-symphony: Enable I2C4
commit: ab80a67f5cdb42797d0a92d7951242291bb97f3a
[12/15] arm64: dts: imx8mn-var-som-symphony: add wakeup sources
commit: e2e47af10c90f4c5eaf415fa98f6ca2f33ef30da
[13/15] arm64: dts: imx8mn-var-som-symphony: keep RGB_SEL low
commit: 164cb0d61a3fd0d9376005aae3b112a3dbba2e07
[14/15] arm64: dts: imx8mn-var-som-symphony: enable PWM1
commit: 8a6c812cd5a721aa0af9b7dd35b43d12c831349e
[15/15] arm64: dts: imx8mn-var-som-symphony: Disable internal RTC
commit: be578db51f789f0b88ec4f5e5f78e232b42c6b15Best regards,
Signature · 1 line
Frank Li <[email protected]>