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CPUFREQ OPP's, DVFS and Tegra30 support by tegra20-cpufreq driver

RFC PATCH In review Dmitry Osipenko 5 participants 33 messages Oct 21, 2018 – Nov 8, 2018

Subsystems (7)
Device tree bindings Arm (32-bit) Arm sub-architectures Tegra architecture support +3 more subsystems
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Dmitry Osipenko

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#0 lore raw

v2 cover CPUFREQ OPP's, DVFS and Tegra30 support by tegra20-cpufreq driver

Hello,

This series adds support for CPU frequency/voltage scaling on Tegra20/30, it adds device tree support that allow to specify clock rate/voltages per board and to implement thermal throttling. The tegra20-cpufreq driver has been re-worked to support that all.

Note that this series depends on in-progress clock [0] and regulator [1] patches.

Changelog:

v2:
- Implemented DVFS support. Currently only CPU rail changes voltage, while CORE/RTC locked to maximum. The CORE can be unlocked once all of peripheral drivers will gain support for DVFS. See "TODO" comment in the driver. On Tegra20 CPU temperature is lower by 5-6 C during idling with DVFS. On Tegra30 CPU temperature is lower by 1-2 C, and it drops by 6-7 C if CORE rail scaling is unlocked.

- Device-tree binding has been reworked to support voltage regulators and HW versioning. Now CPU OPP's are specified per HW version and include voltage entry. OPP values are taken from downstream kernel [2][3]. The "backup" clock has been renamed to "intermediate".

[0] https://lkml.org/lkml/2018/8/30/960
[1] https://lkml.org/lkml/2018/10/5/682
[2] https://nv-tegra.nvidia.com/gitweb/?p=linux-2.6.git;a=blob;f=arch/arm/mach-tegra/tegra2_dvfs.c;hb=l4t/l4t-r16-r2
[3] https://nv-tegra.nvidia.com/gitweb/?p=linux-2.6.git;a=blob;f=arch/arm/mach-tegra/tegra3_dvfs.c;hb=l4t/l4t-r16-r2

Dmitry Osipenko (17):
OPP: Allow to request stub voltage regulators soc/tegra: fuse: Export tegra_get_chip_id()
dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30
cpufreq: tegra20: Support OPP, thermal cooling, DVFS and Tegra30
ARM: tegra: Create tegra20-cpufreq device on Tegra30
ARM: dts: tegra20: Add CPU Operating Performance Points
ARM: dts: tegra30: Add CPU Operating Performance Points
ARM: dts: tegra20: colibri: Setup voltage regulators for DVFS
ARM: dts: tegra20: harmony: Setup voltage regulators for DVFS
ARM: dts: tegra20: paz00: Setup voltage regulators for DVFS
ARM: dts: tegra20: seaboard: Setup voltage regulators for DVFS
ARM: dts: tegra20: tamonten: Setup voltage regulators for DVFS
ARM: dts: tegra20: ventana: Setup voltage regulators for DVFS
ARM: dts: tegra30: apalis: Setup voltage regulators for DVFS
ARM: dts: tegra30: beaver: Setup voltage regulators for DVFS
ARM: dts: tegra30: cardhu: Setup voltage regulators for DVFS
ARM: dts: tegra30: colibri: Setup voltage regulators for DVFS

 .../cpufreq/nvidia,tegra20-cpufreq.txt        |  96 ++
 arch/arm/boot/dts/tegra20-colibri.dtsi        |  31 +-
 arch/arm/boot/dts/tegra20-harmony.dts         |  31 +-
 arch/arm/boot/dts/tegra20-paz00.dts           |  31 +-
 arch/arm/boot/dts/tegra20-seaboard.dts        |  27 +-
 arch/arm/boot/dts/tegra20-tamonten.dtsi       |  31 +-
 arch/arm/boot/dts/tegra20-ventana.dts         |  31 +-
 arch/arm/boot/dts/tegra20.dtsi                | 277 ++++++
 arch/arm/boot/dts/tegra30-apalis.dtsi         |  19 +-
 arch/arm/boot/dts/tegra30-beaver.dts          |  19 +-
 arch/arm/boot/dts/tegra30-cardhu.dtsi         |  19 +-
 arch/arm/boot/dts/tegra30-colibri.dtsi        |  19 +-
 arch/arm/boot/dts/tegra30.dtsi                | 688 +++++++++++++++
 arch/arm/mach-tegra/tegra.c                   |   4 +
 drivers/cpufreq/Kconfig.arm                   |   2 +
 drivers/cpufreq/cpufreq-dt-platdev.c          |   2 +
 drivers/cpufreq/cpufreq-dt.c                  |   2 +-
 drivers/cpufreq/tegra20-cpufreq.c             | 832 +++++++++++++++---
 drivers/cpufreq/ti-cpufreq.c                  |   3 +-
 drivers/opp/core.c                            |   9 +-
 drivers/soc/tegra/fuse/tegra-apbmisc.c        |   1 +
 include/linux/pm_opp.h                        |   4 +-
 22 files changed, 2006 insertions(+), 172 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt
Signature · 1 line
2.19.0
author
#1 lore raw

RFC PATCH v2 1/17 OPP: Allow to request stub voltage regulators

Voltage regulators may be not available on some variations of HW, allow to request stub voltage regulators by OPP core in a such case to reduce code churning within drivers.

Signed-off-by Dmitry Osipenko <[email protected]>
---
 drivers/cpufreq/cpufreq-dt.c | 2 +-
 drivers/cpufreq/ti-cpufreq.c | 3 ++-
 drivers/opp/core.c           | 9 +++++++--
 include/linux/pm_opp.h       | 4 ++--
 4 files changed, 12 insertions(+), 6 deletions(-)
drivers/cpufreq/cpufreq-dt.c +1 -1
index e58bfcb1169e..6ebca472ec76 100644
@@ -196,7 +196,7 @@ static int cpufreq_init(struct cpufreq_policy *policy)
 	 */
 	name = find_supply_name(cpu_dev);
 	if (name) {
-		opp_table = dev_pm_opp_set_regulators(cpu_dev, &name, 1);
+		opp_table = dev_pm_opp_set_regulators(cpu_dev, &name, 1, false);
 		if (IS_ERR(opp_table)) {
 			ret = PTR_ERR(opp_table);
 			dev_err(cpu_dev, "Failed to set regulator for cpu%d: %d\n",
drivers/cpufreq/ti-cpufreq.c +2 -1
index 3f0e2a14895a..9099c8cdf447 100644
@@ -268,7 +268,8 @@ static int ti_cpufreq_probe(struct platform_device *pdev)
 	if (opp_data->soc_data->multi_regulator) {
 		ti_opp_table = dev_pm_opp_set_regulators(opp_data->cpu_dev,
 							 reg_names,
-							 ARRAY_SIZE(reg_names));
+							 ARRAY_SIZE(reg_names),
+							 false);
 		if (IS_ERR(ti_opp_table)) {
 			dev_pm_opp_put_supported_hw(opp_data->opp_table);
 			ret =  PTR_ERR(ti_opp_table);
drivers/opp/core.c +7 -2
index 2c2df4e4fc14..fba1d7a1eb7c 100644
@@ -1365,6 +1365,7 @@ static void _free_set_opp_data(struct opp_table *opp_table)
  * @dev: Device for which regulator name is being set.
  * @names: Array of pointers to the names of the regulator.
  * @count: Number of regulators.
+ * @allow_stub_regulator: Some or all regulators can be missed.
  *
  * In order to support OPP switching, OPP layer needs to know the name of the
  * device's regulators, as the core would be required to switch voltages as

@@ -1374,7 +1375,8 @@ static void _free_set_opp_data(struct opp_table *opp_table)
  */
 struct opp_table *dev_pm_opp_set_regulators(struct device *dev,
 					    const char * const names[],
-					    unsigned int count)
+					    unsigned int count,
+					    bool allow_stub_regulator)
 {
 	struct opp_table *opp_table;
 	struct regulator *reg;

@@ -1403,7 +1405,10 @@ struct opp_table *dev_pm_opp_set_regulators(struct device *dev,
 	}
 
 	for (i = 0; i < count; i++) {
-		reg = regulator_get_optional(dev, names[i]);
+		if (allow_stub_regulator)
+			reg = regulator_get(dev, names[i]);
+		else
+			reg = regulator_get_optional(dev, names[i]);
 		if (IS_ERR(reg)) {
 			ret = PTR_ERR(reg);
 			if (ret != -EPROBE_DEFER)
include/linux/pm_opp.h +2 -2
index 5d399eeef172..480666b0a008 100644
@@ -120,7 +120,7 @@ struct opp_table *dev_pm_opp_set_supported_hw(struct device *dev, const u32 *ver
 void dev_pm_opp_put_supported_hw(struct opp_table *opp_table);
 struct opp_table *dev_pm_opp_set_prop_name(struct device *dev, const char *name);
 void dev_pm_opp_put_prop_name(struct opp_table *opp_table);
-struct opp_table *dev_pm_opp_set_regulators(struct device *dev, const char * const names[], unsigned int count);
+struct opp_table *dev_pm_opp_set_regulators(struct device *dev, const char * const names[], unsigned int count, bool allow_stub_regulator);
 void dev_pm_opp_put_regulators(struct opp_table *opp_table);
 struct opp_table *dev_pm_opp_set_clkname(struct device *dev, const char * name);
 void dev_pm_opp_put_clkname(struct opp_table *opp_table);

@@ -258,7 +258,7 @@ static inline struct opp_table *dev_pm_opp_set_prop_name(struct device *dev, con
 
 static inline void dev_pm_opp_put_prop_name(struct opp_table *opp_table) {}
 
-static inline struct opp_table *dev_pm_opp_set_regulators(struct device *dev, const char * const names[], unsigned int count)
+static inline struct opp_table *dev_pm_opp_set_regulators(struct device *dev, const char * const names[], unsigned int count, bool allow_stub_regulator)
 {
 	return ERR_PTR(-ENOTSUPP);
 }
Signature · 1 line
2.19.0
maintainer
#2 lore raw

Re: [RFC PATCH v2 01/17] OPP: Allow to request stub voltage regulators

Quoted 17 lines · Dmitry Osipenko

Voltage regulators may be not available on some variations of HW, allow to request stub voltage regulators by OPP core in a such case to reduce code churning within drivers.

Signed-off-by Dmitry Osipenko <[email protected]>
---
 drivers/cpufreq/cpufreq-dt.c | 2 +-
 drivers/cpufreq/ti-cpufreq.c | 3 ++-
 drivers/opp/core.c           | 9 +++++++--
 include/linux/pm_opp.h       | 4 ++--
 4 files changed, 12 insertions(+), 6 deletions(-)
drivers/cpufreq/cpufreq-dt.c +0 -0
index e58bfcb1169e..6ebca472ec76 100644

drivers/cpufreq/cpufreq-dt.c static int cpufreq_init(struct cpufreq_policy *policy) · line 202

Quoted 8 lines
drivers/cpufreq/cpufreq-dt.c +1 -1
@@ -196,7 +196,7 @@ static int cpufreq_init(struct cpufreq_policy *policy)
 	 */
 	name = find_supply_name(cpu_dev);
 	if (name) {
-		opp_table = dev_pm_opp_set_regulators(cpu_dev, &name, 1);
+		opp_table = dev_pm_opp_set_regulators(cpu_dev, &name, 1, false);
 		if (IS_ERR(opp_table)) {
 			ret = PTR_ERR(opp_table);
 			dev_err(cpu_dev, "Failed to set regulator for cpu%d: %d\n",

Have you actually tested this stuff ? The cpufreq-dt driver will probably fail to probe if the CPU node has a "-supply" property, but no regulator matching that.

Signature · 1 line
viresh
author
#3 lore raw

Re: [RFC PATCH v2 01/17] OPP: Allow to request stub voltage regulators

Quoted 22 lines · Viresh Kumar
Quoted 21 lines · Dmitry Osipenko

Voltage regulators may be not available on some variations of HW, allow to request stub voltage regulators by OPP core in a such case to reduce code churning within drivers.

Signed-off-by Dmitry Osipenko <[email protected]>
---
 drivers/cpufreq/cpufreq-dt.c | 2 +-
 drivers/cpufreq/ti-cpufreq.c | 3 ++-
 drivers/opp/core.c           | 9 +++++++--
 include/linux/pm_opp.h       | 4 ++--
 4 files changed, 12 insertions(+), 6 deletions(-)
drivers/cpufreq/cpufreq-dt.c +0 -1
index e58bfcb1169e..6ebca472ec76 100644
@@ -196,7 +196,7 @@ static int cpufreq_init(struct cpufreq_policy *policy)
 	 */
 	name = find_supply_name(cpu_dev);
 	if (name) {
-		opp_table = dev_pm_opp_set_regulators(cpu_dev, &name, 1);
Quoted 9 lines

drivers/cpufreq/cpufreq-dt.c static int cpufreq_init(struct cpufreq_policy *policy) · line 202

Quoted 4 lines
drivers/cpufreq/cpufreq-dt.c +1 -0
+		opp_table = dev_pm_opp_set_regulators(cpu_dev, &name, 1, false);
 		if (IS_ERR(opp_table)) {
 			ret = PTR_ERR(opp_table);
 			dev_err(cpu_dev, "Failed to set regulator for cpu%d: %d\n",

Have you actually tested this stuff ? The cpufreq-dt driver will probably fail to probe if the CPU node has a "-supply" property, but no regulator matching that.

Please notice that this patch doesn't change the original behaviour and I suppose that failing in a case of missing regulator is the expected behaviour for cpufreq-dt. Hence can't see any problem here.

maintainer
#4 lore raw

Re: [RFC PATCH v2 01/17] OPP: Allow to request stub voltage regulators

Quoted 33 lines · Dmitry Osipenko
Quoted 22 lines · Viresh Kumar
Quoted 21 lines · Dmitry Osipenko

Voltage regulators may be not available on some variations of HW, allow to request stub voltage regulators by OPP core in a such case to reduce code churning within drivers.

Signed-off-by Dmitry Osipenko <[email protected]>
---
 drivers/cpufreq/cpufreq-dt.c | 2 +-
 drivers/cpufreq/ti-cpufreq.c | 3 ++-
 drivers/opp/core.c           | 9 +++++++--
 include/linux/pm_opp.h       | 4 ++--
 4 files changed, 12 insertions(+), 6 deletions(-)
drivers/cpufreq/cpufreq-dt.c +0 -1
index e58bfcb1169e..6ebca472ec76 100644
@@ -196,7 +196,7 @@ static int cpufreq_init(struct cpufreq_policy *policy)
 	 */
 	name = find_supply_name(cpu_dev);
 	if (name) {
-		opp_table = dev_pm_opp_set_regulators(cpu_dev, &name, 1);
Quoted 9 lines

drivers/cpufreq/cpufreq-dt.c static int cpufreq_init(struct cpufreq_policy *policy) · line 202

Quoted 4 lines
drivers/cpufreq/cpufreq-dt.c +1 -0
+		opp_table = dev_pm_opp_set_regulators(cpu_dev, &name, 1, false);
 		if (IS_ERR(opp_table)) {
 			ret = PTR_ERR(opp_table);
 			dev_err(cpu_dev, "Failed to set regulator for cpu%d: %d\n",

Have you actually tested this stuff ? The cpufreq-dt driver will probably fail to probe if the CPU node has a "-supply" property, but no regulator matching that.

Quoted 3 lines

Please notice that this patch doesn't change the original behaviour and I suppose that failing in a case of missing regulator is the expected behaviour for cpufreq-dt. Hence can't see any problem here.

So why have this patch then ?

Signature · 1 line
viresh
author
#5 lore raw

Re: [RFC PATCH v2 01/17] OPP: Allow to request stub voltage regulators

Quoted 34 lines · Viresh Kumar
Quoted 33 lines · Dmitry Osipenko
Quoted 31 lines · Viresh Kumar
Quoted 17 lines · Dmitry Osipenko

Voltage regulators may be not available on some variations of HW, allow to request stub voltage regulators by OPP core in a such case to reduce code churning within drivers.

Signed-off-by Dmitry Osipenko <[email protected]>
---
 drivers/cpufreq/cpufreq-dt.c | 2 +-
 drivers/cpufreq/ti-cpufreq.c | 3 ++-
 drivers/opp/core.c           | 9 +++++++--
 include/linux/pm_opp.h       | 4 ++--
 4 files changed, 12 insertions(+), 6 deletions(-)
drivers/cpufreq/cpufreq-dt.c +0 -0
index e58bfcb1169e..6ebca472ec76 100644

drivers/cpufreq/cpufreq-dt.c static int cpufreq_init(struct cpufreq_policy *policy) · line 202

Quoted 8 lines
drivers/cpufreq/cpufreq-dt.c +1 -1
@@ -196,7 +196,7 @@ static int cpufreq_init(struct cpufreq_policy *policy)
 	 */
 	name = find_supply_name(cpu_dev);
 	if (name) {
-		opp_table = dev_pm_opp_set_regulators(cpu_dev, &name, 1);
+		opp_table = dev_pm_opp_set_regulators(cpu_dev, &name, 1, false);
 		if (IS_ERR(opp_table)) {
 			ret = PTR_ERR(opp_table);
 			dev_err(cpu_dev, "Failed to set regulator for cpu%d: %d\n",

Have you actually tested this stuff ? The cpufreq-dt driver will probably fail to probe if the CPU node has a "-supply" property, but no regulator matching that.

Quoted 5 lines
Quoted 3 lines

Please notice that this patch doesn't change the original behaviour and I suppose that failing in a case of missing regulator is the expected behaviour for cpufreq-dt. Hence can't see any problem here.

So why have this patch then ?

Because there is one Tegra20 board (tegra20-trimslice) that doesn't declare necessary regulators, but we want to have CPU frequency scaling. I couldn't find board schematics and so don't know if CPU / CORE voltages are fixed on Trim-Slice or it is just preferable not to have DVFS for that board, it is an outlet-powered device [0]. Hence tegra20-cpufreq driver will request a dummy regulators when appropriate.

[0] http://www.compulab.co.il/utilite-computer/web/trim-slice

maintainer
#6 lore raw

Re: [RFC PATCH v2 01/17] OPP: Allow to request stub voltage regulators

Quoted 6 lines · Dmitry Osipenko

Because there is one Tegra20 board (tegra20-trimslice) that doesn't declare necessary regulators, but we want to have CPU frequency scaling. I couldn't find board schematics and so don't know if CPU / CORE voltages are fixed on Trim-Slice or it is just preferable not to have DVFS for that board, it is an outlet-powered device [0]. Hence tegra20-cpufreq driver will request a dummy regulators when appropriate.

We have been using the regulator_get_optional() variant until now in the OPP core to make sure that we don't do DVFS for the CPU without the mandatory regulators being present, as that may make things unstable and cause harm to the SoC if we try to take CPU to frequency range over the currently programmed regulator can support.

Now coming back to tegra-20 SoC, which actually requires a regulator normally by design. On one of the boards (which is outlet powered), you aren't sure if there is a programmable regulator or not, or if DVFS should really be done or not. Isn't it worth checking the same from Tegra maintainers, or whomsoever has information on that board ? What would happen if there actually was a regulator and its default settings aren't good enough for high end frequencies ?

On the other hand, the tegra20 cpufreq driver is common across a lot of boards. What will happen if the DT for some of the boards isn't correct and missed the necessary regulator node ? And because you are moving to regulator_get() API for the entire SoC (i.e. its cpufreq driver), people will never find the missing regulator.

If we can do it safely for all tegra20 boards, why not migrate to using regulator_get() instead of regulator_get_optional() in the OPP core API itself for everyone ?

Signature · 1 line
viresh
author
#7 lore raw

Re: [RFC PATCH v2 01/17] OPP: Allow to request stub voltage regulators

Quoted 14 lines · Viresh Kumar
Quoted 6 lines · Dmitry Osipenko

Because there is one Tegra20 board (tegra20-trimslice) that doesn't declare necessary regulators, but we want to have CPU frequency scaling. I couldn't find board schematics and so don't know if CPU / CORE voltages are fixed on Trim-Slice or it is just preferable not to have DVFS for that board, it is an outlet-powered device [0]. Hence tegra20-cpufreq driver will request a dummy regulators when appropriate.

We have been using the regulator_get_optional() variant until now in the OPP core to make sure that we don't do DVFS for the CPU without the mandatory regulators being present, as that may make things unstable and cause harm to the SoC if we try to take CPU to frequency range over the currently programmed regulator can support.

Quoted 5 lines

Now coming back to tegra-20 SoC, which actually requires a regulator normally by design. On one of the boards (which is outlet powered), you aren't sure if there is a programmable regulator or not, or if DVFS should really be done or not. Isn't it worth checking the same from Tegra maintainers, or whomsoever has information on that board ?

I'll try to find out more detailed information for the next revision of the patchset.

What would happen if there actually was a regulator

Quoted 1 line

and its default settings aren't good enough for high end frequencies ?

Usually this causes kernel/applications crashes and/or machine hang.

Quoted 3 lines

On the other hand, the tegra20 cpufreq driver is common across a lot of boards. What will happen if the DT for some of the boards isn't correct and missed the necessary regulator node ?

AFAIK, there is assumption that bootloader should setup regulators in a way that kernel could work properly at max clock rates. Otherwise things won't work.

And because you are moving to regulator_get() API for

Quoted 2 lines

the entire SoC (i.e. its cpufreq driver), people will never find the missing regulator.

Regulators core prints info message when dummy regulator is being used.

Quoted 4 lines

If we can do it safely for all tegra20 boards, why not migrate to using regulator_get() instead of regulator_get_optional() in the OPP core API itself for everyone ?

This should be a platform-specific decision. For Tegra we know that regulators should be in a good state at kernel boot time, I don't think that this applies to other platforms.

#8 lore raw

Re: [RFC PATCH v2 01/17] OPP: Allow to request stub voltage regulators

Am Freitag, den 26.10.2018, 15:03 +0300 schrieb Dmitry Osipenko:
[...]

Quoted 7 lines
Quoted 3 lines

On the other hand, the tegra20 cpufreq driver is common across a lot of boards. What will happen if the DT for some of the boards isn't correct and missed the necessary regulator node ?

AFAIK, there is assumption that bootloader should setup regulators in a way that kernel could work properly at max clock rates. Otherwise things won't work.

This isn't true. The assumption is that the bootloader sets up the regulators such that stable operation at the CPU speed used by the bootloader is guaranteed.

Often the bootloader doesn't know about specific SKUs, so drives things at a rate/voltage that is safe across all SKUs [1], in which case the bootloader is totally unaware of the voltage needed to run the CPU at highest possible clock frequency.

Regards,
Lucas

[1] http://git.denx.de/?p=u-boot.git;a=commit;h=2364e151e432b4ccf32dc9e6147121253d4ff86d

author
#9 lore raw

Re: [RFC PATCH v2 01/17] OPP: Allow to request stub voltage regulators

Quoted 19 lines · Lucas Stach

Am Freitag, den 26.10.2018, 15:03 +0300 schrieb Dmitry Osipenko:
[...]

Quoted 7 lines
Quoted 3 lines

On the other hand, the tegra20 cpufreq driver is common across a lot of boards. What will happen if the DT for some of the boards isn't correct and missed the necessary regulator node ?

AFAIK, there is assumption that bootloader should setup regulators in a way that kernel could work properly at max clock rates. Otherwise things won't work.

This isn't true. The assumption is that the bootloader sets up the regulators such that stable operation at the CPU speed used by the bootloader is guaranteed.

Often the bootloader doesn't know about specific SKUs, so drives things at a rate/voltage that is safe across all SKUs [1], in which case the bootloader is totally unaware of the voltage needed to run the CPU at highest possible clock frequency.

Quoted 5 lines

Regards,
Lucas

[1] http://git.denx.de/?p=u-boot.git;a=commit;h=2364e151e432b4ccf32dc9e6147121253d4ff86d

Oh, okay. Thank you for pointing at [1], though the assumption is true for T20.

I agree that it's better not to rely on configuration left from bootloader in general.

maintainer
#10 lore raw

Re: [RFC PATCH v2 01/17] OPP: Allow to request stub voltage regulators

In reply to Dmitry Osipenko
Quoted 15 lines · Dmitry Osipenko
Quoted 14 lines · Viresh Kumar
Quoted 6 lines · Dmitry Osipenko

Because there is one Tegra20 board (tegra20-trimslice) that doesn't declare necessary regulators, but we want to have CPU frequency scaling. I couldn't find board schematics and so don't know if CPU / CORE voltages are fixed on Trim-Slice or it is just preferable not to have DVFS for that board, it is an outlet-powered device [0]. Hence tegra20-cpufreq driver will request a dummy regulators when appropriate.

We have been using the regulator_get_optional() variant until now in the OPP core to make sure that we don't do DVFS for the CPU without the mandatory regulators being present, as that may make things unstable and cause harm to the SoC if we try to take CPU to frequency range over the currently programmed regulator can support.

Quoted 7 lines
Quoted 5 lines

Now coming back to tegra-20 SoC, which actually requires a regulator normally by design. On one of the boards (which is outlet powered), you aren't sure if there is a programmable regulator or not, or if DVFS should really be done or not. Isn't it worth checking the same from Tegra maintainers, or whomsoever has information on that board ?

I'll try to find out more detailed information for the next revision of the patchset.

Thanks Dmitry.

Quoted 1 line

What would happen if there actually was a regulator

Please preserve the '>' from previous replies at the beginning of the lines. Otherwise it looks as if you have written the above line. :)

Quoted 3 lines
Quoted 1 line

and its default settings aren't good enough for high end frequencies ?

Usually this causes kernel/applications crashes and/or machine hang.

Sure. I also do remember from some guys (maybe TI), where they mentioned that such scenarios can harm the hardware as well sometimes. Don't remember the details though.

Quoted 5 lines

And because you are moving to regulator_get() API for

Quoted 2 lines

the entire SoC (i.e. its cpufreq driver), people will never find the missing regulator.

Regulators core prints info message when dummy regulator is being used.

Sure, but they are easy to miss and they are only seen by developers not regular users of a machine.

Quoted 6 lines
Quoted 4 lines

If we can do it safely for all tegra20 boards, why not migrate to using regulator_get() instead of regulator_get_optional() in the OPP core API itself for everyone ?

This should be a platform-specific decision. For Tegra we know that regulators should be in a good state at kernel boot time, I don't think that this applies to other platforms.

Based on the other discussion with Lucas on this thread, I don't think this is correct any more ?

Don't get me wrong, I am all good for changes and another API change doesn't matter much to me. I am just wondering if it would be the right approach to fix the issue. Why not rather call dev_pm_opp_set_regulators() conditionally and avoid calling it for the specific tegra20 board.

Signature · 1 line
viresh
author
#11 lore raw

Re: [RFC PATCH v2 01/17] OPP: Allow to request stub voltage regulators

Quoted 55 lines · Viresh Kumar
Quoted 15 lines · Dmitry Osipenko
Quoted 14 lines · Viresh Kumar
Quoted 6 lines · Dmitry Osipenko

Because there is one Tegra20 board (tegra20-trimslice) that doesn't declare necessary regulators, but we want to have CPU frequency scaling. I couldn't find board schematics and so don't know if CPU / CORE voltages are fixed on Trim-Slice or it is just preferable not to have DVFS for that board, it is an outlet-powered device [0]. Hence tegra20-cpufreq driver will request a dummy regulators when appropriate.

We have been using the regulator_get_optional() variant until now in the OPP core to make sure that we don't do DVFS for the CPU without the mandatory regulators being present, as that may make things unstable and cause harm to the SoC if we try to take CPU to frequency range over the currently programmed regulator can support.

Quoted 7 lines
Quoted 5 lines

Now coming back to tegra-20 SoC, which actually requires a regulator normally by design. On one of the boards (which is outlet powered), you aren't sure if there is a programmable regulator or not, or if DVFS should really be done or not. Isn't it worth checking the same from Tegra maintainers, or whomsoever has information on that board ?

I'll try to find out more detailed information for the next revision of the patchset.

Thanks Dmitry.

Quoted 1 line

What would happen if there actually was a regulator

Please preserve the '>' from previous replies at the beginning of the lines. Otherwise it looks as if you have written the above line. :)

Quoted 3 lines
Quoted 1 line

and its default settings aren't good enough for high end frequencies ?

Usually this causes kernel/applications crashes and/or machine hang.

Sure. I also do remember from some guys (maybe TI), where they mentioned that such scenarios can harm the hardware as well sometimes. Don't remember the details though.

Quoted 5 lines

And because you are moving to regulator_get() API for

Quoted 2 lines

the entire SoC (i.e. its cpufreq driver), people will never find the missing regulator.

Regulators core prints info message when dummy regulator is being used.

Sure, but they are easy to miss and they are only seen by developers not regular users of a machine.

Quoted 6 lines
Quoted 4 lines

If we can do it safely for all tegra20 boards, why not migrate to using regulator_get() instead of regulator_get_optional() in the OPP core API itself for everyone ?

This should be a platform-specific decision. For Tegra we know that regulators should be in a good state at kernel boot time, I don't think that this applies to other platforms.

Quoted 8 lines

Based on the other discussion with Lucas on this thread, I don't think this is correct any more ?

Don't get me wrong, I am all good for changes and another API change doesn't matter much to me. I am just wondering if it would be the right approach to fix the issue. Why not rather call dev_pm_opp_set_regulators() conditionally and avoid calling it for the specific tegra20 board.

The right approach should be to specify device tree correctly. Probably we won't need this change at all with the correct DT, will see.

Calling dev_pm_opp_set_regulators() conditionally should work, but that is extra churning in the driver that I tried to avoid.

author
#12 lore raw

RFC PATCH v2 2/17 soc/tegra: fuse: Export tegra_get_chip_id()

In reply to Dmitry Osipenko

This function is used by tegra20-cpufreq driver which can be built as a kernel module.

Signed-off-by Dmitry Osipenko <[email protected]>
---
 drivers/soc/tegra/fuse/tegra-apbmisc.c | 1 +
 1 file changed, 1 insertion(+)
drivers/soc/tegra/fuse/tegra-apbmisc.c +1 -0
index e5a4d8f98b10..c94dccf3eb30 100644
@@ -51,6 +51,7 @@ u8 tegra_get_chip_id(void)
 {
 	return (tegra_read_chipid() >> 8) & 0xff;
 }
+EXPORT_SYMBOL_GPL(tegra_get_chip_id);
 
 u32 tegra_read_straps(void)
 {
Signature · 1 line
2.19.0
author
#13 lore raw

Re: [RFC PATCH v2 02/17] soc/tegra: fuse: Export tegra_get_chip_id()

Quoted 14 lines · Dmitry Osipenko

This function is used by tegra20-cpufreq driver which can be built as a kernel module.

Signed-off-by Dmitry Osipenko <[email protected]>
---
 drivers/soc/tegra/fuse/tegra-apbmisc.c | 1 +
 1 file changed, 1 insertion(+)
drivers/soc/tegra/fuse/tegra-apbmisc.c +0 -0
index e5a4d8f98b10..c94dccf3eb30 100644

drivers/soc/tegra/fuse/tegra-apbmisc.c u8 tegra_get_chip_id(void) · line 57

Quoted 7 lines
drivers/soc/tegra/fuse/tegra-apbmisc.c +1 -0
@@ -51,6 +51,7 @@ u8 tegra_get_chip_id(void)
 {
 	return (tegra_read_chipid() >> 8) & 0xff;
 }
+EXPORT_SYMBOL_GPL(tegra_get_chip_id);
 
 u32 tegra_read_straps(void)
 {

A quick note.. I just recalled about existence of the of_machine_is_compatible() which will be more appropriate to use in the driver, hence this patch won't be needed.

author
#14 lore raw

RFC PATCH v2 3/17 dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30

In reply to Dmitry Osipenko

Add device-tree binding that describes CPU frequency-scaling hardware found on NVIDIA Tegra20/30 SoC's.

Signed-off-by Dmitry Osipenko <[email protected]>
---
 .../cpufreq/nvidia,tegra20-cpufreq.txt        | 96 +++++++++++++++++++
 1 file changed, 96 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt
Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt new file +96 -0
new file mode 100644
index 000000000000..a8023ea7a99f
@@ -0,0 +1,96 @@
+Binding for NVIDIA Tegra20 CPUFreq
+==================================
+
+Required properties:
+- clocks: Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
+- clock-names: Must include the following entries:
+  - pll_x: main-parent for CPU clock, must be the first entry
+  - intermediate: intermediate-parent for CPU clock
+  - cclk: the CPU clock
+- operating-points-v2: See ../bindings/opp/opp.txt for details.
+- #cooling-cells: Should be 2. See ../thermal/thermal.txt for details.
+
+For each opp entry in 'operating-points-v2' table:
+- opp-supported-hw: Two bitfields indicating:
+	On Tegra20:
+	1. CPU process ID mask
+	2. SoC speedo ID mask
+
+	On Tegra30:
+	1. CPU process ID mask
+	2. CPU speedo ID mask
+
+	A bitwise AND is performed against these values and if any bit
+	matches, the OPP gets enabled.
+
+- opp-microvolt: CPU voltage triplet.
+
+Optional properties:
+- cpu-supply: Phandle to the CPU power supply.
+- core-supply: Phandle to the CORE power supply.
+- rtc-supply: Phandle to the RTC power supply, required only for Tegra20.
+
+Voltage supply requirements:
+- Tegra20:
+	CORE and RTC regulators must be coupled using the regulator-coupled-with
+	property and regulator-coupled-max-spread property must be set to no
+	more than 170mV.
+
+	See ../regulator/regulator.txt for more detail about the properties.
+
+- Tegra30:
+	CORE and CPU regulators must be coupled using the regulator-coupled-with
+	property and regulator-coupled-max-spread property must be set to no
+	more than 300mV. Each of CORE and CPU regulators must set
+	regulator-max-step-microvolt property to no more than 100mV.
+
+	See ../regulator/regulator.txt for more detail about the properties.
+
+
+Example:
+	regulators {
+		cpu_reg: regulator0 {
+			regulator-name = "vdd_cpu";
+		};
+
+		core_reg: regulator1 {
+			regulator-name = "vdd_core";
+			regulator-coupled-with = <&rtc_reg>;
+			regulator-coupled-max-spread = <170000>;
+		};
+
+		rtc_reg: regulator2 {
+			regulator-name = "vdd_rtc";
+			regulator-coupled-with = <&core_reg>;
+			regulator-coupled-max-spread = <170000>;
+		};
+	};
+
+	cpu0_opp_table: opp_table0 {
+		compatible = "operating-points-v2";
+
+		opp@456000000 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <825000 825000 1125000>;
+			opp-supported-hw = <0x03 0x0001>;
+			opp-hz = /bits/ 64 <456000000>;
+		};
+
+		...
+	};
+
+	cpus {
+		cpu@0 {
+			compatible = "arm,cortex-a9";
+			clocks = <&tegra_car TEGRA20_CLK_PLL_X>,
+				 <&tegra_car TEGRA20_CLK_PLL_P>,
+				 <&tegra_car TEGRA20_CLK_CCLK>;
+			clock-names = "pll_x", "intermediate", "cclk";
+			operating-points-v2 = <&cpu0_opp_table>;
+			cpu-supply = <&cpu_reg>;
+			core-supply = <&core_reg>;
+			rtc-supply = <&rtc_reg>;
+			#cooling-cells = <2>;
+		};
+	};
Signature · 1 line
2.19.0
maintainer
#15 lore raw

Re: [RFC PATCH v2 03/17] dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30

Quoted 94 lines · Dmitry Osipenko

Add device-tree binding that describes CPU frequency-scaling hardware found on NVIDIA Tegra20/30 SoC's.

Signed-off-by Dmitry Osipenko <[email protected]>
---
 .../cpufreq/nvidia,tegra20-cpufreq.txt        | 96 +++++++++++++++++++
 1 file changed, 96 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt
Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt new file +79 -0
new file mode 100644
index 000000000000..a8023ea7a99f
@@ -0,0 +1,96 @@
+Binding for NVIDIA Tegra20 CPUFreq
+==================================
+
+Required properties:
+- clocks: Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
+- clock-names: Must include the following entries:
+  - pll_x: main-parent for CPU clock, must be the first entry
+  - intermediate: intermediate-parent for CPU clock
+  - cclk: the CPU clock
+- operating-points-v2: See ../bindings/opp/opp.txt for details.
+- #cooling-cells: Should be 2. See ../thermal/thermal.txt for details.
+
+For each opp entry in 'operating-points-v2' table:
+- opp-supported-hw: Two bitfields indicating:
+	On Tegra20:
+	1. CPU process ID mask
+	2. SoC speedo ID mask
+
+	On Tegra30:
+	1. CPU process ID mask
+	2. CPU speedo ID mask
+
+	A bitwise AND is performed against these values and if any bit
+	matches, the OPP gets enabled.
+
+- opp-microvolt: CPU voltage triplet.
+
+Optional properties:
+- cpu-supply: Phandle to the CPU power supply.
+- core-supply: Phandle to the CORE power supply.
+- rtc-supply: Phandle to the RTC power supply, required only for Tegra20.
+
+Voltage supply requirements:
+- Tegra20:
+	CORE and RTC regulators must be coupled using the regulator-coupled-with
+	property and regulator-coupled-max-spread property must be set to no
+	more than 170mV.
+
+	See ../regulator/regulator.txt for more detail about the properties.
+
+- Tegra30:
+	CORE and CPU regulators must be coupled using the regulator-coupled-with
+	property and regulator-coupled-max-spread property must be set to no
+	more than 300mV. Each of CORE and CPU regulators must set
+	regulator-max-step-microvolt property to no more than 100mV.
+
+	See ../regulator/regulator.txt for more detail about the properties.
+
+
+Example:
+	regulators {
+		cpu_reg: regulator0 {
+			regulator-name = "vdd_cpu";
+		};
+
+		core_reg: regulator1 {
+			regulator-name = "vdd_core";
+			regulator-coupled-with = <&rtc_reg>;
+			regulator-coupled-max-spread = <170000>;
+		};
+
+		rtc_reg: regulator2 {
+			regulator-name = "vdd_rtc";
+			regulator-coupled-with = <&core_reg>;
+			regulator-coupled-max-spread = <170000>;
+		};
+	};
+
+	cpu0_opp_table: opp_table0 {
+		compatible = "operating-points-v2";
+
+		opp@456000000 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <825000 825000 1125000>;
+			opp-supported-hw = <0x03 0x0001>;
+			opp-hz = /bits/ 64 <456000000>;
+		};
+

Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt line 89

Quoted 10 lines
Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt new file +10 -0
+		...
+	};
+
+	cpus {
+		cpu@0 {
+			compatible = "arm,cortex-a9";
+			clocks = <&tegra_car TEGRA20_CLK_PLL_X>,
+				 <&tegra_car TEGRA20_CLK_PLL_P>,
+				 <&tegra_car TEGRA20_CLK_CCLK>;
+			clock-names = "pll_x", "intermediate", "cclk";

I still object to having clocks (and supplies) which don't reflect the h/w and are documented in the CA9 TRM.

Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt line 93

Quoted 4 lines
Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt new file +4 -0
+			operating-points-v2 = <&cpu0_opp_table>;
+			cpu-supply = <&cpu_reg>;
+			core-supply = <&core_reg>;
+			rtc-supply = <&rtc_reg>;

Supplies are suspect too, but perhaps supplies and power domains are beyond the scope of the TRM and part of the physical design.

Rob

author
#16 lore raw

Re: [RFC PATCH v2 03/17] dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30

Quoted 109 lines · Rob Herring
Quoted 94 lines · Dmitry Osipenko

Add device-tree binding that describes CPU frequency-scaling hardware found on NVIDIA Tegra20/30 SoC's.

Signed-off-by Dmitry Osipenko <[email protected]>
---
 .../cpufreq/nvidia,tegra20-cpufreq.txt        | 96 +++++++++++++++++++
 1 file changed, 96 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt
Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt new file +79 -0
new file mode 100644
index 000000000000..a8023ea7a99f
@@ -0,0 +1,96 @@
+Binding for NVIDIA Tegra20 CPUFreq
+==================================
+
+Required properties:
+- clocks: Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
+- clock-names: Must include the following entries:
+  - pll_x: main-parent for CPU clock, must be the first entry
+  - intermediate: intermediate-parent for CPU clock
+  - cclk: the CPU clock
+- operating-points-v2: See ../bindings/opp/opp.txt for details.
+- #cooling-cells: Should be 2. See ../thermal/thermal.txt for details.
+
+For each opp entry in 'operating-points-v2' table:
+- opp-supported-hw: Two bitfields indicating:
+	On Tegra20:
+	1. CPU process ID mask
+	2. SoC speedo ID mask
+
+	On Tegra30:
+	1. CPU process ID mask
+	2. CPU speedo ID mask
+
+	A bitwise AND is performed against these values and if any bit
+	matches, the OPP gets enabled.
+
+- opp-microvolt: CPU voltage triplet.
+
+Optional properties:
+- cpu-supply: Phandle to the CPU power supply.
+- core-supply: Phandle to the CORE power supply.
+- rtc-supply: Phandle to the RTC power supply, required only for Tegra20.
+
+Voltage supply requirements:
+- Tegra20:
+	CORE and RTC regulators must be coupled using the regulator-coupled-with
+	property and regulator-coupled-max-spread property must be set to no
+	more than 170mV.
+
+	See ../regulator/regulator.txt for more detail about the properties.
+
+- Tegra30:
+	CORE and CPU regulators must be coupled using the regulator-coupled-with
+	property and regulator-coupled-max-spread property must be set to no
+	more than 300mV. Each of CORE and CPU regulators must set
+	regulator-max-step-microvolt property to no more than 100mV.
+
+	See ../regulator/regulator.txt for more detail about the properties.
+
+
+Example:
+	regulators {
+		cpu_reg: regulator0 {
+			regulator-name = "vdd_cpu";
+		};
+
+		core_reg: regulator1 {
+			regulator-name = "vdd_core";
+			regulator-coupled-with = <&rtc_reg>;
+			regulator-coupled-max-spread = <170000>;
+		};
+
+		rtc_reg: regulator2 {
+			regulator-name = "vdd_rtc";
+			regulator-coupled-with = <&core_reg>;
+			regulator-coupled-max-spread = <170000>;
+		};
+	};
+
+	cpu0_opp_table: opp_table0 {
+		compatible = "operating-points-v2";
+
+		opp@456000000 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <825000 825000 1125000>;
+			opp-supported-hw = <0x03 0x0001>;
+			opp-hz = /bits/ 64 <456000000>;
+		};
+

Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt line 89

Quoted 10 lines
Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt new file +10 -0
+		...
+	};
+
+	cpus {
+		cpu@0 {
+			compatible = "arm,cortex-a9";
+			clocks = <&tegra_car TEGRA20_CLK_PLL_X>,
+				 <&tegra_car TEGRA20_CLK_PLL_P>,
+				 <&tegra_car TEGRA20_CLK_CCLK>;
+			clock-names = "pll_x", "intermediate", "cclk";

I still object to having clocks (and supplies) which don't reflect the h/w and are documented in the CA9 TRM.

Quoted 7 lines

Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt line 93

Quoted 4 lines
Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt new file +4 -0
+			operating-points-v2 = <&cpu0_opp_table>;
+			cpu-supply = <&cpu_reg>;
+			core-supply = <&core_reg>;
+			rtc-supply = <&rtc_reg>;

Supplies are suspect too, but perhaps supplies and power domains are beyond the scope of the TRM and part of the physical design.

Is it possible to have a "firmware" device-tree node specifically for cpufreq driver? Something like this:

cpufreq {
	compatible = "nvidia,tegra20-cpufreq";
	clocks = <&tegra_car TEGRA20_CLK_PLL_X>,
		 <&tegra_car TEGRA20_CLK_PLL_P>;
	clock-names = "pll_x", "intermediate";
};

We may also need a Tegra-specific DVFS helper-driver that will help to manage CPU-CORE voltage dependency. Yet I'll have to examine this all in more details, but maybe it will be nicer if DVFS could be instantiated via device-tree as well. It will provide a Tegra-specific DVFS API and manage CORE / RTC dependencies for the CPUFreq and peripheral drivers, also helping to maintain proper voltages during kernel boot-up until all drivers are brought into action.

cpufreq {
	compatible = "nvidia,tegra20-dvfs";
	cpu-supply = <&cpu_vdd_reg>;
	core-supply = <&core_vdd_reg>;
	rtc-supply = <&rtc_vdd_reg>;
};

So my question is:

Is it possible to have device-tree nodes that solely describe firmware? Kernel drivers in this case.

author
#17 lore raw

RFC PATCH v2 4/17 cpufreq: tegra20: Support OPP, thermal cooling, DVFS and Tegra30

In reply to Dmitry Osipenko

Add support for thermal throttling, Operating Performance Points and DVFS. Driver now relies on OPP's supplied via device tree and therefore will work only on devices that use the updated device tree. The generalization of the driver allows to transparently support Tegra30.

Signed-off-by Dmitry Osipenko <[email protected]>
---
 drivers/cpufreq/Kconfig.arm          |   2 +
 drivers/cpufreq/cpufreq-dt-platdev.c |   2 +
 drivers/cpufreq/tegra20-cpufreq.c    | 832 +++++++++++++++++++++++----
 3 files changed, 734 insertions(+), 102 deletions(-)
drivers/cpufreq/Kconfig.arm +2 -0
index 0cd8eb76ad59..78795d108f5e 100644
@@ -262,7 +262,9 @@ config ARM_TANGO_CPUFREQ
 
 config ARM_TEGRA20_CPUFREQ
 	tristate "Tegra20 CPUFreq support"
+	depends on !CPU_THERMAL || THERMAL
 	depends on ARCH_TEGRA
+	select PM_OPP
 	default y
 	help
 	  This adds the CPUFreq driver support for Tegra20 SOCs.
drivers/cpufreq/cpufreq-dt-platdev.c +2 -0
index b1c5468dca16..ecc4d3d14850 100644
@@ -118,6 +118,8 @@ static const struct of_device_id blacklist[] __initconst = {
 	{ .compatible = "mediatek,mt8173", },
 	{ .compatible = "mediatek,mt8176", },
 
+	{ .compatible = "nvidia,tegra20", },
+	{ .compatible = "nvidia,tegra30", },
 	{ .compatible = "nvidia,tegra124", },
 
 	{ .compatible = "qcom,apq8096", },
drivers/cpufreq/tegra20-cpufreq.c +730 -102

950 lines not on this page · raw message

Signature · 1 line
2.19.0
author
#18 lore raw

RFC PATCH v2 5/17 ARM: tegra: Create tegra20-cpufreq device on Tegra30

In reply to Dmitry Osipenko

Tegra20-cpufreq driver require a platform device in order to be loaded, instantiate a simple platform device for the driver during of the machines late initialization. Driver now supports Tegra30 SoC's, hence create the device on Tegra30 machines.

Signed-off-by Dmitry Osipenko <[email protected]>
---
 arch/arm/mach-tegra/tegra.c | 4 ++++
 1 file changed, 4 insertions(+)
arch/arm/mach-tegra/tegra.c +4 -0
index 67d8ae60ac67..b559e22eab76 100644
@@ -111,6 +111,10 @@ static void __init tegra_dt_init_late(void)
 	if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) &&
 	    of_machine_is_compatible("nvidia,tegra20"))
 		platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0);
+
+	if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) &&
+	    of_machine_is_compatible("nvidia,tegra30"))
+		platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0);
 }
 
 static const char * const tegra_dt_board_compat[] = {
Signature · 1 line
2.19.0
author
#19 lore raw

RFC PATCH v2 6/17 ARM: dts: tegra20: Add CPU Operating Performance Points

In reply to Dmitry Osipenko

Add CPU's Operating Performance Points to the device tree, they are used by the CPUFreq driver and allow to setup thermal throttling for the boards by linking the cooling device (CPU) with thermal sensors via thermal-zones description.

Signed-off-by Dmitry Osipenko <[email protected]>
---
 arch/arm/boot/dts/tegra20.dtsi | 277 +++++++++++++++++++++++++++++++++
 1 file changed, 277 insertions(+)
arch/arm/boot/dts/tegra20.dtsi +277 -0
index 185cd074eeff..51ffb5d2b974 100644
@@ -859,6 +859,271 @@
 		status = "disabled";
 	};
 
+	cpu0_opp_table: opp_table0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@216000000_750 {
+			clock-latency-ns = <2000>;
+			opp-microvolt = <750000 750000 1125000>;
+			opp-supported-hw = <0xFF 0xFFFF>;
+			opp-hz = /bits/ 64 <216000000>;
+			opp-suspend;
+		};
+
+		opp@314000000_750 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <750000 750000 1125000>;
+			opp-supported-hw = <0x03 0x0001>;
+			opp-hz = /bits/ 64 <314000000>;
+		};
+
+		opp@380000000_750 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <750000 750000 1125000>;
+			opp-supported-hw = <0x01 0x0002>;
+			opp-hz = /bits/ 64 <380000000>;
+		};
+
+		opp@389000000_750 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <750000 750000 1125000>;
+			opp-supported-hw = <0x02 0x0002>;
+			opp-hz = /bits/ 64 <389000000>;
+		};
+
+		opp@456000000_825 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <825000 825000 1125000>;
+			opp-supported-hw = <0x03 0x0001>;
+			opp-hz = /bits/ 64 <456000000>;
+		};
+
+		opp@494000000_750 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <750000 750000 1125000>;
+			opp-supported-hw = <0x04 0x0001>;
+			opp-hz = /bits/ 64 <494000000>;
+		};
+
+		opp@503000000_800 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <800000 800000 1125000>;
+			opp-supported-hw = <0x03 0x0002>;
+			opp-hz = /bits/ 64 <503000000>;
+		};
+
+		opp@598000000_750 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <750000 750000 1125000>;
+			opp-supported-hw = <0x04 0x0002>;
+			opp-hz = /bits/ 64 <598000000>;
+		};
+
+		opp@608000000_900 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <900000 900000 1125000>;
+			opp-supported-hw = <0x01 0x0001>;
+			opp-hz = /bits/ 64 <608000000>;
+		};
+
+		opp@618000000_900 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <900000 900000 1125000>;
+			opp-supported-hw = <0x02 0x0001>;
+			opp-hz = /bits/ 64 <618000000>;
+		};
+
+		opp@655000000_850 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <850000 850000 1125000>;
+			opp-supported-hw = <0x03 0x0002>;
+			opp-hz = /bits/ 64 <655000000>;
+		};
+
+		opp@675000000_825 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <825000 825000 1125000>;
+			opp-supported-hw = <0x04 0x0001>;
+			opp-hz = /bits/ 64 <675000000>;
+		};
+
+		opp@730000000_750 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <750000 750000 1125000>;
+			opp-supported-hw = <0x08 0x0003>;
+			opp-hz = /bits/ 64 <730000000>;
+		};
+
+		opp@750000000_800 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <800000 800000 1125000>;
+			opp-supported-hw = <0x04 0x0002>;
+			opp-hz = /bits/ 64 <750000000>;
+		};
+
+		opp@760000000_775 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <775000 775000 1125000>;
+			opp-supported-hw = <0x08 0x0003>;
+			opp-hz = /bits/ 64 <760000000>;
+		};
+
+		opp@760000000_875 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <875000 875000 1125000>;
+			opp-supported-hw = <0x02 0x0002>;
+			opp-hz = /bits/ 64 <760000000>;
+		};
+
+		opp@760000000_975 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <975000 975000 1125000>;
+			opp-supported-hw = <0x01 0x0001>;
+			opp-hz = /bits/ 64 <760000000>;
+		};
+
+		opp@770000000_975 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <975000 975000 1125000>;
+			opp-supported-hw = <0x02 0x0001>;
+			opp-hz = /bits/ 64 <770000000>;
+		};
+
+		opp@798000000_900 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <900000 900000 1125000>;
+			opp-supported-hw = <0x03 0x0002>;
+			opp-hz = /bits/ 64 <798000000>;
+		};
+
+		opp@817000000_875 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <875000 875000 1125000>;
+			opp-supported-hw = <0x04 0x0001>;
+			opp-hz = /bits/ 64 <817000000>;
+		};
+
+		opp@817000000_1000 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <1000000 1000000 1125000>;
+			opp-supported-hw = <0x01 0x0001>;
+			opp-hz = /bits/ 64 <817000000>;
+		};
+
+		opp@827000000_1000 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <1000000 1000000 1125000>;
+			opp-supported-hw = <0x02 0x0001>;
+			opp-hz = /bits/ 64 <827000000>;
+		};
+
+		opp@845000000_800 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <800000 800000 1125000>;
+			opp-supported-hw = <0x08 0x0003>;
+			opp-hz = /bits/ 64 <845000000>;
+		};
+
+		opp@893000000_850 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <850000 850000 1125000>;
+			opp-supported-hw = <0x04 0x0002>;
+			opp-hz = /bits/ 64 <893000000>;
+		};
+
+		opp@902000000_950 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <950000 950000 1125000>;
+			opp-supported-hw = <0x01 0x0002>;
+			opp-hz = /bits/ 64 <902000000>;
+		};
+
+		opp@912000000_1050 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <1050000 1050000 1125000>;
+			opp-supported-hw = <0x01 0x0001>;
+			opp-hz = /bits/ 64 <912000000>;
+		};
+
+		opp@922000000_925 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <925000 925000 1125000>;
+			opp-supported-hw = <0x04 0x0001>;
+			opp-hz = /bits/ 64 <922000000>;
+		};
+
+		opp@922000000_1050 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <1050000 1050000 1125000>;
+			opp-supported-hw = <0x02 0x0001>;
+			opp-hz = /bits/ 64 <922000000>;
+		};
+
+		opp@940000000_850 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <850000 850000 1125000>;
+			opp-supported-hw = <0x08 0x0003>;
+			opp-hz = /bits/ 64 <940000000>;
+		};
+
+		opp@950000000_950 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <950000 950000 1125000>;
+			opp-supported-hw = <0x02 0x0002>;
+			opp-hz = /bits/ 64 <950000000>;
+		};
+
+		opp@960000000_1000 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <1000000 1000000 1125000>;
+			opp-supported-hw = <0x01 0x0002>;
+			opp-hz = /bits/ 64 <960000000>;
+		};
+
+		opp@1000000000_875 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <875000 875000 1125000>;
+			opp-supported-hw = <0x08 0x0003>;
+			opp-hz = /bits/ 64 <1000000000>;
+		};
+
+		opp@1000000000_900 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <900000 900000 1125000>;
+			opp-supported-hw = <0x04 0x0002>;
+			opp-hz = /bits/ 64 <1000000000>;
+		};
+
+		opp@1000000000_975 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <975000 975000 1125000>;
+			opp-supported-hw = <0x04 0x0001>;
+			opp-hz = /bits/ 64 <1000000000>;
+		};
+
+		opp@1000000000_1000 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <1000000 1000000 1125000>;
+			opp-supported-hw = <0x02 0x0002>;
+			opp-hz = /bits/ 64 <1000000000>;
+		};
+
+		opp@1000000000_1025 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <1025000 1025000 1125000>;
+			opp-supported-hw = <0x01 0x0002>;
+			opp-hz = /bits/ 64 <1000000000>;
+		};
+
+		opp@1000000000_1100 {
+			clock-latency-ns = <125000>;
+			opp-microvolt = <1100000 1100000 1125000>;
+			opp-supported-hw = <0x03 0x0001>;
+			opp-hz = /bits/ 64 <1000000000>;
+		};
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;

@@ -867,12 +1132,24 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <0>;
+			clocks = <&tegra_car TEGRA20_CLK_PLL_X>,
+				 <&tegra_car TEGRA20_CLK_PLL_P>,
+				 <&tegra_car TEGRA20_CLK_CCLK>;
+			clock-names = "pll_x", "intermediate", "cclk";
+			operating-points-v2 = <&cpu0_opp_table>;
+			#cooling-cells = <2>;
 		};
 
 		cpu@1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <1>;
+			clocks = <&tegra_car TEGRA20_CLK_PLL_X>,
+				 <&tegra_car TEGRA20_CLK_PLL_P>,
+				 <&tegra_car TEGRA20_CLK_CCLK>;
+			clock-names = "pll_x", "intermediate", "cclk";
+			operating-points-v2 = <&cpu0_opp_table>;
+			#cooling-cells = <2>;
 		};
 	};
Signature · 1 line
2.19.0
author
#20 lore raw

RFC PATCH v2 7/17 ARM: dts: tegra30: Add CPU Operating Performance Points

In reply to Dmitry Osipenko

Add CPU's Operating Performance Points to the device tree, they are used by the CPUFreq driver and allow to setup thermal throttling for the boards by linking the cooling device (CPU) with thermal sensors via thermal-zones description.

Signed-off-by Dmitry Osipenko <[email protected]>
---
 arch/arm/boot/dts/tegra30.dtsi | 688 +++++++++++++++++++++++++++++++++
 1 file changed, 688 insertions(+)
arch/arm/boot/dts/tegra30.dtsi +688 -0
index 790d3fa7e6d2..0aefc8d9efab 100644
@@ -980,6 +980,670 @@
 		status = "disabled";
 	};
 
+	cpu0_opp_table: opp_table0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@408000000_800 {
+			clock-latency-ns = <2000>;
+			opp-microvolt = <800000 800000 1250000>;
+			opp-supported-hw = <0xFF 0xFFFF>;
+			opp-hz = /bits/ 64 <408000000>;
+			opp-suspend;
+		};
+
+		opp@460000000_800 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <800000 800000 1250000>;
+			opp-supported-hw = <0x01 0x0192>;
+			opp-hz = /bits/ 64 <460000000>;
+		};
+
+		opp@480000000_800 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <800000 800000 1250000>;
+			opp-supported-hw = <0x02 0x019E>;
+			opp-hz = /bits/ 64 <480000000>;
+		};
+
+		opp@520000000_800 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <800000 800000 1250000>;
+			opp-supported-hw = <0x04 0x019E>;
+			opp-hz = /bits/ 64 <520000000>;
+		};
+
+		opp@550000000_800 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <800000 800000 1250000>;
+			opp-supported-hw = <0x18 0x31FE>;
+			opp-hz = /bits/ 64 <550000000>;
+		};
+
+		opp@550000000_850 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <850000 850000 1250000>;
+			opp-supported-hw = <0x01 0x0192>;
+			opp-hz = /bits/ 64 <550000000>;
+		};
+
+		opp@600000000_850 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <850000 850000 1250000>;
+			opp-supported-hw = <0x1F 0x0800>;
+			opp-hz = /bits/ 64 <600000000>;
+		};
+
+		opp@650000000_850 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <850000 850000 1250000>;
+			opp-supported-hw = <0x02 0x019E>;
+			opp-hz = /bits/ 64 <650000000>;
+		};
+
+		opp@680000000_900 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <900000 900000 1250000>;
+			opp-supported-hw = <0x01 0x0192>;
+			opp-hz = /bits/ 64 <680000000>;
+		};
+
+		opp@684000000_850 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <850000 850000 1250000>;
+			opp-supported-hw = <0x01 0x0001>;
+			opp-hz = /bits/ 64 <684000000>;
+		};
+
+		opp@700000000_850 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <850000 850000 1250000>;
+			opp-supported-hw = <0x04 0x019E>;
+			opp-hz = /bits/ 64 <700000000>;
+		};
+
+		opp@770000000_850 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <850000 850000 1250000>;
+			opp-supported-hw = <0x18 0x31FE>;
+			opp-hz = /bits/ 64 <770000000>;
+		};
+
+		opp@780000000_900 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <900000 900000 1250000>;
+			opp-supported-hw = <0x02 0x019E>;
+			opp-hz = /bits/ 64 <780000000>;
+		};
+
+		opp@807000000_850 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <850000 850000 1250000>;
+			opp-supported-hw = <0x02 0x0001>;
+			opp-hz = /bits/ 64 <807000000>;
+		};
+
+		opp@817000000_900 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <900000 900000 1250000>;
+			opp-supported-hw = <0x01 0x0001>;
+			opp-hz = /bits/ 64 <817000000>;
+		};
+
+		opp@820000000_975 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <975000 975000 1250000>;
+			opp-supported-hw = <0x01 0x0192>;
+			opp-hz = /bits/ 64 <820000000>;
+		};
+
+		opp@860000000_900 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <900000 900000 1250000>;
+			opp-supported-hw = <0x04 0x019E>;
+			opp-hz = /bits/ 64 <860000000>;
+		};
+
+		opp@883000000_850 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <850000 850000 1250000>;
+			opp-supported-hw = <0x04 0x0001>;
+			opp-hz = /bits/ 64 <883000000>;
+		};
+
+		opp@900000000_850 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <850000 850000 1250000>;
+			opp-supported-hw = <0x1F 0x0400>;
+			opp-hz = /bits/ 64 <900000000>;
+		};
+
+		opp@900000000_912 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <912000 912000 1250000>;
+			opp-supported-hw = <0x1F 0x0200>;
+			opp-hz = /bits/ 64 <900000000>;
+		};
+
+		opp@910000000_900 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <900000 900000 1250000>;
+			opp-supported-hw = <0x08 0x31FE>;
+			opp-hz = /bits/ 64 <910000000>;
+		};
+
+		opp@931000000_850 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <850000 850000 1250000>;
+			opp-supported-hw = <0x08 0x0001>;
+			opp-hz = /bits/ 64 <931000000>;
+		};
+
+		opp@940000000_900 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <900000 900000 1250000>;
+			opp-supported-hw = <0x10 0x31E0>;
+			opp-hz = /bits/ 64 <940000000>;
+		};
+
+		opp@948000000_900 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <900000 900000 1250000>;
+			opp-supported-hw = <0x02 0x0001>;
+			opp-hz = /bits/ 64 <948000000>;
+		};
+
+		opp@970000000_1000 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1000000 1000000 1250000>;
+			opp-supported-hw = <0x01 0x0192>;
+			opp-hz = /bits/ 64 <970000000>;
+		};
+
+		opp@990000000_975 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <975000 975000 1250000>;
+			opp-supported-hw = <0x02 0x019E>;
+			opp-hz = /bits/ 64 <990000000>;
+		};
+
+		opp@1026000000_975 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <975000 975000 1250000>;
+			opp-supported-hw = <0x01 0x0001>;
+			opp-hz = /bits/ 64 <1026000000>;
+		};
+
+		opp@1039000000_900 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <900000 900000 1250000>;
+			opp-supported-hw = <0x04 0x0001>;
+			opp-hz = /bits/ 64 <1039000000>;
+		};
+
+		opp@1040000000_1000 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1000000 1000000 1250000>;
+			opp-supported-hw = <0x02 0x019E>;
+			opp-hz = /bits/ 64 <1040000000>;
+		};
+
+		opp@1040000000_1025 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1025000 1025000 1250000>;
+			opp-supported-hw = <0x01 0x0192>;
+			opp-hz = /bits/ 64 <1040000000>;
+		};
+
+		opp@1050000000_975 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <975000 975000 1250000>;
+			opp-supported-hw = <0x04 0x019E>;
+			opp-hz = /bits/ 64 <1050000000>;
+		};
+
+		opp@1080000000_1050 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1050000 1050000 1250000>;
+			opp-supported-hw = <0x01 0x0192>;
+			opp-hz = /bits/ 64 <1080000000>;
+		};
+
+		opp@1100000000_1025 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1025000 1025000 1250000>;
+			opp-supported-hw = <0x02 0x019E>;
+			opp-hz = /bits/ 64 <1100000000>;
+		};
+
+		opp@1102000000_900 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <900000 900000 1250000>;
+			opp-supported-hw = <0x08 0x0001>;
+			opp-hz = /bits/ 64 <1102000000>;
+		};
+
+		opp@1102000000_1000 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1000000 1000000 1250000>;
+			opp-supported-hw = <0x01 0x0001>;
+			opp-hz = /bits/ 64 <1102000000>;
+		};
+
+		opp@1117000000_975 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <975000 975000 1250000>;
+			opp-supported-hw = <0x02 0x0001>;
+			opp-hz = /bits/ 64 <1117000000>;
+		};
+
+		opp@1149000000_1025 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1025000 1025000 1250000>;
+			opp-supported-hw = <0x01 0x0001>;
+			opp-hz = /bits/ 64 <1149000000>;
+		};
+
+		opp@1150000000_975 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <975000 975000 1250000>;
+			opp-supported-hw = <0x08 0x31FE>;
+			opp-hz = /bits/ 64 <1150000000>;
+		};
+
+		opp@1150000000_1000 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1000000 1000000 1250000>;
+			opp-supported-hw = <0x04 0x019E>;
+			opp-hz = /bits/ 64 <1150000000>;
+		};
+
+		opp@1150000000_1075 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1075000 1075000 1250000>;
+			opp-supported-hw = <0x01 0x0192>;
+			opp-hz = /bits/ 64 <1150000000>;
+		};
+
+		opp@1160000000_975 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <975000 975000 1250000>;
+			opp-supported-hw = <0x10 0x31E0>;
+			opp-hz = /bits/ 64 <1160000000>;
+		};
+
+		opp@1171000000_1000 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1000000 1000000 1250000>;
+			opp-supported-hw = <0x02 0x0001>;
+			opp-hz = /bits/ 64 <1171000000>;
+		};
+
+		opp@1178000000_975 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <975000 975000 1250000>;
+			opp-supported-hw = <0x04 0x0001>;
+			opp-hz = /bits/ 64 <1178000000>;
+		};
+
+		opp@1187000000_1050 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1050000 1050000 1250000>;
+			opp-supported-hw = <0x01 0x0001>;
+			opp-hz = /bits/ 64 <1187000000>;
+		};
+
+		opp@1200000000_1025 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1025000 1025000 1250000>;
+			opp-supported-hw = <0x04 0x019E>;
+			opp-hz = /bits/ 64 <1200000000>;
+		};
+
+		opp@1200000000_1050 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1050000 1050000 1250000>;
+			opp-supported-hw = <0x02 0x019E>;
+			opp-hz = /bits/ 64 <1200000000>;
+		};
+
+		opp@1200000000_1100 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1100000 1100000 1250000>;
+			opp-supported-hw = <0x01 0x0192>;
+			opp-hz = /bits/ 64 <1200000000>;
+		};
+
+		opp@1206000000_1000 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1000000 1000000 1250000>;
+			opp-supported-hw = <0x04 0x0001>;
+			opp-hz = /bits/ 64 <1206000000>;
+		};
+
+		opp@1206000000_1025 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1025000 1025000 1250000>;
+			opp-supported-hw = <0x02 0x0001>;
+			opp-hz = /bits/ 64 <1206000000>;
+		};
+
+		opp@1216000000_975 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <975000 975000 1250000>;
+			opp-supported-hw = <0x08 0x0001>;
+			opp-hz = /bits/ 64 <1216000000>;
+		};
+
+		opp@1225000000_1075 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1075000 1075000 1250000>;
+			opp-supported-hw = <0x01 0x0001>;
+			opp-hz = /bits/ 64 <1225000000>;
+		};
+
+		opp@1230000000_1000 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1000000 1000000 1250000>;
+			opp-supported-hw = <0x08 0x31FE>;
+			opp-hz = /bits/ 64 <1230000000>;
+		};
+
+		opp@1240000000_1000 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1000000 1000000 1250000>;
+			opp-supported-hw = <0x10 0x3060>;
+			opp-hz = /bits/ 64 <1240000000>;
+		};
+
+		opp@1240000000_1125 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1125000 1125000 1250000>;
+			opp-supported-hw = <0x01 0x0010>;
+			opp-hz = /bits/ 64 <1240000000>;
+		};
+
+		opp@1250000000_1075 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1075000 1075000 1250000>;
+			opp-supported-hw = <0x02 0x001C>;
+			opp-hz = /bits/ 64 <1250000000>;
+		};
+
+		opp@1280000000_1025 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1025000 1025000 1250000>;
+			opp-supported-hw = <0x18 0x307C>;
+			opp-hz = /bits/ 64 <1280000000>;
+		};
+
+		opp@1280000000_1050 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1050000 1050000 1250000>;
+			opp-supported-hw = <0x04 0x001C>;
+			opp-hz = /bits/ 64 <1280000000>;
+		};
+
+		opp@1280000000_1125 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1125000 1125000 1250000>;
+			opp-supported-hw = <0x01 0x0182>;
+			opp-hz = /bits/ 64 <1280000000>;
+		};
+
+		opp@1280000000_1150 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1150000 1150000 1250000>;
+			opp-supported-hw = <0x01 0x0010>;
+			opp-hz = /bits/ 64 <1280000000>;
+		};
+
+		opp@1282000000_1100 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1100000 1100000 1250000>;
+			opp-supported-hw = <0x01 0x0001>;
+			opp-hz = /bits/ 64 <1282000000>;
+		};
+
+		opp@1300000000_1000 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1000000 1000000 1250000>;
+			opp-supported-hw = <0x18 0x0181>;
+			opp-hz = /bits/ 64 <1300000000>;
+		};
+
+		opp@1300000000_1025 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1025000 1025000 1250000>;
+			opp-supported-hw = <0x0C 0x0183>;
+			opp-hz = /bits/ 64 <1300000000>;
+		};
+
+		opp@1300000000_1050 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1050000 1050000 1250000>;
+			opp-supported-hw = <0x0E 0x018F>;
+			opp-hz = /bits/ 64 <1300000000>;
+		};
+
+		opp@1300000000_1075 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1075000 1075000 1250000>;
+			opp-supported-hw = <0x06 0x019E>;
+			opp-hz = /bits/ 64 <1300000000>;
+		};
+
+		opp@1300000000_1100 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1100000 1100000 1250000>;
+			opp-supported-hw = <0x02 0x001C>;
+			opp-hz = /bits/ 64 <1300000000>;
+		};
+
+		opp@1300000000_1125 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1125000 1125000 1250000>;
+			opp-supported-hw = <0x01 0x0001>;
+			opp-hz = /bits/ 64 <1300000000>;
+		};
+
+		opp@1300000000_1150 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1150000 1150000 1250000>;
+			opp-supported-hw = <0x01 0x0182>;
+			opp-hz = /bits/ 64 <1300000000>;
+		};
+
+		opp@1320000000_1175 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1175000 1175000 1250000>;
+			opp-supported-hw = <0x01 0x0010>;
+			opp-hz = /bits/ 64 <1320000000>;
+		};
+
+		opp@1330000000_1050 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1050000 1050000 1250000>;
+			opp-supported-hw = <0x08 0x3070>;
+			opp-hz = /bits/ 64 <1330000000>;
+		};
+
+		opp@1330000000_1125 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1125000 1125000 1250000>;
+			opp-supported-hw = <0x02 0x001C>;
+			opp-hz = /bits/ 64 <1330000000>;
+		};
+
+		opp@1340000000_1100 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1100000 1100000 1250000>;
+			opp-supported-hw = <0x04 0x0010>;
+			opp-hz = /bits/ 64 <1340000000>;
+		};
+
+		opp@1350000000_1075 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1075000 1075000 1250000>;
+			opp-supported-hw = <0x08 0x000C>;
+			opp-hz = /bits/ 64 <1350000000>;
+		};
+
+		opp@1350000000_1100 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1100000 1100000 1250000>;
+			opp-supported-hw = <0x04 0x000C>;
+			opp-hz = /bits/ 64 <1350000000>;
+		};
+
+		opp@1360000000_1050 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1050000 1050000 1250000>;
+			opp-supported-hw = <0x10 0x3060>;
+			opp-hz = /bits/ 64 <1360000000>;
+		};
+
+		opp@1360000000_1150 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1150000 1150000 1250000>;
+			opp-supported-hw = <0x02 0x0010>;
+			opp-hz = /bits/ 64 <1360000000>;
+		};
+
+		opp@1360000000_1200 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1200000 1200000 1250000>;
+			opp-supported-hw = <0x01 0x0010>;
+			opp-hz = /bits/ 64 <1360000000>;
+		};
+
+		opp@1370000000_1075 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1075000 1075000 1250000>;
+			opp-supported-hw = <0x08 0x3070>;
+			opp-hz = /bits/ 64 <1370000000>;
+		};
+
+		opp@1380000000_1125 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1125000 1125000 1250000>;
+			opp-supported-hw = <0x04 0x0010>;
+			opp-hz = /bits/ 64 <1380000000>;
+		};
+
+		opp@1390000000_1075 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1075000 1075000 1250000>;
+			opp-supported-hw = <0x10 0x3060>;
+			opp-hz = /bits/ 64 <1390000000>;
+		};
+
+		opp@1400000000_1100 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1100000 1100000 1250000>;
+			opp-supported-hw = <0x08 0x307C>;
+			opp-hz = /bits/ 64 <1400000000>;
+		};
+
+		opp@1400000000_1125 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1125000 1125000 1250000>;
+			opp-supported-hw = <0x04 0x000C>;
+			opp-hz = /bits/ 64 <1400000000>;
+		};
+
+		opp@1400000000_1150 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1150000 1150000 1250000>;
+			opp-supported-hw = <0x02 0x000C>;
+			opp-hz = /bits/ 64 <1400000000>;
+		};
+
+		opp@1400000000_1175 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1175000 1175000 1250000>;
+			opp-supported-hw = <0x02 0x0010>;
+			opp-hz = /bits/ 64 <1400000000>;
+		};
+
+		opp@1470000000_1100 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1100000 1100000 1250000>;
+			opp-supported-hw = <0x10 0x3060>;
+			opp-hz = /bits/ 64 <1470000000>;
+		};
+
+		opp@1470000000_1125 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1125000 1125000 1250000>;
+			opp-supported-hw = <0x08 0x3060>;
+			opp-hz = /bits/ 64 <1470000000>;
+		};
+
+		opp@1500000000_1125 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1125000 1125000 1250000>;
+			opp-supported-hw = <0x18 0x3070>;
+			opp-hz = /bits/ 64 <1500000000>;
+		};
+
+		opp@1500000000_1150 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1150000 1150000 1250000>;
+			opp-supported-hw = <0x0C 0x3070>;
+			opp-hz = /bits/ 64 <1500000000>;
+		};
+
+		opp@1500000000_1200 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1200000 1200000 1250000>;
+			opp-supported-hw = <0x02 0x0010>;
+			opp-hz = /bits/ 64 <1500000000>;
+		};
+
+		opp@1500000000_1237 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1237000 1237000 1250000>;
+			opp-supported-hw = <0x01 0x0010>;
+			opp-hz = /bits/ 64 <1500000000>;
+		};
+
+		opp@1520000000_1150 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1150000 1150000 1250000>;
+			opp-supported-hw = <0x10 0x3060>;
+			opp-hz = /bits/ 64 <1520000000>;
+		};
+
+		opp@1540000000_1200 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1200000 1200000 1250000>;
+			opp-supported-hw = <0x08 0x3060>;
+			opp-hz = /bits/ 64 <1540000000>;
+		};
+
+		opp@1590000000_1200 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1200000 1200000 1250000>;
+			opp-supported-hw = <0x10 0x3060>;
+			opp-hz = /bits/ 64 <1590000000>;
+		};
+
+		opp@1700000000_1212 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1212000 1212000 1250000>;
+			opp-supported-hw = <0x10 0x3060>;
+			opp-hz = /bits/ 64 <1700000000>;
+		};
+
+		opp@1700000000_1237 {
+			clock-latency-ns = <50000>;
+			opp-microvolt = <1237000 1237000 1250000>;
+			opp-supported-hw = <0x08 0x3060>;
+			opp-hz = /bits/ 64 <1700000000>;
+		};
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;

@@ -988,24 +1652,48 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <0>;
+			clocks = <&tegra_car TEGRA30_CLK_PLL_X>,
+				 <&tegra_car TEGRA30_CLK_PLL_P>,
+				 <&tegra_car TEGRA30_CLK_CCLK_G>;
+			clock-names = "pll_x", "intermediate", "cclk";
+			operating-points-v2 = <&cpu0_opp_table>;
+			#cooling-cells = <2>;
 		};
 
 		cpu@1 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <1>;
+			clocks = <&tegra_car TEGRA30_CLK_PLL_X>,
+				 <&tegra_car TEGRA30_CLK_PLL_P>,
+				 <&tegra_car TEGRA30_CLK_CCLK_G>;
+			clock-names = "pll_x", "intermediate", "cclk";
+			operating-points-v2 = <&cpu0_opp_table>;
+			#cooling-cells = <2>;
 		};
 
 		cpu@2 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <2>;
+			clocks = <&tegra_car TEGRA30_CLK_PLL_X>,
+				 <&tegra_car TEGRA30_CLK_PLL_P>,
+				 <&tegra_car TEGRA30_CLK_CCLK_G>;
+			clock-names = "pll_x", "intermediate", "cclk";
+			operating-points-v2 = <&cpu0_opp_table>;
+			#cooling-cells = <2>;
 		};
 
 		cpu@3 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a9";
 			reg = <3>;
+			clocks = <&tegra_car TEGRA30_CLK_PLL_X>,
+				 <&tegra_car TEGRA30_CLK_PLL_P>,
+				 <&tegra_car TEGRA30_CLK_CCLK_G>;
+			clock-names = "pll_x", "intermediate", "cclk";
+			operating-points-v2 = <&cpu0_opp_table>;
+			#cooling-cells = <2>;
 		};
 	};
Signature · 1 line
2.19.0
author
#21 lore raw

RFC PATCH v2 8/17 ARM: dts: tegra20: colibri: Setup voltage regulators for DVFS

In reply to Dmitry Osipenko

Set min/max regulators voltage and add CPU node that hooks up CPU with voltage regulators.

Signed-off-by Dmitry Osipenko <[email protected]>
---
 arch/arm/boot/dts/tegra20-colibri.dtsi | 31 ++++++++++++++++++--------
 1 file changed, 22 insertions(+), 9 deletions(-)
arch/arm/boot/dts/tegra20-colibri.dtsi +22 -9
index 6162d193e12c..5b3155dbf47a 100644
@@ -495,17 +495,19 @@
 					regulator-always-on;
 				};
 
-				sm0 {
+				core_vdd_reg: sm0 {
 					regulator-name = "VDD_CORE_1.2V";
-					regulator-min-microvolt = <1200000>;
-					regulator-max-microvolt = <1200000>;
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1300000>;
+					regulator-coupled-with = <&rtc_vdd_reg>;
+					regulator-coupled-max-spread = <150000>;
 					regulator-always-on;
 				};
 
-				sm1 {
+				cpu_vdd_reg: sm1 {
 					regulator-name = "VDD_CPU_1.0V";
-					regulator-min-microvolt = <1000000>;
-					regulator-max-microvolt = <1000000>;
+					regulator-min-microvolt = <750000>;
+					regulator-max-microvolt = <1125000>;
 					regulator-always-on;
 				};
 

@@ -530,10 +532,13 @@
 					regulator-always-on;
 				};
 
-				ldo2 {
+				rtc_vdd_reg: ldo2 {
 					regulator-name = "VDD_RTC_1.2V";
-					regulator-min-microvolt = <1200000>;
-					regulator-max-microvolt = <1200000>;
+					regulator-min-microvolt = <950000>;
+					regulator-max-microvolt = <1300000>;
+					regulator-coupled-with = <&core_vdd_reg>;
+					regulator-coupled-max-spread = <150000>;
+					regulator-always-on;
 				};
 
 				/* LDO3 is not connected to anything */

@@ -740,6 +745,14 @@
 			 <&tegra_car TEGRA20_CLK_CDEV1>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
 	};
+
+	cpus {
+		cpu0: cpu@0 {
+			cpu-supply = <&cpu_vdd_reg>;
+			core-supply = <&core_vdd_reg>;
+			rtc-supply = <&rtc_vdd_reg>;
+		};
+	};
 };
 
 &gpio {
Signature · 1 line
2.19.0
author
#22 lore raw

RFC PATCH v2 9/17 ARM: dts: tegra20: harmony: Setup voltage regulators for DVFS

In reply to Dmitry Osipenko

Set min/max regulators voltage and add CPU node that hooks up CPU with voltage regulators.

Signed-off-by Dmitry Osipenko <[email protected]>
---
 arch/arm/boot/dts/tegra20-harmony.dts | 31 +++++++++++++++++++--------
 1 file changed, 22 insertions(+), 9 deletions(-)
arch/arm/boot/dts/tegra20-harmony.dts +22 -9
index 1d96d92b72a7..9d720743fd4e 100644
@@ -339,17 +339,19 @@
 					regulator-always-on;
 				};
 
-				sm0 {
+				core_vdd_reg: sm0 {
 					regulator-name = "vdd_sm0,vdd_core";
-					regulator-min-microvolt = <1200000>;
-					regulator-max-microvolt = <1200000>;
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1300000>;
+					regulator-coupled-with = <&rtc_vdd_reg>;
+					regulator-coupled-max-spread = <150000>;
 					regulator-always-on;
 				};
 
-				sm1 {
+				cpu_vdd_reg: sm1 {
 					regulator-name = "vdd_sm1,vdd_cpu";
-					regulator-min-microvolt = <1000000>;
-					regulator-max-microvolt = <1000000>;
+					regulator-min-microvolt = <750000>;
+					regulator-max-microvolt = <1125000>;
 					regulator-always-on;
 				};
 

@@ -373,10 +375,13 @@
 					regulator-always-on;
 				};
 
-				ldo2 {
+				rtc_vdd_reg: ldo2 {
 					regulator-name = "vdd_ldo2,vdd_rtc";
-					regulator-min-microvolt = <1200000>;
-					regulator-max-microvolt = <1200000>;
+					regulator-min-microvolt = <950000>;
+					regulator-max-microvolt = <1300000>;
+					regulator-coupled-with = <&core_vdd_reg>;
+					regulator-coupled-max-spread = <150000>;
+					regulator-always-on;
 				};
 
 				ldo3 {

@@ -779,4 +784,12 @@
 			 <&tegra_car TEGRA20_CLK_CDEV1>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
 	};
+
+	cpus {
+		cpu0: cpu@0 {
+			cpu-supply = <&cpu_vdd_reg>;
+			core-supply = <&core_vdd_reg>;
+			rtc-supply = <&rtc_vdd_reg>;
+		};
+	};
 };
Signature · 1 line
2.19.0
#23 lore raw

Re: [RFC PATCH v2 09/17] ARM: dts: tegra20: harmony: Setup voltage regulators for DVFS

Quoted 6 lines · Dmitry Osipenko

Set min/max regulators voltage and add CPU node that hooks up CPU with voltage regulators.

arch/arm/boot/dts/tegra20-harmony.dts +0 -1
 
-				sm0 {

arch/arm/boot/dts/tegra20-harmony.dts line 349

Quoted 10 lines
arch/arm/boot/dts/tegra20-harmony.dts +5 -2
+				core_vdd_reg: sm0 {
  					regulator-name = "vdd_sm0,vdd_core";
-					regulator-min-microvolt = <1200000>;
-					regulator-max-microvolt = <1200000>;
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1300000>;
+					regulator-coupled-with = <&rtc_vdd_reg>;
+					regulator-coupled-max-spread = <150000>;
  					regulator-always-on;
  				};

How do you know for sure that these increased ranges are safe (high end) and stable (low end) for this particular board? IIRC the safe/legal range depends on the chip SKU, and to be honest I have no idea which SKU is present on Harmony... For public boards like Colibri I imagine there's enough information out there to tell what will work, but maybe not our internal boards like Harmony, unless you checked our ancient downstream kernels?

author
#24 lore raw

Re: [RFC PATCH v2 09/17] ARM: dts: tegra20: harmony: Setup voltage regulators for DVFS

Quoted 18 lines · Stephen Warren
Quoted 8 lines · Dmitry Osipenko

Set min/max regulators voltage and add CPU node that hooks up CPU with voltage regulators.

arch/arm/boot/dts/tegra20-harmony.dts +1 -1
 
-                sm0 {
+                core_vdd_reg: sm0 {

                      regulator-name = "vdd_sm0,vdd_core";

Quoted 8 lines

-                    regulator-min-microvolt = <1200000>; -                    regulator-max-microvolt = <1200000>; +                    regulator-min-microvolt = <1000000>; +                    regulator-max-microvolt = <1300000>; +                    regulator-coupled-with = <&rtc_vdd_reg>; +                    regulator-coupled-max-spread = <150000>; regulator-always-on;
                  };

Quoted 1 line

How do you know for sure that these increased ranges are safe (high end) and stable (low end) for this particular board? IIRC the safe/legal range depends on the chip SKU, and to be honest I have no idea which SKU is present on Harmony... For public boards like Colibri I imagine there's enough information out there to tell what will work, but maybe not our internal boards like Harmony, unless you checked our ancient downstream kernels?

Yes, the ranges could be inaccurate in these DT patches. But it shouldn't matter much because only OPP's that match actual HW SKU will be used for DVFS. Though certainly it will be nice if we could specify exactly correct ranges.

Looks like downstream doesn't specify safe ranges for any of the boards and it is relying on the SKU-VOLTAGE DVFS table values only.

For now there are quite few obstacles that need to be resolved in order to get a properly working system-wide DVFS, but things are getting a bit closer. Thank you very much for your input!

author
#25 lore raw

RFC PATCH v2 10/17 ARM: dts: tegra20: paz00: Setup voltage regulators for DVFS

In reply to Dmitry Osipenko

Set min/max regulators voltage and add CPU node that hooks up CPU with voltage regulators.

Signed-off-by Dmitry Osipenko <[email protected]>
---
 arch/arm/boot/dts/tegra20-paz00.dts | 31 ++++++++++++++++++++---------
 1 file changed, 22 insertions(+), 9 deletions(-)
arch/arm/boot/dts/tegra20-paz00.dts +22 -9
index 8861e0976e37..51a09ae99f3a 100644
@@ -337,17 +337,19 @@
 					regulator-always-on;
 				};
 
-				sm0 {
+				core_vdd_reg: sm0 {
 					regulator-name = "+1.2vs_sm0,vdd_core";
-					regulator-min-microvolt = <1200000>;
-					regulator-max-microvolt = <1200000>;
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1300000>;
+					regulator-coupled-with = <&rtc_vdd_reg>;
+					regulator-coupled-max-spread = <150000>;
 					regulator-always-on;
 				};
 
-				sm1 {
+				cpu_vdd_reg: sm1 {
 					regulator-name = "+1.0vs_sm1,vdd_cpu";
-					regulator-min-microvolt = <1000000>;
-					regulator-max-microvolt = <1000000>;
+					regulator-min-microvolt = <750000>;
+					regulator-max-microvolt = <1125000>;
 					regulator-always-on;
 				};
 

@@ -367,10 +369,13 @@
 					regulator-always-on;
 				};
 
-				ldo2 {
+				rtc_vdd_reg: ldo2 {
 					regulator-name = "+1.2vs_ldo2,vdd_rtc";
-					regulator-min-microvolt = <1200000>;
-					regulator-max-microvolt = <1200000>;
+					regulator-min-microvolt = <950000>;
+					regulator-max-microvolt = <1300000>;
+					regulator-coupled-with = <&core_vdd_reg>;
+					regulator-coupled-max-spread = <150000>;
+					regulator-always-on;
 				};
 
 				ldo3 {

@@ -603,4 +608,12 @@
 			 <&tegra_car TEGRA20_CLK_CDEV1>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
 	};
+
+	cpus {
+		cpu0: cpu@0 {
+			cpu-supply = <&cpu_vdd_reg>;
+			core-supply = <&core_vdd_reg>;
+			rtc-supply = <&rtc_vdd_reg>;
+		};
+	};
 };
Signature · 1 line
2.19.0
author
#26 lore raw

RFC PATCH v2 11/17 ARM: dts: tegra20: seaboard: Setup voltage regulators for DVFS

In reply to Dmitry Osipenko

Set min/max regulators voltage and add CPU node that hooks up CPU with voltage regulators.

Signed-off-by Dmitry Osipenko <[email protected]>
---
 arch/arm/boot/dts/tegra20-seaboard.dts | 27 +++++++++++++++++++-------
 1 file changed, 20 insertions(+), 7 deletions(-)
arch/arm/boot/dts/tegra20-seaboard.dts +20 -7
index f91441683aad..85bf7e89ebbe 100644
@@ -444,16 +444,18 @@
 					regulator-always-on;
 				};
 
-				sm0 {
+				core_vdd_reg: sm0 {
 					regulator-name = "vdd_sm0,vdd_core";
-					regulator-min-microvolt = <1300000>;
+					regulator-min-microvolt = <1000000>;
 					regulator-max-microvolt = <1300000>;
+					regulator-coupled-with = <&rtc_vdd_reg>;
+					regulator-coupled-max-spread = <150000>;
 					regulator-always-on;
 				};
 
-				sm1 {
+				cpu_vdd_reg: sm1 {
 					regulator-name = "vdd_sm1,vdd_cpu";
-					regulator-min-microvolt = <1125000>;
+					regulator-min-microvolt = <750000>;
 					regulator-max-microvolt = <1125000>;
 					regulator-always-on;
 				};

@@ -474,10 +476,13 @@
 					regulator-always-on;
 				};
 
-				ldo2 {
+				rtc_vdd_reg: ldo2 {
 					regulator-name = "vdd_ldo2,vdd_rtc";
-					regulator-min-microvolt = <1200000>;
-					regulator-max-microvolt = <1200000>;
+					regulator-min-microvolt = <950000>;
+					regulator-max-microvolt = <1300000>;
+					regulator-coupled-with = <&core_vdd_reg>;
+					regulator-coupled-max-spread = <150000>;
+					regulator-always-on;
 				};
 
 				ldo3 {

@@ -938,4 +943,12 @@
 			 <&tegra_car TEGRA20_CLK_CDEV1>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
 	};
+
+	cpus {
+		cpu0: cpu@0 {
+			cpu-supply = <&cpu_vdd_reg>;
+			core-supply = <&core_vdd_reg>;
+			rtc-supply = <&rtc_vdd_reg>;
+		};
+	};
 };
Signature · 1 line
2.19.0
author
#27 lore raw

RFC PATCH v2 12/17 ARM: dts: tegra20: tamonten: Setup voltage regulators for DVFS

In reply to Dmitry Osipenko

Set min/max regulators voltage and add CPU node that hooks up CPU with voltage regulators.

Signed-off-by Dmitry Osipenko <[email protected]>
---
 arch/arm/boot/dts/tegra20-tamonten.dtsi | 31 ++++++++++++++++++-------
 1 file changed, 22 insertions(+), 9 deletions(-)
arch/arm/boot/dts/tegra20-tamonten.dtsi +22 -9
index 20137fc578b1..e9db60f4c317 100644
@@ -357,17 +357,19 @@
 					regulator-always-on;
 				};
 
-				sm0 {
+				core_vdd_reg: sm0 {
 					regulator-name = "vdd_sys_sm0,vdd_core";
-					regulator-min-microvolt = <1200000>;
-					regulator-max-microvolt = <1200000>;
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1300000>;
+					regulator-coupled-with = <&rtc_vdd_reg>;
+					regulator-coupled-max-spread = <150000>;
 					regulator-always-on;
 				};
 
-				sm1 {
+				cpu_vdd_reg: sm1 {
 					regulator-name = "vdd_sys_sm1,vdd_cpu";
-					regulator-min-microvolt = <1000000>;
-					regulator-max-microvolt = <1000000>;
+					regulator-min-microvolt = <750000>;
+					regulator-max-microvolt = <1125000>;
 					regulator-always-on;
 				};
 

@@ -391,10 +393,13 @@
 					regulator-always-on;
 				};
 
-				ldo2 {
+				rtc_vdd_reg: ldo2 {
 					regulator-name = "vdd_ldo2,vdd_rtc";
-					regulator-min-microvolt = <1200000>;
-					regulator-max-microvolt = <1200000>;
+					regulator-min-microvolt = <950000>;
+					regulator-max-microvolt = <1300000>;
+					regulator-coupled-with = <&core_vdd_reg>;
+					regulator-coupled-max-spread = <150000>;
+					regulator-always-on;
 				};
 
 				ldo3 {

@@ -531,4 +536,12 @@
 			enable-active-high;
 		};
 	};
+
+	cpus {
+		cpu0: cpu@0 {
+			cpu-supply = <&cpu_vdd_reg>;
+			core-supply = <&core_vdd_reg>;
+			rtc-supply = <&rtc_vdd_reg>;
+		};
+	};
 };
Signature · 1 line
2.19.0
author
#28 lore raw

RFC PATCH v2 13/17 ARM: dts: tegra20: ventana: Setup voltage regulators for DVFS

In reply to Dmitry Osipenko

Set min/max regulators voltage and add CPU node that hooks up CPU with voltage regulators.

Signed-off-by Dmitry Osipenko <[email protected]>
---
 arch/arm/boot/dts/tegra20-ventana.dts | 31 +++++++++++++++++++--------
 1 file changed, 22 insertions(+), 9 deletions(-)
arch/arm/boot/dts/tegra20-ventana.dts +22 -9
index f44551e2d9d0..ef9cdd7335ae 100644
@@ -419,17 +419,19 @@
 					regulator-always-on;
 				};
 
-				sm0 {
+				core_vdd_reg: sm0 {
 					regulator-name = "vdd_sm0,vdd_core";
-					regulator-min-microvolt = <1200000>;
-					regulator-max-microvolt = <1200000>;
+					regulator-min-microvolt = <1000000>;
+					regulator-max-microvolt = <1300000>;
+					regulator-coupled-with = <&rtc_vdd_reg>;
+					regulator-coupled-max-spread = <150000>;
 					regulator-always-on;
 				};
 
-				sm1 {
+				cpu_vdd_reg: sm1 {
 					regulator-name = "vdd_sm1,vdd_cpu";
-					regulator-min-microvolt = <1000000>;
-					regulator-max-microvolt = <1000000>;
+					regulator-min-microvolt = <750000>;
+					regulator-max-microvolt = <1125000>;
 					regulator-always-on;
 				};
 

@@ -449,10 +451,13 @@
 					regulator-always-on;
 				};
 
-				ldo2 {
+				rtc_vdd_reg: ldo2 {
 					regulator-name = "vdd_ldo2,vdd_rtc";
-					regulator-min-microvolt = <1200000>;
-					regulator-max-microvolt = <1200000>;
+					regulator-min-microvolt = <950000>;
+					regulator-max-microvolt = <1300000>;
+					regulator-coupled-with = <&core_vdd_reg>;
+					regulator-coupled-max-spread = <150000>;
+					regulator-always-on;
 				};
 
 				ldo3 {

@@ -704,4 +709,12 @@
 			 <&tegra_car TEGRA20_CLK_CDEV1>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
 	};
+
+	cpus {
+		cpu0: cpu@0 {
+			cpu-supply = <&cpu_vdd_reg>;
+			core-supply = <&core_vdd_reg>;
+			rtc-supply = <&rtc_vdd_reg>;
+		};
+	};
 };
Signature · 1 line
2.19.0
author
#29 lore raw

RFC PATCH v2 14/17 ARM: dts: tegra30: apalis: Setup voltage regulators for DVFS

In reply to Dmitry Osipenko

Set min/max regulators voltage and add CPU node that hooks up CPU with voltage regulators.

Signed-off-by Dmitry Osipenko <[email protected]>
---
 arch/arm/boot/dts/tegra30-apalis.dtsi | 19 ++++++++++++++++---
 1 file changed, 16 insertions(+), 3 deletions(-)
arch/arm/boot/dts/tegra30-apalis.dtsi +16 -3
index 7f112f192fe9..1ca9bec8380f 100644
@@ -890,8 +890,11 @@
 
 				vddctrl_reg: vddctrl {
 					regulator-name = "+V1.0_VDD_CPU";
-					regulator-min-microvolt = <1150000>;
-					regulator-max-microvolt = <1150000>;
+					regulator-min-microvolt = <800000>;
+					regulator-max-microvolt = <1250000>;
+					regulator-coupled-with = <&core_vdd_reg>;
+					regulator-coupled-max-spread = <300000>;
+					regulator-max-step-microvolt = <100000>;
 					regulator-always-on;
 				};
 

@@ -1013,13 +1016,16 @@
 		};
 
 		/* SW: +V1.2_VDD_CORE */
-		regulator@60 {
+		core_vdd_reg: regulator@60 {
 			compatible = "ti,tps62362";
 			reg = <0x60>;
 
 			regulator-name = "tps62362-vout";
 			regulator-min-microvolt = <900000>;
 			regulator-max-microvolt = <1400000>;
+			regulator-coupled-with = <&vddctrl_reg>;
+			regulator-coupled-max-spread = <300000>;
+			regulator-max-step-microvolt = <100000>;
 			regulator-boot-on;
 			regulator-always-on;
 			ti,vsel0-state-low;

@@ -1168,4 +1174,11 @@
 			 <&tegra_car TEGRA30_CLK_EXTERN1>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
 	};
+
+	cpus {
+		cpu0: cpu@0 {
+			cpu-supply = <&vddctrl_reg>;
+			core-supply = <&core_vdd_reg>;
+		};
+	};
 };
Signature · 1 line
2.19.0
author
#30 lore raw

RFC PATCH v2 15/17 ARM: dts: tegra30: beaver: Setup voltage regulators for DVFS

In reply to Dmitry Osipenko

Set min/max regulators voltage and add CPU node that hooks up CPU with voltage regulators.

Signed-off-by Dmitry Osipenko <[email protected]>
---
 arch/arm/boot/dts/tegra30-beaver.dts | 19 ++++++++++++++++---
 1 file changed, 16 insertions(+), 3 deletions(-)
arch/arm/boot/dts/tegra30-beaver.dts +16 -3
index b0d40ac8ac6e..39941489d005 100644
@@ -1806,8 +1806,11 @@
 
 				vddctrl_reg: vddctrl {
 					regulator-name = "vdd_cpu,vdd_sys";
-					regulator-min-microvolt = <1000000>;
-					regulator-max-microvolt = <1000000>;
+					regulator-min-microvolt = <800000>;
+					regulator-max-microvolt = <1250000>;
+					regulator-coupled-with = <&core_vdd_reg>;
+					regulator-coupled-max-spread = <300000>;
+					regulator-max-step-microvolt = <100000>;
 					regulator-always-on;
 				};
 

@@ -1868,13 +1871,16 @@
 			};
 		};
 
-		tps62361@60 {
+		core_vdd_reg: tps62361@60 {
 			compatible = "ti,tps62361";
 			reg = <0x60>;
 
 			regulator-name = "tps62361-vout";
 			regulator-min-microvolt = <500000>;
 			regulator-max-microvolt = <1500000>;
+			regulator-coupled-with = <&vddctrl_reg>;
+			regulator-coupled-max-spread = <300000>;
+			regulator-max-step-microvolt = <100000>;
 			regulator-boot-on;
 			regulator-always-on;
 			ti,vsel0-state-high;

@@ -2114,4 +2120,11 @@
 			 <&tegra_car TEGRA30_CLK_EXTERN1>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
 	};
+
+	cpus {
+		cpu0: cpu@0 {
+			cpu-supply = <&vddctrl_reg>;
+			core-supply = <&core_vdd_reg>;
+		};
+	};
 };
Signature · 1 line
2.19.0
author
#31 lore raw

RFC PATCH v2 16/17 ARM: dts: tegra30: cardhu: Setup voltage regulators for DVFS

In reply to Dmitry Osipenko

Set min/max regulators voltage and add CPU node that hooks up CPU with voltage regulators.

Signed-off-by Dmitry Osipenko <[email protected]>
---
 arch/arm/boot/dts/tegra30-cardhu.dtsi | 19 ++++++++++++++++---
 1 file changed, 16 insertions(+), 3 deletions(-)
arch/arm/boot/dts/tegra30-cardhu.dtsi +16 -3
index fb9222b479d2..5fcf5ac09530 100644
@@ -272,8 +272,11 @@
 
 				vddctrl_reg: vddctrl {
 					regulator-name = "vdd_cpu,vdd_sys";
-					regulator-min-microvolt = <1000000>;
-					regulator-max-microvolt = <1000000>;
+					regulator-min-microvolt = <800000>;
+					regulator-max-microvolt = <1250000>;
+					regulator-coupled-with = <&core_vdd_reg>;
+					regulator-coupled-max-spread = <300000>;
+					regulator-max-step-microvolt = <100000>;
 					regulator-always-on;
 				};
 

@@ -342,13 +345,16 @@
 			interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>;
 		};
 
-		tps62361@60 {
+		core_vdd_reg: tps62361@60 {
 			compatible = "ti,tps62361";
 			reg = <0x60>;
 
 			regulator-name = "tps62361-vout";
 			regulator-min-microvolt = <500000>;
 			regulator-max-microvolt = <1500000>;
+			regulator-coupled-with = <&vddctrl_reg>;
+			regulator-coupled-max-spread = <300000>;
+			regulator-max-step-microvolt = <100000>;
 			regulator-boot-on;
 			regulator-always-on;
 			ti,vsel0-state-high;

@@ -649,4 +655,11 @@
 			debounce-interval = <10>;
 		};
 	};
+
+	cpus {
+		cpu0: cpu@0 {
+			cpu-supply = <&vddctrl_reg>;
+			core-supply = <&core_vdd_reg>;
+		};
+	};
 };
Signature · 1 line
2.19.0
author
#32 lore raw

RFC PATCH v2 17/17 ARM: dts: tegra30: colibri: Setup voltage regulators for DVFS

In reply to Dmitry Osipenko

Set min/max regulators voltage and add CPU node that hooks up CPU with voltage regulators.

Signed-off-by Dmitry Osipenko <[email protected]>
---
 arch/arm/boot/dts/tegra30-colibri.dtsi | 19 ++++++++++++++++---
 1 file changed, 16 insertions(+), 3 deletions(-)
arch/arm/boot/dts/tegra30-colibri.dtsi +16 -3
index 35af03ca9e90..c59099c1e2c3 100644
@@ -763,8 +763,11 @@
 
 				vddctrl_reg: vddctrl {
 					regulator-name = "+V1.0_VDD_CPU";
-					regulator-min-microvolt = <1150000>;
-					regulator-max-microvolt = <1150000>;
+					regulator-min-microvolt = <800000>;
+					regulator-max-microvolt = <1250000>;
+					regulator-coupled-with = <&core_vdd_reg>;
+					regulator-coupled-max-spread = <300000>;
+					regulator-max-step-microvolt = <100000>;
 					regulator-always-on;
 				};
 

@@ -882,13 +885,16 @@
 		};
 
 		/* SW: +V1.2_VDD_CORE */
-		regulator@60 {
+		core_vdd_reg: regulator@60 {
 			compatible = "ti,tps62362";
 			reg = <0x60>;
 
 			regulator-name = "tps62362-vout";
 			regulator-min-microvolt = <900000>;
 			regulator-max-microvolt = <1400000>;
+			regulator-coupled-with = <&vddctrl_reg>;
+			regulator-coupled-max-spread = <300000>;
+			regulator-max-step-microvolt = <100000>;
 			regulator-boot-on;
 			regulator-always-on;
 			ti,vsel0-state-low;

@@ -1027,6 +1033,13 @@
 			 <&tegra_car TEGRA30_CLK_EXTERN1>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
 	};
+
+	cpus {
+		cpu0: cpu@0 {
+			cpu-supply = <&vddctrl_reg>;
+			core-supply = <&core_vdd_reg>;
+		};
+	};
 };
 
 &gpio {
Signature · 1 line
2.19.0