small BAR uapi bits
Subsystems (4)
cover small BAR uapi bits
Test-with: [email protected]
Signature · 1 line
2.34.3
PATCH 1/10 drm/doc: add rfc section for small BAR uapi
Add an entry for the new uapi needed for small BAR on DG2+.
v2:
- Some spelling fixes and other small tweaks. (Akeem & Thomas)
- Rework error capture interactions, including no longer needing NEEDS_CPU_ACCESS for objects marked for capture. (Thomas)
- Add probed_cpu_visible_size. (Lionel)
v3:
- Drop the vma query for now.
- Add unallocated_cpu_visible_size as part of the region query.
- Improve the docs some more, including documenting the expected behaviour on older kernels, since this came up in some offline discussion.
v4:
- Various improvements all over. (Tvrtko)
--- Documentation/gpu/rfc/i915_small_bar.h | 189 +++++++++++++++++++++++ Documentation/gpu/rfc/i915_small_bar.rst | 47 ++++++ Documentation/gpu/rfc/index.rst | 4 + 3 files changed, 240 insertions(+) create mode 100644 Documentation/gpu/rfc/i915_small_bar.h create mode 100644 Documentation/gpu/rfc/i915_small_bar.rst
Documentation/gpu/rfc/i915_small_bar.h new file +189 -0
@@ -0,0 +1,189 @@ +/** +* struct __drm_i915_memory_region_info - Describes one region as known to the +* driver. +* +* Note this is using both struct drm_i915_query_item and struct drm_i915_query. +* For this new query we are adding the new query id DRM_I915_QUERY_MEMORY_REGIONS +* at &drm_i915_query_item.query_id. +*/ +struct __drm_i915_memory_region_info { +/** @region: The class:instance pair encoding */ +struct drm_i915_gem_memory_class_instance region; + +/** @rsvd0: MBZ */ +__u32 rsvd0; + +/** +* @probed_size: Memory probed by the driver (-1 = unknown) +* +* Note that it should not be possible to ever encounter a zero value +* here, also note that no current region type will ever return -1 here. +* Although for future region types, this might be a possibility. The +* same applies to the other size fields. +*/ +__u64 probed_size; + +/** +* @unallocated_size: Estimate of memory remaining (-1 = unknown) +* +* Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting. +* Without this (or if this is an older kernel) the value here will +* always equal the @probed_size. Note this is only currently tracked +* for I915_MEMORY_CLASS_DEVICE regions (for other types the value here +* will always equal the @probed_size). +*/ +__u64 unallocated_size; + +union { +/** @rsvd1: MBZ */ +__u64 rsvd1[8 ]; +struct { +/** +* @probed_cpu_visible_size: Memory probed by the driver +* that is CPU accessible. (-1 = unknown). +* +* This will be always be <= @probed_size, and the +* remainder (if there is any) will not be CPU +* accessible. +* +* On systems without small BAR, the @probed_size will +* always equal the @probed_cpu_visible_size, since all +* of it will be CPU accessible. +* +* Note this is only tracked for +* I915_MEMORY_CLASS_DEVICE regions (for other types the +* value here will always equal the @probed_size). +* +* Note that if the value returned here is zero, then +* this must be an old kernel which lacks the relevant +* small-bar uAPI support (including +* I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS), but on +* such systems we should never actually end up with a +* small BAR configuration, assuming we are able to load +* the kernel module. Hence it should be safe to treat +* this the same as when @probed_cpu_visible_size == +* @probed_size. +*/ +__u64 probed_cpu_visible_size; + +/** +* @unallocated_cpu_visible_size: Estimate of CPU +* visible memory remaining (-1 = unknown). +* +* Note this is only tracked for +* I915_MEMORY_CLASS_DEVICE regions (for other types the +* value here will always equal the +* @probed_cpu_visible_size). +* +* Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable +* accounting. Without this the value here will always +* equal the @probed_cpu_visible_size. Note this is only +* currently tracked for I915_MEMORY_CLASS_DEVICE +* regions (for other types the value here will also +* always equal the @probed_cpu_visible_size). +* +* If this is an older kernel the value here will be +* zero, see also @probed_cpu_visible_size. +*/ +__u64 unallocated_cpu_visible_size; + }; + }; +}; + +/** +* struct __drm_i915_gem_create_ext - Existing gem_create behaviour, with added +* extension support using struct i915_user_extension. +* +* Note that new buffer flags should be added here, at least for the stuff that +* is immutable. Previously we would have two ioctls, one to create the object +* with gem_create, and another to apply various parameters, however this +* creates some ambiguity for the params which are considered immutable. Also in +* general we're phasing out the various SET/GET ioctls. +*/ +struct __drm_i915_gem_create_ext { +/** +* @size: Requested size for the object. +* +* The (page-aligned) allocated size for the object will be returned. +* +* Note that for some devices we have might have further minimum +* page-size restrictions (larger than 4K), like for device local-memory. +* However in general the final size here should always reflect any +* rounding up, if for example using the I915_GEM_CREATE_EXT_MEMORY_REGIONS +* extension to place the object in device local-memory. The kernel will +* always select the largest minimum page-size for the set of possible +* placements as the value to use when rounding up the @size. +*/ +__u64 size; + +/** +* @handle: Returned handle for the object. +* +* Object handles are nonzero. +*/ +__u32 handle; + +/** +* @flags: Optional flags. +* +* Supported values: +* +* I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS - Signal to the kernel that +* the object will need to be accessed via the CPU. +* +* Only valid when placing objects in I915_MEMORY_CLASS_DEVICE, and only +* strictly required on configurations where some subset of the device +* memory is directly visible/mappable through the CPU (which we also +* call small BAR), like on some DG2+ systems. Note that this is quite +* undesirable, but due to various factors like the client CPU, BIOS etc +* it's something we can expect to see in the wild. See +* &__drm_i915_memory_region_info.probed_cpu_visible_size for how to +* determine if this system applies. +* +* Note that one of the placements MUST be I915_MEMORY_CLASS_SYSTEM, to +* ensure the kernel can always spill the allocation to system memory, +* if the object can't be allocated in the mappable part of +* I915_MEMORY_CLASS_DEVICE. +* +* Also note that since the kernel only supports flat-CCS on objects +* that can *only* be placed in I915_MEMORY_CLASS_DEVICE, we therefore +* don't support I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS together with +* flat-CCS. +* +* Without this hint, the kernel will assume that non-mappable +* I915_MEMORY_CLASS_DEVICE is preferred for this object. Note that the +* kernel can still migrate the object to the mappable part, as a last +* resort, if userspace ever CPU faults this object, but this might be +* expensive, and so ideally should be avoided. +* +* On older kernels which lack the relevant small-bar uAPI support (see +* also &__drm_i915_memory_region_info.probed_cpu_visible_size), +* usage of the flag will result in an error, but it should NEVER be +* possible to end up with a small BAR configuration, assuming we can +* also successfully load the i915 kernel module. In such cases the +* entire I915_MEMORY_CLASS_DEVICE region will be CPU accessible, and as +* such there are zero restrictions on where the object can be placed. +*/ +#define I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS (1 << 0) +__u32 flags; + +/** +* @extensions: The chain of extensions to apply to this object. +* +* This will be useful in the future when we need to support several +* different extensions, and we need to apply more than one when +* creating the object. See struct i915_user_extension. +* +* If we don't supply any extensions then we get the same old gem_create +* behaviour. +* +* For I915_GEM_CREATE_EXT_MEMORY_REGIONS usage see +* struct drm_i915_gem_create_ext_memory_regions. +* +* For I915_GEM_CREATE_EXT_PROTECTED_CONTENT usage see +* struct drm_i915_gem_create_ext_protected_content. +*/ +#define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0 +#define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1 +__u64 extensions; +};
Documentation/gpu/rfc/i915_small_bar.rst new file +47 -0
47 lines not on this page · raw message
Documentation/gpu/rfc/index.rst +4 -0
@@ -23,3 +23,7 @@ host such documentation: .. toctree:: i915_scheduler.rst + +.. toctree:: + + i915_small_bar.rst
Signature · 1 line
2.34.3
Re: [Intel-gfx] [PATCH 01/10] drm/doc: add rfc section for small BAR uapi
Quoted 274 lines · Matthew Auld
Add an entry for the new uapi needed for small BAR on DG2+.
v2:
- Some spelling fixes and other small tweaks. (Akeem & Thomas)
- Rework error capture interactions, including no longer needingNEEDS_CPU_ACCESSfor objects marked for capture. (Thomas)
- Addprobed_cpu_visible_size. (Lionel)
v3:
- Drop the vma query for now.
- Addunallocated_cpu_visible_sizeas part of the region query.
- Improve the docs some more, including documenting the expected behaviour on older kernels, since this came up in some offline discussion.
v4:
- Various improvements all over. (Tvrtko)Signed-off-by Matthew Auld <[email protected]>Cc Thomas Hellström <[email protected]>Cc Lionel Landwerlin <[email protected]>Cc Tvrtko Ursulin <[email protected]>Cc Jon Bloomfield <[email protected]>Cc Daniel Vetter <[email protected]>Cc Jordan Justen <[email protected]>Cc Kenneth Graunke <[email protected]>Cc Akeem G Abodunrin <[email protected]>Acked-by Tvrtko Ursulin <[email protected]>--- Documentation/gpu/rfc/i915_small_bar.h | 189 +++++++++++++++++++++++ Documentation/gpu/rfc/i915_small_bar.rst | 47 ++++++ Documentation/gpu/rfc/index.rst | 4 + 3 files changed, 240 insertions(+)create mode 100644
Documentation/gpu/rfc/i915_small_bar.hcreate mode 100644Documentation/gpu/rfc/i915_small_bar.rstDocumentation/gpu/rfc/i915_small_bar.h new file +189
-0@@ -0,0 +1,189 @@ +/** +* struct __drm_i915_memory_region_info - Describes one region as known to the +* driver. +* +* Note this is using both struct drm_i915_query_item and struct drm_i915_query. +* For this new query we are adding the new query id DRM_I915_QUERY_MEMORY_REGIONS +* at &drm_i915_query_item.query_id. +*/ +struct __drm_i915_memory_region_info { +/** @region: The class:instance pair encoding */ +struct drm_i915_gem_memory_class_instance region; + +/** @rsvd0: MBZ */ +__u32 rsvd0; + +/** +* @probed_size: Memory probed by the driver (-1 = unknown) +* +* Note that it should not be possible to ever encounter a zero value +* here, also note that no current region type will ever return -1 here. +* Although for future region types, this might be a possibility. The +* same applies to the other size fields. +*/ +__u64 probed_size; + +/** +* @unallocated_size: Estimate of memory remaining (-1 = unknown) +* +* Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting. +* Without this (or if this is an older kernel) the value here will +* always equal the @probed_size. Note this is only currently tracked +* for I915_MEMORY_CLASS_DEVICE regions (for other types the value here +* will always equal the @probed_size). +*/ +__u64 unallocated_size; + +union { +/** @rsvd1: MBZ */ +__u64 rsvd1[8 ]; +struct { +/** +* @probed_cpu_visible_size: Memory probed by the driver +* that is CPU accessible. (-1 = unknown). +* +* This will be always be <= @probed_size, and the +* remainder (if there is any) will not be CPU +* accessible. +* +* On systems without small BAR, the @probed_size will +* always equal the @probed_cpu_visible_size, since all +* of it will be CPU accessible. +* +* Note this is only tracked for +* I915_MEMORY_CLASS_DEVICE regions (for other types the +* value here will always equal the @probed_size). +* +* Note that if the value returned here is zero, then +* this must be an old kernel which lacks the relevant +* small-bar uAPI support (including +* I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS), but on +* such systems we should never actually end up with a +* small BAR configuration, assuming we are able to load +* the kernel module. Hence it should be safe to treat +* this the same as when @probed_cpu_visible_size == +* @probed_size. +*/ +__u64 probed_cpu_visible_size; + +/** +* @unallocated_cpu_visible_size: Estimate of CPU +* visible memory remaining (-1 = unknown). +* +* Note this is only tracked for +* I915_MEMORY_CLASS_DEVICE regions (for other types the +* value here will always equal the +* @probed_cpu_visible_size). +* +* Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable +* accounting. Without this the value here will always +* equal the @probed_cpu_visible_size. Note this is only +* currently tracked for I915_MEMORY_CLASS_DEVICE +* regions (for other types the value here will also +* always equal the @probed_cpu_visible_size). +* +* If this is an older kernel the value here will be +* zero, see also @probed_cpu_visible_size. +*/ +__u64 unallocated_cpu_visible_size; + }; + }; +}; + +/** +* struct __drm_i915_gem_create_ext - Existing gem_create behaviour, with added +* extension support using struct i915_user_extension. +* +* Note that new buffer flags should be added here, at least for the stuff that +* is immutable. Previously we would have two ioctls, one to create the object +* with gem_create, and another to apply various parameters, however this +* creates some ambiguity for the params which are considered immutable. Also in +* general we're phasing out the various SET/GET ioctls. +*/ +struct __drm_i915_gem_create_ext { +/** +* @size: Requested size for the object. +* +* The (page-aligned) allocated size for the object will be returned. +* +* Note that for some devices we have might have further minimum +* page-size restrictions (larger than 4K), like for device local-memory. +* However in general the final size here should always reflect any +* rounding up, if for example using the I915_GEM_CREATE_EXT_MEMORY_REGIONS +* extension to place the object in device local-memory. The kernel will +* always select the largest minimum page-size for the set of possible +* placements as the value to use when rounding up the @size. +*/ +__u64 size; + +/** +* @handle: Returned handle for the object. +* +* Object handles are nonzero. +*/ +__u32 handle; + +/** +* @flags: Optional flags. +* +* Supported values: +* +* I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS - Signal to the kernel that +* the object will need to be accessed via the CPU. +* +* Only valid when placing objects in I915_MEMORY_CLASS_DEVICE, and only +* strictly required on configurations where some subset of the device +* memory is directly visible/mappable through the CPU (which we also +* call small BAR), like on some DG2+ systems. Note that this is quite +* undesirable, but due to various factors like the client CPU, BIOS etc +* it's something we can expect to see in the wild. See +* &__drm_i915_memory_region_info.probed_cpu_visible_size for how to +* determine if this system applies. +* +* Note that one of the placements MUST be I915_MEMORY_CLASS_SYSTEM, to +* ensure the kernel can always spill the allocation to system memory, +* if the object can't be allocated in the mappable part of +* I915_MEMORY_CLASS_DEVICE. +* +* Also note that since the kernel only supports flat-CCS on objects +* that can *only* be placed in I915_MEMORY_CLASS_DEVICE, we therefore +* don't support I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS together with +* flat-CCS. +* +* Without this hint, the kernel will assume that non-mappable +* I915_MEMORY_CLASS_DEVICE is preferred for this object. Note that the +* kernel can still migrate the object to the mappable part, as a last +* resort, if userspace ever CPU faults this object, but this might be +* expensive, and so ideally should be avoided. +* +* On older kernels which lack the relevant small-bar uAPI support (see +* also &__drm_i915_memory_region_info.probed_cpu_visible_size), +* usage of the flag will result in an error, but it should NEVER be +* possible to end up with a small BAR configuration, assuming we can +* also successfully load the i915 kernel module. In such cases the +* entire I915_MEMORY_CLASS_DEVICE region will be CPU accessible, and as +* such there are zero restrictions on where the object can be placed. +*/ +#define I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS (1 << 0) +__u32 flags; + +/** +* @extensions: The chain of extensions to apply to this object. +* +* This will be useful in the future when we need to support several +* different extensions, and we need to apply more than one when +* creating the object. See struct i915_user_extension. +* +* If we don't supply any extensions then we get the same old gem_create +* behaviour. +* +* For I915_GEM_CREATE_EXT_MEMORY_REGIONS usage see +* struct drm_i915_gem_create_ext_memory_regions. +* +* For I915_GEM_CREATE_EXT_PROTECTED_CONTENT usage see +* struct drm_i915_gem_create_ext_protected_content. +*/ +#define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0 +#define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1 +__u64 extensions; +};Documentation/gpu/rfc/i915_small_bar.rst new file +37
-0@@ -0,0 +1,47 @@ +========================== +I915 Small BAR RFC Section +========================== +Starting from DG2 we will have resizable BAR support for device local-memory(i.e +I915_MEMORY_CLASS_DEVICE), but in some cases the final BAR size might still be +smaller than the total probed_size. In such cases, only some subset of +I915_MEMORY_CLASS_DEVICE will be CPU accessible(for example the first 256M), +while the remainder is only accessible via the GPU. + +I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS flag +---------------------------------------------- +New gem_create_ext flag to tell the kernel that a BO will require CPU access. +This becomes important when placing an object in I915_MEMORY_CLASS_DEVICE, where +underneath the device has a small BAR, meaning only some portion of it is CPU +accessible. Without this flag the kernel will assume that CPU access is not +required, and prioritize using the non-CPU visible portion of +I915_MEMORY_CLASS_DEVICE. + +.. kernel-doc:: Documentation/gpu/rfc/i915_small_bar.h + :functions: __drm_i915_gem_create_ext + +probed_cpu_visible_size attribute +--------------------------------- +New struct__drm_i915_memory_region attribute which returns the total size of the +CPU accessible portion, for the particular region. This should only be +applicable for I915_MEMORY_CLASS_DEVICE. We also report the +unallocated_cpu_visible_size, alongside the unallocated_size. + +Vulkan will need this as part of creating a separate VkMemoryHeap with the +VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT set, to represent the CPU visible portion, +where the total size of the heap needs to be known. It also wants to be able to +give a rough estimate of how memory can potentially be allocated. + +.. kernel-doc:: Documentation/gpu/rfc/i915_small_bar.h + :functions: __drm_i915_memory_region_info + +Error Capture restrictions
Documentation/gpu/rfc/i915_small_bar.rst line 47
Quoted 10 lines
Documentation/gpu/rfc/i915_small_bar.rst new file +10
-0+-------------------------- +With error capture we have two new restrictions: + + 1) Error capture is best effort on small BAR systems; if the pages are not + CPU accessible, at the time of capture, then the kernel is free to skip + trying to capture them. + + 2) On discrete we now reject error capture on recoverable contexts. In the + future the kernel may want to blit during error capture, when for example + something is not currently CPU accessible.
Change this to all upcoming hardware so that we are more likely to be able to allocate memory outside of a fence signalling critical section?
/Thomas
Quoted 12 lines
Documentation/gpu/rfc/index.rst +4
-0@@ -23,3 +23,7 @@ host such documentation: .. toctree:: i915_scheduler.rst + +.. toctree:: + + i915_small_bar.rst
PATCH 2/10 drm/i915/uapi: add probed_cpu_visible_size
In reply to Matthew AuldUserspace wants to know the size of CPU visible portion of device local-memory, and on small BAR devices the probed_size is no longer enough. In Vulkan, for example, it would like to know the size in bytes for CPU visible VkMemoryHeap. We already track the io_size for each region, so it's just case of plumbing that through to the region query.
Testcase: igt@i915_query@query-regions-sanity-check
--- drivers/gpu/drm/i915/i915_query.c | 6 +++ include/uapi/drm/i915_drm.h | 74 +++++++++++++++++-------------- 2 files changed, 47 insertions(+), 33 deletions(-)
drivers/gpu/drm/i915/i915_query.c +6 -0
@@ -496,6 +496,12 @@ static int query_memregion_info(struct drm_i915_private *i915, info.region.memory_class = mr->type; info.region.memory_instance = mr->instance; info.probed_size = mr->total; + +if (mr->type ==INTEL_MEMORY_LOCAL ) + info.probed_cpu_visible_size = mr->io_size; +else + info.probed_cpu_visible_size = mr->total; + info.unallocated_size = mr->avail;if (__copy_to_user (info_ptr, &info,sizeof (info)))
include/uapi/drm/i915_drm.h +41 -33
91 lines not on this page · raw message
Signature · 1 line
2.34.3
Re: [PATCH 02/10] drm/i915/uapi: add probed_cpu_visible_size
Quoted 135 lines · Matthew Auld
Userspace wants to know the size of CPU visible portion of device local-memory, and on small BAR devices the
probed_sizeis no longer enough. In Vulkan, for example, it would like to know the size in bytes for CPU visible VkMemoryHeap. We already track theio_sizefor each region, so it's just case of plumbing that through to the region query.Testcase: igt@i915_query@query-regions-sanity-check
Signed-off-by Matthew Auld <[email protected]>Cc Thomas Hellström <[email protected]>Cc Lionel Landwerlin <[email protected]>Cc Tvrtko Ursulin <[email protected]>Cc Jon Bloomfield <[email protected]>Cc Daniel Vetter <[email protected]>Cc Jordan Justen <[email protected]>Cc Kenneth Graunke <[email protected]>Cc Akeem G Abodunrin <[email protected]>--- drivers/gpu/drm/i915/i915_query.c | 6 +++ include/uapi/drm/i915_drm.h | 74 +++++++++++++++++-------------- 2 files changed, 47 insertions(+), 33 deletions(-)drivers/gpu/drm/i915/i915_query.c +6
-0@@ -496,6 +496,12 @@ static int query_memregion_info(struct drm_i915_private *i915, info.region.memory_class = mr->type; info.region.memory_instance = mr->instance; info.probed_size = mr->total; + +if (mr->type ==INTEL_MEMORY_LOCAL ) + info.probed_cpu_visible_size = mr->io_size; +else + info.probed_cpu_visible_size = mr->total; + info.unallocated_size = mr->avail;if (__copy_to_user (info_ptr, &info,sizeof (info)))include/uapi/drm/i915_drm.h +41
-33@@ -3207,36 +3207,6 @@ struct drm_i915_gem_memory_class_instance {* struct drm_i915_memory_region_info - Describes one region as known to the * driver. * -* Note that we reserve some stuff here for potential future work. As an example -* we might want expose the capabilities for a given region, which could include -* things like if the region is CPU mappable/accessible, what are the supported -* mapping types etc. -* -* Note that to extend struct drm_i915_memory_region_info and struct -* drm_i915_query_memory_regions in the future the plan is to do the following: -* -* .. code-block:: C -* -* struct drm_i915_memory_region_info { -* struct drm_i915_gem_memory_class_instance region; -* union { -* __u32 rsvd0; -* __u32 new_thing1; -* }; -* ... -* union { -* __u64 rsvd1[8]; -* struct { -* __u64 new_thing2; -* __u64 new_thing3; -* ... -* }; -* }; -* }; -* -* With this things should remain source compatible between versions for -* userspace, even as we add new fields. -* * Note this is using both struct drm_i915_query_item and struct drm_i915_query. * For this new query we are adding the new query id DRM_I915_QUERY_MEMORY_REGIONS * at &drm_i915_query_item.query_id. @@ -3248,14 +3218,52 @@ struct drm_i915_memory_region_info {/** @rsvd0: MBZ */ __u32 rsvd0; -/** @probed_size: Memory probed by the driver (-1 = unknown) */ +/** +* @probed_size: Memory probed by the driver (-1 = unknown) +* +* Note that it should not be possible to ever encounter a zero value +* here, also note that no current region type will ever return -1 here. +* Although for future region types, this might be a possibility. The +* same applies to the other size fields. +*/ __u64 probed_size;/** @unallocated_size: Estimate of memory remaining (-1 = unknown) */ __u64 unallocated_size; -/** @rsvd1: MBZ */ -__u64 rsvd1[8 ]; +union { +/** @rsvd1: MBZ */ +__u64 rsvd1[8 ]; +struct { +/** +* @probed_cpu_visible_size: Memory probed by the driver +* that is CPU accessible. (-1 = unknown). +* +* This will be always be <= @probed_size, and the +* remainder (if there is any) will not be CPU +* accessible. +* +* On systems without small BAR, the @probed_size will +* always equal the @probed_cpu_visible_size, since all +* of it will be CPU accessible. +* +* Note this is only tracked for +* I915_MEMORY_CLASS_DEVICE regions (for other types the +* value here will always equal the @probed_size). +* +* Note that if the value returned here is zero, then +* this must be an old kernel which lacks the relevant +* small-bar uAPI support (including +* I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS), but on +* such systems we should never actually end up with a +* small BAR configuration, assuming we are able to load +* the kernel module. Hence it should be safe to treat +* this the same as when @probed_cpu_visible_size == +* @probed_size. +*/ +__u64 probed_cpu_visible_size; + }; + }; };/**
Re: [Intel-gfx] [PATCH 02/10] drm/i915/uapi: add probed_cpu_visible_size
In reply to Matthew AuldQuoted 5 lines · Matthew Auld
Userspace wants to know the size of CPU visible portion of device local-memory, and on small BAR devices the
probed_sizeis no longer enough. In Vulkan, for example, it would like to know the size in bytes for CPU visible VkMemoryHeap. We already track theio_sizefor each region, so it's just case of plumbing that through to the region query.
Nit: so plumb that through (imperative)
Quoted 120 lines
Testcase: igt@i915_query@query-regions-sanity-check
Signed-off-by Matthew Auld <[email protected]>Cc Thomas Hellström <[email protected]>Cc Lionel Landwerlin <[email protected]>Cc Tvrtko Ursulin <[email protected]>Cc Jon Bloomfield <[email protected]>Cc Daniel Vetter <[email protected]>Cc Jordan Justen <[email protected]>Cc Kenneth Graunke <[email protected]>Cc Akeem G Abodunrin <[email protected]>--- drivers/gpu/drm/i915/i915_query.c | 6 +++ include/uapi/drm/i915_drm.h | 74 +++++++++++++++++-------------- 2 files changed, 47 insertions(+), 33 deletions(-)drivers/gpu/drm/i915/i915_query.c +6
-0@@ -496,6 +496,12 @@ static int query_memregion_info(struct drm_i915_private *i915, info.region.memory_class = mr->type; info.region.memory_instance = mr->instance; info.probed_size = mr->total; + +if (mr->type ==INTEL_MEMORY_LOCAL ) + info.probed_cpu_visible_size = mr->io_size; +else + info.probed_cpu_visible_size = mr->total; + info.unallocated_size = mr->avail;if (__copy_to_user (info_ptr, &info,sizeof (info)))include/uapi/drm/i915_drm.h +34
-33@@ -3207,36 +3207,6 @@ struct drm_i915_gem_memory_class_instance {* struct drm_i915_memory_region_info - Describes one region as known to the * driver. * -* Note that we reserve some stuff here for potential future work. As an example -* we might want expose the capabilities for a given region, which could include -* things like if the region is CPU mappable/accessible, what are the supported -* mapping types etc. -* -* Note that to extend struct drm_i915_memory_region_info and struct -* drm_i915_query_memory_regions in the future the plan is to do the following: -* -* .. code-block:: C -* -* struct drm_i915_memory_region_info { -* struct drm_i915_gem_memory_class_instance region; -* union { -* __u32 rsvd0; -* __u32 new_thing1; -* }; -* ... -* union { -* __u64 rsvd1[8]; -* struct { -* __u64 new_thing2; -* __u64 new_thing3; -* ... -* }; -* }; -* }; -* -* With this things should remain source compatible between versions for -* userspace, even as we add new fields. -* * Note this is using both struct drm_i915_query_item and struct drm_i915_query. * For this new query we are adding the new query id DRM_I915_QUERY_MEMORY_REGIONS * at &drm_i915_query_item.query_id. @@ -3248,14 +3218,52 @@ struct drm_i915_memory_region_info {/** @rsvd0: MBZ */ __u32 rsvd0; -/** @probed_size: Memory probed by the driver (-1 = unknown) */ +/** +* @probed_size: Memory probed by the driver (-1 = unknown) +* +* Note that it should not be possible to ever encounter a zero value +* here, also note that no current region type will ever return -1 here. +* Although for future region types, this might be a possibility. The +* same applies to the other size fields. +*/ __u64 probed_size;/** @unallocated_size: Estimate of memory remaining (-1 = unknown) */ __u64 unallocated_size; -/** @rsvd1: MBZ */ -__u64 rsvd1[8 ]; +union { +/** @rsvd1: MBZ */ +__u64 rsvd1[8 ]; +struct { +/** +* @probed_cpu_visible_size: Memory probed by the driver +* that is CPU accessible. (-1 = unknown). +* +* This will be always be <= @probed_size, and the +* remainder (if there is any) will not be CPU +* accessible. +* +* On systems without small BAR, the @probed_size will +* always equal the @probed_cpu_visible_size, since all +* of it will be CPU accessible. +* +* Note this is only tracked for +* I915_MEMORY_CLASS_DEVICE regions (for other types the +* value here will always equal the @probed_size). +* +* Note that if the value returned here is zero, then +* this must be an old kernel which lacks the relevant +* small-bar uAPI support (including +* I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS), but on +* such systems we should never actually end up with a +* small BAR configuration, assuming we are able to load
include/uapi/drm/i915_drm.h struct drm_i915_memory_region_info { · line 3269
Quoted 10 lines
include/uapi/drm/i915_drm.h +7
-0+* the kernel module. Hence it should be safe to treat +* this the same as when @probed_cpu_visible_size == +* @probed_size. +*/ +__u64 probed_cpu_visible_size; + }; + }; };/**
PATCH 3/10 drm/i915/uapi: expose the avail tracking
In reply to Matthew AuldVulkan would like to have a rough measure of how much device memory can in theory be allocated. Also add unallocated_cpu_visible_size to track the visible portion, in case the device is using small BAR.
Testcase: igt@i915_query@query-regions-unallocated
Testcase: igt@i915_query@query-regions-sanity-check
--- drivers/gpu/drm/i915/i915_query.c | 10 +++++- drivers/gpu/drm/i915/i915_ttm_buddy_manager.c | 20 ++++++++++++ drivers/gpu/drm/i915/i915_ttm_buddy_manager.h | 3 ++ drivers/gpu/drm/i915/intel_memory_region.c | 14 +++++++++ drivers/gpu/drm/i915/intel_memory_region.h | 3 ++ include/uapi/drm/i915_drm.h | 31 ++++++++++++++++++- 6 files changed, 79 insertions(+), 2 deletions(-)
drivers/gpu/drm/i915/i915_query.c +9 -1
@@ -502,7 +502,15 @@ static int query_memregion_info(struct drm_i915_private *i915,else info.probed_cpu_visible_size = mr->total; - info.unallocated_size = mr->avail; +if (perfmon_capable ()) { +intel_memory_region_avail (mr, + &info.unallocated_size, + &info.unallocated_cpu_visible_size); + }else { + info.unallocated_size = info.probed_size; + info.unallocated_cpu_visible_size = + info.probed_cpu_visible_size; + }if (__copy_to_user (info_ptr, &info,sizeof (info)))return -EFAULT ;
drivers/gpu/drm/i915/i915_ttm_buddy_manager.c +20 -0
@@ -365,6 +365,26 @@ u64 i915_ttm_buddy_man_visible_size(struct ttm_resource_manager *man)return bman->visible_size; } +/** +* i915_ttm_buddy_man_visible_size - Query the avail tracking for the manager. +* +* @man: The buddy allocator ttm manager +* @avail: The total available memory in pages for the entire manager. +* @visible_avail: The total available memory in pages for the CPU visible +* portion. Note that this will always give the same value as @avail on +* configurations that don't have a small BAR. +*/ +void i915_ttm_buddy_man_avail (struct ttm_resource_manager *man, +u64 *avail,u64 *visible_avail) +{ +struct i915_ttm_buddy_manager *bman =to_buddy_manager (man); + +mutex_lock (&bman->lock); + *avail = bman->mm.avail >>PAGE_SHIFT ; + *visible_avail = bman->visible_avail; +mutex_unlock (&bman->lock); +} +#if IS_ENABLED (CONFIG_DRM_I915_SELFTEST )void i915_ttm_buddy_man_force_visible_size (struct ttm_resource_manager *man,u64 size)
drivers/gpu/drm/i915/i915_ttm_buddy_manager.h +3 -0
@@ -61,6 +61,9 @@ int i915_ttm_buddy_man_reserve(struct ttm_resource_manager *man,u64 i915_ttm_buddy_man_visible_size (struct ttm_resource_manager *man); +void i915_ttm_buddy_man_avail (struct ttm_resource_manager *man, +u64 *avail,u64 *avail_visible); +#if IS_ENABLED (CONFIG_DRM_I915_SELFTEST )void i915_ttm_buddy_man_force_visible_size (struct ttm_resource_manager *man,u64 size);
drivers/gpu/drm/i915/intel_memory_region.c +14 -0
@@ -279,6 +279,20 @@ void intel_memory_region_set_name(struct intel_memory_region *mem,va_end (ap); } +void intel_memory_region_avail (struct intel_memory_region *mr, +u64 *avail,u64 *visible_avail) +{ +if (mr->type ==INTEL_MEMORY_LOCAL ) { +i915_ttm_buddy_man_avail (mr->region_private, + avail, visible_avail); + *avail <<=PAGE_SHIFT ; + *visible_avail <<=PAGE_SHIFT ; + }else { + *avail = mr->total; + *visible_avail = mr->total; + } +} +void intel_memory_region_destroy (struct intel_memory_region *mem) {int ret =0 ;
drivers/gpu/drm/i915/intel_memory_region.h +3 -0
@@ -127,6 +127,9 @@ int intel_memory_region_reserve(struct intel_memory_region *mem,void intel_memory_region_debug (struct intel_memory_region *mr,struct drm_printer *printer); +void intel_memory_region_avail (struct intel_memory_region *mr, +u64 *avail,u64 *visible_avail); +struct intel_memory_region *i915_gem_ttm_system_setup (struct drm_i915_private *i915,u16 type,u16 instance);
include/uapi/drm/i915_drm.h +30 -1
@@ -3228,7 +3228,15 @@ struct drm_i915_memory_region_info {*/ __u64 probed_size; -/** @unallocated_size: Estimate of memory remaining (-1 = unknown) */ +/** +* @unallocated_size: Estimate of memory remaining (-1 = unknown) +* +* Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting. +* Without this (or if this is an older kernel) the value here will +* always equal the @probed_size. Note this is only currently tracked +* for I915_MEMORY_CLASS_DEVICE regions (for other types the value here +* will always equal the @probed_size). +*/ __u64 unallocated_size;union {
@@ -3262,6 +3270,27 @@ struct drm_i915_memory_region_info {* @probed_size. */ __u64 probed_cpu_visible_size; + +/** +* @unallocated_cpu_visible_size: Estimate of CPU +* visible memory remaining (-1 = unknown). +* +* Note this is only tracked for +* I915_MEMORY_CLASS_DEVICE regions (for other types the +* value here will always equal the +* @probed_cpu_visible_size). +* +* Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable +* accounting. Without this the value here will always +* equal the @probed_cpu_visible_size. Note this is only +* currently tracked for I915_MEMORY_CLASS_DEVICE +* regions (for other types the value here will also +* always equal the @probed_cpu_visible_size). +* +* If this is an older kernel the value here will be +* zero, see also @probed_cpu_visible_size. +*/ +__u64 unallocated_cpu_visible_size; }; }; };
Signature · 1 line
2.34.3
kernel test robot
build botRe: [Intel-gfx] [PATCH 03/10] drm/i915/uapi: expose the avail tracking
Thank you for the patch! Perhaps something to improve:
Hi Matthew,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
[also build test WARNING on v5.18 next-20220525]
[cannot apply to drm-intel/for-linux-next drm/drm-next]
[If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/intel-lab-lkp/linux/commits/Matthew-Auld/small-BAR-uapi-bits/20220526-024641 base: git://anongit.freedesktop.org/drm/drm-tip drm-tip config: x86_64-rhel-8.3-kunit (https://download.01.org/0day-ci/archive/20220526/[email protected]/config) compiler: gcc-11 (Debian 11.3.0-1) 11.3.0 reproduce (this is a W=1 build): # https://github.com/intel-lab-lkp/linux/commit/614521eb68cc1e72a489c1c796827329c98bf031 git remote add linux-review https://github.com/intel-lab-lkp/linux git fetch --no-tags linux-review Matthew-Auld/small-BAR-uapi-bits/20220526-024641 git checkout 614521eb68cc1e72a489c1c796827329c98bf031 # save the config file mkdir build_dir && cp config build_dir/.config make W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/gpu/drm/i915/
If you fix the issue, kindly add following tag where applicable
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/i915/i915_ttm_buddy_manager.c:379: warning: expecting prototype for i915_ttm_buddy_man_visible_size(). Prototype was for i915_ttm_buddy_man_avail() instead
vim +379 drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
367
368 /**
369 * i915_ttm_buddy_man_visible_size - Query the avail tracking for the manager.
370 *
371 * @man: The buddy allocator ttm manager
372 * @avail: The total available memory in pages for the entire manager.
373 * @visible_avail: The total available memory in pages for the CPU visible
374 * portion. Note that this will always give the same value as @avail on
375 * configurations that don't have a small BAR.
376 */
377 void i915_ttm_buddy_man_avail(struct ttm_resource_manager *man,
378 u64 *avail, u64 *visible_avail)
> 379 { 380 struct i915_ttm_buddy_manager *bman = to_buddy_manager(man);
381
382 mutex_lock(&bman->lock);
383 *avail = bman->mm.avail >> PAGE_SHIFT;
384 *visible_avail = bman->visible_avail;
385 mutex_unlock(&bman->lock);
386 }
387
Signature · 2 lines
0-DAY CI Kernel Test Service https://01.org/lkp
Re: [PATCH 03/10] drm/i915/uapi: expose the avail tracking
In reply to Matthew AuldQuoted 3 lines · Matthew Auld
Vulkan would like to have a rough measure of how much device memory can in theory be allocated. Also add
unallocated_cpu_visible_sizeto track the visible portion, in case the device is using small BAR.
I have concerns here that it isn't useful and could even be counter-productive. If we give unprivileged access it may be considered a side channel, but if we "lie" (report total region size) to unprivileged clients (like in this patch), then they don't co-operate well and end trashing.
Is Vulkan really sure it wants this and why?
Regards,
Tvrtko
Quoted 174 lines
Testcase: igt@i915_query@query-regions-unallocated
Testcase: igt@i915_query@query-regions-sanity-checkSigned-off-by Matthew Auld <[email protected]>Cc Thomas Hellström <[email protected]>Cc Lionel Landwerlin <[email protected]>Cc Tvrtko Ursulin <[email protected]>Cc Jon Bloomfield <[email protected]>Cc Daniel Vetter <[email protected]>Cc Jordan Justen <[email protected]>Cc Kenneth Graunke <[email protected]>Cc Akeem G Abodunrin <[email protected]>--- drivers/gpu/drm/i915/i915_query.c | 10 +++++- drivers/gpu/drm/i915/i915_ttm_buddy_manager.c | 20 ++++++++++++ drivers/gpu/drm/i915/i915_ttm_buddy_manager.h | 3 ++ drivers/gpu/drm/i915/intel_memory_region.c | 14 +++++++++ drivers/gpu/drm/i915/intel_memory_region.h | 3 ++ include/uapi/drm/i915_drm.h | 31 ++++++++++++++++++- 6 files changed, 79 insertions(+), 2 deletions(-)drivers/gpu/drm/i915/i915_query.c +9
-1@@ -502,7 +502,15 @@ static int query_memregion_info(struct drm_i915_private *i915,else info.probed_cpu_visible_size = mr->total; - info.unallocated_size = mr->avail; +if (perfmon_capable ()) { +intel_memory_region_avail (mr, + &info.unallocated_size, + &info.unallocated_cpu_visible_size); + }else { + info.unallocated_size = info.probed_size; + info.unallocated_cpu_visible_size = + info.probed_cpu_visible_size; + }if (__copy_to_user (info_ptr, &info,sizeof (info)))return -EFAULT ;drivers/gpu/drm/i915/i915_ttm_buddy_manager.c +20
-0@@ -365,6 +365,26 @@ u64 i915_ttm_buddy_man_visible_size(struct ttm_resource_manager *man)return bman->visible_size; } +/** +* i915_ttm_buddy_man_visible_size - Query the avail tracking for the manager. +* +* @man: The buddy allocator ttm manager +* @avail: The total available memory in pages for the entire manager. +* @visible_avail: The total available memory in pages for the CPU visible +* portion. Note that this will always give the same value as @avail on +* configurations that don't have a small BAR. +*/ +void i915_ttm_buddy_man_avail (struct ttm_resource_manager *man, +u64 *avail,u64 *visible_avail) +{ +struct i915_ttm_buddy_manager *bman =to_buddy_manager (man); + +mutex_lock (&bman->lock); + *avail = bman->mm.avail >>PAGE_SHIFT ; + *visible_avail = bman->visible_avail; +mutex_unlock (&bman->lock); +} +#if IS_ENABLED (CONFIG_DRM_I915_SELFTEST )void i915_ttm_buddy_man_force_visible_size (struct ttm_resource_manager *man,u64 size)drivers/gpu/drm/i915/i915_ttm_buddy_manager.h +3
-0@@ -61,6 +61,9 @@ int i915_ttm_buddy_man_reserve(struct ttm_resource_manager *man,u64 i915_ttm_buddy_man_visible_size (struct ttm_resource_manager *man); +void i915_ttm_buddy_man_avail (struct ttm_resource_manager *man, +u64 *avail,u64 *avail_visible); +#if IS_ENABLED (CONFIG_DRM_I915_SELFTEST )void i915_ttm_buddy_man_force_visible_size (struct ttm_resource_manager *man,u64 size);drivers/gpu/drm/i915/intel_memory_region.c +14
-0@@ -279,6 +279,20 @@ void intel_memory_region_set_name(struct intel_memory_region *mem,va_end (ap); } +void intel_memory_region_avail (struct intel_memory_region *mr, +u64 *avail,u64 *visible_avail) +{ +if (mr->type ==INTEL_MEMORY_LOCAL ) { +i915_ttm_buddy_man_avail (mr->region_private, + avail, visible_avail); + *avail <<=PAGE_SHIFT ; + *visible_avail <<=PAGE_SHIFT ; + }else { + *avail = mr->total; + *visible_avail = mr->total; + } +} +void intel_memory_region_destroy (struct intel_memory_region *mem) {int ret =0 ;drivers/gpu/drm/i915/intel_memory_region.h +3
-0@@ -127,6 +127,9 @@ int intel_memory_region_reserve(struct intel_memory_region *mem,void intel_memory_region_debug (struct intel_memory_region *mr,struct drm_printer *printer); +void intel_memory_region_avail (struct intel_memory_region *mr, +u64 *avail,u64 *visible_avail); +struct intel_memory_region *i915_gem_ttm_system_setup (struct drm_i915_private *i915,u16 type,u16 instance);include/uapi/drm/i915_drm.h +30
-1@@ -3228,7 +3228,15 @@ struct drm_i915_memory_region_info {*/ __u64 probed_size; -/** @unallocated_size: Estimate of memory remaining (-1 = unknown) */ +/** +* @unallocated_size: Estimate of memory remaining (-1 = unknown) +* +* Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting. +* Without this (or if this is an older kernel) the value here will +* always equal the @probed_size. Note this is only currently tracked +* for I915_MEMORY_CLASS_DEVICE regions (for other types the value here +* will always equal the @probed_size). +*/ __u64 unallocated_size;union {@@ -3262,6 +3270,27 @@ struct drm_i915_memory_region_info {* @probed_size. */ __u64 probed_cpu_visible_size; + +/** +* @unallocated_cpu_visible_size: Estimate of CPU +* visible memory remaining (-1 = unknown). +* +* Note this is only tracked for +* I915_MEMORY_CLASS_DEVICE regions (for other types the +* value here will always equal the +* @probed_cpu_visible_size). +* +* Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable +* accounting. Without this the value here will always +* equal the @probed_cpu_visible_size. Note this is only +* currently tracked for I915_MEMORY_CLASS_DEVICE +* regions (for other types the value here will also +* always equal the @probed_cpu_visible_size). +* +* If this is an older kernel the value here will be +* zero, see also @probed_cpu_visible_size. +*/ +__u64 unallocated_cpu_visible_size; }; }; };
Re: [PATCH 03/10] drm/i915/uapi: expose the avail tracking
Quoted 9 lines · Tvrtko Ursulin
Quoted 3 lines · Matthew Auld
Vulkan would like to have a rough measure of how much device memory can in theory be allocated. Also add
unallocated_cpu_visible_sizeto track the visible portion, in case the device is using small BAR.I have concerns here that it isn't useful and could even be counter-productive. If we give unprivileged access it may be considered a side channel, but if we "lie" (report total region size) to unprivileged clients (like in this patch), then they don't co-operate well and end trashing.
Is Vulkan really sure it wants this and why?
Lionel pointed out: https://www.khronos.org/registry/vulkan/specs/1.3-extensions/man/html/VK_EXT_memory_budget.html
Also note that the existing behaviour was to lie. I'm not sure what's the best option here.
Quoted 180 lines
Regards,
Tvrtko
Quoted 175 lines
Testcase: igt@i915_query@query-regions-unallocated
Testcase: igt@i915_query@query-regions-sanity-checkSigned-off-by Matthew Auld <[email protected]>Cc Thomas Hellström <[email protected]>Cc Lionel Landwerlin <[email protected]>Cc Tvrtko Ursulin <[email protected]>Cc Jon Bloomfield <[email protected]>Cc Daniel Vetter <[email protected]>Cc Jordan Justen <[email protected]>Cc Kenneth Graunke <[email protected]>Cc Akeem G Abodunrin <[email protected]>---
drivers/gpu/drm/i915/i915_query.c | 10 +++++-drivers/gpu/drm/i915/i915_ttm_buddy_manager.c| 20 ++++++++++++drivers/gpu/drm/i915/i915_ttm_buddy_manager.h| 3 ++ drivers/gpu/drm/i915/intel_memory_region.c | 14 +++++++++ drivers/gpu/drm/i915/intel_memory_region.h | 3 ++ include/uapi/drm/i915_drm.h | 31 ++++++++++++++++++-6 files changed, 79 insertions(+), 2 deletions(-)drivers/gpu/drm/i915/i915_query.c +0
-0@@ -502,7 +502,15 @@ static int query_memregion_info(struct drm_i915_private *i915,else
info.probed_cpu_visible_size =mr->total; - info.unallocated_size =mr->avail;
+ if (perfmon_capable()) {
+ intel_memory_region_avail(mr,
+ &info.unallocated_size,
+ &info.unallocated_cpu_visible_size); + } else {
+ info.unallocated_size = info.probed_size; + info.unallocated_cpu_visible_size =
+ info.probed_cpu_visible_size;
+ }
if (__copy_to_user(info_ptr, &info, sizeof(info))) return-EFAULT;drivers/gpu/drm/i915/i915_ttm_buddy_manager.c +2
-0@@ -365,6 +365,26 @@ u64 i915_ttm_buddy_man_visible_size(struct ttm_resource_manager *man) return bman->visible_size; } +/** +* i915_ttm_buddy_man_visible_size - Query the avail tracking for the manager.
+ *
+ * @man: The buddy allocator ttm manager
+ * @avail: The total available memory in pages for the entire manager.
+ * @visible_avail: The total available memory in pages for the CPU visible
+ * portion. Note that this will always give the same value as @avail on
+ * configurations that don't have a small BAR.
+ */drivers/gpu/drm/i915/i915_ttm_buddy_manager.c +11
-0+void i915_ttm_buddy_man_avail (struct ttm_resource_manager *man, + u64 *avail, u64 *visible_avail) +{ + struct i915_ttm_buddy_manager *bman = to_buddy_manager(man); + + mutex_lock(&bman->lock); + *avail = bman->mm.avail >> PAGE_SHIFT; + *visible_avail = bman->visible_avail; + mutex_unlock(&bman->lock); +} +#if
IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
voidi915_ttm_buddy_man_force_visible_size(struct ttm_resource_manager *man, u64 size)drivers/gpu/drm/i915/i915_ttm_buddy_manager.h +3
-0@@ -61,6 +61,9 @@ int i915_ttm_buddy_man_reserve(structttm_resource_manager *man, u64 i915_ttm_buddy_man_visible_size(struct ttm_resource_manager *man); +void i915_ttm_buddy_man_avail (struct ttm_resource_manager *man, + u64 *avail, u64 *avail_visible); + #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) void i915_ttm_buddy_man_force_visible_size(struct ttm_resource_manager *man, u64 size);drivers/gpu/drm/i915/intel_memory_region.c +14
-0@@ -279,6 +279,20 @@ void intel_memory_region_set_name(structintel_memory_region *mem, va_end(ap); } +void intel_memory_region_avail (struct intel_memory_region *mr, + u64 *avail, u64 *visible_avail) +{ + if (mr->type == INTEL_MEMORY_LOCAL) { + i915_ttm_buddy_man_avail(mr->region_private, + avail, visible_avail); + *avail <<= PAGE_SHIFT; + *visible_avail <<= PAGE_SHIFT; + } else { + *avail = mr->total; + *visible_avail = mr->total; + } +} + void intel_memory_region_destroy(struct intel_memory_region *mem) { int ret = 0;drivers/gpu/drm/i915/intel_memory_region.h +3
-0@@ -127,6 +127,9 @@ int intel_memory_region_reserve(structintel_memory_region *mem, void intel_memory_region_debug(struct intel_memory_region *mr, struct drm_printer *printer); +void intel_memory_region_avail (struct intel_memory_region *mr, + u64 *avail, u64 *visible_avail); +struct
intel_memory_region*i915_gem_ttm_system_setup(struct drm_i915_private *i915, u16 type, u16 instance);include/uapi/drm/i915_drm.h +0
-1@@ -3228,7 +3228,15 @@ struct drm_i915_memory_region_info {*/ __u64 probed_size; - /** @unallocated_size: Estimate of memory remaining (-1 =unknown) */
+ /**
+ * @unallocated_size: Estimate of memory remaining (-1 = unknown) + *
+ * RequiresCAP_PERFMONorCAP_SYS_ADMINto get reliable accounting. + * Without this (or if this is an older kernel) the value here will + * always equal the @probed_size. Note this is only currently tracked
+ * forI915_MEMORY_CLASS_DEVICEregions (for other types the value here
+ * will always equal the @probed_size).
+ */
__u64unallocated_size;
union {include/uapi/drm/i915_drm.h +21
-0@@ -3262,6 +3270,27 @@ struct drm_i915_memory_region_info {* @probed_size. */ __u64 probed_cpu_visible_size; + + /** + * @unallocated_cpu_visible_size: Estimate of CPU + * visible memory remaining (-1 = unknown). + * + * Note this is only tracked for + * I915_MEMORY_CLASS_DEVICE regions (for other types the + * value here will always equal the + * @probed_cpu_visible_size). + * + * Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable + * accounting. Without this the value here will always + * equal the @probed_cpu_visible_size. Note this is only + * currently tracked for I915_MEMORY_CLASS_DEVICE + * regions (for other types the value here will also + * always equal the @probed_cpu_visible_size). + * + * If this is an older kernel the value here will be + * zero, see also @probed_cpu_visible_size. + */ + __u64 unallocated_cpu_visible_size; }; }; };
Re: [PATCH 03/10] drm/i915/uapi: expose the avail tracking
Quoted 7 lines · Matthew Auld
Quoted 6 lines · Tvrtko Ursulin
Quoted 3 lines · Matthew Auld
Vulkan would like to have a rough measure of how much device memory can in theory be allocated. Also add
unallocated_cpu_visible_sizeto track the visible portion, in case the device is using small BAR.
Quoted 5 lines
Quoted 3 lines
I have concerns here that it isn't useful and could even be counter-productive. If we give unprivileged access it may be considered a side channel, but if we "lie" (report total region size) to unprivileged clients (like in this patch), then they don't co-operate well and end trashing.
Is Vulkan really sure it wants this and why?
Lionel pointed out: https://www.khronos.org/registry/vulkan/specs/1.3-extensions/man/html/VK_EXT_memory_budget.html
So this query would provide VkPhysicalDeviceMemoryBudgetPropertiesEXT::heapBudget. Apart that it wouldn't since we thought to lie. And apart that it's text says:
"""
...how much total memory from each heap the current process can use at any given time, before allocations may start failing or causing performance degradation. The values may change based on other activity in the system that is outside the scope and control of the Vulkan implementation. """
It acknowledges itself in the second sentence that the first sentence is questionable.
And VkPhysicalDeviceMemoryBudgetPropertiesEXT::heapUsage would be still missing and would maybe come via fdinfo? Or you plan to add it to this same query later?
I like to source knowledge of best practices from the long established world of CPU scheduling and process memory management. Is anyone aware of this kind of techniques there - applications actively looking at free memory data from /proc/meminfo and dynamically adjusting their runtime behaviour based on it? And that they are not single application on a dedicated system type of things.
Or perhaps this Vk extension is envisaged for exactly those kind of scenarios? However if so then userspace can know all this data from probed size and the data set it created.
Quoted 1 line
Also note that the existing behaviour was to lie. I'm not sure what's the best option here.
Uapi reserved -1 for unknown so we could do that?
Regards,
Tvrtko
Quoted 181 lines
Quoted 181 lines
Regards,
Tvrtko
Quoted 176 lines
Testcase: igt@i915_query@query-regions-unallocated
Testcase: igt@i915_query@query-regions-sanity-checkSigned-off-by Matthew Auld <[email protected]>Cc Thomas Hellström <[email protected]>Cc Lionel Landwerlin <[email protected]>Cc Tvrtko Ursulin <[email protected]>Cc Jon Bloomfield <[email protected]>Cc Daniel Vetter <[email protected]>Cc Jordan Justen <[email protected]>Cc Kenneth Graunke <[email protected]>Cc Akeem G Abodunrin <[email protected]>---
drivers/gpu/drm/i915/i915_query.c | 10 +++++-drivers/gpu/drm/i915/i915_ttm_buddy_manager.c| 20 ++++++++++++drivers/gpu/drm/i915/i915_ttm_buddy_manager.h| 3 ++ drivers/gpu/drm/i915/intel_memory_region.c | 14 +++++++++ drivers/gpu/drm/i915/intel_memory_region.h | 3 ++ include/uapi/drm/i915_drm.h | 31 ++++++++++++++++++-6 files changed, 79 insertions(+), 2 deletions(-)drivers/gpu/drm/i915/i915_query.c +0
-0@@ -502,7 +502,15 @@ static int query_memregion_info(struct drm_i915_private *i915,else
info.probed_cpu_visible_size =mr->total; - info.unallocated_size =mr->avail;
+ if (perfmon_capable()) {
+ intel_memory_region_avail(mr,
+ &info.unallocated_size,
+ &info.unallocated_cpu_visible_size); + } else {
+ info.unallocated_size = info.probed_size; + info.unallocated_cpu_visible_size =
+ info.probed_cpu_visible_size;
+ }
if (__copy_to_user(info_ptr, &info, sizeof(info))) return-EFAULT;drivers/gpu/drm/i915/i915_ttm_buddy_manager.c +2
-0@@ -365,6 +365,26 @@ u64 i915_ttm_buddy_man_visible_size(struct ttm_resource_manager *man) return bman->visible_size; } +/** +* i915_ttm_buddy_man_visible_size - Query the avail tracking for the manager.
+ *
+ * @man: The buddy allocator ttm manager
+ * @avail: The total available memory in pages for the entire manager.
+ * @visible_avail: The total available memory in pages for the CPU visible
+ * portion. Note that this will always give the same value as @avail on
+ * configurations that don't have a small BAR.
+ */drivers/gpu/drm/i915/i915_ttm_buddy_manager.c +11
-0+void i915_ttm_buddy_man_avail (struct ttm_resource_manager *man, + u64 *avail, u64 *visible_avail) +{ + struct i915_ttm_buddy_manager *bman = to_buddy_manager(man); + + mutex_lock(&bman->lock); + *avail = bman->mm.avail >> PAGE_SHIFT; + *visible_avail = bman->visible_avail; + mutex_unlock(&bman->lock); +} +#if
IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
voidi915_ttm_buddy_man_force_visible_size(struct ttm_resource_manager *man, u64 size)drivers/gpu/drm/i915/i915_ttm_buddy_manager.h +3
-0@@ -61,6 +61,9 @@ int i915_ttm_buddy_man_reserve(structttm_resource_manager *man, u64 i915_ttm_buddy_man_visible_size(struct ttm_resource_manager *man); +void i915_ttm_buddy_man_avail (struct ttm_resource_manager *man, + u64 *avail, u64 *avail_visible); + #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) void i915_ttm_buddy_man_force_visible_size(struct ttm_resource_manager *man, u64 size);drivers/gpu/drm/i915/intel_memory_region.c +14
-0@@ -279,6 +279,20 @@ void intel_memory_region_set_name(structintel_memory_region *mem, va_end(ap); } +void intel_memory_region_avail (struct intel_memory_region *mr, + u64 *avail, u64 *visible_avail) +{ + if (mr->type == INTEL_MEMORY_LOCAL) { + i915_ttm_buddy_man_avail(mr->region_private, + avail, visible_avail); + *avail <<= PAGE_SHIFT; + *visible_avail <<= PAGE_SHIFT; + } else { + *avail = mr->total; + *visible_avail = mr->total; + } +} + void intel_memory_region_destroy(struct intel_memory_region *mem) { int ret = 0;drivers/gpu/drm/i915/intel_memory_region.h +3
-0@@ -127,6 +127,9 @@ int intel_memory_region_reserve(structintel_memory_region *mem, void intel_memory_region_debug(struct intel_memory_region *mr, struct drm_printer *printer); +void intel_memory_region_avail (struct intel_memory_region *mr, + u64 *avail, u64 *visible_avail); +struct
intel_memory_region*i915_gem_ttm_system_setup(struct drm_i915_private *i915, u16 type, u16 instance);include/uapi/drm/i915_drm.h +0
-1@@ -3228,7 +3228,15 @@ struct drm_i915_memory_region_info {*/ __u64 probed_size; - /** @unallocated_size: Estimate of memory remaining (-1 =unknown) */
+ /**
+ * @unallocated_size: Estimate of memory remaining (-1 = unknown) + *
+ * RequiresCAP_PERFMONorCAP_SYS_ADMINto get reliable accounting.
+ * Without this (or if this is an older kernel) the value here will + * always equal the @probed_size. Note this is only currently tracked
+ * forI915_MEMORY_CLASS_DEVICEregions (for other types the value here
+ * will always equal the @probed_size).
+ */
__u64unallocated_size;
union {include/uapi/drm/i915_drm.h +21
-0@@ -3262,6 +3270,27 @@ struct drm_i915_memory_region_info {* @probed_size. */ __u64 probed_cpu_visible_size; + + /** + * @unallocated_cpu_visible_size: Estimate of CPU + * visible memory remaining (-1 = unknown). + * + * Note this is only tracked for + * I915_MEMORY_CLASS_DEVICE regions (for other types the + * value here will always equal the + * @probed_cpu_visible_size). + * + * Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable + * accounting. Without this the value here will always + * equal the @probed_cpu_visible_size. Note this is only + * currently tracked for I915_MEMORY_CLASS_DEVICE + * regions (for other types the value here will also + * always equal the @probed_cpu_visible_size). + * + * If this is an older kernel the value here will be + * zero, see also @probed_cpu_visible_size. + */ + __u64 unallocated_cpu_visible_size; }; }; };
Re: [PATCH 03/10] drm/i915/uapi: expose the avail tracking
Quoted 18 lines · Tvrtko Ursulin
Quoted 7 lines · Matthew Auld
Quoted 6 lines · Tvrtko Ursulin
Quoted 3 lines · Matthew Auld
Vulkan would like to have a rough measure of how much device memory can in theory be allocated. Also add
unallocated_cpu_visible_sizeto track the visible portion, in case the device is using small BAR.Quoted 5 lines
Quoted 3 lines
I have concerns here that it isn't useful and could even be counter-productive. If we give unprivileged access it may be considered a side channel, but if we "lie" (report total region size) to unprivileged clients (like in this patch), then they don't co-operate well and end trashing.
Is Vulkan really sure it wants this and why?
Lionel pointed out: https://www.khronos.org/registry/vulkan/specs/1.3-extensions/man/html/VK_EXT_memory_budget.html
So this query would provide
VkPhysicalDeviceMemoryBudgetPropertiesEXT::heapBudget. Apart that it wouldn't since we thought to lie. And apart that it's text says:
Quoted 7 lines
"""
...how much total memory from each heap the current process can use at any given time, before allocations may start failing or causing performance degradation. The values may change based on other activity in the system that is outside the scope and control of the Vulkan implementation. """It acknowledges itself in the second sentence that the first sentence is questionable.
And
VkPhysicalDeviceMemoryBudgetPropertiesEXT::heapUsagewould be still missing and would maybe come via fdinfo? Or you plan to add it to this same query later?
IIUC the heapUsage is something like per app usage, which already looks to be tracked in anv, although I don't think it knows if stuff is actually resident or not. The heapBudget looks to then be roughly the heapUsage + info.unallocated.
Quoted 8 lines
I like to source knowledge of best practices from the long established world of CPU scheduling and process memory management. Is anyone aware of this kind of techniques there - applications actively looking at free memory data from
/proc/meminfoand dynamically adjusting their runtime behaviour based on it? And that they are not single application on a dedicated system type of things.Or perhaps this Vk extension is envisaged for exactly those kind of scenarios? However if so then userspace can know all this data from probed size and the data set it created.
Quoted 1 line
Also note that the existing behaviour was to lie. I'm not sure what's the best option here.
Uapi reserved -1 for unknown so we could do that?
AFAICT we can do that for the info.unallocated_cpu_visible, but not for the existing info.unallocated without maybe breaking something?
Quoted 189 lines
Regards,
Tvrtko
Quoted 184 lines
Quoted 184 lines
Regards,
Tvrtko
Quoted 179 lines
Testcase: igt@i915_query@query-regions-unallocated
Testcase: igt@i915_query@query-regions-sanity-checkSigned-off-by Matthew Auld <[email protected]>Cc Thomas Hellström <[email protected]>Cc Lionel Landwerlin <[email protected]>Cc Tvrtko Ursulin <[email protected]>Cc Jon Bloomfield <[email protected]>Cc Daniel Vetter <[email protected]>Cc Jordan Justen <[email protected]>Cc Kenneth Graunke <[email protected]>Cc Akeem G Abodunrin <[email protected]>---
drivers/gpu/drm/i915/i915_query.c | 10 +++++-drivers/gpu/drm/i915/i915_ttm_buddy_manager.c| 20 ++++++++++++drivers/gpu/drm/i915/i915_ttm_buddy_manager.h| 3 ++ drivers/gpu/drm/i915/intel_memory_region.c | 14 +++++++++ drivers/gpu/drm/i915/intel_memory_region.h | 3 ++ include/uapi/drm/i915_drm.h | 31
++++++++++++++++++-6 files changed, 79 insertions(+), 2 deletions(-)drivers/gpu/drm/i915/i915_query.c +0
-0@@ -502,7 +502,15 @@ static int query_memregion_info(struct drm_i915_private *i915,else
info.probed_cpu_visible_size =mr->total; - info.unallocated_size =mr->avail;
+ if (perfmon_capable()) {
+ intel_memory_region_avail(mr,
+ &info.unallocated_size,
+ &info.unallocated_cpu_visible_size); + } else {
+ info.unallocated_size = info.probed_size; + info.unallocated_cpu_visible_size =
+ info.probed_cpu_visible_size;
+ }
if (__copy_to_user(info_ptr, &info, sizeof(info))) return-EFAULT;drivers/gpu/drm/i915/i915_ttm_buddy_manager.c +2
-0@@ -365,6 +365,26 @@ u64 i915_ttm_buddy_man_visible_size(struct ttm_resource_manager *man) return bman->visible_size; } +/** +* i915_ttm_buddy_man_visible_size - Query the avail tracking for the manager.
+ *
+ * @man: The buddy allocator ttm manager
+ * @avail: The total available memory in pages for the entire manager.
+ * @visible_avail: The total available memory in pages for the CPU visible
+ * portion. Note that this will always give the same value as @avail on
+ * configurations that don't have a small BAR.
+ */drivers/gpu/drm/i915/i915_ttm_buddy_manager.c +11
-0+void i915_ttm_buddy_man_avail (struct ttm_resource_manager *man, + u64 *avail, u64 *visible_avail) +{ + struct i915_ttm_buddy_manager *bman = to_buddy_manager(man); + + mutex_lock(&bman->lock); + *avail = bman->mm.avail >> PAGE_SHIFT; + *visible_avail = bman->visible_avail; + mutex_unlock(&bman->lock); +} +#if
IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
voidi915_ttm_buddy_man_force_visible_size(struct ttm_resource_manager *man, u64 size)drivers/gpu/drm/i915/i915_ttm_buddy_manager.h +3
-0@@ -61,6 +61,9 @@ int i915_ttm_buddy_man_reserve(structttm_resource_manager *man, u64 i915_ttm_buddy_man_visible_size(struct ttm_resource_manager *man); +void i915_ttm_buddy_man_avail (struct ttm_resource_manager *man, + u64 *avail, u64 *avail_visible); + #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) void i915_ttm_buddy_man_force_visible_size(struct ttm_resource_manager *man, u64 size);drivers/gpu/drm/i915/intel_memory_region.c +14
-0@@ -279,6 +279,20 @@ void intel_memory_region_set_name(structintel_memory_region *mem, va_end(ap); } +void intel_memory_region_avail (struct intel_memory_region *mr, + u64 *avail, u64 *visible_avail) +{ + if (mr->type == INTEL_MEMORY_LOCAL) { + i915_ttm_buddy_man_avail(mr->region_private, + avail, visible_avail); + *avail <<= PAGE_SHIFT; + *visible_avail <<= PAGE_SHIFT; + } else { + *avail = mr->total; + *visible_avail = mr->total; + } +} + void intel_memory_region_destroy(struct intel_memory_region *mem) { int ret = 0;drivers/gpu/drm/i915/intel_memory_region.h +3
-0@@ -127,6 +127,9 @@ int intel_memory_region_reserve(structintel_memory_region *mem, void intel_memory_region_debug(struct intel_memory_region *mr, struct drm_printer *printer); +void intel_memory_region_avail (struct intel_memory_region *mr, + u64 *avail, u64 *visible_avail); +struct
intel_memory_region*i915_gem_ttm_system_setup(struct drm_i915_private *i915, u16 type, u16 instance);include/uapi/drm/i915_drm.h +0
-1@@ -3228,7 +3228,15 @@ struct drm_i915_memory_region_info {*/ __u64 probed_size; - /** @unallocated_size: Estimate of memory remaining (-1 =unknown) */
+ /**
+ * @unallocated_size: Estimate of memory remaining (-1 = unknown) + *
+ * RequiresCAP_PERFMONorCAP_SYS_ADMINto get reliable accounting.
+ * Without this (or if this is an older kernel) the value here will
+ * always equal the @probed_size. Note this is only currently tracked
+ * forI915_MEMORY_CLASS_DEVICEregions (for other types the value here
+ * will always equal the @probed_size).
+ */
__u64unallocated_size;
union {include/uapi/drm/i915_drm.h +21
-0@@ -3262,6 +3270,27 @@ struct drm_i915_memory_region_info {* @probed_size. */ __u64 probed_cpu_visible_size; + + /** + * @unallocated_cpu_visible_size: Estimate of CPU + * visible memory remaining (-1 = unknown). + * + * Note this is only tracked for + * I915_MEMORY_CLASS_DEVICE regions (for other types the + * value here will always equal the + * @probed_cpu_visible_size). + * + * Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable + * accounting. Without this the value here will always + * equal the @probed_cpu_visible_size. Note this is only + * currently tracked for I915_MEMORY_CLASS_DEVICE + * regions (for other types the value here will also + * always equal the @probed_cpu_visible_size). + * + * If this is an older kernel the value here will be + * zero, see also @probed_cpu_visible_size. + */ + __u64 unallocated_cpu_visible_size; }; }; };
PATCH 4/10 drm/i915: remove intel_memory_region avail
In reply to Matthew AuldNo longer used.
--- drivers/gpu/drm/i915/intel_memory_region.c | 4 +--- drivers/gpu/drm/i915/intel_memory_region.h | 1 - 2 files changed, 1 insertion(+), 4 deletions(-)
drivers/gpu/drm/i915/intel_memory_region.c +1 -3
@@ -198,8 +198,7 @@ void intel_memory_region_debug(struct intel_memory_region *mr,if (mr->region_private)ttm_resource_manager_debug (mr->region_private, printer);else -drm_printf (printer,"total:%pa, available:%pa bytes\n" , - &mr->total, &mr->avail); +drm_printf (printer,"total:%pa bytes\n" , &mr->total); } static int intel_memory_region_memtest(struct intel_memory_region *mem,
@@ -242,7 +241,6 @@ intel_memory_region_create(struct drm_i915_private *i915, mem->min_page_size = min_page_size; mem->ops = ops; mem->total = size; - mem->avail = mem->total; mem->type = type; mem->instance = instance;
drivers/gpu/drm/i915/intel_memory_region.h +0 -1
@@ -75,7 +75,6 @@ struct intel_memory_region {resource_size_t io_size;resource_size_t min_page_size;resource_size_t total; -resource_size_t avail;u16 type;u16 instance;
Signature · 1 line
2.34.3
Re: [Intel-gfx] [PATCH 04/10] drm/i915: remove intel_memory_region avail
Quoted 43 lines · Matthew Auld
No longer used.
Signed-off-by Matthew Auld <[email protected]>Cc Thomas Hellström <[email protected]>Cc Lionel Landwerlin <[email protected]>Cc Tvrtko Ursulin <[email protected]>Cc Jon Bloomfield <[email protected]>Cc Daniel Vetter <[email protected]>Cc Jordan Justen <[email protected]>Cc Kenneth Graunke <[email protected]>Cc Akeem G Abodunrin <[email protected]>--- drivers/gpu/drm/i915/intel_memory_region.c | 4 +--- drivers/gpu/drm/i915/intel_memory_region.h | 1 - 2 files changed, 1 insertion(+), 4 deletions(-)drivers/gpu/drm/i915/intel_memory_region.c +1
-3@@ -198,8 +198,7 @@ void intel_memory_region_debug(struct intel_memory_region *mr,if (mr->region_private)ttm_resource_manager_debug (mr->region_private, printer);else -drm_printf (printer,"total:%pa, available:%pa bytes\n" , - &mr->total, &mr->avail); +drm_printf (printer,"total:%pa bytes\n" , &mr->total); } static int intel_memory_region_memtest(struct intel_memory_region *mem,@@ -242,7 +241,6 @@ intel_memory_region_create(struct drm_i915_private *i915, mem->min_page_size = min_page_size; mem->ops = ops; mem->total = size; - mem->avail = mem->total; mem->type = type; mem->instance = instance;drivers/gpu/drm/i915/intel_memory_region.h +0
-0
drivers/gpu/drm/i915/intel_memory_region.h struct intel_memory_region { · line 80
Quoted 7 lines
drivers/gpu/drm/i915/intel_memory_region.h +0
-1@@ -75,7 +75,6 @@ struct intel_memory_region {resource_size_t io_size;resource_size_t min_page_size;resource_size_t total; -resource_size_t avail;u16 type;u16 instance;
PATCH 5/10 drm/i915/uapi: apply ALLOC_GPU_ONLY by default
In reply to Matthew AuldOn small BAR configurations, when dealing with I915_MEMORY_CLASS_DEVICE allocations, we assume that by default, all userspace allocations should be placed in the non-CPU visible portion. Note that dumb buffers are not included here, since these are not "GPU accelerated" and likely need CPU access. We choose to just always set GPU_ONLY, and let the backend figure out if that should be ignored or not, for example on full BAR systems.
In a later patch userspace will be able to provide a hint if CPU access to the buffer is needed.
v2(Thomas)
- Apply GPU_ONLY on all discrete devices, but only if the BO can be placed in LMEM. Down in the depths this should be turned into a noop, where required, and as an annotation it still make some sense. If we apply it regardless of the placements then we end up needing to check the placements during exec capture. Also it's slightly inconsistent since the NEEDS_CPU_ACCESS can only be applied on objects that can be placed in LMEM. The other annoyance would be gem_create_ext vs plain gem_create, if we were to always apply GPU_ONLY.
Testcase: igt@gem-create@create-ext-cpu-access-sanity-check
Testcase: igt@gem-create@create-ext-cpu-access-big
--- drivers/gpu/drm/i915/gem/i915_gem_create.c | 8 ++++++++ 1 file changed, 8 insertions(+)
drivers/gpu/drm/i915/gem/i915_gem_create.c +8 -0
@@ -427,6 +427,14 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void *data, ext_data.n_placements =1 ; } +/* +* TODO: add a userspace hint to force CPU_ACCESS for the object, which +* can override this. +*/ +if (ext_data.n_placements >1 || + ext_data.placements[0 ]->type !=INTEL_MEMORY_SYSTEM ) + ext_data.flags |=I915_BO_ALLOC_GPU_ONLY ; + obj = __i915_gem_object_create_user_ext(i915, args->size, ext_data.placements, ext_data.n_placements,
Signature · 1 line
2.34.3
PATCH 6/10 drm/i915/uapi: add NEEDS_CPU_ACCESS hint
In reply to Matthew AuldIf set, force the allocation to be placed in the mappable portion of I915_MEMORY_CLASS_DEVICE. One big restriction here is that system memory (i.e I915_MEMORY_CLASS_SYSTEM) must be given as a potential placement for the object, that way we can always spill the object into system memory if we can't make space.
Testcase: igt@gem-create@create-ext-cpu-access-sanity-check
Testcase: igt@gem-create@create-ext-cpu-access-big
--- drivers/gpu/drm/i915/gem/i915_gem_create.c | 26 ++++++--- include/uapi/drm/i915_drm.h | 61 +++++++++++++++++++--- 2 files changed, 71 insertions(+), 16 deletions(-)
drivers/gpu/drm/i915/gem/i915_gem_create.c +18 -8
@@ -241,6 +241,7 @@ struct create_ext {struct drm_i915_private *i915;struct intel_memory_region *placements[INTEL_REGION_UNKNOWN ];unsigned int n_placements; +unsigned int placement_mask;unsigned long flags; };
@@ -337,6 +338,7 @@ static int set_placements(struct drm_i915_gem_create_ext_memory_regions *args,for (i =0 ; i < args->num_regions; i++) ext_data->placements[i] = placements[i]; + ext_data->placement_mask = mask;return 0 ; out_dump:
@@ -411,7 +413,7 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void *data,struct drm_i915_gem_object *obj;int ret; -if (args->flags) +if (args->flags & ~I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS )return -EINVAL ; ret = i915_user_extensions(u64_to_user_ptr(args->extensions),
@@ -427,13 +429,21 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void *data, ext_data.n_placements =1 ; } -/* -* TODO: add a userspace hint to force CPU_ACCESS for the object, which -* can override this. -*/ -if (ext_data.n_placements >1 || - ext_data.placements[0 ]->type !=INTEL_MEMORY_SYSTEM ) - ext_data.flags |=I915_BO_ALLOC_GPU_ONLY ; +if (args->flags &I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS ) { +if (ext_data.n_placements ==1 ) +return -EINVAL ; + +/* +* We always need to be able to spill to system memory, if we +* can't place in the mappable part of LMEM. +*/ +if (!(ext_data.placement_mask &BIT (INTEL_REGION_SMEM ))) +return -EINVAL ; + }else { +if (ext_data.n_placements >1 || + ext_data.placements[0 ]->type !=INTEL_MEMORY_SYSTEM ) + ext_data.flags |=I915_BO_ALLOC_GPU_ONLY ; + } obj = __i915_gem_object_create_user_ext(i915, args->size, ext_data.placements,
include/uapi/drm/i915_drm.h +53 -8
92 lines not on this page · raw message
Signature · 1 line
2.34.3
Re: [Intel-gfx] [PATCH 06/10] drm/i915/uapi: add NEEDS_CPU_ACCESS hint
LGTM Reviewed-by: Nirmoy Das <[email protected]>
Quoted 179 lines · Matthew Auld
If set, force the allocation to be placed in the mappable portion of
I915_MEMORY_CLASS_DEVICE. One big restriction here is that system memory (i.eI915_MEMORY_CLASS_SYSTEM) must be given as a potential placement for the object, that way we can always spill the object into system memory if we can't make space.Testcase: igt@gem-create@create-ext-cpu-access-sanity-check
Testcase: igt@gem-create@create-ext-cpu-access-bigSigned-off-by Matthew Auld <[email protected]>Cc Thomas Hellström <[email protected]>Cc Lionel Landwerlin <[email protected]>Cc Jon Bloomfield <[email protected]>Cc Daniel Vetter <[email protected]>Cc Jordan Justen <[email protected]>Cc Kenneth Graunke <[email protected]>Cc Akeem G Abodunrin <[email protected]>--- drivers/gpu/drm/i915/gem/i915_gem_create.c | 26 ++++++--- include/uapi/drm/i915_drm.h | 61 +++++++++++++++++++--- 2 files changed, 71 insertions(+), 16 deletions(-)drivers/gpu/drm/i915/gem/i915_gem_create.c +18
-8@@ -241,6 +241,7 @@ struct create_ext {struct drm_i915_private *i915;struct intel_memory_region *placements[INTEL_REGION_UNKNOWN ];unsigned int n_placements; +unsigned int placement_mask;unsigned long flags; };@@ -337,6 +338,7 @@ static int set_placements(struct drm_i915_gem_create_ext_memory_regions *args,for (i =0 ; i < args->num_regions; i++) ext_data->placements[i] = placements[i]; + ext_data->placement_mask = mask;return 0 ; out_dump:@@ -411,7 +413,7 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void *data,struct drm_i915_gem_object *obj;int ret; -if (args->flags) +if (args->flags & ~I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS )return -EINVAL ; ret = i915_user_extensions(u64_to_user_ptr(args->extensions),@@ -427,13 +429,21 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void *data, ext_data.n_placements =1 ; } -/* -* TODO: add a userspace hint to force CPU_ACCESS for the object, which -* can override this. -*/ -if (ext_data.n_placements >1 || - ext_data.placements[0 ]->type !=INTEL_MEMORY_SYSTEM ) - ext_data.flags |=I915_BO_ALLOC_GPU_ONLY ; +if (args->flags &I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS ) { +if (ext_data.n_placements ==1 ) +return -EINVAL ; + +/* +* We always need to be able to spill to system memory, if we +* can't place in the mappable part of LMEM. +*/ +if (!(ext_data.placement_mask &BIT (INTEL_REGION_SMEM ))) +return -EINVAL ; + }else { +if (ext_data.n_placements >1 || + ext_data.placements[0 ]->type !=INTEL_MEMORY_SYSTEM ) + ext_data.flags |=I915_BO_ALLOC_GPU_ONLY ; + } obj = __i915_gem_object_create_user_ext(i915, args->size, ext_data.placements,include/uapi/drm/i915_drm.h +53
-8@@ -3366,11 +3366,11 @@ struct drm_i915_query_memory_regions {* struct drm_i915_gem_create_ext - Existing gem_create behaviour, with added * extension support using struct i915_user_extension. * -* Note that in the future we want to have our buffer flags here, at least for -* the stuff that is immutable. Previously we would have two ioctls, one to -* create the object with gem_create, and another to apply various parameters, -* however this creates some ambiguity for the params which are considered -* immutable. Also in general we're phasing out the various SET/GET ioctls. +* Note that new buffer flags should be added here, at least for the stuff that +* is immutable. Previously we would have two ioctls, one to create the object +* with gem_create, and another to apply various parameters, however this +* creates some ambiguity for the params which are considered immutable. Also in +* general we're phasing out the various SET/GET ioctls. */ struct drm_i915_gem_create_ext {/** @@ -3378,7 +3378,6 @@ struct drm_i915_gem_create_ext {* * The (page-aligned) allocated size for the object will be returned. * -* * DG2 64K min page size implications: * * On discrete platforms, starting from DG2, we have to contend with GTT @@ -3390,7 +3389,9 @@ struct drm_i915_gem_create_ext {* * Note that the returned size here will always reflect any required * rounding up done by the kernel, i.e 4K will now become 64K on devices -* such as DG2. +* such as DG2. The kernel will always select the largest minimum +* page-size for the set of possible placements as the value to use when +* rounding up the @size. * * Special DG2 GTT address alignment requirement: * @@ -3414,14 +3415,58 @@ struct drm_i915_gem_create_ext {* is deemed to be a good compromise. */ __u64 size; +/** * @handle: Returned handle for the object. * * Object handles are nonzero. */ __u32 handle; -/** @flags: MBZ */ + +/** +* @flags: Optional flags. +* +* Supported values: +* +* I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS - Signal to the kernel that +* the object will need to be accessed via the CPU. +* +* Only valid when placing objects in I915_MEMORY_CLASS_DEVICE, and only +* strictly required on configurations where some subset of the device +* memory is directly visible/mappable through the CPU (which we also +* call small BAR), like on some DG2+ systems. Note that this is quite +* undesirable, but due to various factors like the client CPU, BIOS etc +* it's something we can expect to see in the wild. See +* &drm_i915_memory_region_info.probed_cpu_visible_size for how to +* determine if this system applies. +* +* Note that one of the placements MUST be I915_MEMORY_CLASS_SYSTEM, to +* ensure the kernel can always spill the allocation to system memory, +* if the object can't be allocated in the mappable part of +* I915_MEMORY_CLASS_DEVICE. +* +* Also note that since the kernel only supports flat-CCS on objects +* that can *only* be placed in I915_MEMORY_CLASS_DEVICE, we therefore +* don't support I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS together with +* flat-CCS. +* +* Without this hint, the kernel will assume that non-mappable +* I915_MEMORY_CLASS_DEVICE is preferred for this object. Note that the +* kernel can still migrate the object to the mappable part, as a last +* resort, if userspace ever CPU faults this object, but this might be +* expensive, and so ideally should be avoided. +* +* On older kernels which lack the relevant small-bar uAPI support (see +* also &drm_i915_memory_region_info.probed_cpu_visible_size), +* usage of the flag will result in an error, but it should NEVER be +* possible to end up with a small BAR configuration, assuming we can +* also successfully load the i915 kernel module. In such cases the +* entire I915_MEMORY_CLASS_DEVICE region will be CPU accessible, and as +* such there are zero restrictions on where the object can be placed. +*/ +#define I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS (1 << 0)__u32 flags; +/** * @extensions: The chain of extensions to apply to this object. *
Re: [Intel-gfx] [PATCH 06/10] drm/i915/uapi: add NEEDS_CPU_ACCESS hint
In reply to Matthew AuldQuoted 169 lines · Matthew Auld
If set, force the allocation to be placed in the mappable portion of
I915_MEMORY_CLASS_DEVICE. One big restriction here is that system memory (i.eI915_MEMORY_CLASS_SYSTEM) must be given as a potential placement for the object, that way we can always spill the object into system memory if we can't make space.Testcase: igt@gem-create@create-ext-cpu-access-sanity-check
Testcase: igt@gem-create@create-ext-cpu-access-bigSigned-off-by Matthew Auld <[email protected]>Cc Thomas Hellström <[email protected]>Cc Lionel Landwerlin <[email protected]>Cc Jon Bloomfield <[email protected]>Cc Daniel Vetter <[email protected]>Cc Jordan Justen <[email protected]>Cc Kenneth Graunke <[email protected]>Cc Akeem G Abodunrin <[email protected]>--- drivers/gpu/drm/i915/gem/i915_gem_create.c | 26 ++++++--- include/uapi/drm/i915_drm.h | 61 +++++++++++++++++++--- 2 files changed, 71 insertions(+), 16 deletions(-)drivers/gpu/drm/i915/gem/i915_gem_create.c +18
-8@@ -241,6 +241,7 @@ struct create_ext {struct drm_i915_private *i915;struct intel_memory_region *placements[INTEL_REGION_UNKNOWN ];unsigned int n_placements; +unsigned int placement_mask;unsigned long flags; };@@ -337,6 +338,7 @@ static int set_placements(struct drm_i915_gem_create_ext_memory_regions *args,for (i =0 ; i < args->num_regions; i++) ext_data->placements[i] = placements[i]; + ext_data->placement_mask = mask;return 0 ; out_dump:@@ -411,7 +413,7 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void *data,struct drm_i915_gem_object *obj;int ret; -if (args->flags) +if (args->flags & ~I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS )return -EINVAL ; ret = i915_user_extensions(u64_to_user_ptr(args->extensions),@@ -427,13 +429,21 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void *data, ext_data.n_placements =1 ; } -/* -* TODO: add a userspace hint to force CPU_ACCESS for the object, which -* can override this. -*/ -if (ext_data.n_placements >1 || - ext_data.placements[0 ]->type !=INTEL_MEMORY_SYSTEM ) - ext_data.flags |=I915_BO_ALLOC_GPU_ONLY ; +if (args->flags &I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS ) { +if (ext_data.n_placements ==1 ) +return -EINVAL ; + +/* +* We always need to be able to spill to system memory, if we +* can't place in the mappable part of LMEM. +*/ +if (!(ext_data.placement_mask &BIT (INTEL_REGION_SMEM ))) +return -EINVAL ; + }else { +if (ext_data.n_placements >1 || + ext_data.placements[0 ]->type !=INTEL_MEMORY_SYSTEM ) + ext_data.flags |=I915_BO_ALLOC_GPU_ONLY ; + } obj = __i915_gem_object_create_user_ext(i915, args->size, ext_data.placements,include/uapi/drm/i915_drm.h +47
-8@@ -3366,11 +3366,11 @@ struct drm_i915_query_memory_regions {* struct drm_i915_gem_create_ext - Existing gem_create behaviour, with added * extension support using struct i915_user_extension. * -* Note that in the future we want to have our buffer flags here, at least for -* the stuff that is immutable. Previously we would have two ioctls, one to -* create the object with gem_create, and another to apply various parameters, -* however this creates some ambiguity for the params which are considered -* immutable. Also in general we're phasing out the various SET/GET ioctls. +* Note that new buffer flags should be added here, at least for the stuff that +* is immutable. Previously we would have two ioctls, one to create the object +* with gem_create, and another to apply various parameters, however this +* creates some ambiguity for the params which are considered immutable. Also in +* general we're phasing out the various SET/GET ioctls. */ struct drm_i915_gem_create_ext {/** @@ -3378,7 +3378,6 @@ struct drm_i915_gem_create_ext {* * The (page-aligned) allocated size for the object will be returned. * -* * DG2 64K min page size implications: * * On discrete platforms, starting from DG2, we have to contend with GTT @@ -3390,7 +3389,9 @@ struct drm_i915_gem_create_ext {* * Note that the returned size here will always reflect any required * rounding up done by the kernel, i.e 4K will now become 64K on devices -* such as DG2. +* such as DG2. The kernel will always select the largest minimum +* page-size for the set of possible placements as the value to use when +* rounding up the @size. * * Special DG2 GTT address alignment requirement: * @@ -3414,14 +3415,58 @@ struct drm_i915_gem_create_ext {* is deemed to be a good compromise. */ __u64 size; +/** * @handle: Returned handle for the object. * * Object handles are nonzero. */ __u32 handle; -/** @flags: MBZ */ + +/** +* @flags: Optional flags. +* +* Supported values: +* +* I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS - Signal to the kernel that +* the object will need to be accessed via the CPU. +* +* Only valid when placing objects in I915_MEMORY_CLASS_DEVICE, and only +* strictly required on configurations where some subset of the device +* memory is directly visible/mappable through the CPU (which we also +* call small BAR), like on some DG2+ systems. Note that this is quite +* undesirable, but due to various factors like the client CPU, BIOS etc +* it's something we can expect to see in the wild. See +* &drm_i915_memory_region_info.probed_cpu_visible_size for how to +* determine if this system applies. +* +* Note that one of the placements MUST be I915_MEMORY_CLASS_SYSTEM, to +* ensure the kernel can always spill the allocation to system memory, +* if the object can't be allocated in the mappable part of +* I915_MEMORY_CLASS_DEVICE. +* +* Also note that since the kernel only supports flat-CCS on objects +* that can *only* be placed in I915_MEMORY_CLASS_DEVICE, we therefore +* don't support I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS together with +* flat-CCS. +* +* Without this hint, the kernel will assume that non-mappable +* I915_MEMORY_CLASS_DEVICE is preferred for this object. Note that the +* kernel can still migrate the object to the mappable part, as a last +* resort, if userspace ever CPU faults this object, but this might be +* expensive, and so ideally should be avoided. +* +* On older kernels which lack the relevant small-bar uAPI support (see +* also &drm_i915_memory_region_info.probed_cpu_visible_size), +* usage of the flag will result in an error, but it should NEVER be +* possible to end up with a small BAR configuration, assuming we can
include/uapi/drm/i915_drm.h struct drm_i915_gem_create_ext { · line 3472
Quoted 10 lines
include/uapi/drm/i915_drm.h +6
-0+* also successfully load the i915 kernel module. In such cases the +* entire I915_MEMORY_CLASS_DEVICE region will be CPU accessible, and as +* such there are zero restrictions on where the object can be placed. +*/ +#define I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS (1 << 0)__u32 flags; +/** * @extensions: The chain of extensions to apply to this object. *
PATCH 7/10 drm/i915/error: skip non-mappable pages
In reply to Matthew AuldSkip capturing any lmem pages that can't be copied using the CPU. This in now only best effort on platforms that have small BAR.
Testcase: igt@gem-exec-capture@capture-invisible
--- drivers/gpu/drm/i915/i915_gpu_error.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-)
drivers/gpu/drm/i915/i915_gpu_error.c +7 -3
@@ -1116,11 +1116,15 @@ i915_vma_coredump_create(const struct intel_gt *gt,dma_addr_t dma;for_each_sgt_daddr (dma, iter, vma_res->bi.pages) { +dma_addr_t offset = dma - mem->region.start;void __iomem *s; - s =io_mapping_map_wc (&mem->iomap, - dma - mem->region.start, -PAGE_SIZE ); +if (offset +PAGE_SIZE > mem->io_size) { + ret = -EINVAL ; +break ; + } + + s =io_mapping_map_wc (&mem->iomap, offset,PAGE_SIZE ); ret =compress_page (compress, (void __force *)s, dst, true);
Signature · 1 line
2.34.3
Re: [Intel-gfx] [PATCH 07/10] drm/i915/error: skip non-mappable pages
Quoted 40 lines · Matthew Auld
Skip capturing any lmem pages that can't be copied using the CPU. This in now only best effort on platforms that have small BAR.
Testcase: igt@gem-exec-capture@capture-invisible
Signed-off-by Matthew Auld <[email protected]>Cc Thomas Hellström <[email protected]>Cc Lionel Landwerlin <[email protected]>Cc Tvrtko Ursulin <[email protected]>Cc Jon Bloomfield <[email protected]>Cc Daniel Vetter <[email protected]>Cc Jordan Justen <[email protected]>Cc Kenneth Graunke <[email protected]>Cc Akeem G Abodunrin <[email protected]>--- drivers/gpu/drm/i915/i915_gpu_error.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-)drivers/gpu/drm/i915/i915_gpu_error.c +7
-3@@ -1116,11 +1116,15 @@ i915_vma_coredump_create(const struct intel_gt *gt,dma_addr_t dma;for_each_sgt_daddr (dma, iter, vma_res->bi.pages) { +dma_addr_t offset = dma - mem->region.start;void __iomem *s; - s =io_mapping_map_wc (&mem->iomap, - dma - mem->region.start, -PAGE_SIZE ); +if (offset +PAGE_SIZE > mem->io_size) { + ret = -EINVAL ; +break ; + } + + s =io_mapping_map_wc (&mem->iomap, offset,PAGE_SIZE ); ret =compress_page (compress, (void __force *)s, dst, true);
Re: [Intel-gfx] [PATCH 07/10] drm/i915/error: skip non-mappable pages
In reply to Matthew AuldQuoted 30 lines · Matthew Auld
Skip capturing any lmem pages that can't be copied using the CPU. This in now only best effort on platforms that have small BAR.
Testcase: igt@gem-exec-capture@capture-invisible
Signed-off-by Matthew Auld <[email protected]>Cc Thomas Hellström <[email protected]>Cc Lionel Landwerlin <[email protected]>Cc Tvrtko Ursulin <[email protected]>Cc Jon Bloomfield <[email protected]>Cc Daniel Vetter <[email protected]>Cc Jordan Justen <[email protected]>Cc Kenneth Graunke <[email protected]>Cc Akeem G Abodunrin <[email protected]>--- drivers/gpu/drm/i915/i915_gpu_error.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-)drivers/gpu/drm/i915/i915_gpu_error.c +1
-2@@ -1116,11 +1116,15 @@ i915_vma_coredump_create(const struct intel_gt *gt,dma_addr_t dma;for_each_sgt_daddr (dma, iter, vma_res->bi.pages) { +dma_addr_t offset = dma - mem->region.start;void __iomem *s; - s = io_mapping_map_wc(&mem->iomap, - dma - mem->region.start,
drivers/gpu/drm/i915/i915_gpu_error.c i915_vma_coredump_create(const struct intel_gt *gt, · line 1130
Quoted 10 lines
drivers/gpu/drm/i915/i915_gpu_error.c +6
-1- PAGE_SIZE); +if (offset +PAGE_SIZE > mem->io_size) { + ret = -EINVAL ; +break ; + } + + s =io_mapping_map_wc (&mem->iomap, offset,PAGE_SIZE ); ret =compress_page (compress, (void __force *)s, dst, true);
PATCH 8/10 drm/i915/uapi: disable capturing objects on recoverable contexts
In reply to Matthew AuldA non-recoverable context must be used if the user wants proper error capture on discrete platforms. In the future the kernel may want to blit the contents of some objects when later doing the capture stage.
Testcase: igt@gem_exec_capture@capture-recoverable-discrete
--- drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-)
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +10 -2
@@ -1961,7 +1961,7 @@ eb_find_first_request_added(struct i915_execbuffer *eb)#if IS_ENABLED (CONFIG_DRM_I915_CAPTURE_ERROR )/* Stage with GFP_KERNEL allocations before we enter the signaling critical path */ -static void eb_capture_stage (struct i915_execbuffer *eb) +static int eb_capture_stage (struct i915_execbuffer *eb) {const unsigned int count = eb->buffer_count;unsigned int i = count, j;
@@ -1974,6 +1974,10 @@ static void eb_capture_stage(struct i915_execbuffer *eb)if (!(flags &EXEC_OBJECT_CAPTURE ))continue ; +if (i915_gem_context_is_recoverable (eb->gem_context) && +IS_DGFX (eb->i915)) +return -EINVAL ; +for_each_batch_create_order (eb, j) {struct i915_capture_list *capture;
@@ -1986,6 +1990,8 @@ static void eb_capture_stage(struct i915_execbuffer *eb) eb->capture_lists[j] = capture; } } + +return 0 ; }/* Commit once we're in the critical path */
@@ -3420,7 +3426,9 @@ i915_gem_do_execbuffer(struct drm_device *dev, }ww_acquire_done (&eb.ww.ctx); -eb_capture_stage (&eb); + err =eb_capture_stage (&eb); +if (err) + goto err_vma; out_fence =eb_requests_create (&eb, in_fence, out_fence_fd);if (IS_ERR (out_fence)) {
Signature · 1 line
2.34.3
kernel test robot
build botRe: [Intel-gfx] [PATCH 08/10] drm/i915/uapi: disable capturing objects on recoverable contexts
Thank you for the patch! Yet something to improve:
Hi Matthew,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-tip/drm-tip]
[also build test ERROR on v5.18 next-20220525]
[cannot apply to drm-intel/for-linux-next drm/drm-next]
[If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/intel-lab-lkp/linux/commits/Matthew-Auld/small-BAR-uapi-bits/20220526-024641 base: git://anongit.freedesktop.org/drm/drm-tip drm-tip config: i386-randconfig-a004 (https://download.01.org/0day-ci/archive/20220526/[email protected]/config) compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project d52a6e75b0c402c7f3b42a2b1b2873f151220947)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/fdc3574e30bb0fdfdc9569fa42d369b1fae41e9e
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Matthew-Auld/small-BAR-uapi-bits/20220526-024641 git checkout fdc3574e30bb0fdfdc9569fa42d369b1fae41e9e
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=i386 SHELL=/bin/bash
If you fix the issue, kindly add following tag where applicable
All errors (new ones prefixed by >>):
>> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:3429:6: error: assigning to 'int' from incompatible type 'void'
err = eb_capture_stage(&eb);
^ ~~~~~~~~~~~~~~~~~~~~~1 error generated.
vim +3429 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
3384
3385 if (args->flags & I915_EXEC_FENCE_OUT) {
3386 out_fence_fd = get_unused_fd_flags(O_CLOEXEC);
3387 if (out_fence_fd < 0) {
3388 err = out_fence_fd;
3389 goto err_in_fence;
3390 }
3391 }
3392
3393 err = eb_create(&eb);
3394 if (err)
3395 goto err_out_fence;
3396
3397 GEM_BUG_ON(!eb.lut_size);
3398
3399 err = eb_select_context(&eb);
3400 if (unlikely(err))
3401 goto err_destroy;
3402
3403 err = eb_select_engine(&eb);
3404 if (unlikely(err))
3405 goto err_context;
3406
3407 err = eb_lookup_vmas(&eb);
3408 if (err) {
3409 eb_release_vmas(&eb, true);
3410 goto err_engine;
3411 }
3412
3413 i915_gem_ww_ctx_init(&eb.ww, true);
3414
3415 err = eb_relocate_parse(&eb);
3416 if (err) {
3417 /*
3418 * If the user expects the execobject.offset and
3419 * reloc.presumed_offset to be an exact match,
3420 * as for using NO_RELOC, then we cannot update
3421 * the execobject.offset until we have completed
3422 * relocation.
3423 */
3424 args->flags &= ~__EXEC_HAS_RELOC;
3425 goto err_vma;
3426 }
3427
3428 ww_acquire_done(&eb.ww.ctx);
> 3429 err = eb_capture_stage(&eb);
3430 if (err)
3431 goto err_vma;
3432
3433 out_fence = eb_requests_create(&eb, in_fence, out_fence_fd);
3434 if (IS_ERR(out_fence)) {
3435 err = PTR_ERR(out_fence);
3436 out_fence = NULL;
3437 if (eb.requests[0])
3438 goto err_request;
3439 else
3440 goto err_vma;
3441 }
3442
3443 err = eb_submit(&eb);
3444
3445 err_request:
3446 eb_requests_get(&eb);
3447 err = eb_requests_add(&eb, err);
3448
3449 if (eb.fences)
3450 signal_fence_array(&eb, eb.composite_fence ?
3451 eb.composite_fence :
3452 &eb.requests[0]->fence);
3453
3454 if (out_fence) {
3455 if (err == 0) {
3456 fd_install(out_fence_fd, out_fence->file);
3457 args->rsvd2 &= GENMASK_ULL(31, 0); /* keep in-fence */
3458 args->rsvd2 |= (u64)out_fence_fd << 32;
3459 out_fence_fd = -1;
3460 } else {
3461 fput(out_fence->file);
3462 }
3463 }
3464
3465 if (unlikely(eb.gem_context->syncobj)) {
3466 drm_syncobj_replace_fence(eb.gem_context->syncobj,
3467 eb.composite_fence ?
3468 eb.composite_fence :
3469 &eb.requests[0]->fence); 3470 }
3471
3472 if (!out_fence && eb.composite_fence)
3473 dma_fence_put(eb.composite_fence);
3474
3475 eb_requests_put(&eb);
3476
3477 err_vma:
3478 eb_release_vmas(&eb, true);
3479 WARN_ON(err == -EDEADLK);
3480 i915_gem_ww_ctx_fini(&eb.ww);
3481
3482 if (eb.batch_pool)
3483 intel_gt_buffer_pool_put(eb.batch_pool);
3484 err_engine:
3485 eb_put_engine(&eb);
3486 err_context:
3487 i915_gem_context_put(eb.gem_context);
3488 err_destroy:
3489 eb_destroy(&eb);
3490 err_out_fence:
3491 if (out_fence_fd != -1)
3492 put_unused_fd(out_fence_fd);
3493 err_in_fence:
3494 dma_fence_put(in_fence);
3495 err_ext:
3496 put_fence_array(eb.fences, eb.num_fences);
3497 return err;
3498 }
3499
Signature · 2 lines
0-DAY CI Kernel Test Service https://01.org/lkp
Re: [Intel-gfx] [PATCH 08/10] drm/i915/uapi: disable capturing objects on recoverable contexts
In reply to Matthew AuldQuoted 32 lines · Matthew Auld
A non-recoverable context must be used if the user wants proper error capture on discrete platforms. In the future the kernel may want to blit the contents of some objects when later doing the capture stage.
Testcase: igt@gem_exec_capture@capture-recoverable-discrete
Signed-off-by Matthew Auld <[email protected]>Cc Thomas Hellström <[email protected]>Cc Lionel Landwerlin <[email protected]>Cc Tvrtko Ursulin <[email protected]>Cc Jon Bloomfield <[email protected]>Cc Daniel Vetter <[email protected]>Cc Jordan Justen <[email protected]>Cc Kenneth Graunke <[email protected]>Cc Akeem G Abodunrin <[email protected]>--- drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-)drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +1
-1@@ -1961,7 +1961,7 @@ eb_find_first_request_added(struct i915_execbuffer *eb)#if IS_ENABLED (CONFIG_DRM_I915_CAPTURE_ERROR )/* Stage with GFP_KERNEL allocations before we enter the signaling critical path */ -static void eb_capture_stage (struct i915_execbuffer *eb) +static int eb_capture_stage (struct i915_execbuffer *eb) {const unsigned int count = eb->buffer_count;unsigned int i = count, j;
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c static void eb_capture_stage(struct i915_execbuffer *eb) · line 1980
Quoted 7 lines
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c +4
-0@@ -1974,6 +1974,10 @@ static void eb_capture_stage(struct i915_execbuffer *eb)if (!(flags &EXEC_OBJECT_CAPTURE ))continue ; +if (i915_gem_context_is_recoverable (eb->gem_context) && +IS_DGFX (eb->i915)) +return -EINVAL ; +
We should also require this for future integrated, for capture buffer memory allocation purposes.
Otherwise Reviewed-by: Thomas Hellström <[email protected]>
PATCH 9/10 drm/i915: turn on small BAR support
In reply to Matthew AuldWith the uAPI in place we should now have enough in place to ensure a working system on small BAR configurations.
--- drivers/gpu/drm/i915/gt/intel_region_lmem.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-)
drivers/gpu/drm/i915/gt/intel_region_lmem.c +4 -6
@@ -111,12 +111,6 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt) flat_ccs_base =intel_gt_read_register (gt,XEHPSDV_FLAT_CCS_BASE_ADDR ); flat_ccs_base = (flat_ccs_base >>XEHPSDV_CCS_BASE_SHIFT ) *SZ_64K ; -/* FIXME: Remove this when we have small-bar enabled */ -if (pci_resource_len (pdev,2 ) < lmem_size) { -drm_err (&i915->drm,"System requires small-BAR support, which is currently unsupported on this kernel\n" ); -return ERR_PTR (-EINVAL ); - } -if (GEM_WARN_ON (lmem_size < flat_ccs_base))return ERR_PTR (-EIO );
@@ -169,6 +163,10 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)drm_info (&i915->drm,"Local memory available: %pa\n" , &lmem_size); +if (io_size < lmem_size) +drm_info (&i915->drm,"Using a reduced BAR size of %lluMiB. Consider enabling the full BAR size if available in the BIOS.\n" , + (u64 )io_size >>20 ); +return mem; err_region_put:
Signature · 1 line
2.34.3
Re: [Intel-gfx] [PATCH 09/10] drm/i915: turn on small BAR support
Quoted 34 lines · Matthew Auld
With the uAPI in place we should now have enough in place to ensure a working system on small BAR configurations.
Signed-off-by Matthew Auld <[email protected]>Cc Thomas Hellström <[email protected]>Cc Lionel Landwerlin <[email protected]>Cc Tvrtko Ursulin <[email protected]>Cc Jon Bloomfield <[email protected]>Cc Daniel Vetter <[email protected]>Cc Jordan Justen <[email protected]>Cc Kenneth Graunke <[email protected]>Cc Akeem G Abodunrin <[email protected]>--- drivers/gpu/drm/i915/gt/intel_region_lmem.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-)drivers/gpu/drm/i915/gt/intel_region_lmem.c +0
-6@@ -111,12 +111,6 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt) flat_ccs_base =intel_gt_read_register (gt,XEHPSDV_FLAT_CCS_BASE_ADDR ); flat_ccs_base = (flat_ccs_base >>XEHPSDV_CCS_BASE_SHIFT ) *SZ_64K ; -/* FIXME: Remove this when we have small-bar enabled */ -if (pci_resource_len (pdev,2 ) < lmem_size) { -drm_err (&i915->drm,"System requires small-BAR support, which is currently unsupported on this kernel\n" ); -return ERR_PTR (-EINVAL ); - } -if (GEM_WARN_ON (lmem_size < flat_ccs_base))return ERR_PTR (-EIO );
drivers/gpu/drm/i915/gt/intel_region_lmem.c static struct intel_memory_region *setup_lmem(struct intel_gt *gt) · line 169
Quoted 7 lines
drivers/gpu/drm/i915/gt/intel_region_lmem.c +4
-0@@ -169,6 +163,10 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)drm_info (&i915->drm,"Local memory available: %pa\n" , &lmem_size); +if (io_size < lmem_size) +drm_info (&i915->drm,"Using a reduced BAR size of %lluMiB. Consider enabling the full BAR size if available in the BIOS.\n" , + (u64 )io_size >>20 ); +
Hmm. I wonder what BIOS uis typically call the mappable portion of VRAM. I'll se if I can check that on my DG1 system. Might be that an average user misinterprets "full BAR".
/Thomas
Quoted 3 lines
drivers/gpu/drm/i915/gt/intel_region_lmem.c +0
-0return mem; err_region_put:
Re: [Intel-gfx] [PATCH 09/10] drm/i915: turn on small BAR support
Quoted 38 lines · Thomas Hellström
Quoted 36 lines · Matthew Auld
With the uAPI in place we should now have enough in place to ensure a working system on small BAR configurations.
Signed-off-by Matthew Auld <[email protected]>Cc Thomas Hellström <[email protected]>Cc Lionel Landwerlin <[email protected]>Cc Tvrtko Ursulin <[email protected]>Cc Jon Bloomfield <[email protected]>Cc Daniel Vetter <[email protected]>Cc Jordan Justen <[email protected]>Cc Kenneth Graunke <[email protected]>Cc Akeem G Abodunrin <[email protected]>---
drivers/gpu/drm/i915/gt/intel_region_lmem.c| 10 ++++------1 file changed, 4 insertions(+), 6 deletions(-)drivers/gpu/drm/i915/gt/intel_region_lmem.c +0
-6@@ -111,12 +111,6 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt) flat_ccs_base = intel_gt_read_register(gt, XEHPSDV_FLAT_CCS_BASE_ADDR); flat_ccs_base = (flat_ccs_base >> XEHPSDV_CCS_BASE_SHIFT) * SZ_64K; - /* FIXME: Remove this when we have small-bar enabled */ - if (pci_resource_len(pdev, 2) < lmem_size) { - drm_err(&i915->drm, "System requires small-BAR support, which is currently unsupported on this kernel\n"); - return ERR_PTR(-EINVAL); - } - if (GEM_WARN_ON(lmem_size < flat_ccs_base)) return ERR_PTR(-EIO);@@ -169,6 +163,10 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt) drm_info(&i915->drm, "Local memory available: %pa\n",
Quoted 8 lines
drivers/gpu/drm/i915/gt/intel_region_lmem.c static struct intel_memory_region *setup_lmem(struct intel_gt *gt) · line 169
Quoted 6 lines
drivers/gpu/drm/i915/gt/intel_region_lmem.c +4
-0&lmem_size); + if (io_size < lmem_size) + drm_info(&i915->drm, "Using a reduced BAR size of %lluMiB. Consider enabling the full BAR size if available in the BIOS.\n", + (u64)io_size >> 20); +Hmm. I wonder what BIOS uis typically call the mappable portion of VRAM. I'll se if I can check that on my DG1 system. Might be that an average user misinterprets "full BAR".
"PCI Subsystem settings" -> "Above 4G memory [enabled/disabled]"
Sample size of one though.
Maybe s/full BAR size/full memory size/ ?
Quoted 7 lines
/Thomas
Quoted 2 lines
drivers/gpu/drm/i915/gt/intel_region_lmem.c +0
-0return mem;
err_region_put:
Re: [Intel-gfx] [PATCH 09/10] drm/i915: turn on small BAR support
Quoted 48 lines · Matthew Auld
Quoted 38 lines · Thomas Hellström
Quoted 36 lines · Matthew Auld
With the uAPI in place we should now have enough in place to ensure a working system on small BAR configurations.
Signed-off-by Matthew Auld <[email protected]>Cc Thomas Hellström <[email protected]>Cc Lionel Landwerlin <[email protected]>Cc Tvrtko Ursulin <[email protected]>Cc Jon Bloomfield <[email protected]>Cc Daniel Vetter <[email protected]>Cc Jordan Justen <[email protected]>Cc Kenneth Graunke <[email protected]>Cc Akeem G Abodunrin <[email protected]>---
drivers/gpu/drm/i915/gt/intel_region_lmem.c| 10 ++++------1 file changed, 4 insertions(+), 6 deletions(-)drivers/gpu/drm/i915/gt/intel_region_lmem.c +0
-6@@ -111,12 +111,6 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt) flat_ccs_base = intel_gt_read_register(gt, XEHPSDV_FLAT_CCS_BASE_ADDR); flat_ccs_base = (flat_ccs_base >> XEHPSDV_CCS_BASE_SHIFT) * SZ_64K; - /* FIXME: Remove this when we have small-bar enabled */ - if (pci_resource_len(pdev, 2) < lmem_size) { - drm_err(&i915->drm, "System requires small-BAR support, which is currently unsupported on this kernel\n"); - return ERR_PTR(-EINVAL); - } - if (GEM_WARN_ON(lmem_size < flat_ccs_base)) return ERR_PTR(-EIO);@@ -169,6 +163,10 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt) drm_info(&i915->drm, "Local memory available: %pa\n",Quoted 8 lines
drivers/gpu/drm/i915/gt/intel_region_lmem.c static struct intel_memory_region *setup_lmem(struct intel_gt *gt) · line 169
Quoted 6 lines
drivers/gpu/drm/i915/gt/intel_region_lmem.c +4
-0&lmem_size); + if (io_size < lmem_size) + drm_info(&i915->drm, "Using a reduced BAR size of %lluMiB. Consider enabling the full BAR size if available in the BIOS.\n", + (u64)io_size >> 20); +Hmm. I wonder what BIOS uis typically call the mappable portion of VRAM. I'll se if I can check that on my DG1 system. Might be that an average user misinterprets "full BAR".
Quoted 5 lines
"PCI Subsystem settings" -> "Above 4G memory [enabled/disabled]"
Sample size of one though.
Maybe s/full BAR size/full memory size/ ?
Or s/full BAR size/re-sizable BAR/
In newer BIOS, there is a more direct option to enable re-sizable bar: "Re-Size BAR"/"Resizable BAR".
Nirmoy
Quoted 8 lines
Quoted 8 lines
/Thomas
Quoted 2 lines
drivers/gpu/drm/i915/gt/intel_region_lmem.c +0
-0return mem;
err_region_put:
Re: [Intel-gfx] [PATCH 09/10] drm/i915: turn on small BAR support
Quoted 67 lines · Nirmoy
Quoted 65 lines · Matthew Auld
Quoted 51 lines · Thomas Hellström
Quoted 49 lines · Matthew Auld
With the uAPI in place we should now have enough in place to ensure a
working system on small BAR configurations.Signed-off-by Matthew Auld <[email protected]>Cc Thomas Hellström <[email protected]>Cc Lionel Landwerlin <[email protected]>Cc Tvrtko Ursulin <[email protected]>Cc Jon Bloomfield <[email protected]>Cc Daniel Vetter <[email protected]>Cc Jordan Justen <[email protected]>Cc Kenneth Graunke <[email protected]>Cc Akeem G Abodunrin <[email protected]>---
drivers/gpu/drm/i915/gt/intel_region_lmem.c| 10 ++++------1 file changed, 4 insertions(+), 6 deletions(-)drivers/gpu/drm/i915/gt/intel_region_lmem.c +0
-0@@ -111,12 +111,6 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt) flat_ccs_base = intel_gt_read_register(gt,XEHPSDV_FLAT_CCS_BASE_ADDR );
flat_ccs_base= (flat_ccs_base>>XEHPSDV_CCS_BASE_SHIFT)
*SZ_64K;
- /* FIXME: Remove this when we have small-bar enabled */
- if (pci_resource_len(pdev, 2)<lmem_size) { - drm_err(&i915->drm, "System requires small-BAR support,
which is currently unsupported on this kernel\n"); - returnERR_PTR(-EINVAL);
- }
-
if (GEM_WARN_ON(lmem_size < flat_ccs_base)) returnERR_PTR(-EIO);drivers/gpu/drm/i915/gt/intel_region_lmem.c +2
-0@@ -169,6 +163,10 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt) drm_info(&i915->drm, "Local memory available: %pa\n", &lmem_size); + if (io_size < lmem_size) + drm_info(&i915->drm, "Using a reduced BAR size of%lluMiB.
Consider enabling the full BAR size if available in the BIOS.\n",Quoted 8 lines
Quoted 2 lines
+ (u64)io_size >> 20);
+Hmm. I wonder what BIOS uis typically call the mappable portion of
VRAM. I'll se if I can check that on my DG1 system. Might be that an
average user misinterprets "full BAR"."PCI Subsystem settings" -> "Above 4G memory [enabled/disabled]"
Sample size of one though.
Quoted 8 lines
Quoted 1 line
Maybe s/full BAR size/full memory size/ ?
Or s/full BAR size/re-sizable BAR/
In newer BIOS, there is a more direct option to enable re-sizable bar:
"Re-Size BAR"/"Resizable BAR".
A quick googling turns up "Resizable BAR". My Asus Bios on the DG1 machine says "ReSize BAR (Resizable BAR support to harness full GPU memory)".
So "Resizable BAR" should hopefully be understood by most people. Not sure though if this is the same as "Above 4G memory", although the latter must be a prerequisite I assume.
/Thomas
Quoted 12 lines
Nirmoy
Quoted 8 lines
Quoted 8 lines
/Thomas
Quoted 2 lines
return mem;
err_region_put:
PATCH 10/10 HAX: force small BAR on dg2
In reply to Matthew AuldJust for CI.
--- drivers/gpu/drm/i915/gt/intel_region_lmem.c | 5 +++++ 1 file changed, 5 insertions(+)
drivers/gpu/drm/i915/gt/intel_region_lmem.c +5 -0
@@ -137,6 +137,11 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)if (!io_size)return ERR_PTR (-EIO ); +if (io_size == lmem_size) { +drm_info (&i915->drm,"NOTE!! Forcing small BAR for testing\n" ); + io_size =SZ_256M ; + } + min_page_size =HAS_64K_PAGES (i915) ?I915_GTT_PAGE_SIZE_64K :I915_GTT_PAGE_SIZE_4K ; mem = intel_memory_region_create(i915,
Signature · 1 line
2.34.3
Patchwork
CI[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for small BAR uapi bits
In reply to Matthew Auld== Series Details ==
== Series Details ==
Series: small BAR uapi bits
URL : https://patchwork.freedesktop.org/series/104369/
State : warning
== Summary ==
Error: dim checkpatch failed66b32284c514 drm/doc: add rfc section for small BAR uapi
-:39: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #39:
new file mode 100644
-:44: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #44: FILE: Documentation/gpu/rfc/i915_small_bar.h:1:
+/**
-:239: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1 #239: FILE: Documentation/gpu/rfc/i915_small_bar.rst:1:
+==========================
total: 0 errors, 3 warnings, 0 checks, 243 lines checked d0b07a894a2d drm/i915/uapi: add probed_cpu_visible_size 8032649ad9b4 drm/i915/uapi: expose the avail tracking
-:64: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #64: FILE: drivers/gpu/drm/i915/i915_ttm_buddy_manager.c:378:
+void i915_ttm_buddy_man_avail(struct ttm_resource_manager *man,
+ u64 *avail, u64 *visible_avail)
total: 0 errors, 0 warnings, 1 checks, 123 lines checkedf35be1eecfeb drm/i915: remove intel_memory_region avail067a5be47ce8 drm/i915/uapi: apply ALLOC_GPU_ONLY by defaultd8b5695bf10d drm/i915/uapi: add NEEDS_CPU_ACCESS hint
-:11: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #11:
(i.e I915_MEMORY_CLASS_SYSTEM) must be given as a potential placement for the
total: 0 errors, 1 warnings, 0 checks, 142 lines checked 5db83995a280 drm/i915/error: skip non-mappable pages11b92ed0b0fb drm/i915/uapi: disable capturing objects on recoverable contexts 405a2d9301e6 drm/i915: turn on small BAR support6a930607cce6 HAX: force small BAR on dg2
Patchwork
CI[Intel-gfx] ✗ Fi.CI.SPARSE: warning for small BAR uapi bits
In reply to Matthew Auld== Series Details ==
== Series Details ==
Series: small BAR uapi bits
URL : https://patchwork.freedesktop.org/series/104369/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
Patchwork
CI[Intel-gfx] ✓ Fi.CI.BAT: success for small BAR uapi bits
In reply to Matthew Auld== Series Details ==
== Series Details ==
Series: small BAR uapi bits
URL : https://patchwork.freedesktop.org/series/104369/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11700 -> Patchwork_104369v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/index.html
Participating hosts (46 -> 43)
------------------------------
Missing (3): bat-dg2-8 fi-rkl-11600 bat-dg1-5
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_104369v1:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses. They do not affect the overall result.
* igt@i915_pm_rpm@basic-rte:
- {bat-dg2-9}: [SKIP][1] ([i915#5174]) -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/bat-dg2-9/igt@[email protected]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/bat-dg2-9/igt@[email protected]
Known issues
------------
Here are the changes found in Patchwork_104369v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@gem:
- fi-pnv-d510: NOTRUN -> [DMESG-FAIL][3] ([i915#4528])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/fi-pnv-d510/igt@i915_selftest@[email protected]
* igt@i915_selftest@live@gt_engines:
- bat-dg1-6: [PASS][4] -> [INCOMPLETE][5] ([i915#4418])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/bat-dg1-6/igt@i915_selftest@live@gt_engines.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/bat-dg1-6/igt@i915_selftest@live@gt_engines.html
* igt@i915_selftest@live@gtt:
- fi-bdw-5557u: [PASS][6] -> [DMESG-FAIL][7] ([i915#3674])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/fi-bdw-5557u/igt@i915_selftest@[email protected]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/fi-bdw-5557u/igt@i915_selftest@[email protected]
* igt@kms_flip@basic-flip-vs-dpms@a-edp1:
- fi-tgl-u2: [PASS][8] -> [DMESG-WARN][9] ([i915#402]) +1 similar issue
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/fi-tgl-u2/igt@kms_flip@[email protected]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/fi-tgl-u2/igt@kms_flip@[email protected]
* igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- bat-adlp-4: [PASS][10] -> [DMESG-WARN][11] ([i915#3576])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/bat-adlp-4/igt@kms_flip@[email protected]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/bat-adlp-4/igt@kms_flip@[email protected]
#### Possible fixes ####
* igt@fbdev@read:
- {bat-dg2-9}: [SKIP][12] ([i915#2582]) -> [PASS][13] +4 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/bat-dg2-9/igt@[email protected]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/bat-dg2-9/igt@[email protected]
* igt@i915_getparams_basic@basic-eu-total:
- {bat-dg2-9}: [SKIP][14] ([i915#2575]) -> [PASS][15] +27 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/bat-dg2-9/igt@[email protected]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/bat-dg2-9/igt@[email protected]
* igt@i915_pm_rpm@basic-pci-d3-state:
- {bat-dg2-9}: [SKIP][16] ([i915#5174]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/bat-dg2-9/igt@[email protected]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/bat-dg2-9/igt@[email protected]
* igt@i915_selftest@live@hugepages:
- {bat-adln-1}: [DMESG-WARN][18] -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/bat-adln-1/igt@i915_selftest@[email protected]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/bat-adln-1/igt@i915_selftest@[email protected]
* igt@i915_selftest@live@requests:
- bat-adlp-4: [DMESG-FAIL][20] -> [PASS][21]
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/bat-adlp-4/igt@i915_selftest@[email protected]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/bat-adlp-4/igt@i915_selftest@[email protected]
- fi-pnv-d510: [DMESG-FAIL][22] ([i915#4528]) -> [PASS][23]
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/fi-pnv-d510/igt@i915_selftest@[email protected]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/fi-pnv-d510/igt@i915_selftest@[email protected]
* igt@kms_addfb_basic@addfb25-yf-tiled-legacy:
- {bat-dg2-9}: [SKIP][24] ([i915#5171] / [i915#5190]) -> [PASS][25] +1 similar issue
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/bat-dg2-9/igt@[email protected]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/bat-dg2-9/igt@[email protected]
* igt@kms_addfb_basic@bo-too-small:
- {bat-dg2-9}: [SKIP][26] ([i915#5171]) -> [PASS][27] +45 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/bat-dg2-9/igt@[email protected]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/bat-dg2-9/igt@[email protected]
* igt@kms_flip@basic-flip-vs-modeset@b-edp1:
- {bat-adlp-6}: [DMESG-WARN][28] ([i915#3576]) -> [PASS][29]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/bat-adlp-6/igt@kms_flip@[email protected]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/bat-adlp-6/igt@kms_flip@[email protected]
- bat-adlp-4: [DMESG-WARN][30] ([i915#3576]) -> [PASS][31] +1 similar issue
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/bat-adlp-4/igt@kms_flip@[email protected]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/bat-adlp-4/igt@kms_flip@[email protected]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
[i915#3674]: https://gitlab.freedesktop.org/drm/intel/issues/3674
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4418]: https://gitlab.freedesktop.org/drm/intel/issues/4418
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#5171]: https://gitlab.freedesktop.org/drm/intel/issues/5171
[i915#5174]: https://gitlab.freedesktop.org/drm/intel/issues/5174
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
Build changes
-------------
* IGT: IGT_6492 -> IGTPW_7174
* Linux: CI_DRM_11700 -> Patchwork_104369v1
CI-20190529: 20190529
CI_DRM_11700: f5895776c32b7fc5c196fafef3f5dab7e5ad19c6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_7174: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/index.html
IGT_6492: ef18e59c374472e961a3a145724e7381eb4800aa @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_104369v1: f5895776c32b7fc5c196fafef3f5dab7e5ad19c6 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
47888d6ee3aa HAX: force small BAR on dg25e24a572e647 drm/i915: turn on small BAR support326cfef39f1c drm/i915/uapi: disable capturing objects on recoverable contexts 1d8aa973c112 drm/i915/error: skip non-mappable pagesf430a36e818d drm/i915/uapi: add NEEDS_CPU_ACCESS hint aea0098389b6 drm/i915/uapi: apply ALLOC_GPU_ONLY by default 0a6d83d93733 drm/i915: remove intel_memory_region avail e8c79f7d40cd drm/i915/uapi: expose the avail tracking e8217645ee2f drm/i915/uapi: add probed_cpu_visible_size 4c06fd9d298d drm/doc: add rfc section for small BAR uapi
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/index.html
Patchwork
CI[Intel-gfx] ✓ Fi.CI.IGT: success for small BAR uapi bits
In reply to Matthew Auld== Series Details ==
== Series Details ==
Series: small BAR uapi bits
URL : https://patchwork.freedesktop.org/series/104369/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11700_full -> Patchwork_104369v1_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (10 -> 13)
------------------------------
Additional (3): shard-rkl shard-dg1 shard-tglu
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_104369v1_full:
### IGT changes ###
#### Possible regressions ####
* {igt@gem_exec_capture@capture-invisible} (NEW):
- shard-tglb: NOTRUN -> [SKIP][1] +3 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb5/igt@[email protected]
- {shard-rkl}: NOTRUN -> [SKIP][2] +2 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-rkl-6/igt@[email protected]
- {shard-dg1}: NOTRUN -> [INCOMPLETE][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-dg1-12/igt@[email protected]
* {igt@gem_exec_capture@capture-recoverable-discrete} (NEW):
- shard-iclb: NOTRUN -> [SKIP][4] +3 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb6/igt@[email protected]
- {shard-tglu}: NOTRUN -> [SKIP][5] +2 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglu-2/igt@[email protected]
* {igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-d-hdmi-a-3} (NEW):
- {shard-dg1}: NOTRUN -> [SKIP][6] +3 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-dg1-18/igt@kms_plane_scaling@[email protected]
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses. They do not affect the overall result.
* igt@gem_exec_capture@pi@rcs0:
- {shard-dg1}: NOTRUN -> [INCOMPLETE][7] +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-dg1-16/igt@gem_exec_capture@[email protected]
* igt@kms_big_fb@y-tiled-16bpp-rotate-270:
- {shard-dg1}: NOTRUN -> [FAIL][8] +17 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-dg1-13/igt@[email protected]
* {igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-c-hdmi-a-1}:
- {shard-dg1}: NOTRUN -> [SKIP][9] +3 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-dg1-12/igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-25@pipe-c-hdmi-a-1.html
* {igt@kms_plane_scaling@plane-downscale-with-pixel-format-factor-0-5@pipe-b-edp-1}:
- {shard-rkl}: NOTRUN -> [SKIP][10] +2 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-rkl-6/igt@kms_plane_scaling@[email protected]
* {igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-a-hdmi-a-1}:
- {shard-tglu}: NOTRUN -> [SKIP][11] +7 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglu-6/igt@kms_plane_scaling@[email protected]
* {igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-5@pipe-b-edp-1}:
- shard-tglb: NOTRUN -> [SKIP][12] +7 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb3/igt@kms_plane_scaling@[email protected]
New tests
---------
New tests have been introduced between CI_DRM_11700_full and Patchwork_104369v1_full:
### New IGT tests (17) ###
* igt@gem_create@create-ext-cpu-access-big:
- Statuses : 7 skip(s)
- Exec time: [0.0, 0.00] s
* igt@gem_create@create-ext-cpu-access-sanity-check:
- Statuses : 1 pass(s) 9 skip(s)
- Exec time: [0.0, 0.01] s
* igt@gem_exec_capture@capture-invisible:
- Statuses : 1 incomplete(s) 9 skip(s)
- Exec time: [0.0, 0.00] s
* igt@gem_exec_capture@capture-recoverable-discrete:
- Statuses : 1 pass(s) 9 skip(s)
- Exec time: [0.0, 0.00] s
* igt@i915_query@query-regions-unallocated:
- Statuses : 10 pass(s)
- Exec time: [0.0, 0.29] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-a-hdmi-a-3:
- Statuses : 1 skip(s)
- Exec time: [0.04] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-b-hdmi-a-3:
- Statuses : 1 skip(s)
- Exec time: [0.03] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-c-hdmi-a-3:
- Statuses : 1 skip(s)
- Exec time: [0.03] s
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-d-hdmi-a-3:
- Statuses : 1 skip(s)
- Exec time: [0.03] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-20x20@pipe-a-hdmi-a-3:
- Statuses : 1 pass(s)
- Exec time: [0.40] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-20x20@pipe-b-hdmi-a-3:
- Statuses : 1 pass(s)
- Exec time: [0.41] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-20x20@pipe-c-hdmi-a-3:
- Statuses : 1 pass(s)
- Exec time: [0.40] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-20x20@pipe-d-hdmi-a-3:
- Statuses : 1 pass(s)
- Exec time: [0.41] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-a-hdmi-a-3:
- Statuses : 1 pass(s)
- Exec time: [0.38] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-3:
- Statuses : 1 pass(s)
- Exec time: [0.41] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-c-hdmi-a-3:
- Statuses : 1 pass(s)
- Exec time: [0.41] s
* igt@kms_plane_scaling@plane-upscale-with-modifiers-factor-0-25@pipe-d-hdmi-a-3:
- Statuses : 1 pass(s)
- Exec time: [0.40] s
Known issues
------------
Here are the changes found in Patchwork_104369v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@chamelium:
- shard-tglb: NOTRUN -> [SKIP][13] ([fdo#111827])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb6/igt@[email protected]
* igt@gem_ccs@block-copy-inplace:
- shard-tglb: NOTRUN -> [SKIP][14] ([i915#3555] / [i915#5325])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb3/igt@[email protected]
* {igt@gem_create@create-ext-cpu-access-big} (NEW):
- shard-snb: NOTRUN -> [SKIP][15] ([fdo#109271]) +76 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-snb2/igt@[email protected]
* igt@gem_create@create-massive:
- shard-iclb: NOTRUN -> [DMESG-WARN][16] ([i915#4991])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb2/igt@[email protected]
- shard-kbl: NOTRUN -> [DMESG-WARN][17] ([i915#4991])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-kbl7/igt@[email protected]
- shard-tglb: NOTRUN -> [DMESG-WARN][18] ([i915#4991])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb3/igt@[email protected]
- shard-skl: NOTRUN -> [DMESG-WARN][19] ([i915#4991])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-skl7/igt@[email protected]
* igt@gem_ctx_param@set-priority-not-supported:
- shard-tglb: NOTRUN -> [SKIP][20] ([fdo#109314])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb6/igt@[email protected]
- shard-iclb: NOTRUN -> [SKIP][21] ([fdo#109314])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb3/igt@[email protected]
* igt@gem_ctx_sseu@engines:
- shard-tglb: NOTRUN -> [SKIP][22] ([i915#280])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb6/igt@[email protected]
* igt@gem_exec_capture@pi@rcs0:
- shard-tglb: [PASS][23] -> [INCOMPLETE][24] ([i915#3371])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-tglb5/igt@gem_exec_capture@[email protected]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb8/igt@gem_exec_capture@[email protected]
* igt@gem_exec_fair@basic-deadline:
- shard-kbl: [PASS][25] -> [FAIL][26] ([i915#2846])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl3/igt@[email protected]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-kbl6/igt@[email protected]
- shard-glk: [PASS][27] -> [FAIL][28] ([i915#2846])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-glk6/igt@[email protected]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-glk4/igt@[email protected]
* igt@gem_exec_fair@basic-none@vecs0:
- shard-glk: [PASS][29] -> [FAIL][30] ([i915#2842])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-glk2/igt@gem_exec_fair@[email protected]
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-glk1/igt@gem_exec_fair@[email protected]
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-kbl: NOTRUN -> [FAIL][31] ([i915#2842])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-kbl7/igt@gem_exec_fair@[email protected]
- shard-tglb: NOTRUN -> [FAIL][32] ([i915#2842])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb3/igt@gem_exec_fair@[email protected]
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-iclb: NOTRUN -> [FAIL][33] ([i915#2842]) +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb4/igt@gem_exec_fair@[email protected]
- shard-kbl: [PASS][34] -> [FAIL][35] ([i915#2842])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl6/igt@gem_exec_fair@[email protected]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-kbl6/igt@gem_exec_fair@[email protected]
* igt@gem_exec_flush@basic-wb-rw-default:
- shard-snb: [PASS][36] -> [SKIP][37] ([fdo#109271]) +2 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-snb5/igt@[email protected]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-snb6/igt@[email protected]
* igt@gem_exec_params@secure-non-root:
- shard-tglb: NOTRUN -> [SKIP][38] ([fdo#112283])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb2/igt@[email protected]
- shard-iclb: NOTRUN -> [SKIP][39] ([fdo#112283])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb2/igt@[email protected]
* igt@gem_lmem_swapping@heavy-multi:
- shard-tglb: NOTRUN -> [SKIP][40] ([i915#4613]) +2 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb8/igt@[email protected]
* igt@gem_lmem_swapping@parallel-random:
- shard-glk: NOTRUN -> [SKIP][41] ([fdo#109271] / [i915#4613])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-glk3/igt@[email protected]
- shard-iclb: NOTRUN -> [SKIP][42] ([i915#4613]) +1 similar issue
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb8/igt@[email protected]
- shard-kbl: NOTRUN -> [SKIP][43] ([fdo#109271] / [i915#4613]) +3 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-kbl4/igt@[email protected]
* igt@gem_lmem_swapping@random:
- shard-apl: NOTRUN -> [SKIP][44] ([fdo#109271] / [i915#4613]) +1 similar issue
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-apl2/igt@[email protected]
* igt@gem_lmem_swapping@verify-random-ccs:
- shard-skl: NOTRUN -> [SKIP][45] ([fdo#109271] / [i915#4613])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-skl10/igt@[email protected]
* igt@gem_mmap_gtt@coherency:
- shard-tglb: NOTRUN -> [SKIP][46] ([fdo#111656])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb2/igt@[email protected]
* igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted:
- shard-iclb: NOTRUN -> [SKIP][47] ([i915#4270]) +3 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb8/igt@[email protected]
* igt@gem_pxp@regular-baseline-src-copy-readible:
- shard-tglb: NOTRUN -> [SKIP][48] ([i915#4270]) +2 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb2/igt@[email protected]
* igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled:
- shard-iclb: NOTRUN -> [SKIP][49] ([i915#768]) +4 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb1/igt@[email protected]
* igt@gem_userptr_blits@unsync-overlap:
- shard-iclb: NOTRUN -> [SKIP][50] ([i915#3297]) +1 similar issue
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb3/igt@[email protected]
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-tglb: NOTRUN -> [SKIP][51] ([i915#3297]) +3 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb1/igt@[email protected]
* igt@gen7_exec_parse@batch-without-end:
- shard-tglb: NOTRUN -> [SKIP][52] ([fdo#109289]) +1 similar issue
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb5/igt@[email protected]
* igt@gen9_exec_parse@shadow-peek:
- shard-tglb: NOTRUN -> [SKIP][53] ([i915#2527] / [i915#2856]) +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb5/igt@[email protected]
- shard-iclb: NOTRUN -> [SKIP][54] ([i915#2856]) +1 similar issue
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb4/igt@[email protected]
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-tglb: NOTRUN -> [WARN][55] ([i915#2681])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb1/igt@[email protected]
- shard-iclb: NOTRUN -> [WARN][56] ([i915#2684])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb6/igt@[email protected]
* igt@i915_pm_rpm@modeset-non-lpsp-stress:
- shard-tglb: NOTRUN -> [SKIP][57] ([fdo#111644] / [i915#1397] / [i915#2411])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb1/igt@[email protected]
- shard-iclb: NOTRUN -> [SKIP][58] ([fdo#110892])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb8/igt@[email protected]
* igt@i915_selftest@live@hangcheck:
- shard-snb: [PASS][59] -> [INCOMPLETE][60] ([i915#3921])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-snb6/igt@i915_selftest@[email protected]
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-snb5/igt@i915_selftest@[email protected]
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
- shard-tglb: NOTRUN -> [SKIP][61] ([i915#1769])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb7/igt@[email protected]
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-iclb: NOTRUN -> [SKIP][62] ([i915#5286]) +3 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb7/igt@[email protected]
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-tglb: NOTRUN -> [SKIP][63] ([i915#5286]) +4 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb5/igt@[email protected]
* igt@kms_big_fb@x-tiled-32bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][64] ([fdo#110725] / [fdo#111614]) +1 similar issue
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb4/igt@[email protected]
* igt@kms_big_fb@x-tiled-8bpp-rotate-90:
- shard-tglb: NOTRUN -> [SKIP][65] ([fdo#111614]) +3 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb1/igt@[email protected]
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-skl: NOTRUN -> [FAIL][66] ([i915#3743]) +1 similar issue
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-skl6/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-90:
- shard-tglb: NOTRUN -> [SKIP][67] ([fdo#111615]) +6 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb3/igt@[email protected]
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-iclb: NOTRUN -> [SKIP][68] ([fdo#110723]) +3 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb4/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_joiner@invalid-modeset:
- shard-iclb: NOTRUN -> [SKIP][69] ([i915#2705])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb1/igt@[email protected]
- shard-tglb: NOTRUN -> [SKIP][70] ([i915#2705])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb3/igt@[email protected]
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#3886]) +10 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-kbl1/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#3886]) +5 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-apl3/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][73] ([i915#3689] / [i915#3886]) +2 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb6/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#3886]) +12 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-skl6/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
- shard-glk: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#3886]) +2 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-glk4/igt@kms_ccs@pipe-b-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-crc-primary-basic-4_tiled_dg2_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][76] ([i915#6095]) +2 similar issues
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb3/igt@kms_ccs@pipe-b-crc-primary-basic-4_tiled_dg2_mc_ccs.html
- shard-iclb: NOTRUN -> [SKIP][77] ([fdo#109278] / [i915#6095]) +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb1/igt@kms_ccs@pipe-b-crc-primary-basic-4_tiled_dg2_mc_ccs.html
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][78] ([fdo#111615] / [i915#3689]) +1 similar issue
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb7/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-yf_tiled_ccs.html
* igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc:
- shard-iclb: NOTRUN -> [SKIP][79] ([fdo#109278] / [i915#3886]) +8 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb6/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-bad-pixel-format-4_tiled_dg2_rc_ccs:
- shard-skl: NOTRUN -> [SKIP][80] ([fdo#109271] / [i915#6095])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-skl4/igt@kms_ccs@pipe-c-bad-pixel-format-4_tiled_dg2_rc_ccs.html
* igt@kms_ccs@pipe-d-crc-sprite-planes-basic-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][81] ([i915#3689]) +10 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb2/igt@kms_ccs@pipe-d-crc-sprite-planes-basic-y_tiled_ccs.html
* igt@kms_cdclk@mode-transition:
- shard-iclb: NOTRUN -> [SKIP][82] ([i915#3742])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb3/igt@[email protected]
- shard-tglb: NOTRUN -> [SKIP][83] ([i915#3742])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb3/igt@[email protected]
* igt@kms_chamelium@common-hpd-after-suspend:
- shard-apl: NOTRUN -> [SKIP][84] ([fdo#109271] / [fdo#111827]) +4 similar issues
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-apl8/igt@[email protected]
* igt@kms_chamelium@hdmi-hpd-enable-disable-mode:
- shard-iclb: NOTRUN -> [SKIP][85] ([fdo#109284] / [fdo#111827]) +7 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb2/igt@[email protected]
* igt@kms_chamelium@hdmi-hpd-fast:
- shard-snb: NOTRUN -> [SKIP][86] ([fdo#109271] / [fdo#111827])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-snb7/igt@[email protected]
- shard-glk: NOTRUN -> [SKIP][87] ([fdo#109271] / [fdo#111827])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-glk4/igt@[email protected]
* igt@kms_chamelium@hdmi-mode-timings:
- shard-kbl: NOTRUN -> [SKIP][88] ([fdo#109271] / [fdo#111827]) +15 similar issues
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-kbl3/igt@[email protected]
* igt@kms_chamelium@vga-frame-dump:
- shard-skl: NOTRUN -> [SKIP][89] ([fdo#109271] / [fdo#111827]) +15 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-skl9/igt@[email protected]
* igt@kms_color@pipe-d-gamma:
- shard-iclb: NOTRUN -> [SKIP][90] ([fdo#109278] / [i915#1149]) +1 similar issue
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb5/igt@[email protected]
* igt@kms_color_chamelium@pipe-b-ctm-0-75:
- shard-tglb: NOTRUN -> [SKIP][91] ([fdo#109284] / [fdo#111827]) +11 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb8/igt@[email protected]
* igt@kms_content_protection@dp-mst-type-0:
- shard-tglb: NOTRUN -> [SKIP][92] ([i915#3116] / [i915#3299])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb6/igt@[email protected]
* igt@kms_cursor_crc@pipe-a-cursor-32x32-sliding:
- shard-tglb: NOTRUN -> [SKIP][93] ([i915#3319]) +1 similar issue
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb7/igt@[email protected]
* igt@kms_cursor_crc@pipe-b-cursor-512x512-sliding:
- shard-iclb: NOTRUN -> [SKIP][94] ([fdo#109278] / [fdo#109279]) +2 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb8/igt@[email protected]
* igt@kms_cursor_crc@pipe-c-cursor-512x170-rapid-movement:
- shard-tglb: NOTRUN -> [SKIP][95] ([i915#3359]) +4 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb1/igt@[email protected]
* igt@kms_cursor_crc@pipe-d-cursor-512x170-offscreen:
- shard-tglb: NOTRUN -> [SKIP][96] ([fdo#109279] / [i915#3359]) +4 similar issues
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb6/igt@[email protected]
* igt@kms_cursor_crc@pipe-d-cursor-64x21-sliding:
- shard-iclb: NOTRUN -> [SKIP][97] ([fdo#109278]) +35 similar issues
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb1/igt@[email protected]
* igt@kms_cursor_crc@pipe-d-cursor-suspend:
- shard-kbl: NOTRUN -> [SKIP][98] ([fdo#109271]) +250 similar issues
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-kbl1/igt@[email protected]
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-iclb: NOTRUN -> [SKIP][99] ([fdo#109274] / [fdo#109278]) +1 similar issue
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb8/igt@[email protected]
* igt@kms_dither@fb-8bpc-vs-panel-8bpc@edp-1-pipe-a:
- shard-tglb: NOTRUN -> [SKIP][100] ([i915#6076])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb1/igt@kms_dither@[email protected]
* igt@kms_dither@fb-8bpc-vs-panel-8bpc@hdmi-a-1-pipe-a:
- shard-glk: [PASS][101] -> [SKIP][102] ([fdo#109271])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-glk9/igt@kms_dither@[email protected]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-glk8/igt@kms_dither@[email protected]
* igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-4tiled:
- shard-tglb: NOTRUN -> [SKIP][103] ([i915#5287]) +5 similar issues
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb6/igt@[email protected]
* igt@kms_draw_crc@draw-method-xrgb8888-pwrite-4tiled:
- shard-iclb: NOTRUN -> [SKIP][104] ([i915#5287]) +4 similar issues
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb4/igt@[email protected]
* igt@kms_flip@2x-flip-vs-rmfb-interruptible:
- shard-iclb: NOTRUN -> [SKIP][105] ([fdo#109274]) +5 similar issues
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb4/igt@[email protected]
* igt@kms_flip@2x-plain-flip-interruptible:
- shard-tglb: NOTRUN -> [SKIP][106] ([fdo#109274] / [fdo#111825]) +9 similar issues
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb5/igt@[email protected]
* igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1:
- shard-glk: [PASS][107] -> [FAIL][108] ([i915#79]) +1 similar issue
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-glk1/igt@kms_flip@[email protected]
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-glk2/igt@kms_flip@[email protected]
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: NOTRUN -> [DMESG-WARN][109] ([i915#180]) +1 similar issue
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-kbl1/igt@kms_flip@[email protected]
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
- shard-skl: NOTRUN -> [SKIP][110] ([fdo#109271] / [i915#3701])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-skl10/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling:
- shard-iclb: NOTRUN -> [SKIP][111] ([i915#3701])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-shrfb-fliptrack-mmap-gtt:
- shard-iclb: NOTRUN -> [SKIP][112] ([fdo#109280]) +28 similar issues
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb1/igt@[email protected]
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
- shard-tglb: NOTRUN -> [SKIP][113] ([i915#5439])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb2/igt@[email protected]
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-tglb: NOTRUN -> [SKIP][114] ([fdo#109280] / [fdo#111825]) +35 similar issues
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb7/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_pipe_crc_basic@disable-crc-after-crtc-pipe-d:
- shard-skl: NOTRUN -> [SKIP][115] ([fdo#109271] / [i915#533])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-skl8/igt@[email protected]
* igt@kms_pipe_crc_basic@read-crc-pipe-d:
- shard-kbl: NOTRUN -> [SKIP][116] ([fdo#109271] / [i915#533])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-kbl6/igt@[email protected]
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-kbl: [PASS][117] -> [DMESG-WARN][118] ([i915#180])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl6/igt@[email protected]
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-kbl1/igt@[email protected]
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-apl: NOTRUN -> [FAIL][119] ([fdo#108145] / [i915#265])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-apl3/igt@[email protected]
- shard-glk: NOTRUN -> [FAIL][120] ([fdo#108145] / [i915#265])
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-glk8/igt@[email protected]
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
- shard-kbl: NOTRUN -> [FAIL][121] ([fdo#108145] / [i915#265]) +1 similar issue
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-kbl4/igt@[email protected]
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-kbl: NOTRUN -> [FAIL][122] ([i915#265])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-kbl7/igt@[email protected]
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-skl: NOTRUN -> [FAIL][123] ([fdo#108145] / [i915#265]) +3 similar issues
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-skl6/igt@[email protected]
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][124] -> [FAIL][125] ([fdo#108145] / [i915#265])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-skl10/igt@[email protected]
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-skl8/igt@[email protected]
* igt@kms_plane_alpha_blend@pipe-d-alpha-opaque-fb:
- shard-glk: NOTRUN -> [SKIP][126] ([fdo#109271]) +43 similar issues
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-glk1/igt@[email protected]
* igt@kms_plane_lowres@pipe-d-tiling-x:
- shard-tglb: NOTRUN -> [SKIP][127] ([i915#3536])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb3/igt@[email protected]
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf:
- shard-skl: NOTRUN -> [SKIP][128] ([fdo#109271] / [i915#658]) +3 similar issues
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-skl8/igt@[email protected]
* igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
- shard-apl: NOTRUN -> [SKIP][129] ([fdo#109271] / [i915#658])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-apl3/igt@[email protected]
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
- shard-kbl: NOTRUN -> [SKIP][130] ([fdo#109271] / [i915#658]) +3 similar issues
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-kbl4/igt@[email protected]
- shard-tglb: NOTRUN -> [SKIP][131] ([i915#2920]) +1 similar issue
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb1/igt@[email protected]
* igt@kms_psr2_su@page_flip-p010:
- shard-tglb: NOTRUN -> [SKIP][132] ([i915#1911])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb8/igt@kms_psr2_su@page_flip-p010.html
- shard-iclb: NOTRUN -> [SKIP][133] ([fdo#109642] / [fdo#111068] / [i915#658])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb4/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr@psr2_cursor_plane_onoff:
- shard-tglb: NOTRUN -> [FAIL][134] ([i915#132] / [i915#3467]) +2 similar issues
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb1/igt@kms_psr@psr2_cursor_plane_onoff.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: NOTRUN -> [SKIP][135] ([fdo#109441]) +1 similar issue
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb5/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_rotation_crc@cursor-rotation-180:
- shard-skl: [PASS][136] -> [SKIP][137] ([fdo#109271]) +5 similar issues
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-skl10/igt@[email protected]
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-skl1/igt@[email protected]
* igt@kms_scaling_modes@scaling-mode-none@edp-1-pipe-a:
- shard-skl: NOTRUN -> [SKIP][138] ([fdo#109271]) +269 similar issues
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-skl10/igt@kms_scaling_modes@[email protected]
* igt@kms_setmode@invalid-clone-single-crtc-stealing:
- shard-iclb: NOTRUN -> [SKIP][139] ([i915#3555])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb5/igt@[email protected]
- shard-tglb: NOTRUN -> [SKIP][140] ([i915#3555])
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb5/igt@[email protected]
* igt@kms_vblank@pipe-d-ts-continuation-idle:
- shard-apl: NOTRUN -> [SKIP][141] ([fdo#109271]) +87 similar issues
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-apl8/igt@[email protected]
* igt@kms_writeback@writeback-invalid-parameters:
- shard-tglb: NOTRUN -> [SKIP][142] ([i915#2437]) +1 similar issue
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb6/igt@[email protected]
- shard-skl: NOTRUN -> [SKIP][143] ([fdo#109271] / [i915#2437]) +1 similar issue
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-skl4/igt@[email protected]
* igt@kms_writeback@writeback-pixel-formats:
- shard-kbl: NOTRUN -> [SKIP][144] ([fdo#109271] / [i915#2437]) +1 similar issue
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-kbl4/igt@[email protected]
* igt@nouveau_crc@pipe-a-source-rg:
- shard-iclb: NOTRUN -> [SKIP][145] ([i915#2530]) +2 similar issues
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb8/igt@[email protected]
- shard-tglb: NOTRUN -> [SKIP][146] ([i915#2530]) +4 similar issues
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb1/igt@[email protected]
* igt@nouveau_crc@pipe-d-source-rg:
- shard-iclb: NOTRUN -> [SKIP][147] ([fdo#109278] / [i915#2530])
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb3/igt@[email protected]
* igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name:
- shard-tglb: NOTRUN -> [SKIP][148] ([fdo#109291]) +6 similar issues
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb3/igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name.html
* igt@prime_nv_test@nv_i915_sharing:
- shard-iclb: NOTRUN -> [SKIP][149] ([fdo#109291]) +4 similar issues
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb1/igt@prime_nv_test@nv_i915_sharing.html
* igt@prime_vgem@fence-flip-hang:
- shard-iclb: NOTRUN -> [SKIP][150] ([fdo#109295])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb7/igt@[email protected]
- shard-tglb: NOTRUN -> [SKIP][151] ([fdo#109295])
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb2/igt@[email protected]
* igt@syncobj_timeline@invalid-transfer-non-existent-point:
- shard-iclb: NOTRUN -> [DMESG-WARN][152] ([i915#5098])
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb6/igt@[email protected]
- shard-kbl: NOTRUN -> [DMESG-WARN][153] ([i915#5098])
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-kbl7/igt@[email protected]
- shard-tglb: NOTRUN -> [DMESG-WARN][154] ([i915#5098])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb2/igt@[email protected]
* igt@sysfs_clients@sema-25:
- shard-iclb: NOTRUN -> [SKIP][155] ([i915#2994])
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb7/igt@[email protected]
- shard-kbl: NOTRUN -> [SKIP][156] ([fdo#109271] / [i915#2994]) +1 similar issue
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-kbl7/igt@[email protected]
- shard-tglb: NOTRUN -> [SKIP][157] ([i915#2994])
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb7/igt@[email protected]
- shard-skl: NOTRUN -> [SKIP][158] ([fdo#109271] / [i915#2994])
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-skl3/igt@[email protected]
- shard-glk: NOTRUN -> [SKIP][159] ([fdo#109271] / [i915#2994])
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-glk7/igt@[email protected]
- shard-apl: NOTRUN -> [SKIP][160] ([fdo#109271] / [i915#2994])
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-apl6/igt@[email protected]
#### Possible fixes ####
* igt@gem_ctx_param@basic:
- shard-skl: [DMESG-WARN][161] ([i915#1982]) -> [PASS][162]
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-skl2/igt@[email protected]
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-skl6/igt@[email protected]
* igt@gem_eio@kms:
- shard-tglb: [FAIL][163] ([i915#5784]) -> [PASS][164]
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-tglb2/igt@[email protected]
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb6/igt@[email protected]
* igt@gem_exec_balancer@parallel-balancer:
- shard-iclb: [SKIP][165] ([i915#4525]) -> [PASS][166]
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-iclb3/igt@[email protected]
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb4/igt@[email protected]
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [FAIL][167] ([i915#2842]) -> [PASS][168] +1 similar issue
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-apl4/igt@gem_exec_fair@[email protected]
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-apl6/igt@gem_exec_fair@[email protected]
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [FAIL][169] ([i915#2842]) -> [PASS][170] +2 similar issues
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl7/igt@gem_exec_fair@[email protected]
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-kbl6/igt@gem_exec_fair@[email protected]
- shard-glk: [FAIL][171] ([i915#2842]) -> [PASS][172]
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-glk2/igt@gem_exec_fair@[email protected]
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-glk1/igt@gem_exec_fair@[email protected]
* igt@gem_exec_flush@basic-uc-rw-default:
- shard-snb: [SKIP][173] ([fdo#109271]) -> [PASS][174]
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-snb6/igt@[email protected]
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-snb7/igt@[email protected]
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [FAIL][175] ([i915#2346] / [i915#533]) -> [PASS][176]
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-glk5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [FAIL][177] ([i915#4767]) -> [PASS][178]
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-apl8/igt@[email protected]
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-apl6/igt@[email protected]
* igt@kms_flip@flip-vs-expired-vblank@b-edp1:
- shard-skl: [FAIL][179] ([i915#79]) -> [PASS][180]
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-skl4/igt@kms_flip@[email protected]
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-skl8/igt@kms_flip@[email protected]
* igt@kms_flip@flip-vs-expired-vblank@c-edp1:
- shard-tglb: [FAIL][181] ([i915#79]) -> [PASS][182]
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-tglb8/igt@kms_flip@[email protected]
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb6/igt@kms_flip@[email protected]
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
- shard-glk: [FAIL][183] ([i915#1888] / [i915#2546]) -> [PASS][184]
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-glk3/igt@[email protected]
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-glk8/igt@[email protected]
* igt@kms_hdmi_inject@inject-audio:
- shard-tglb: [SKIP][185] ([i915#433]) -> [PASS][186]
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-tglb2/igt@[email protected]
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb1/igt@[email protected]
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-kbl: [DMESG-WARN][187] ([i915#180]) -> [PASS][188]
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl1/igt@[email protected]
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-kbl7/igt@[email protected]
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
- shard-apl: [DMESG-WARN][189] ([i915#180]) -> [PASS][190] +3 similar issues
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-apl3/igt@kms_plane@[email protected]
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-apl6/igt@kms_plane@[email protected]
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [FAIL][191] ([fdo#108145] / [i915#265]) -> [PASS][192]
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-skl8/igt@[email protected]
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-skl7/igt@[email protected]
* {igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1}:
- shard-iclb: [SKIP][193] ([i915#5235]) -> [PASS][194] +2 similar issues
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-iclb2/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb8/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5@pipe-a-edp-1.html
* igt@kms_psr@psr2_sprite_render:
- shard-iclb: [SKIP][195] ([fdo#109441]) -> [PASS][196]
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-iclb1/igt@kms_psr@psr2_sprite_render.html
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb2/igt@kms_psr@psr2_sprite_render.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-tglb: [SKIP][197] ([i915#5519]) -> [PASS][198]
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-tglb1/igt@[email protected]
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-tglb2/igt@[email protected]
* igt@perf@polling-small-buf:
- shard-skl: [FAIL][199] ([i915#1722]) -> [PASS][200]
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-skl8/igt@[email protected]
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-skl3/igt@[email protected]
#### Warnings ####
* igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [DMESG-WARN][201] ([i915#5614]) -> [SKIP][202] ([i915#4525]) +2 similar issues
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-iclb4/igt@[email protected]
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb5/igt@[email protected]
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-kbl: [SKIP][203] ([fdo#109271]) -> [FAIL][204] ([i915#2842])
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl6/igt@gem_exec_fair@[email protected]
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-kbl6/igt@gem_exec_fair@[email protected]
* igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
- shard-skl: [SKIP][205] ([fdo#109271] / [i915#3886]) -> [SKIP][206] ([fdo#109271])
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-skl8/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-skl10/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [FAIL][207] ([i915#2346]) -> [SKIP][208] ([fdo#109271])
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-skl9/igt@[email protected]
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-skl10/igt@[email protected]
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [INCOMPLETE][209] ([i915#180]) -> [FAIL][210] ([i915#4767])
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl1/igt@[email protected]
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-kbl6/igt@[email protected]
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-sf:
- shard-iclb: [SKIP][211] ([i915#2920]) -> [SKIP][212] ([i915#658])
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-iclb2/igt@[email protected]
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb3/igt@[email protected]
* igt@kms_psr2_sf@overlay-plane-move-continuous-sf:
- shard-iclb: [SKIP][213] ([i915#658]) -> [SKIP][214] ([i915#2920])
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-iclb5/igt@[email protected]
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb2/igt@[email protected]
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-iclb: [SKIP][215] ([i915#2920]) -> [SKIP][216] ([fdo#111068] / [i915#658]) +1 similar issue
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-iclb2/igt@[email protected]
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb8/igt@[email protected]
* igt@kms_psr2_sf@plane-move-sf-dmg-area:
- shard-iclb: [SKIP][217] ([fdo#111068] / [i915#658]) -> [SKIP][218] ([i915#2920])
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-iclb7/igt@[email protected]
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-iclb2/igt@[email protected]
* igt@kms_sysfs_edid_timing:
- shard-skl: [FAIL][219] ([IGT#2] / [i915#1888]) -> [FAIL][220] ([IGT#2])
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-skl8/igt@kms_sysfs_edid_timing.html
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-skl10/igt@kms_sysfs_edid_timing.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][221], [FAIL][222], [FAIL][223], [FAIL][224], [FAIL][225], [FAIL][226], [FAIL][227], [FAIL][228], [FAIL][229], [FAIL][230], [FAIL][231], [FAIL][232], [FAIL][233]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257] / [i915#92]) -> ([FAIL][234], [FAIL][235], [FAIL][236], [FAIL][237], [FAIL][238], [FAIL][239], [FAIL][240], [FAIL][241], [FAIL][242], [FAIL][243]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257])
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl1/igt@[email protected]
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl1/igt@[email protected]
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl4/igt@[email protected]
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl3/igt@[email protected]
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl3/igt@[email protected]
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl1/igt@[email protected]
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl6/igt@[email protected]
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl4/igt@[email protected]
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl1/igt@[email protected]
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl4/igt@[email protected]
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl7/igt@[email protected]
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl7/igt@[email protected]
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-kbl7/igt@[email protected]
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-kbl3/igt@[email protected]
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-kbl1/igt@[email protected]
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-kbl3/igt@[email protected]
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-kbl7/igt@[email protected]
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-kbl6/igt@[email protected]
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-kbl1/igt@[email protected]
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-kbl7/igt@[email protected]
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-kbl7/igt@[email protected]
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-kbl6/igt@[email protected]
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-kbl4/igt@[email protected]
- shard-apl: ([FAIL][244], [FAIL][245], [FAIL][246], [FAIL][247], [FAIL][248], [FAIL][249], [FAIL][250]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][251], [FAIL][252], [FAIL][253], [FAIL][254], [FAIL][255]) ([i915#3002] / [i915#4312] / [i915#5257])
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-apl2/igt@[email protected]
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-apl7/igt@[email protected]
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-apl3/igt@[email protected]
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-apl1/igt@[email protected]
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-apl6/igt@[email protected]
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-apl8/igt@[email protected]
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11700/shard-apl7/igt@[email protected]
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-apl1/igt@[email protected]
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-apl6/igt@[email protected]
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-apl7/igt@[email protected]
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-apl1/igt@[email protected]
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/shard-apl6/igt@[email protected]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110254]: https://bugs.freedesktop.org/show_bug.cgi?id=110254
[fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
[fdo#110892]: https://bugs.freedesktop.org/show_bug.cgi?id=110892
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112022]: https://bugs.freedesktop.org/show_bug.cgi?id=112022
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1911]: https://gitlab.freedesktop.org/drm/intel/issues/1911
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2410]: https://gitlab.freedesktop.org/drm/intel/issues/2410
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2435]: https://gitlab.freedesktop.org/drm/intel/issues/2435
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3319]: https://gitlab.freedesktop.org/drm/intel/issues/3319
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3371]: https://gitlab.freedesktop.org/drm/intel/issues/3371
[i915#3376]: https://gitlab.freedesktop.org/drm/intel/issues/3376
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3464]: https://gitlab.freedesktop.org/drm/intel/issues/3464
[i915#3467]: https://gitlab.freedesktop.org/drm/intel/issues/3467
[i915#3528]: https://gitlab.freedesktop.org/drm/intel/issues/3528
[i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3639]: https://gitlab.freedesktop.org/drm/intel/issues/3639
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
[i915#3963]: https://gitlab.freedesktop.org/drm/intel/issues/3963
[i915#4016]: https://gitlab.freedesktop.org/drm/intel/issues/4016
[i915#4036]: https://gitlab.freedesktop.org/drm/intel/issues/4036
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4278]: https://gitlab.freedesktop.org/drm/intel/issues/4278
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4807]: https://gitlab.freedesktop.org/drm/intel/issues/4807
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4842]: https://gitlab.freedesktop.org/drm/intel/issues/4842
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4853]: https://gitlab.freedesktop.org/drm/intel/issues/4853
[i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
[i915#4883]: https://gitlab.freedesktop.org/drm/intel/issues/4883
[i915#4884]: https://gitlab.freedesktop.org/drm/intel/issues/4884
[i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
[i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893
[i915#4929]: https://gitlab.freedesktop.org/drm/intel/issues/4929
[i915#4958]: https://gitlab.freedesktop.org/drm/intel/issues/4958
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5076]: https://gitlab.freedesktop.org/drm/intel/issues/5076
[i915#5098]: https://gitlab.freedesktop.org/drm/intel/issues/5098
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5234]: https://gitlab.freedesktop.org/drm/intel/issues/5234
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5303]: https://gitlab.freedesktop.org/drm/intel/issues/5303
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5614]: https://gitlab.freedesktop.org/drm/intel/issues/5614
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#5903]: https://gitlab.freedesktop.org/drm/intel/issues/5903
[i915#6076]: https://gitlab.freedesktop.org/drm/intel/issues/6076
[i915#6079]: https://gitlab.freedesktop.org/drm/intel/issues/6079
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#768]: https://gitlab.freedesktop.org/drm/intel/issues/768
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
Build changes
-------------
* IGT: IGT_6492 -> IGTPW_7174
* Linux: CI_DRM_11700 -> Patchwork_104369v1
CI-20190529: 20190529
CI_DRM_11700: f5895776c32b7fc5c196fafef3f5dab7e5ad19c6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_7174: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_7174/index.html
IGT_6492: ef18e59c374472e961a3a145724e7381eb4800aa @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_104369v1: f5895776c32b7fc5c196fafef3f5dab7e5ad19c6 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_104369v1/index.html