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ddrmc: vybrid: We shall perform bitwise AND, not logical one

PATCH New Lukasz Majewski 3 participants 3 messages Nov 30, 2018 – Dec 3, 2018

Subsystems (4)
Arm (32-bit) Arm sub-architectures Arm i.MX and Layerscape Arm/Freescale vybrid Arm architecture
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Lukasz Majewski

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#0 lore raw

PATCH 1/1 ddrmc: vybrid: We shall perform bitwise AND, not logical one

With logical AND - we exit the memory setup procedure on any interrupt - also on errors.

Signed-off-by Lukasz Majewski <[email protected]>

---

 arch/arm/mach-imx/ddrmc-vf610.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/mach-imx/ddrmc-vf610.c +1 -1
index 3d7da1c25e..ea6a49e0fa 100644
@@ -231,6 +231,6 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
 	/* all inits done, start the DDR controller */
 	writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);
 
-	while (!(readl(&ddrmr->cr[80]) && 0x100))
+	while (!(readl(&ddrmr->cr[80]) & 0x100))
 		udelay(10);
 }
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2.11.0
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#2 lore raw

PATCH 1/1 ddrmc: vybrid: We shall perform bitwise AND, not logical one

Quoted 8 lines · Fabio Estevam
Quoted 5 lines · Lukasz Majewski

With logical AND - we exit the memory setup procedure on any interrupt - also on errors.

Signed-off-by Lukasz Majewski <[email protected]>
Reviewed-by Fabio Estevam <[email protected]>

I have a similar patch downstream which also creates a proper define for the magic 0x100.

Will send soon.

--
Stefan

Quoted 4 lines

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