This is continued work on Samsung S9(SM-9600) starqltechn

sdm845 has "General Purpose" clocks that can be muxed to SoC pins.

Those clocks may be used as e.g. PWM sources for external peripherals. Add more frequencies to the table for those clocks so it's possible for arbitrary peripherals to make use of them.

See also: bf8bb8eaccf(clk: qcom: gcc-msm8916: Add rates to the GP clocks)

Signed-off-by Dzmitry Sankouski <[email protected]>

---
 drivers/clk/qcom/gcc-sdm845.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

drivers/clk/qcom/gcc-sdm845.c +14 -0

index ea4c3bf4fb9b..0efd3364e8f5 100644
@@ -283,7 +283,21 @@ static struct clk_rcg2 gcc_sdm670_cpuss_rbcpr_clk_src = {
 	},
 };
 
+/*
+ * This is a frequency table for "General Purpose" clocks.
+ * These clocks can be muxed to the SoC pins and may be used by
+ * external devices. They're often used as PWM source.
+ *
+ * See comment in gcc-mam8916.c at ftbl_gcc_gp1_3_clk.
+ */
 static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {
+	F(10000,   P_BI_TCXO,    16,  1, 120),
+	F(20000,   P_BI_TCXO,    16,  1, 60),
+	F(100000,  P_BI_TCXO,    16,  1,  12),
+	F(500000,  P_GPLL0_OUT_EVEN, 12, 1, 100),
+	F(1000000, P_GPLL0_OUT_EVEN, 12, 1, 50),
+	F(2500000, P_GPLL0_OUT_EVEN, 12, 1, 10),
+	F(5000000, P_GPLL0_OUT_EVEN, 12, 1, 5),
 	F(19200000, P_BI_TCXO, 1, 0, 0),
 	F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
 	F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),

Signature · 2 lines

-- 
2.39.2

Quoted 7 lines · Dzmitry Sankouski

sdm845 has "General Purpose" clocks that can be muxed to SoC pins.

Those clocks may be used as e.g. PWM sources for external peripherals. Add more frequencies to the table for those clocks so it's possible for arbitrary peripherals to make use of them.

Quoted 1 line

See also: bf8bb8eaccf(clk: qcom: gcc-msm8916: Add rates to the GP clocks)

Each time I look at the table attached to the GP CLK, I feel that it's plain wrong. In the end the GPCLK can in theory have arbitrary value depending on the usecase.

Bjorn, Konrad, maybe we should add special clk_ops for GP CLK which allow more flexibility than a default clk_rcg2_ops?

Quoted 10 lines · Dmitry Baryshkov

Quoted 8 lines · Dzmitry Sankouski

sdm845 has "General Purpose" clocks that can be muxed to SoC pins.

Those clocks may be used as e.g. PWM sources for external peripherals. Add more frequencies to the table for those clocks so it's possible for arbitrary peripherals to make use of them.

See also: bf8bb8eaccf(clk: qcom: gcc-msm8916: Add rates to the GP clocks)

Quoted 6 lines

Each time I look at the table attached to the GP CLK, I feel that it's plain wrong. In the end the GPCLK can in theory have arbitrary value depending on the usecase.

Bjorn, Konrad, maybe we should add special clk_ops for GP CLK which allow more flexibility than a default clk_rcg2_ops?

If we can somehow get max m/n/d values for all possible parents, sure

Quoted 17 lines · Konrad Dybcio

Quoted 14 lines · Dmitry Baryshkov

Quoted 8 lines · Dzmitry Sankouski

sdm845 has "General Purpose" clocks that can be muxed to SoC pins.

Those clocks may be used as e.g. PWM sources for external peripherals. Add more frequencies to the table for those clocks so it's possible for arbitrary peripherals to make use of them.

See also: bf8bb8eaccf(clk: qcom: gcc-msm8916: Add rates to the GP clocks)

Each time I look at the table attached to the GP CLK, I feel that it's plain wrong. In the end the GPCLK can in theory have arbitrary value depending on the usecase.

Quoted 4 lines

Quoted 2 lines

Bjorn, Konrad, maybe we should add special clk_ops for GP CLK which allow more flexibility than a default clk_rcg2_ops?

If we can somehow get max m/n/d values for all possible parents, sure

Calculate them at runtime?

Quoted 21 lines · Dmitry Baryshkov

Quoted 20 lines · Konrad Dybcio

Quoted 16 lines · Dmitry Baryshkov

Quoted 8 lines · Dzmitry Sankouski

sdm845 has "General Purpose" clocks that can be muxed to SoC pins.

Those clocks may be used as e.g. PWM sources for external peripherals. Add more frequencies to the table for those clocks so it's possible for arbitrary peripherals to make use of them.

See also: bf8bb8eaccf(clk: qcom: gcc-msm8916: Add rates to the GP clocks)

Each time I look at the table attached to the GP CLK, I feel that it's plain wrong. In the end the GPCLK can in theory have arbitrary value depending on the usecase.

Bjorn, Konrad, maybe we should add special clk_ops for GP CLK which allow more flexibility than a default clk_rcg2_ops?

Quoted 3 lines

Quoted 1 line

If we can somehow get max m/n/d values for all possible parents, sure

Calculate them at runtime?

We'd be calculating the mnd values for a frequency that's either equal or reasonably close to the one requested. My worry is that we somehow need to get the maximum values they can take (unless they're well-known)

drivers/clk/qcom/clk-rcg2.c +1 -1

index 30b19bd39d08..44b257481556 100644
@@ -32,6 +32,7 @@
 
 #define CFG_REG                        0x4
 #define CFG_SRC_DIV_SHIFT      0
+#define CFG_SRC_DIV_LENGTH     8
 #define CFG_SRC_SEL_SHIFT      8
 #define CFG_SRC_SEL_MASK       (0x7 << CFG_SRC_SEL_SHIFT)
 #define CFG_MODE_SHIFT         12

@@ -393,16 +394,103 @@ static int clk_rcg2_fm_determine_rate(struct clk_hw *hw,
        return _freq_tbl_fm_determine_rate(hw, rcg->freq_multi_tbl, req);
 }
 
-static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f,

drivers/clk/qcom/clk-rcg2.c +34 -0

+}
+
+static int clk_calc_mnd(u64 parent_rate, u64 rate, struct freq_tbl *f)
+{
+       u64 hcf;
+       u64 hid_div = 1, n = 1;
+       int i = 2, count = 0;
+
+       hcf = find_hcf(parent_rate, rate);
+       u64 scaled_rate = rate / hcf;
+       u64 scaled_parent_rate = parent_rate / hcf;
+
+       while (scaled_parent_rate > 1) {
+               while (scaled_parent_rate % i == 0) {
+                       scaled_parent_rate /= i;
+                       if (count % 2 == 0)
+                               hid_div *= i;
+                       else
+                               n *= i;
+               }
+               i++;
+               count++;
+       }
+
+       f->m = scaled_rate;
+       f->n = n;
+       f->pre_div = hid_div;
+
+       return 0;
+}
+
+static int clk_rcg2_determine_gp_rate(struct clk_hw *hw,
+                                  struct clk_rate_request *req)
+{

drivers/clk/qcom/clk-rcg2.c +14 -0

+
+       if (!f)
+               return 0;
+
+       ret = clk_calc_mnd(parent_rate, req->rate, f);
+       if (ret)
+               return 0;
+
+
+       while (f->n - f->m >= mnd_max) {
+               f->m = f->m >> 1;
+               f->n = f->n >> 1;
+       }
+       while (f->pre_div >= hid_max) {

drivers/clk/qcom/clk-rcg2.c +51 -4

 {
-       u32 cfg, mask, d_val, not2d_val, n_minus_m;
        struct clk_hw *hw = &rcg->clkr.hw;
-       int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src);
+       u32 mask = CFG_SRC_SEL_MASK;
+       int index = qcom_find_src_index(hw, rcg->parent_map, src);
 
        if (index < 0)
                return index;
 
+       *_cfg &= ~mask;
+       *_cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
+
+       return 0;
+}
+
+static int __clk_rcg2_configure_mnd(struct clk_rcg2 *rcg, const struct freq_tbl *f,
+                               u32 *_cfg)
+{
+       u32 cfg, mask, d_val, not2d_val, n_minus_m;
+       int ret;
+
        if (rcg->mnd_width && f->n) {
                mask = BIT(rcg->mnd_width) - 1;
                ret = regmap_update_bits(rcg->clkr.regmap,

@@ -431,9 +519,8 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f,
        }
 
        mask = BIT(rcg->hid_width) - 1;
-       mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK;
+       mask |= CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK;
        cfg = f->pre_div << CFG_SRC_DIV_SHIFT;
-       cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
        if (rcg->mnd_width && f->n && (f->m != f->n))
                cfg |= CFG_MODE_DUAL_EDGE;
        if (rcg->hw_clk_ctrl)

@@ -445,6 +532,22 @@ static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f,
        return 0;
 }
 
+static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f,
+                               u32 *_cfg)
+{
+       int ret;
+
+       ret = __clk_rcg2_configure_parent(rcg, f->src, _cfg);
+       if (ret)
+               return ret;
+
+       ret = __clk_rcg2_configure_mnd(rcg, f, _cfg);
+       if (ret)
+               return ret;
+
+       return 0;
+}
+
 static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
 {
        u32 cfg;

@@ -465,6 +568,26 @@ static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
        return update_config(rcg);
 }
 
+static int clk_rcg2_configure_gp(struct clk_rcg2 *rcg, const struct freq_tbl *f)
+{
+       u32 cfg;
+       int ret;
+
+       ret = regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg);
+       if (ret)
+               return ret;
+
+       ret = __clk_rcg2_configure_mnd(rcg, f, &cfg);
+       if (ret)
+               return ret;
+
+       ret = regmap_write(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), cfg);
+       if (ret)
+               return ret;
+
+       return update_config(rcg);
+}
+
 static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
                               enum freq_policy policy)
 {

drivers/clk/qcom/clk-rcg2.c +20 -0

+
+       if (!f)
+               return -ENOMEM;
+
+       clk_calc_mnd(parent_rate, rate, f);
+
+       return clk_rcg2_configure_gp(rcg, f);
+}
+
 static int clk_rcg2_set_floor_rate(struct clk_hw *hw, unsigned long rate,
                                   unsigned long parent_rate)
 {

@@ -645,6 +784,17 @@ const struct clk_ops clk_rcg2_ops = {
 };
 EXPORT_SYMBOL_GPL(clk_rcg2_ops);
 
+const struct clk_ops clk_rcg2_gp_ops = {
+       .is_enabled = clk_rcg2_is_enabled,
+       .get_parent = clk_rcg2_get_parent,
+       .set_parent = clk_rcg2_set_parent,
+       .determine_rate = clk_rcg2_determine_gp_rate,
+       .set_rate = clk_rcg2_set_gp_rate,
+       .get_duty_cycle = clk_rcg2_get_duty_cycle,
+       .set_duty_cycle = clk_rcg2_set_duty_cycle,
+};
+EXPORT_SYMBOL_GPL(clk_rcg2_gp_ops);
+
 const struct clk_ops clk_rcg2_floor_ops = {
        .is_enabled = clk_rcg2_is_enabled,
        .get_parent = clk_rcg2_get_parent,

drivers/pwm/pwm-clk.c +1 -0

index c19a482d7e28..1bfc7870e3aa 100644
@@ -25,6 +25,7 @@
 #include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/clk.h>
+#include <linux/clk/clk-conf.h>
 #include <linux/pwm.h>
 
 struct pwm_clk_chip {

drivers/pwm/pwm-clk.c +0 -0

        chip = devm_pwmchip_alloc(&pdev->dev, 1, sizeof(*pcchip));
        if (IS_ERR(chip))
                return PTR_ERR(chip);

Signature · 1 line

2.39.2

Quoted 18 lines · Konrad Dybcio

Quoted 17 lines · Dmitry Baryshkov

Quoted 14 lines · Dzmitry Sankouski

Quoted 8 lines

sdm845 has "General Purpose" clocks that can be muxed to SoC pins.

Those clocks may be used as e.g. PWM sources for external peripherals. Add more frequencies to the table for those clocks so it's possible for arbitrary peripherals to make use of them.

See also: bf8bb8eaccf(clk: qcom: gcc-msm8916: Add rates to the GP clocks)

Each time I look at the table attached to the GP CLK, I feel that it's plain wrong. In the end the GPCLK can in theory have arbitrary value depending on the usecase.

Quoted 6 lines

Quoted 4 lines

Quoted 2 lines

Bjorn, Konrad, maybe we should add special clk_ops for GP CLK which allow more flexibility than a default clk_rcg2_ops?

If we can somehow get max m/n/d values for all possible parents, sure

Calculate them at runtime?

We'd be calculating the mnd values for a frequency that's either equal or reasonably close to the one requested. My worry is that we somehow need to get the maximum values they can take (unless they're well-known)

Konrad

Add binding for the Samsung s6e3ha8 panel found in the Samsung S9.

Signed-off-by Dzmitry Sankouski <[email protected]>

---
 .../bindings/display/panel/samsung,s6e3ha8.yaml    | 76 ++++++++++++++++++++++
 MAINTAINERS                                        |  5 ++
 2 files changed, 81 insertions(+)

Documentation/devicetree/bindings/display/panel/samsung,s6e3ha8.yaml new file +16 -0

new file mode 100644
index 000000000000..9d7d747264dd
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/samsung,s6e3ha8.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung s6e3ha8 AMOLED DSI panel
+
+description: The s6e3ha8 is a 1440x2960 DPI display panel from Samsung Mobile
+  Displays (SMD).
+
+maintainers:
+  - Dzmitry Sankouski <[email protected]>
+
+allOf:
+  - $ref: panel-common.yaml#

Documentation/devicetree/bindings/display/panel/samsung,s6e3ha8.yaml new file +22 -0

+
+  port: true
+
+  vdd3-supply:
+    description: VDD regulator
+
+  vci-supply:
+    description: VCI regulator
+
+  vddr-supply:
+    description: VDDR regulator
+
+required:
+  - compatible
+  - reset-gpios
+  - vdd3-supply
+  - vddr-supply
+  - vci-supply
+
+unevaluatedProperties: false
+
+examples:

maxim,max77705 is MAX77705 pmic binding part

Signed-off-by Dzmitry Sankouski <[email protected]>

---
 .../devicetree/bindings/mfd/maxim,max77705.yaml    | 112 +++++++++++++++++++++
 MAINTAINERS                                        |   1 +
 2 files changed, 113 insertions(+)

maxim,max77705 is MAX77705 pmic binding part

Signed-off-by Dzmitry Sankouski <[email protected]>

---
 .../devicetree/bindings/mfd/maxim,max77705.yaml    | 112 +++++++++++++++++++++

 MAINTAINERS                                        |   1 +
 2 files changed, 113 insertions(+)

Documentation/devicetree/bindings/mfd/maxim,max77705.yaml new file +14 -0

new file mode 100644
index 000000000000..b54408e3d792
@@ -0,0 +1,112 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/maxim,max77705.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Maxim MAX77705 Companion Power Management IC and USB Type-C interface IC
+
+maintainers:
+  - Dzmitry Sankouski <[email protected]>
+
+description: |
+  This is a part of device tree bindings for Maxim MAX77705 multi functional device.
+

Documentation/devicetree/bindings/mfd/maxim,max77705.yaml new file +15 -0

+
+  charger:
+    $ref: /schemas/power/supply/maxim,max77705-charger.yaml
+
+  fuelgauge:
+    $ref: /schemas/power/supply/maxim,max77705-fg.yaml
+
+  haptic:
+    $ref: /schemas/input/maxim,max77705.yaml
+
+  leds:
+    $ref: /schemas/leds/maxim,max77705.yaml
+
+
+required:

Quoted 5 lines

maxim,max77705 is MAX77705 pmic binding part

Signed-off-by Dzmitry Sankouski <[email protected]>

---
 .../devicetree/bindings/mfd/maxim,max77705.yaml    | 112 +++++++++++++++++++++

Your patch order is totally messed. Not tested by automation. Only limited review follows.

чт, 20 июн. 2024 г. в 18:46, Krzysztof Kozlowski <[email protected]>:

Quoted 8 lines · Dzmitry Sankouski

Quoted 5 lines

maxim,max77705 is MAX77705 pmic binding part

Signed-off-by Dzmitry Sankouski <[email protected]>

---
 .../devicetree/bindings/mfd/maxim,max77705.yaml    | 112 +++++++++++++++++++++

Quoted 3 lines

Your patch order is totally messed. Not tested by automation. Only limited review follows.

Hmm, not sure what was wrong. I sent version 4 to myself with b4 send --reflect, the order looks good.

add maxim,max77705 charger binding part

Signed-off-by Dzmitry Sankouski <[email protected]>

---
 .../power/supply/maxim,max77705-charger.yaml       | 30 ++++++++++++++++++++++
 1 file changed, 30 insertions(+)

Documentation/devicetree/bindings/power/supply/maxim,max77705-charger.yaml new file +13 -0

new file mode 100644
index 000000000000..2b805da2a328
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/supply/maxim,max77705-charger.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Maxim MAX77705 and Companion Power Management IC charger
+
+maintainers:
+  - Dzmitry Sankouski <[email protected]>
+
+description: |
+  This is a part of device tree bindings for Maxim MAX77705 multi functional device.

add maxim,max77705 fuel gauge binding part

Signed-off-by Dzmitry Sankouski <[email protected]>

---
 .../bindings/power/supply/maxim,max77705-fg.yaml   | 35 ++++++++++++++++++++++
 1 file changed, 35 insertions(+)

add maxim,max77705 fuel gauge binding part

Signed-off-by Dzmitry Sankouski <[email protected]>

---
 .../bindings/power/supply/maxim,max77705-fg.yaml   | 35 ++++++++++++++++++++++
 1 file changed, 35 insertions(+)

Documentation/devicetree/bindings/power/supply/maxim,max77705-fg.yaml new file +18 -0

new file mode 100644
index 000000000000..b24db0aba0d7
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/supply/maxim,max77705-fg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Maxim MAX77705 Companion Power Management IC fuelgauge
+
+maintainers:
+  - Dzmitry Sankouski <[email protected]>
+
+description: |
+  This is a part of device tree bindings for Maxim MAX77705 multi functional device.
+
+  MAX77705 fuelgauge with ModelGauge m5 EZ algorithm support.
+
+  See also Documentation/devicetree/bindings/mfd/maxim,max77705.yaml for
+  additional information and example.

add samsung,s2dos05 core MFD module binding

Signed-off-by Dzmitry Sankouski <[email protected]>

---
 .../devicetree/bindings/mfd/samsung,s2dos05.yaml   | 89 ++++++++++++++++++++++
 MAINTAINERS                                        |  1 +
 2 files changed, 90 insertions(+)

add samsung,s2dos05 core MFD module binding

Signed-off-by Dzmitry Sankouski <[email protected]>

---
 .../devicetree/bindings/mfd/samsung,s2dos05.yaml   | 89 ++++++++++++++++++++++
 MAINTAINERS                                        |  1 +
 2 files changed, 90 insertions(+)

Documentation/devicetree/bindings/mfd/samsung,s2dos05.yaml new file +4 -0

new file mode 100644
index 000000000000..f2ef5171cc40
@@ -0,0 +1,89 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/samsung,s2dos05.yaml#

Documentation/devicetree/bindings/mfd/samsung,s2dos05.yaml new file +16 -0

+
+  reg:
+    maxItems: 1
+
+  regulators:
+    $ref: /schemas/regulator/samsung,s2dos05.yaml
+    description: List of regulators and its properties
+
+required:
+  - compatible
+  - reg
+  - regulators
+
+additionalProperties: false
+
+examples:

add samsung,s2dos05 regulator binding part

Signed-off-by Dzmitry Sankouski <[email protected]>

---
 .../bindings/regulator/samsung,s2dos05.yaml        | 36 ++++++++++++++++++++++
 MAINTAINERS                                        |  1 +
 2 files changed, 37 insertions(+)

Documentation/devicetree/bindings/regulator/samsung,s2dos05.yaml new file +4 -0

new file mode 100644
index 000000000000..4b8e4389329c
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/regulator/samsung,s2dos05.yaml#

Add support for MIPI-DSI based S6E3HA8 AMOLED panel driver. This panel has 1440x2960 resolution, 5.8-inch physical size, and can be found in starqltechn device. Brightness regulation is not yet supported.

Signed-off-by Dzmitry Sankouski <[email protected]>

---
 MAINTAINERS                                   |   1 +
 drivers/gpu/drm/panel/Kconfig                 |   7 +
 drivers/gpu/drm/panel/Makefile                |   1 +
 drivers/gpu/drm/panel/panel-samsung-s6e3ha8.c | 426 ++++++++++++++++++++++++++
 4 files changed, 435 insertions(+)

MAINTAINERS +1 -0

index 92a5d0a56353..fae3b8ea9ce4 100644
@@ -7154,6 +7154,7 @@ DRM DRIVER FOR SAMSUNG S6E3HA8 PANELS
 M:	Dzmitry Sankouski <[email protected]>
 S:	Maintained
 F:	Documentation/devicetree/bindings/display/panel/samsung,s6e3ha8.yaml
+F:	drivers/gpu/drm/panel/panel-samsung-s6e3ha8.c
 
 DRM DRIVER FOR SITRONIX ST7586 PANELS
 M:	David Lechner <[email protected]>

drivers/gpu/drm/panel/Kconfig +7 -0

index 2ae0eb0638f3..903fc8c155c0 100644
@@ -651,6 +651,13 @@ config DRM_PANEL_SAMSUNG_S6E3HA2
 	depends on BACKLIGHT_CLASS_DEVICE
 	select VIDEOMODE_HELPERS
 
+config DRM_PANEL_SAMSUNG_S6E3HA8
+	tristate "Samsung S6E3HA8 DSI video mode panel"
+	depends on OF
+	depends on DRM_MIPI_DSI
+	depends on BACKLIGHT_CLASS_DEVICE
+	select VIDEOMODE_HELPERS
+
 config DRM_PANEL_SAMSUNG_S6E63J0X03
 	tristate "Samsung S6E63J0X03 DSI command mode panel"
 	depends on OF

drivers/gpu/drm/panel/Makefile +1 -0

index f0203f6e02f4..71774cc5820a 100644
@@ -66,6 +66,7 @@ obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6D27A1) += panel-samsung-s6d27a1.o
 obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0) += panel-samsung-s6d7aa0.o
 obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E3FA7) += panel-samsung-s6e3fa7.o
 obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2) += panel-samsung-s6e3ha2.o
+obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E3HA8) += panel-samsung-s6e3ha8.o
 obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03) += panel-samsung-s6e63j0x03.o
 obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E63M0) += panel-samsung-s6e63m0.o
 obj-$(CONFIG_DRM_PANEL_SAMSUNG_S6E63M0_SPI) += panel-samsung-s6e63m0-spi.o

drivers/gpu/drm/panel/panel-samsung-s6e3ha8.c new file +28 -0

new file mode 100644
index 000000000000..49d629643171
@@ -0,0 +1,426 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Generated with linux-mdss-dsi-panel-driver-generator from vendor device tree:
+ *  Copyright (c) 2013, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024 Dzmitry Sankouski <[email protected]>
+ */
+
+#include <linux/delay.h>
+#include <linux/gpio/consumer.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/regulator/consumer.h>
+
+#include <drm/display/drm_dsc.h>
+#include <drm/display/drm_dsc_helper.h>
+#include <drm/drm_mipi_dsi.h>
+#include <drm/drm_modes.h>
+#include <drm/drm_panel.h>
+
+struct s6e3ha8 {
+	struct drm_panel panel;
+	struct mipi_dsi_device *dsi;
+	struct drm_dsc_config dsc;
+	struct gpio_desc *reset_gpio;
+	struct regulator_bulk_data supplies[3];
+};
+
+static inline

drivers/gpu/drm/panel/panel-samsung-s6e3ha8.c new file +2 -0

+}
+

drivers/gpu/drm/panel/panel-samsung-s6e3ha8.c new file +27 -0

+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+static int s6e3ha8_power_off(struct s6e3ha8 *ctx)
+{
+	return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies);
+}
+
+static void s6e3ha8_amb577px01_wqhd_reset(struct s6e3ha8 *ctx)
+{
+	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+	usleep_range(5000, 6000);
+	gpiod_set_value_cansleep(ctx->reset_gpio, 0);
+	usleep_range(5000, 6000);
+	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+	usleep_range(5000, 6000);
+}
+
+static int s6e3ha8_amb577px01_wqhd_on(struct s6e3ha8 *ctx)
+{
+	struct mipi_dsi_device *dsi = ctx->dsi;
+	struct device *dev = &dsi->dev;
+	int ret;
+

drivers/gpu/drm/panel/panel-samsung-s6e3ha8.c new file +129 -0

+
+	s6e3ha8_test_key_off_lvl2(dsi);
+
+	ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
+	if (ret < 0) {
+		dev_err(dev, "Failed to exit sleep mode: %d\n", ret);
+		return ret;
+	}
+	usleep_range(5000, 6000);
+
+	s6e3ha8_test_key_on_lvl2(dsi);
+	mipi_dsi_generic_write_seq(dsi, 0xf2, 0x13);
+	s6e3ha8_test_key_off_lvl2(dsi);
+
+	usleep_range(10000, 11000);
+
+	s6e3ha8_test_key_on_lvl2(dsi);
+	mipi_dsi_generic_write_seq(dsi, 0xf2, 0x13);
+	s6e3ha8_test_key_off_lvl2(dsi);
+
+	/* OMOK setting 1 (Initial setting) - Scaler Latch Setting Guide */
+	s6e3ha8_test_key_on_lvl2(dsi);
+	mipi_dsi_generic_write_seq(dsi, 0xb0, 0x07);
+	/* latch setting 1 : Scaler on/off & address setting & PPS setting -> Image update latch */
+	mipi_dsi_generic_write_seq(dsi, 0xf2, 0x3c, 0x10);
+	mipi_dsi_generic_write_seq(dsi, 0xb0, 0x0b);
+	/* latch setting 2 : Ratio change mode -> Image update latch */
+	mipi_dsi_generic_write_seq(dsi, 0xf2, 0x30);
+	/* OMOK setting 2 - Seamless setting guide : WQHD */
+	mipi_dsi_generic_write_seq(dsi, 0x2a, 0x00, 0x00, 0x05, 0x9f); /* CASET */
+	mipi_dsi_generic_write_seq(dsi, 0x2b, 0x00, 0x00, 0x0b, 0x8f); /* PASET */
+	mipi_dsi_generic_write_seq(dsi, 0xba, 0x01); /* scaler setup : scaler off */
+	s6e3ha8_test_key_off_lvl2(dsi);
+	mipi_dsi_generic_write_seq(dsi, 0x35, 0x00); /* TE Vsync ON */
+	s6e3ha8_test_key_on_lvl2(dsi);
+	mipi_dsi_generic_write_seq(dsi, 0xed, 0x4c); /* ERR_FG */
+	s6e3ha8_test_key_off_lvl2(dsi);
+	s6e3ha8_test_key_on_lvl3(dsi);
+	/* FFC Setting 897.6Mbps */
+	mipi_dsi_generic_write_seq(dsi, 0xc5, 0x0d, 0x10, 0xb4, 0x3e, 0x01);
+	s6e3ha8_test_key_off_lvl3(dsi);
+	s6e3ha8_test_key_on_lvl2(dsi);
+	mipi_dsi_generic_write_seq(dsi, 0xb9,
+				   0x00, 0xb0, 0x81, 0x09, 0x00, 0x00, 0x00,
+				   0x11, 0x03); /* TSP HSYNC Setting */
+	s6e3ha8_test_key_off_lvl2(dsi);
+	s6e3ha8_test_key_on_lvl2(dsi);
+	mipi_dsi_generic_write_seq(dsi, 0xb0, 0x03);
+	mipi_dsi_generic_write_seq(dsi, 0xf6, 0x43);
+	s6e3ha8_test_key_off_lvl2(dsi);
+	s6e3ha8_test_key_on_lvl2(dsi);
+	/* Brightness condition set */
+	mipi_dsi_generic_write_seq(dsi, 0xca,
+				   0x07, 0x00, 0x00, 0x00, 0x80, 0x80, 0x80,
+				   0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+				   0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+				   0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
+				   0x80, 0x80, 0x80, 0x00, 0x00, 0x00);
+	mipi_dsi_generic_write_seq(dsi, 0xb1, 0x00, 0x0c); /* AID Set : 0% */
+	mipi_dsi_generic_write_seq(dsi, 0xb5,
+				   0x19, 0xdc, 0x16, 0x01, 0x34, 0x67, 0x9a,
+				   0xcd, 0x01, 0x22, 0x33, 0x44, 0x00, 0x00,
+				   0x05, 0x55, 0xcc, 0x0c, 0x01, 0x11, 0x11,
+				   0x10); /* MPS/ELVSS Setting */
+	mipi_dsi_generic_write_seq(dsi, 0xf4, 0xeb, 0x28); /* VINT */
+	mipi_dsi_generic_write_seq(dsi, 0xf7, 0x03); /* Gamma, LTPS(AID) update */
+	s6e3ha8_test_key_off_lvl2(dsi);
+	s6e3ha8_test_key_off_lvl1(dsi);
+
+	return 0;
+}
+
+static int s6e3ha8_enable(struct drm_panel *panel)
+{
+	struct s6e3ha8 *ctx = to_s6e3ha8_amb577px01_wqhd(panel);
+	struct mipi_dsi_device *dsi = ctx->dsi;
+	int ret;
+
+	s6e3ha8_call_write_func(ret, s6e3ha8_test_key_on_lvl1(dsi));
+	s6e3ha8_call_write_func(ret, mipi_dsi_dcs_set_display_on(dsi));
+	s6e3ha8_call_write_func(ret, s6e3ha8_test_key_off_lvl1(dsi));
+
+	return 0;
+}
+
+static int s6e3ha8_disable(struct drm_panel *panel)
+{
+	struct s6e3ha8 *ctx = to_s6e3ha8_amb577px01_wqhd(panel);
+	struct mipi_dsi_device *dsi = ctx->dsi;
+	int ret;
+
+	s6e3ha8_call_write_func(ret, s6e3ha8_test_key_on_lvl1(dsi));
+	s6e3ha8_call_write_func(ret, mipi_dsi_dcs_set_display_off(dsi));
+	s6e3ha8_call_write_func(ret, s6e3ha8_test_key_off_lvl1(dsi));
+	msleep(20);
+
+	s6e3ha8_call_write_func(ret, s6e3ha8_test_key_on_lvl2(dsi));
+	s6e3ha8_call_write_func(ret, s6e3ha8_afc_off(dsi));
+	s6e3ha8_call_write_func(ret, s6e3ha8_test_key_off_lvl2(dsi));
+
+	msleep(160);
+
+	return 0;
+}
+
+static int s6e3ha8_amb577px01_wqhd_prepare(struct drm_panel *panel)
+{
+	struct s6e3ha8 *ctx = to_s6e3ha8_amb577px01_wqhd(panel);
+	struct mipi_dsi_device *dsi = ctx->dsi;
+	struct device *dev = &dsi->dev;
+	struct drm_dsc_picture_parameter_set pps;
+	int ret;
+
+	s6e3ha8_power_on(ctx);
+	msleep(120);
+	s6e3ha8_amb577px01_wqhd_reset(ctx);
+	ret = s6e3ha8_amb577px01_wqhd_on(ctx);
+
+	if (ret < 0) {
+		dev_err(dev, "Failed to initialize panel: %d\n", ret);
+		gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+		goto err;
+	}
+
+	drm_dsc_pps_payload_pack(&pps, &ctx->dsc);
+
+	s6e3ha8_test_key_on_lvl1(dsi);
+	ret = mipi_dsi_picture_parameter_set(ctx->dsi, &pps);
+	if (ret < 0) {

drivers/gpu/drm/panel/panel-samsung-s6e3ha8.c new file +36 -0

+
+
+	msleep(28);
+
+	return 0;
+err:
+	s6e3ha8_power_off(ctx);
+	return ret;
+}
+
+static int s6e3ha8_amb577px01_wqhd_unprepare(struct drm_panel *panel)
+{
+	struct s6e3ha8 *ctx = to_s6e3ha8_amb577px01_wqhd(panel);
+
+	return s6e3ha8_power_off(ctx);
+}
+
+static const struct drm_display_mode s6e3ha8_amb577px01_wqhd_mode = {
+	.clock = (1440 + 116 + 44 + 120) * (2960 + 120 + 80 + 124) * 60 / 1000,
+	.hdisplay = 1440,
+	.hsync_start = 1440 + 116,
+	.hsync_end = 1440 + 116 + 44,
+	.htotal = 1440 + 116 + 44 + 120,
+	.vdisplay = 2960,
+	.vsync_start = 2960 + 120,
+	.vsync_end = 2960 + 120 + 80,
+	.vtotal = 2960 + 120 + 80 + 124,
+	.width_mm = 64,
+	.height_mm = 132,
+};
+
+static int s6e3ha8_amb577px01_wqhd_get_modes(struct drm_panel *panel,
+					     struct drm_connector *connector)
+{
+	struct drm_display_mode *mode;
+

drivers/gpu/drm/panel/panel-samsung-s6e3ha8.c new file +4 -0

+
+	return 1;
+}
+

drivers/gpu/drm/panel/panel-samsung-s6e3ha8.c line 133

Quoted 6 lines

drivers/gpu/drm/panel/panel-samsung-s6e3ha8.c new file +5 -0

+     ret = mipi_dsi_compression_mode(dsi, true);
+     if (ret < 0) {
+             dev_err(dev, "Failed to set compression mode: %d\n", ret);
+             return ret;
+     }

Interesting, compression mode is being set before the PPS programming?

вт, 18 июн. 2024 г. в 21:39, Dmitry Baryshkov <[email protected]>:

Quoted 7 lines

Quoted 6 lines

drivers/gpu/drm/panel/panel-samsung-s6e3ha8.c new file +5 -0

+     ret = mipi_dsi_compression_mode(dsi, true);
+     if (ret < 0) {
+             dev_err(dev, "Failed to set compression mode: %d\n", ret);
+             return ret;
+     }

Quoted 2 lines

Interesting, compression mode is being set before the PPS programming?

Yes, as per vendor kernel:
https://github.com/klabit87/twrp_android_samsung_kernel_sdm845/blob/e8bb63039008e1704a2f1bde68d39ded9c16ea88/drivers/gpu/drm/msm/samsung/S6E3HA8_AMB577PX01/dsi_panel_S6E3HA8_AMB577PX01_wqhd_octa_cmd.dtsi#L5508

Add the core MFD driver for max77705 PMIC. We define five sub-devices for which the drivers will be added in subsequent patches.

Signed-off-by Dzmitry Sankouski <[email protected]>

Co-authored-by Rose Hudson <[email protected]>

---
 MAINTAINERS                          |   2 +
 drivers/mfd/Kconfig                  |  12 ++
 drivers/mfd/Makefile                 |   3 +
 drivers/mfd/max77705-core.c          | 278 ++++++++++++++++++++++++++++++++
 drivers/mfd/max77705-irq.c           | 299 +++++++++++++++++++++++++++++++++++
 include/linux/mfd/max77705-private.h | 281 ++++++++++++++++++++++++++++++++
 include/linux/mfd/max77705.h         |  20 +++
 7 files changed, 895 insertions(+)

MAINTAINERS +2 -0

index fae3b8ea9ce4..f66f08825db9 100644
@@ -13690,6 +13690,7 @@ F:	drivers/*/*max77843.c
 F:	drivers/*/max14577*.c
 F:	drivers/*/max77686*.c
 F:	drivers/*/max77693*.c
+F:	drivers/*/max77705*.c
 F:	drivers/clk/clk-max77686.c
 F:	drivers/extcon/extcon-max14577.c
 F:	drivers/extcon/extcon-max77693.c

@@ -13697,6 +13698,7 @@ F:	drivers/rtc/rtc-max77686.c
 F:	include/linux/mfd/max14577*.h
 F:	include/linux/mfd/max77686*.h
 F:	include/linux/mfd/max77693*.h
+F:	include/linux/mfd/max77705*.h
 
 MAXIRADIO FM RADIO RECEIVER DRIVER
 M:	Hans Verkuil <[email protected]>

drivers/mfd/Kconfig +12 -0

index 266b4f54af60..c4eb8ff2dcad 100644
@@ -880,6 +880,18 @@ config MFD_MAX77693
 	  additional drivers must be enabled in order to use the functionality
 	  of the device.
 
+config MFD_MAX77705
+	tristate "Maxim Semiconductor MAX77705 PMIC Support"
+	depends on I2C
+	select MFD_CORE
+	help
+	  Say yes here to add support for Maxim Semiconductor MAX77705.
+	  This is a Power Management IC with Charger, safe LDOs, Flash, Haptic
+	  and MUIC controls on chip.
+	  This driver provides common support for accessing the device;
+	  additional drivers must be enabled in order to use the functionality
+	  of the device.
+
 config MFD_MAX77714
 	tristate "Maxim Semiconductor MAX77714 PMIC Support"
 	depends on I2C

drivers/mfd/Makefile +2 -0

index db1ba39de3b5..bf65cc36d59c 100644
@@ -162,6 +162,8 @@ obj-$(CONFIG_MFD_MAX77620)	+= max77620.o
 obj-$(CONFIG_MFD_MAX77650)	+= max77650.o
 obj-$(CONFIG_MFD_MAX77686)	+= max77686.o
 obj-$(CONFIG_MFD_MAX77693)	+= max77693.o
+max77705-objs := max77705-core.o max77705-irq.o
+obj-$(CONFIG_MFD_MAX77705)	+= max77705.o
 obj-$(CONFIG_MFD_MAX77714)	+= max77714.o
 obj-$(CONFIG_MFD_MAX77843)	+= max77843.o
 obj-$(CONFIG_MFD_MAX8907)	+= max8907.o

drivers/mfd/Makefile +0 -0

 obj-$(CONFIG_MFD_SYSCON)	+= syscon.o
 obj-$(CONFIG_MFD_LM3533)	+= lm3533-core.o lm3533-ctrlbank.o
 obj-$(CONFIG_MFD_VEXPRESS_SYSREG)	+= vexpress-sysreg.o

drivers/mfd/max77705-core.c new file +58 -0

new file mode 100644
index 000000000000..7cb71a0a9688
@@ -0,0 +1,278 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * max77705.c - mfd core driver for the Maxim 77705
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Copyright (C) 2024 Dzmitry Sankouski <[email protected]>
+ */
+
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/i2c.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/mutex.h>
+#include <linux/mfd/core.h>
+#include <linux/mfd/max77705.h>
+#include <linux/mfd/max77705-private.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/debugfs.h>
+#include <linux/of_device.h>
+#include <linux/of_gpio.h>
+
+#define I2C_ADDR_PMIC	(0xCC >> 1)	/* Top sys, Haptic */
+#define I2C_ADDR_MUIC	(0x4A >> 1)
+#define I2C_ADDR_CHG    (0xD2 >> 1)
+#define I2C_ADDR_FG     (0x6C >> 1)
+#define I2C_ADDR_DEBUG  (0xC4 >> 1)
+
+static struct dentry *debugfs_file;
+
+static int max77705_debugfs_show(struct seq_file *s, void *data)
+{
+	struct max77705_dev *max77705 = s->private;
+	struct regmap *regmap = max77705->regmap;
+	unsigned int i, reg, reg_data, pmic_id, pmic_rev;
+	int regs[] = {
+		MAX77705_PMIC_REG_MAINCTRL1,
+		MAX77705_PMIC_REG_MCONFIG,
+		MAX77705_PMIC_REG_MCONFIG2,
+		MAX77705_PMIC_REG_INTSRC,
+		MAX77705_PMIC_REG_INTSRC_MASK,
+		MAX77705_PMIC_REG_SYSTEM_INT,
+		MAX77705_PMIC_REG_SYSTEM_INT_MASK,
+		MAX77705_RGBLED_REG_LEDEN,
+		MAX77705_RGBLED_REG_LED0BRT,
+		MAX77705_RGBLED_REG_LED1BRT,
+		MAX77705_RGBLED_REG_LED2BRT,
+		MAX77705_RGBLED_REG_LED3BRT,
+		MAX77705_RGBLED_REG_LEDBLNK
+	};
+
+	regmap_read(regmap, MAX77705_PMIC_REG_PMICID1, &pmic_id);
+	regmap_read(regmap, MAX77705_PMIC_REG_PMICREV, &pmic_rev);
+	seq_printf(s, "MAX77705, pmic id: %d, pmic rev: %d\n",

drivers/mfd/max77705-core.c new file +35 -0

+}
+
+DEFINE_SHOW_ATTRIBUTE(max77705_debugfs);
+
+static const struct regmap_config max77705_regmap_config = {
+	.reg_bits = 8,
+	.val_bits = 8,
+	.max_register = MAX77705_PMIC_REG_END,
+};
+
+static const struct regmap_config max77705_leds_regmap_config = {
+	.reg_bits = 8,
+	.val_bits = 8,
+	.max_register = MAX77705_LED_REG_END,
+};
+
+static const struct regmap_config max77705_fg_regmap_config = {
+	.reg_bits = 8,
+	.val_bits = 8,
+	.max_register = MAX77705_FG_END,
+};
+
+static struct mfd_cell max77705_devs[] = {
+	{
+		.name = "leds-max77705-rgb",
+		.of_compatible = "maxim,max77705-led",
+	},
+	{
+		.name = "max77705-fuelgauge",
+		.of_compatible = "maxim,max77705-fg",
+	},
+	{
+		.name = "max77705-charger",
+		.of_compatible = "maxim,max77705-charger",
+	},

drivers/mfd/max77705-core.c new file +14 -0

+		return ret;
+	}
+
+	max77705->regmap_leds = devm_regmap_init_i2c(max77705->i2c, &max77705_leds_regmap_config);
+	if (IS_ERR(max77705->regmap_leds)) {
+		ret = PTR_ERR(max77705->regmap_leds);
+		dev_err(max77705->dev, "failed to allocate register map: %d\n",
+				ret);
+		return ret;
+	}
+
+	i2c_set_clientdata(i2c, max77705);
+
+	if (regmap_read(max77705->regmap, MAX77705_PMIC_REG_PMICREV, &reg_data) < 0) {

drivers/mfd/max77705-core.c new file +13 -0

+	}
+
+	max77705->charger = devm_i2c_new_dummy_device(max77705->dev, i2c->adapter, I2C_ADDR_CHG);
+	i2c_set_clientdata(max77705->charger, max77705);
+	max77705->regmap_charger = devm_regmap_init_i2c(max77705->charger, &max77705_regmap_config);
+	if (IS_ERR(max77705->regmap)) {
+		ret = PTR_ERR(max77705->regmap);
+		dev_err(max77705->dev, "failed to allocate register map: %d\n",
+				ret);
+		return ret;
+	}
+
+	max77705->fuelgauge = devm_i2c_new_dummy_device(max77705->dev, i2c->adapter, I2C_ADDR_FG);

drivers/mfd/max77705-core.c new file +6 -0

+	ret = max77705_irq_init(max77705);
+	if (ret) {
+		dev_err(max77705->dev, "failed to init irq system: %d\n", ret);
+		return ret;
+	}
+

drivers/mfd/max77705-core.c new file +11 -0

+
+	device_init_wakeup(max77705->dev, true);
+
+	return ret;
+
+err_mfd:
+	mfd_remove_devices(max77705->dev);
+err:
+	kfree(max77705);
+	return ret;
+}

drivers/mfd/max77705-core.c new file +30 -0

+}
+
+static int __maybe_unused max77705_suspend(struct device *dev)
+{
+	struct i2c_client *i2c = to_i2c_client(dev);
+	struct max77705_dev *max77705 = i2c_get_clientdata(i2c);
+
+	disable_irq(max77705->irq);
+	if (device_may_wakeup(dev))
+		enable_irq_wake(max77705->irq);
+
+	return 0;
+}
+
+static int __maybe_unused max77705_resume(struct device *dev)
+{
+	struct i2c_client *i2c = to_i2c_client(dev);
+	struct max77705_dev *max77705 = i2c_get_clientdata(i2c);
+
+	if (device_may_wakeup(dev))
+		disable_irq_wake(max77705->irq);
+	enable_irq(max77705->irq);
+
+	return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(max77705_pm, max77705_suspend, max77705_resume);
+
+static const struct of_device_id max77705_i2c_dt_ids[] = {
+	{ .compatible = "maxim,max77705" },

drivers/mfd/max77705-core.c new file +9 -0

+	},
+	.probe		= max77705_i2c_probe,
+	.remove		= max77705_i2c_remove,
+};
+module_i2c_driver(max77705_i2c_driver);
+
+MODULE_DESCRIPTION("MAXIM 77705 multi-function core driver");
+MODULE_AUTHOR("Dzmitry Sankouski <[email protected]>");
+MODULE_LICENSE("GPL");

drivers/mfd/max77705-irq.c new file +79 -0

new file mode 100644
index 000000000000..0da17fc95e18
@@ -0,0 +1,299 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * max77705-irq.c - Interrupt controller support for MAX77705
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Copyright (C) 2024 Dzmitry Sankouski <[email protected]>
+ */
+
+#include <linux/err.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/mfd/max77705.h>
+#include <linux/mfd/max77705-private.h>
+#include <linux/regmap.h>
+
+static const u8 max77705_mask_reg[] = {
+	[SYS_INT] = MAX77705_PMIC_REG_SYSTEM_INT_MASK,
+	[CHG_INT] = MAX77705_CHG_REG_INT_MASK,
+	[FUEL_INT] = MAX77705_REG_INVALID,
+};
+
+static struct regmap *get_i2c(struct max77705_dev *max77705,
+				enum max77705_irq_source src)
+{
+	switch (src) {
+	case SYS_INT:
+		return max77705->regmap;
+	case FUEL_INT:
+		return max77705->regmap_fg;
+	case CHG_INT:
+		return max77705->regmap_charger;
+	default:
+		return ERR_PTR(-EINVAL);
+	}
+}
+
+struct max77705_irq_data {
+	int mask;
+	enum max77705_irq_source group;
+};
+
+static const struct max77705_irq_data max77705_irqs[] = {
+	[MAX77705_SYSTEM_IRQ_BSTEN_INT] = { .group = SYS_INT, .mask = BIT(3) },
+	[MAX77705_SYSTEM_IRQ_SYSUVLO_INT] = { .group = SYS_INT, .mask = BIT(4) },
+	[MAX77705_SYSTEM_IRQ_SYSOVLO_INT] = { .group = SYS_INT, .mask = BIT(5) },
+	[MAX77705_SYSTEM_IRQ_TSHDN_INT] = { .group = SYS_INT, .mask = BIT(6) },
+	[MAX77705_SYSTEM_IRQ_TM_INT] = { .group = SYS_INT, .mask = BIT(7) },
+
+	[MAX77705_CHG_IRQ_BYP_I] = { .group = CHG_INT, .mask = BIT(0) },
+	[MAX77705_CHG_IRQ_BAT_I] = { .group = CHG_INT, .mask = BIT(3) },
+	[MAX77705_CHG_IRQ_CHG_I] = { .group = CHG_INT, .mask = BIT(4) },
+	[MAX77705_CHG_IRQ_WCIN_I] = { .group = CHG_INT, .mask = BIT(5) },
+	[MAX77705_CHG_IRQ_CHGIN_I] = { .group = CHG_INT, .mask = BIT(6) },
+	[MAX77705_CHG_IRQ_AICL_I] = { .group = CHG_INT, .mask = BIT(7) },
+
+	[MAX77705_FG_IRQ_ALERT] = { .group = FUEL_INT, .mask = BIT(1) },
+};
+
+static void max77705_irq_lock(struct irq_data *data)
+{
+	struct max77705_dev *max77705 = irq_get_chip_data(data->irq);
+
+	mutex_lock(&max77705->irqlock);
+}
+
+static void max77705_irq_sync_unlock(struct irq_data *data)
+{
+	struct max77705_dev *max77705 = irq_get_chip_data(data->irq);
+	int i;
+
+	for (i = 0; i < MAX77705_IRQ_GROUP_NR; i++) {
+		u8 mask_reg = max77705_mask_reg[i];
+		struct regmap *i2c = get_i2c(max77705, i);
+

drivers/mfd/max77705-irq.c new file +2 -0

+
+MODULE_LICENSE("GPL");

include/linux/mfd/max77705-private.h new file +0 -0

new file mode 100644
index 000000000000..bd6ab9c582b8

include/linux/mfd/max77705-private.h new file +36 -0

+ */
+
+#ifndef __LINUX_MFD_MAX77705_PRIV_H
+#define __LINUX_MFD_MAX77705_PRIV_H
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+
+#define MAX77705_REG_INVALID		(0xff)
+#define MAX77705_IRQSRC_CHG			BIT(0)
+#define MAX77705_IRQSRC_TOP			BIT(1)
+#define MAX77705_IRQSRC_FG			BIT(2)
+#define MAX77705_IRQSRC_USBC		BIT(3)
+
+/* STATUS_REG */
+#define MAX77705_BAT_ABSENT_MASK	BIT(3)
+/* MAX77705 MAINCTRL1 register */
+#define MAX77705_MAINCTRL1_BIASEN_SHIFT		7
+#define MAX77705_MAINCTRL1_BIASEN_MASK		BIT(MAX77705_MAINCTRL1_BIASEN_SHIFT)
+
+/* max77705-haptic configuration register */
+#define MAX77705_CONFIG2_MEN_SHIFT		6
+#define MAX77705_CONFIG2_MODE_SHIFT		7
+#define MAX77705_CONFIG2_HTYP_SHIFT		5
+
+#define MAX77705_REVISION_MASK	7
+#define MAX77705_VERSION_MASK	0xF8
+#define MAX77705_VERSION_SHIFT	3
+
+enum max77705_hw_rev {
+	MAX77705_PASS1 = 1,
+	MAX77705_PASS2,

include/linux/mfd/max77705-private.h new file +186 -0

+	MAX77705_PMIC_REG_INTSRC_MASK		= 0x23,
+	MAX77705_PMIC_REG_SYSTEM_INT		= 0x24,
+	MAX77705_PMIC_REG_RESERVED_25		= 0x25,
+	MAX77705_PMIC_REG_SYSTEM_INT_MASK	= 0x26,
+	MAX77705_PMIC_REG_RESERVED_27		= 0x27,
+	MAX77705_PMIC_REG_RESERVED_28		= 0x28,
+	MAX77705_PMIC_REG_RESERVED_29		= 0x29,
+	MAX77705_PMIC_REG_BOOSTCONTROL1		= 0x4C,
+	MAX77705_PMIC_REG_BSTOUT_MASK		= 0x03,
+	MAX77705_PMIC_REG_BOOSTCONTROL2		= 0x4F,
+	MAX77705_PMIC_REG_FORCE_EN_MASK		= 0x08,
+	MAX77705_PMIC_REG_SW_RESET		= 0x50,
+	MAX77705_PMIC_REG_USBC_RESET		= 0x51,
+
+	/* Haptic motor driver Registers */
+	MAX77705_PMIC_REG_MCONFIG		= 0x10,
+	MAX77705_PMIC_REG_MCONFIG2		= 0x11,
+
+	MAX77705_CHG_REG_INT			= 0xB0,
+	MAX77705_CHG_REG_INT_MASK		= 0xB1,
+	MAX77705_CHG_REG_INT_OK			= 0xB2,
+	MAX77705_CHG_REG_DETAILS_00		= 0xB3,
+	MAX77705_CHG_REG_DETAILS_01		= 0xB4,
+	MAX77705_CHG_REG_DETAILS_02		= 0xB5,
+	MAX77705_CHG_REG_DTLS_03		= 0xB6,
+	MAX77705_CHG_REG_CNFG_00		= 0xB7,
+	MAX77705_CHG_REG_CNFG_01		= 0xB8,
+	MAX77705_CHG_REG_CNFG_02		= 0xB9,
+	MAX77705_CHG_REG_CNFG_03		= 0xBA,
+	MAX77705_CHG_REG_CNFG_04		= 0xBB,
+	MAX77705_CHG_REG_CNFG_05		= 0xBC,
+	MAX77705_CHG_REG_CNFG_06		= 0xBD,
+	MAX77705_CHG_REG_CNFG_07		= 0xBE,
+	MAX77705_CHG_REG_CNFG_08		= 0xBF,
+	MAX77705_CHG_REG_CNFG_09		= 0xC0,
+	MAX77705_CHG_REG_CNFG_10		= 0xC1,
+	MAX77705_CHG_REG_CNFG_11		= 0xC2,
+	MAX77705_CHG_REG_CNFG_12		= 0xC3,
+	MAX77705_CHG_REG_CNFG_13		= 0xC4,
+	MAX77705_CHG_REG_CNFG_14		= 0xC5,
+	MAX77705_CHG_REG_SAFEOUT_CTRL		= 0xC6,
+
+	MAX77705_PMIC_REG_END,
+};
+
+enum max77705_charger_battery_state {
+	MAX77705_BATTERY_NOBAT,
+	MAX77705_BATTERY_PREQUALIFICATION,
+	MAX77705_BATTERY_DEAD,
+	MAX77705_BATTERY_GOOD,
+	MAX77705_BATTERY_LOWVOLTAGE,
+	MAX77705_BATTERY_OVERVOLTAGE,
+	MAX77705_BATTERY_RESERVED,
+};
+
+enum max77705_charger_charge_type {
+	MAX77705_CHARGER_CONSTANT_CURRENT	= 1,
+	MAX77705_CHARGER_CONSTANT_VOLTAGE,
+	MAX77705_CHARGER_END_OF_CHARGE,
+	MAX77705_CHARGER_DONE,
+};
+
+/* Slave addr = 0x6C : Fuelgauge */
+enum max77705_fuelgauge_reg {
+	STATUS_REG				= 0x00,
+	VALRT_THRESHOLD_REG			= 0x01,
+	TALRT_THRESHOLD_REG			= 0x02,
+	SALRT_THRESHOLD_REG			= 0x03,
+	REMCAP_REP_REG				= 0x05,
+	SOCREP_REG				= 0x06,
+	TEMPERATURE_REG				= 0x08,
+	VCELL_REG				= 0x09,
+	TIME_TO_EMPTY_REG			= 0x11,
+	FULLSOCTHR_REG				= 0x13,
+	CURRENT_REG				= 0x0A,
+	AVG_CURRENT_REG				= 0x0B,
+	SOCMIX_REG				= 0x0D,
+	SOCAV_REG				= 0x0E,
+	REMCAP_MIX_REG				= 0x0F,
+	FULLCAP_REG				= 0x10,
+	RFAST_REG				= 0x15,
+	AVR_TEMPERATURE_REG			= 0x16,
+	CYCLES_REG				= 0x17,
+	DESIGNCAP_REG				= 0x18,
+	AVR_VCELL_REG				= 0x19,
+	TIME_TO_FULL_REG			= 0x20,
+	CONFIG_REG				= 0x1D,
+	ICHGTERM_REG				= 0x1E,
+	REMCAP_AV_REG				= 0x1F,
+	FULLCAP_NOM_REG				= 0x23,
+	LEARN_CFG_REG				= 0x28,
+	FILTER_CFG_REG				= 0x29,
+	MISCCFG_REG				= 0x2B,
+	QRTABLE20_REG				= 0x32,
+	FULLCAP_REP_REG				= 0x35,
+	RCOMP_REG				= 0x38,
+	VEMPTY_REG				= 0x3A,
+	FSTAT_REG				= 0x3D,
+	DISCHARGE_THRESHOLD_REG			= 0x40,
+	QRTABLE30_REG				= 0x42,
+	ISYS_REG				= 0x43,
+	DQACC_REG				= 0x45,
+	DPACC_REG				= 0x46,
+	AVGISYS_REG				= 0x4B,
+	QH_REG					= 0x4D,
+	VSYS_REG				= 0xB1,
+	TALRTTH2_REG				= 0xB2,
+	/* "not used REG(0xB2)" is for checking fuelgague init result. */
+	FG_INIT_RESULT_REG			= TALRTTH2_REG,
+	VBYP_REG				= 0xB3,
+	CONFIG2_REG				= 0xBB,
+	IIN_REG					= 0xD0,
+	OCV_REG					= 0xEE,
+	VFOCV_REG				= 0xFB,
+	VFSOC_REG				= 0xFF,
+
+	MAX77705_FG_END,
+};
+
+enum max77705_irq_source {
+	SYS_INT = 0,
+	CHG_INT,
+	FUEL_INT,
+	MAX77705_IRQ_GROUP_NR,
+};
+
+
+#define MAX77705_REG_MAINCTRL1_BIASEN		BIT(7)
+
+/* Slave addr = 0x94: RGB LED */
+enum max77705_led_reg {
+	MAX77705_RGBLED_REG_LEDEN			= 0x30,
+	MAX77705_RGBLED_REG_LED0BRT			= 0x31,
+	MAX77705_RGBLED_REG_LED1BRT			= 0x32,
+	MAX77705_RGBLED_REG_LED2BRT			= 0x33,
+	MAX77705_RGBLED_REG_LED3BRT			= 0x34,
+	MAX77705_RGBLED_REG_LEDRMP			= 0x36,
+	MAX77705_RGBLED_REG_LEDBLNK			= 0x38,
+	MAX77705_LED_REG_END,
+};
+
+enum max77705_irq {
+	/* PMIC; TOPSYS */
+	MAX77705_SYSTEM_IRQ_BSTEN_INT,
+	MAX77705_SYSTEM_IRQ_SYSUVLO_INT,
+	MAX77705_SYSTEM_IRQ_SYSOVLO_INT,
+	MAX77705_SYSTEM_IRQ_TSHDN_INT,
+	MAX77705_SYSTEM_IRQ_TM_INT,
+
+	/* PMIC; Charger */
+	MAX77705_CHG_IRQ_BYP_I,
+	MAX77705_CHG_IRQ_BAT_I,
+	MAX77705_CHG_IRQ_CHG_I,
+	MAX77705_CHG_IRQ_WCIN_I,
+	MAX77705_CHG_IRQ_CHGIN_I,
+	MAX77705_CHG_IRQ_AICL_I,
+
+	/* Fuelgauge */
+	MAX77705_FG_IRQ_ALERT,
+
+	MAX77705_IRQ_NR,
+};
+
+struct max77705_dev {
+	struct device *dev;
+	struct i2c_client *i2c; /* 0xCC; Haptic, PMIC */
+	struct i2c_client *charger; /* 0xD2; Charger */
+	struct i2c_client *fuelgauge; /* 0x6C; Fuelgauge */
+	struct i2c_client *muic; /* 0x4A; MUIC */
+	struct i2c_client *debug; /* 0xC4; Debug */
+	struct mutex i2c_lock;
+
+	struct regmap *regmap;
+	struct regmap *regmap_fg;
+	struct regmap *regmap_charger;
+	struct regmap *regmap_leds;
+
+	int type;
+
+	int irq;
+	int irq_base;
+	int irq_masks_cur[MAX77705_IRQ_GROUP_NR];
+	int irq_masks_cache[MAX77705_IRQ_GROUP_NR];
+	bool wakeup;
+	struct mutex irqlock;
+

include/linux/mfd/max77705-private.h new file +2 -0

+
+#endif /* __LINUX_MFD_MAX77705_PRIV_H */

include/linux/mfd/max77705.h new file +6 -0

new file mode 100644
index 000000000000..e2d757c77973
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * max77705.h - Driver for the Maxim 77705
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as

Add support for haptic controller on MAX77705 Multifunction device.

This driver supports external pwm and LRA (Linear Resonant Actuator) motor. User can control the haptic device via force feedback framework.

Signed-off-by Dzmitry Sankouski <[email protected]>

---

drivers/input/misc/max77705-haptic.c new file +107 -0

+static int max77705_haptic_bias(struct max77705_haptic *haptic, bool on)
+{
+	int error;
+
+	error = regmap_update_bits(haptic->regmap_haptic,
+							   MAX77705_PMIC_REG_MAINCTRL1,
+							   MAX77705_MAINCTRL1_BIASEN_MASK,
+							   on << MAX77705_MAINCTRL1_BIASEN_SHIFT);
+
+	if (error) {
+		dev_err(haptic->dev, "failed to %s bias: %d\n",
+			on ? "enable" : "disable", error);
+		return error;
+	}
+
+	return 0;
+}
+
+static int max77705_haptic_configure(struct max77705_haptic *haptic,
+				     bool enable)
+{
+	unsigned int value, config_reg;
+	int error;
+
+	value = ((haptic->type << MAX77705_CONFIG2_MODE_SHIFT) |
+		(enable << MAX77705_CONFIG2_MEN_SHIFT) |
+		(haptic->mode << MAX77705_CONFIG2_HTYP_SHIFT) |
+		MAX77705_HAPTIC_PWM_DIVISOR_128);
+	config_reg = MAX77705_PMIC_REG_MCONFIG;
+
+	error = regmap_write(haptic->regmap_haptic,
+			     config_reg, value);
+	if (error) {
+		dev_err(haptic->dev,
+			"failed to update haptic config: %d\n", error);
+		return error;
+	}
+
+	return 0;
+}
+
+static void max77705_haptic_enable(struct max77705_haptic *haptic)
+{
+	int error;
+
+	if (haptic->enabled)
+		return;
+
+	error = pwm_enable(haptic->pwm_dev);
+	if (error) {
+		dev_err(haptic->dev,
+			"failed to enable haptic pwm device: %d\n", error);
+		return;
+	}
+
+	error = max77705_haptic_configure(haptic, true);
+	if (error)
+		goto err_enable_config;
+
+	haptic->enabled = true;
+
+	return;
+
+err_enable_config:
+	pwm_disable(haptic->pwm_dev);
+}
+
+static void max77705_haptic_disable(struct max77705_haptic *haptic)
+{
+	int error;
+
+	if (!haptic->enabled)
+		return;
+
+	error = max77705_haptic_configure(haptic, false);
+	if (error)
+		return;
+
+	pwm_disable(haptic->pwm_dev);
+	haptic->enabled = false;
+}
+
+static void max77705_haptic_play_work(struct work_struct *work)
+{
+	struct max77705_haptic *haptic =
+			container_of(work, struct max77705_haptic, work);
+	int error;
+
+	error = max77705_haptic_set_duty_cycle(haptic);
+	if (error) {
+		dev_err(haptic->dev, "failed to set duty cycle: %d\n", error);
+		return;
+	}
+
+	if (haptic->magnitude)
+		max77705_haptic_enable(haptic);
+	else
+		max77705_haptic_disable(haptic);
+}
+
+static int max77705_haptic_play_effect(struct input_dev *dev, void *data,
+				       struct ff_effect *effect)
+{
+	struct max77705_haptic *haptic = input_get_drvdata(dev);
+	struct pwm_args pargs;
+	u64 period_mag_multi;
+

(quoted diff) +24 -0

+	pwm_get_args(haptic->pwm_dev, &pargs);
+	period_mag_multi = (u64)pargs.period * haptic->magnitude;
+	haptic->pwm_duty = (unsigned int)(period_mag_multi >>
+						MAX_MAGNITUDE_SHIFT);
+
+	schedule_work(&haptic->work);
+
+	return 0;
+}
 
 
+
+static DEFINE_SIMPLE_DEV_PM_OPS(max77705_haptic_pm_ops,
+				max77705_haptic_suspend,
+				max77705_haptic_resume);
+
+static const struct of_device_id of_max77705_haptic_dt_match[] = {
+	{ .compatible = "maxim,max77705-haptic", },
+	{ /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, of_max77705_haptic_dt_match);
+
+static struct platform_driver max77705_haptic_driver = {
+	.driver		= {
+		.name	= "max77705-haptic",
+		.pm	= pm_sleep_ptr(&max77705_haptic_pm_ops),