Updates for atevk1100 support

index 8ed5659..0b8bae9 100644
@@ -29,26 +29,11 @@
 void portmux_select_peripheral(void *port, unsigned long pin_mask,
 		enum portmux_function func, unsigned long flags)
 {
-	/* Both pull-up and pull-down set means buskeeper */
-	if (flags & PORTMUX_PULL_DOWN)
-		gpio_writel(port, PDERS, pin_mask);
-	else
-		gpio_writel(port, PDERC, pin_mask);
 	if (flags & PORTMUX_PULL_UP)
 		gpio_writel(port, PUERS, pin_mask);
 	else
 		gpio_writel(port, PUERC, pin_mask);
 
-	/* Select drive strength */
-	if (flags & PORTMUX_DRIVE_LOW)
-		gpio_writel(port, ODCR0S, pin_mask);
-	else
-		gpio_writel(port, ODCR0C, pin_mask);
-	if (flags & PORTMUX_DRIVE_HIGH)
-		gpio_writel(port, ODCR1S, pin_mask);
-	else
-		gpio_writel(port, ODCR1C, pin_mask);
-
 	/* Select function */
 	if (func & PORTMUX_FUNC_B)
 		gpio_writel(port, PMR0S, pin_mask);

@@ -66,11 +51,6 @@ void portmux_select_peripheral(void *port, unsigned long pin_mask,
 void portmux_select_gpio(void *port, unsigned long pin_mask,
 		unsigned long flags)
 {
-	/* Both pull-up and pull-down set means buskeeper */
-	if (flags & PORTMUX_PULL_DOWN)
-		gpio_writel(port, PDERS, pin_mask);
-	else
-		gpio_writel(port, PDERC, pin_mask);
 	if (flags & PORTMUX_PULL_UP)
 		gpio_writel(port, PUERS, pin_mask);
 	else

@@ -82,16 +62,6 @@ void portmux_select_gpio(void *port, unsigned long pin_mask,
 	else
 		gpio_writel(port, ODMERC, pin_mask);
 
-	/* Select drive strength */
-	if (flags & PORTMUX_DRIVE_LOW)
-		gpio_writel(port, ODCR0S, pin_mask);
-	else
-		gpio_writel(port, ODCR0C, pin_mask);
-	if (flags & PORTMUX_DRIVE_HIGH)
-		gpio_writel(port, ODCR1S, pin_mask);
-	else
-		gpio_writel(port, ODCR1C, pin_mask);
-
 	/* Select direction and initial pin state */
 	if (flags & PORTMUX_DIR_OUTPUT) {
 		if (flags & PORTMUX_INIT_HIGH)

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new file mode 100644
index 0000000..3306d0b
@@ -0,0 +1,34 @@
+#ifndef __ASM_AVR32_SRAM_H
+#define __ASM_AVR32_SRAM_H
+#include <asm/types.h>
+
+struct sram_config {
+	/* Number of data bits. */
+	u8 data_bits;
+
+	/* Chip select */
+	u8 chip_select;
+
+	/* Number of address bits */
+	u8 address_bits;
+
+	/* nwe/nrd waveforms */
+	u8 nwe_setup, nwe_pulse, nwe_hold;
+	u8 nrd_setup, nrd_pulse, nrd_hold;
+
+	/* ncs waveforms */
+	u8 ncs_wr_setup, ncs_wr_pulse, ncs_wr_hold;
+	u8 ncs_rd_setup, ncs_rd_pulse, ncs_rd_hold;
+
+	/* Cycle length */
+	u16 nwe_cycle, nrd_cycle;
+
+	/* mode */
+	u8 read_mode, write_mode, exnw_mode;
+	u8 bat, dbw, tdf_cycles, tdf_mode, pmen, ps;
+};
+
+
+unsigned long sram_init(const struct sram_config *config);
+
+#endif /* __ASM_AVR32_SRAM_H */

index 105e5c9..a85337e 100644
@@ -22,30 +22,51 @@
 #include <common.h>
 
 #include <asm/io.h>
-#include <asm/sdram.h>
+#include <asm/sram.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/hmatrix.h>
 #include <asm/arch/portmux.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct sdram_config sdram_config = {
-	/* MT48LC16M16A2-7E (32 MB) */
-	.data_bits	= SDRAM_DATA_16BIT,
-	.row_bits	= 13,
-	.col_bits	= 9,
-	.bank_bits	= 2,
-	.cas		= 2,
-	.twr		= 2,
-	.trc		= 7,
-	.trp		= 2,
-	.trcd		= 2,
-	.tras		= 4,
-	.txsr		= 7,
-	/* 7.81 us */
-	.refresh_period	= (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
-};
+static const struct sram_config sram_config = {
+	/* 2x16MBit, CY7C1069AV33-10ZXC */
+	.data_bits	= 16,
+	.address_bits	= 21,
+	.ncs_rd_setup	= 0,
+	.ncs_wr_setup 	= 0,
+	.nwe_setup	= 0,
+	.nrd_setup	= 0,
+	/*
+	 * These settings works when running at 33Mhz,
+	 * but fails at 54MHz
+	 */
+
+	/*
+	.ncs_wr_pulse 	= 1,
+	.ncs_rd_pulse	= 1,
+	.nwe_pulse	= 1,
+	.nrd_pulse	= 1,
+	.nwe_cycle	= 2,
+	.nrd_cycle	= 2,
+	*/
+	.ncs_wr_pulse 	= 2,
+	.ncs_rd_pulse	= 2,
+	.nwe_pulse	= 2,
+	.nrd_pulse	= 2,
+	.nwe_cycle	= 3,
+	.nrd_cycle	= 3,
+	.chip_select	= 2,
+	.read_mode	= 1,
+	.write_mode	= 1,
+	.exnw_mode	= 0,
+	.bat		= 1,
+	.tdf_cycles	= 0,
+	.tdf_mode	= 0,
+	.pmen		= 0,
+	.ps		= 1,
 
+};
 int board_early_init_f(void)
 {
 	/* Enable SDRAM in the EBI mux according to AP7000 datasheet */

@@ -65,14 +86,14 @@ phys_size_t initdram(int board_type)
 {
 	unsigned long expected_size;
 	unsigned long actual_size;
-	void *sdram_base;
+	void *sram_base;
 
-	sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE);
+	sram_base = map_physmem(EBI_SRAM_CS2_BASE, EBI_SRAM_CS2_SIZE, MAP_NOCACHE);
 
-	expected_size = sdram_init(sdram_base, &sdram_config);
-	actual_size = get_ram_size(sdram_base, expected_size);
+	expected_size = sram_init(&sram_config);
+	actual_size = get_ram_size(sram_base, expected_size);
 
-	unmap_physmem(sdram_base, EBI_SDRAM_SIZE);
+	unmap_physmem(sram_base, EBI_SRAM_CS2_SIZE);
 
 	if (expected_size != actual_size)
 		printf("Warning: Only %lu of %lu MiB SDRAM is working\n",

index db5af37..166027a 100644
@@ -148,7 +148,8 @@
 #define CONFIG_ATMEL_SPI		1
 #define CONFIG_PORTMUX_GPIO		1
 #define CFG_NR_PIOS			5
-#define CFG_SDRAMC			1
+#define CFG_SDRAMC			0
+#define CFG_SMC				1
 
 #define CFG_DCACHE_LINESZ		32
 #define CFG_ICACHE_LINESZ		32

@@ -165,7 +166,8 @@
 
 #define CFG_INTRAM_BASE			INTERNAL_SRAM_BASE
 #define CFG_INTRAM_SIZE			INTERNAL_SRAM_SIZE
-#define CFG_SDRAM_BASE			EBI_SDRAM_BASE
+/* Not really SDRAM, maybe change to SRAM? */
+#define CFG_SDRAM_BASE			EBI_SRAM_CS2_BASE
 
 #define CONFIG_ENV_IS_IN_FLASH		1
 #define CONFIG_ENV_SIZE			65536

@@ -176,8 +178,8 @@
 #define CFG_MALLOC_LEN			(256*1024)
 #define CFG_DMA_ALLOC_LEN		(16384)
 
-/* Allow 4MB for the kernel run-time image */
-#define CFG_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00400000)
+/* Allow 3MB(TODO:update) for the kernel run-time image */
+#define CFG_LOAD_ADDR			(CFG_SDRAM_BASE + 0x00270000)
 #define CFG_BOOTPARAMS_LEN		(16 * 1024)
 
 /* Other configuration settings that shouldn't have to change all that often */

@@ -187,7 +189,7 @@
 #define CFG_PBSIZE			(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
 #define CFG_LONGHELP			1
 
-#define CFG_MEMTEST_START		EBI_SDRAM_BASE
+#define CFG_MEMTEST_START		CFG_SDRAM_BASE
 #define CFG_MEMTEST_END			(CFG_MEMTEST_START + 0x700000)
 #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
 

index 6afa8bd..216ff74 100644
@@ -294,13 +294,8 @@ void board_init_r(gd_t *new_gd, ulong dest_addr)
 	     cmdtp !=  &__u_boot_cmd_end; cmdtp++) {
 		unsigned long addr;
 
-		/* We don't relocate code in the at32uc3a0xxx cpu yet due to
-		 * SDRAM bug. See errata 41.4.6.1.
-		 */
-#ifndef CONFIG_AT32UC
 		addr = (unsigned long)cmdtp->cmd + gd->reloc_off;
 		cmdtp->cmd = (typeof(cmdtp->cmd))addr;
-#endif
 
 		addr = (unsigned long)cmdtp->name + gd->reloc_off;
 		cmdtp->name = (typeof(cmdtp->name))addr;

index f33a4bb..e626e1f 100644
@@ -45,6 +45,7 @@ unsigned long flash_init(void)
 {
 	unsigned long fsz;
 	unsigned long size;
+	unsigned int i;
 
 	fsz = FLASHC_BFEXT(FSZ, flashc_readl(FSR));
 

@@ -55,6 +56,10 @@ unsigned long flash_init(void)
 	/* Currently, all interflash have pages which are 128 words. */
 	flash_info[0].sector_count = size / (128*4);
 
+	for(i=0; i<flash_info[0].sector_count; i++){
+		flash_info[0].start[i] = i*128*4 + CFG_FLASH_BASE;
+	}
+
 	return size;
 }
 

@@ -62,19 +67,77 @@ void flash_print_info(flash_info_t *info)
 {
 	printf("Flash: Vendor ID: 0x%02lx, Product ID: 0x%02lx\n",
 	       info->flash_id >> 16, info->flash_id & 0xffff);
-	printf("Size: %ld MB in %d sectors\n",
+	printf("Size: %ld kB in %d sectors\n",
 	       info->size >> 10, info->sector_count);
 }
 
+static void flash_wait_ready(void)
+{
+	while(! flashc_readl(FSR) & FLASHC_BIT(FRDY) );
+}
+
 int flash_erase(flash_info_t *info, int s_first, int s_last)
 {
-	/* TODO */
+	int page;
+
+	for(page=s_first;page<s_last; page++){
+		flash_wait_ready();
+		flashc_writel(
+			FCMD,FLASHC_BF(CMD, FLASHC_EP)
+			|FLASHC_BF(PAGEN, page)
+			|FLASHC_BF(KEY, 0xa5));
+	}
 	return ERR_OK;
 }
 
+static void write_flash_page(unsigned int pagen, const u32 *data)
+{
+	unsigned int i;
+	u32 *dst;
+
+	dst = (u32 *) CFG_FLASH_BASE;
+
+	/* clear page buffer */
+	flash_wait_ready();
+	flashc_writel(FCMD,
+		FLASHC_BF(CMD, FLASHC_CPB) |
+		FLASHC_BF(KEY, 0xa5));
+
+	/* fill page buffer*/
+	flash_wait_ready();
+	for(i=0; i<128; i++){
+		dst[i]=data[i];
+	}
+
+	/* issue write command */
+	flashc_writel(FCMD,
+		FLASHC_BF(CMD, FLASHC_WP)|
+		FLASHC_BF(PAGEN, pagen)|
+		FLASHC_BF(KEY, 0xa5));
+}
+
 int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong count)
 {
-	/* TODO */
+	unsigned int i;
+
+	if (addr % (4*128)) {
+		printf("flash: write_buff(): ERROR, addr(0x%08lx) not "
+			"on page boundary", addr);
+		return ERR_ALIGN;
+	}
+	if (count % (4*128)) {
+		printf("flash: write_buff(): ERROR, count(0x%lu) not "
+			"a multiple of pagesize", count);
+		return ERR_ALIGN;
+	}
+
+	for (i = 0; i < count; i += 128*4) {
+		unsigned int pagen;
+		pagen = (addr-CFG_FLASH_BASE+i) / (128*4);
+		write_flash_page(pagen, (u32*) (src+i));
+	}
+
+
 	return ERR_OK;
 }
 

index 23618bc..3e97781 100644
@@ -43,6 +43,23 @@
 #define FLASHC_LOCK_OFFSET			16
 #define FLASHC_LOCK_SIZE			16
 
+#define FLASHC_NOP 	0 /*No operation*/
+#define FLASHC_WP 	1 /*Write Page*/
+#define FLASHC_EP	2 /*Erase Page*/
+#define FLASHC_CPB 	3 /*Clear Page Buffer*/
+#define FLASHC_LP 	4 /*Lock region containing given Page*/
+#define FLASHC_UP 	5 /*Unlock region containing given Page*/
+#define FLASHC_EA 	6 /*Erase All*/
+#define FLASHC_WGPB	7 /*Write General-Purpose Fuse Bit*/
+#define FLASHC_EGPB 	8 /*Erase General-Purpose Fuse Bit*/
+#define FLASHC_SSB 	9 /*Set Security Bit*/
+#define FLASHC_PGPFB 	10 /*Program GP Fuse Byte*/
+#define FLASHC_EAGPF 	11 /*Erase All GPFuses*/
+#define FLASHC_QPR 	12 /*Quick Page Read*/
+#define FLASHC_WUP	13 /*Write User Page*/
+#define FLASHC_EUP	14 /*Erase User Page*/
+#define FLASHC_QPRUP 	15 /*Quick Page Read User Page*/
+
 
 /* Bit manipulation macros */
 #define FLASHC_BIT(name)					\

index 166027a..776a3a1 100644
@@ -160,7 +160,7 @@
 #define CFG_FLASH_BASE			0x80000000
 #define CFG_FLASH_SIZE			0x80000
 #define CFG_MAX_FLASH_BANKS		1
-#define CFG_MAX_FLASH_SECT		135
+#define CFG_MAX_FLASH_SECT		1024
 
 #define CFG_MONITOR_BASE		CFG_FLASH_BASE
 

index 776a3a1..2a9d91b 100644
@@ -95,17 +95,17 @@
 
 #define CONFIG_BAUDRATE			9600
 #define CONFIG_BOOTARGS							\
-	"console=ttyS0 root=/dev/mmcblk0p1 fbmem=600k rootwait=1"
+	"console=ttyS0 ip=dhcp root=/dev/nfs rootwait=1"
 
 #define CONFIG_BOOTCOMMAND						\
-	"fsload; bootm $(fileaddr)"
+	"dhcp; bootm $(fileaddr)"
 
 /*
  * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
  * data on the serial line may interrupt the boot sequence.
  */
-#define CONFIG_BOOTDELAY		-1
-#define CONFIG_AUTOBOOT			0
+#define CONFIG_BOOTDELAY		1
+#define CONFIG_AUTOBOOT			1
 #define CONFIG_AUTOBOOT_KEYED		1
 #define CONFIG_AUTOBOOT_PROMPT		\
 	"Press SPACE to abort autoboot in %d seconds\n", bootdelay