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Add support for SPEAr13xx SoCs

PATCH Superseded Viresh Kumar 4 participants 23 messages Apr 20, 2012 – Apr 24, 2012

Subsystems (7)

v1 of 2 Superseded Latest is v2 →

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#0 lore raw

cover Add support for SPEAr13xx SoCs

Arnd,

Sorry for yet another patchset for you :(

This one adds in support for SPEAr1310 and SPEAr1340. It supports:
- DT probing
- pinctrl drivers
- common clock framework

All you requested to get this upstream. :)

I have CC-ed Linus and Mike for their patches and would ask them for their Acks, as this would evantually make through your ARM-SoC tree.

Few devices/drivers mentioned in dts files have their DT probing patches under review.

Viresh Kumar (9):
SPEAr13xx: Add header files
SPEAr13xx: Add source files
SPEAr13xx: Add common clock framework support
pinctrl: SPEAr: Create macro for declaring GPIO PINS
pinctrl: Add SPEAr13xx pinctrl drivers
SPEAr13xx: Add dts and dtsi files
SPEAr13xx: Add compilation support
SPEAr13xx: Add defconfig
SPEAr: Update MAINTAINERS and Documentation

 Documentation/arm/SPEAr/overview.txt               |   32 +-
 Documentation/devicetree/bindings/arm/spear.txt    |   14 +-
 .../devicetree/bindings/pinctrl/pinctrl_spear.txt  |   47 +
 MAINTAINERS                                        |   13 +
 arch/arm/Makefile                                  |    2 +
 arch/arm/boot/dts/spear1310-evb.dts                |  267 +++
 arch/arm/boot/dts/spear1310.dtsi                   |  184 ++
 arch/arm/boot/dts/spear1340-evb.dts                |  291 +++
 arch/arm/boot/dts/spear1340.dtsi                   |   56 +
 arch/arm/boot/dts/spear13xx.dtsi                   |  258 +++
 arch/arm/configs/spear13xx_defconfig               |   91 +
 arch/arm/mach-spear13xx/Kconfig                    |   20 +
 arch/arm/mach-spear13xx/Makefile                   |   10 +
 arch/arm/mach-spear13xx/Makefile.boot              |    6 +
 arch/arm/mach-spear13xx/headsmp.S                  |   47 +
 arch/arm/mach-spear13xx/hotplug.c                  |  119 ++
 arch/arm/mach-spear13xx/include/mach/debug-macro.S |   14 +
 arch/arm/mach-spear13xx/include/mach/dma.h         |  128 ++
 arch/arm/mach-spear13xx/include/mach/generic.h     |   49 +
 arch/arm/mach-spear13xx/include/mach/gpio.h        |   19 +
 arch/arm/mach-spear13xx/include/mach/hardware.h    |    1 +
 arch/arm/mach-spear13xx/include/mach/irqs.h        |   23 +
 arch/arm/mach-spear13xx/include/mach/spear.h       |  173 ++
 arch/arm/mach-spear13xx/include/mach/timex.h       |   19 +
 arch/arm/mach-spear13xx/include/mach/uncompress.h  |   19 +
 arch/arm/mach-spear13xx/platsmp.c                  |  127 ++
 arch/arm/mach-spear13xx/spear1310.c                |   88 +
 arch/arm/mach-spear13xx/spear1340.c                |  192 ++
 arch/arm/mach-spear13xx/spear13xx.c                |  210 ++
 arch/arm/plat-spear/Kconfig                        |   12 +
 arch/arm/plat-spear/Makefile                       |    5 +-
 arch/arm/plat-spear/restart.c                      |    5 +
 drivers/clk/spear/Makefile                         |    2 +
 drivers/clk/spear/spear1310_clock.c                | 1051 ++++++++++
 drivers/clk/spear/spear1340_clock.c                |  968 +++++++++
 drivers/pinctrl/spear/Kconfig                      |   10 +
 drivers/pinctrl/spear/Makefile                     |    2 +
 drivers/pinctrl/spear/pinctrl-spear.h              |  251 +++
 drivers/pinctrl/spear/pinctrl-spear1310.c          | 2198 ++++++++++++++++++++
 drivers/pinctrl/spear/pinctrl-spear1340.c          | 1989 ++++++++++++++++++
 drivers/pinctrl/spear/pinctrl-spear3xx.c           |  103 +-
 41 files changed, 8989 insertions(+), 126 deletions(-)
 create mode 100644 arch/arm/boot/dts/spear1310-evb.dts
 create mode 100644 arch/arm/boot/dts/spear1310.dtsi
 create mode 100644 arch/arm/boot/dts/spear1340-evb.dts
 create mode 100644 arch/arm/boot/dts/spear1340.dtsi
 create mode 100644 arch/arm/boot/dts/spear13xx.dtsi
 create mode 100644 arch/arm/configs/spear13xx_defconfig
 create mode 100644 arch/arm/mach-spear13xx/Kconfig
 create mode 100644 arch/arm/mach-spear13xx/Makefile
 create mode 100644 arch/arm/mach-spear13xx/Makefile.boot
 create mode 100644 arch/arm/mach-spear13xx/headsmp.S
 create mode 100644 arch/arm/mach-spear13xx/hotplug.c
 create mode 100644 arch/arm/mach-spear13xx/include/mach/debug-macro.S
 create mode 100644 arch/arm/mach-spear13xx/include/mach/dma.h
 create mode 100644 arch/arm/mach-spear13xx/include/mach/generic.h
 create mode 100644 arch/arm/mach-spear13xx/include/mach/gpio.h
 create mode 100644 arch/arm/mach-spear13xx/include/mach/hardware.h
 create mode 100644 arch/arm/mach-spear13xx/include/mach/irqs.h
 create mode 100644 arch/arm/mach-spear13xx/include/mach/spear.h
 create mode 100644 arch/arm/mach-spear13xx/include/mach/spear1310_misc_regs.h
 create mode 100644 arch/arm/mach-spear13xx/include/mach/spear1340_misc_regs.h
 create mode 100644 arch/arm/mach-spear13xx/include/mach/timex.h
 create mode 100644 arch/arm/mach-spear13xx/include/mach/uncompress.h
 create mode 100644 arch/arm/mach-spear13xx/platsmp.c
 create mode 100644 arch/arm/mach-spear13xx/spear1310.c
 create mode 100644 arch/arm/mach-spear13xx/spear1340.c
 create mode 100644 arch/arm/mach-spear13xx/spear13xx.c
 create mode 100644 drivers/clk/spear/spear1310_clock.c
 create mode 100644 drivers/clk/spear/spear1340_clock.c
 create mode 100644 drivers/pinctrl/spear/pinctrl-spear1310.c
 create mode 100644 drivers/pinctrl/spear/pinctrl-spear1340.c
Signature · 1 line
1.7.9
#1 lore raw

PATCH 1/9 SPEAr13xx: Add header files

This patch adds basic header files for SPEAr13xx Machines.

---
 arch/arm/mach-spear13xx/include/mach/debug-macro.S |   14 ++
 arch/arm/mach-spear13xx/include/mach/dma.h         |  128 +++++++++++++++
 arch/arm/mach-spear13xx/include/mach/generic.h     |   49 ++++++
 arch/arm/mach-spear13xx/include/mach/gpio.h        |   19 ++
 arch/arm/mach-spear13xx/include/mach/hardware.h    |    1 +
 arch/arm/mach-spear13xx/include/mach/irqs.h        |   23 +++
 arch/arm/mach-spear13xx/include/mach/spear.h       |  173 ++++++++++++++++++++
 arch/arm/mach-spear13xx/include/mach/timex.h       |   19 ++
 arch/arm/mach-spear13xx/include/mach/uncompress.h  |   19 ++
 9 files changed, 445 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-spear13xx/include/mach/debug-macro.S
 create mode 100644 arch/arm/mach-spear13xx/include/mach/dma.h
 create mode 100644 arch/arm/mach-spear13xx/include/mach/generic.h
 create mode 100644 arch/arm/mach-spear13xx/include/mach/gpio.h
 create mode 100644 arch/arm/mach-spear13xx/include/mach/hardware.h
 create mode 100644 arch/arm/mach-spear13xx/include/mach/irqs.h
 create mode 100644 arch/arm/mach-spear13xx/include/mach/spear.h
 create mode 100644 arch/arm/mach-spear13xx/include/mach/spear1310_misc_regs.h
 create mode 100644 arch/arm/mach-spear13xx/include/mach/spear1340_misc_regs.h
 create mode 100644 arch/arm/mach-spear13xx/include/mach/timex.h
 create mode 100644 arch/arm/mach-spear13xx/include/mach/uncompress.h
arch/arm/mach-spear13xx/include/mach/debug-macro.S new file +14 -0
new file mode 100644
index 0000000..ea15646
@@ -0,0 +1,14 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/debug-macro.S
+ *
+ * Debugging macro include header spear13xx machine family
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <plat/debug-macro.S>
arch/arm/mach-spear13xx/include/mach/dma.h new file +128 -0

128 lines not on this page · raw message

arch/arm/mach-spear13xx/include/mach/generic.h new file +49 -0

49 lines not on this page · raw message

arch/arm/mach-spear13xx/include/mach/gpio.h new file +19 -0
new file mode 100644
index 0000000..cd6f4f8
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/gpio.h
+ *
+ * GPIO macros for SPEAr13xx machine family
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_GPIO_H
+#define __MACH_GPIO_H
+
+#include <plat/gpio.h>
+
+#endif /* __MACH_GPIO_H */
arch/arm/mach-spear13xx/include/mach/hardware.h new file +1 -0
new file mode 100644
index 0000000..40a8c17
@@ -0,0 +1 @@
+/* empty */
arch/arm/mach-spear13xx/include/mach/irqs.h new file +23 -0
new file mode 100644
index 0000000..ddf5721
@@ -0,0 +1,23 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/irqs.h
+ *
+ * IRQ helper macros for spear13xx machine family
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_IRQS_H
+#define __MACH_IRQS_H
+
+#define IRQ_LOCALTIMER			29
+#define SPEAR13XX_IRQ_GPT0_TMR0		69
+#define SPEAR13XX_IRQ_GPT0_TMR1		70
+#define IRQ_GIC_END			160
+#define NR_IRQS				IRQ_GIC_END
+
+#endif /* __MACH_IRQS_H */
arch/arm/mach-spear13xx/include/mach/spear.h new file +173 -0

173 lines not on this page · raw message

arch/arm/mach-spear13xx/include/mach/spear1310_misc_regs.h new file +0 -0
new file mode 100644
index 0000000..e69de29
arch/arm/mach-spear13xx/include/mach/spear1340_misc_regs.h new file +0 -0
new file mode 100644
index 0000000..e69de29
arch/arm/mach-spear13xx/include/mach/timex.h new file +19 -0
new file mode 100644
index 0000000..31af3e8
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear3xx/include/mach/timex.h
+ *
+ * SPEAr3XX machine family specific timex definitions
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_TIMEX_H
+#define __MACH_TIMEX_H
+
+#include <plat/timex.h>
+
+#endif /* __MACH_TIMEX_H */
arch/arm/mach-spear13xx/include/mach/uncompress.h new file +19 -0
new file mode 100644
index 0000000..c784089
@@ -0,0 +1,19 @@
+/*
+ * arch/arm/mach-spear13xx/include/mach/uncompress.h
+ *
+ * Serial port stubs for kernel decompress status messages
+ *
+ * Copyright (C) 2012 ST Microelectronics
+ * Viresh Kumar <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_UNCOMPRESS_H
+#define __MACH_UNCOMPRESS_H
+
+#include <plat/uncompress.h>
+
+#endif /* __MACH_UNCOMPRESS_H */
Signature · 1 line
1.7.9
#2 lore raw

PATCH 1/9 SPEAr13xx: Add header files

Quoted 11 lines · Viresh Kumar
arch/arm/mach-spear13xx/include/mach/dma.h new file +4 -0
new file mode 100644
index 0000000..383ab04
@@ -0,0 +1,128 @@
 
+#ifndef __MACH_DMA_H
+#define __MACH_DMA_H
+
+/* request id of all the peripherals */

arch/arm/mach-spear13xx/include/mach/dma.h line 27

Quoted 10 lines
arch/arm/mach-spear13xx/include/mach/dma.h new file +10 -0
+enum dma_master_info {
+	/* Accessible from only one master */
+	DMA_MASTER_MCIF = 0,
+	DMA_MASTER_FSMC = 1,
+	/* Accessible from both 0 & 1 */
+	DMA_MASTER_MEMORY = 0,
+	DMA_MASTER_ADC = 0,
+	DMA_MASTER_UART0 = 0,
+	DMA_MASTER_SSP0 = 0,
+	DMA_MASTER_I2C0 = 0,

Ideally we wouldn't have this file and put all the data into the device tree of course but we're still lacking bindings for that, so it's still ok for v3.5.

arch/arm/mach-spear13xx/include/mach/irqs.h line 5

Quoted 11 lines
arch/arm/mach-spear13xx/include/mach/irqs.h new file +5 -0
new file mode 100644
index 0000000..ddf5721
@@ -0,0 +1,23 @@
+
+#ifndef __MACH_IRQS_H
+#define __MACH_IRQS_H
+
+#define IRQ_LOCALTIMER			29

I think we can now probe localtimer from devicetree so you should not need this one any more.

arch/arm/mach-spear13xx/include/mach/irqs.h line 19

Quoted 2 lines
arch/arm/mach-spear13xx/include/mach/irqs.h new file +2 -0
+#define SPEAR13XX_IRQ_GPT0_TMR0		69
+#define SPEAR13XX_IRQ_GPT0_TMR1		70

I'd also prefer if you could add bindings for GPT and probe these interrupts and the GPT address from the devicetree for the three spear platforms, that would make the code much nicer in this area.

Quoted 39 lines
arch/arm/mach-spear13xx/include/mach/irqs.h new file +39 -0
+#define PERIP_GRP2_BASE				UL(0xB3000000)
+#define VA_PERIP_GRP2_BASE			UL(0xFE000000)
+#define MCIF_SDHCI_BASE				UL(0xB3000000)
+#define SYSRAM0_BASE				UL(0xB3800000)
+#define VA_SYSRAM0_BASE				UL(0xFE800000)
+#define SYS_LOCATION				(VA_SYSRAM0_BASE + 0x600)
+
+#define PERIP_GRP1_BASE				UL(0xE0000000)
+#define VA_PERIP_GRP1_BASE			UL(0xFD000000)
+#define UART_BASE				UL(0xE0000000)
+#define VA_UART_BASE				UL(0xFD000000)
+#define ADC_BASE				UL(0xE0080000)
+#define SSP_BASE				UL(0xE0100000)
+#define I2C_BASE				UL(0xE0280000)
+#define KBD_BASE				UL(0xE0300000)
+#define GPT0_BASE				UL(0xE0380000)
+#define GPIO0_BASE				UL(0xE0600000)
+#define GPIO1_BASE				UL(0xE0680000)
+#define MISC_BASE				UL(0xE0700000)
+#define VA_MISC_BASE				IOMEM(UL(0xFD700000))
+#define SYSRAM1_BASE				UL(0xE0800000)
+
+#define A9SM_AND_MPMC_BASE			UL(0xEC000000)
+#define VA_A9SM_AND_MPMC_BASE			UL(0xFC000000)
+
+/* A9SM peripheral offsets */
+#define A9SM_PERIP_BASE				UL(0xEC800000)
+#define VA_A9SM_PERIP_BASE			UL(0xFC800000)
+#define VA_SCU_BASE				(VA_A9SM_PERIP_BASE + 0x00)
+#define GIC_CPU_BASE				(A9SM_PERIP_BASE + 0x100)
+#define GLOBAL_TMR_BASE				(A9SM_PERIP_BASE + 0x200)
+#define LOCAL_TMR_BASE				(A9SM_PERIP_BASE + 0x600)
+#define GIC_DIST_BASE				(A9SM_PERIP_BASE + 0x1000)
+
+#define L2CC_BASE				UL(0xED000000)
+#define VA_L2CC_BASE				IOMEM(UL(0xFB000000))
+
+/* others */
+#define GETH_BASE				UL(0xE2000000)

arch/arm/mach-spear13xx/include/mach/irqs.h

Quoted 10 lines
arch/arm/mach-spear13xx/include/mach/irqs.h new file +10 -0
+#define DMAC0_BASE				UL(0xEA800000)
+#define DMAC1_BASE				UL(0xEB000000)
+#define MCIF_CF_BASE				UL(0xB2800000)
+
+/* Devices present in SPEAr1310 */
+#ifdef CONFIG_MACH_SPEAR1310
+#define SPEAR1310_RAS_GRP1_BASE			UL(0xD8000000)
+#define VA_SPEAR1310_RAS_GRP1_BASE		UL(0xFA000000)
+#define SPEAR1310_RAS_BASE			UL(0xD8400000)
+#define VA_SPEAR1310_RAS_BASE			IOMEM(UL(0xFA400000))

Can you go through this list one more time and check which ones are still needed here? I think most of them can just get removed.

arch/arm/mach-spear13xx/include/mach/irqs.h

Quoted 13 lines
arch/arm/mach-spear13xx/include/mach/irqs.h new file +13 -0
+/* RAS Area Control Register */
+#define SPEAR1310_RAS_CTRL_REG0			(VA_SPEAR1310_RAS_BASE + 0x000)
+	#define SPEAR1310_GPT64_SYNC_ENB		0
+	#define SPEAR1310_GPT64_SYNC_ENB_MASK		1
+	#define SPEAR1310_GPT64_SYNC_ENB_SHIFT		31
+	#define SPEAR1310_SSP1_CS_SEL_CS0		0
+	#define SPEAR1310_SSP1_CS_SEL_CS1		1
+	#define SPEAR1310_SSP1_CS_SEL_MASK		3
+	#define SPEAR1310_SSP1_CS_SEL_SHIFT		30
+	#define SPEAR1310_SSP1_CS_VAL_MASK		1
+	#define SPEAR1310_SSP1_CS_VAL_SHIFT		28
+	#define SPEAR1310_SSP1_CS_CTL_HW		0
+	#define SPEAR1310_SSP1_CS_CTL_SW		1

Why are the RAS control registers in a global header? It looks like you only use them from the clock driver, so they can be moved into a local header file there.

Arnd

#3 lore raw

PATCH 1/9 SPEAr13xx: Add header files

Quoted 16 lines · Arnd Bergmann

arch/arm/mach-spear13xx/include/mach/irqs.h line 5

Quoted 12 lines · Viresh Kumar
arch/arm/mach-spear13xx/include/mach/irqs.h new file +5 -0
new file mode 100644
index 0000000..ddf5721
@@ -0,0 +1,23 @@
+
+#ifndef __MACH_IRQS_H
+#define __MACH_IRQS_H
+
+#define IRQ_LOCALTIMER			29

I think we can now probe localtimer from devicetree so you should not need this one any more.

Done in V2.

Quoted 7 lines

arch/arm/mach-spear13xx/include/mach/irqs.h line 19

Quoted 2 lines
arch/arm/mach-spear13xx/include/mach/irqs.h new file +2 -0
+#define SPEAR13XX_IRQ_GPT0_TMR0		69
+#define SPEAR13XX_IRQ_GPT0_TMR1		70

I'd also prefer if you could add bindings for GPT and probe these interrupts and the GPT address from the devicetree for the three spear platforms, that would make the code much nicer in this area.

Done in V2.

Quoted 7 lines

arch/arm/mach-spear13xx/include/mach/irqs.h line 11

Quoted 4 lines
arch/arm/mach-spear13xx/include/mach/irqs.h new file +4 -0
+#define PERIP_GRP2_BASE				UL(0xB3000000)
+#define VA_PERIP_GRP2_BASE			UL(0xFE000000)
+#define MCIF_SDHCI_BASE				UL(0xB3000000)
+#define SYSRAM0_BASE				UL(0xB3800000)

Can you go through this list one more time and check which ones are still needed here? I think most of them can just get removed.

Yes. Removed whatever is not used currently.

Quoted 9 lines
Quoted 9 lines
arch/arm/mach-spear13xx/include/mach/irqs.h new file +9 -0
+/* RAS Area Control Register */
+#define SPEAR1310_RAS_CTRL_REG0			(VA_SPEAR1310_RAS_BASE + 0x000)
+	#define SPEAR1310_GPT64_SYNC_ENB		0
+	#define SPEAR1310_GPT64_SYNC_ENB_MASK		1
+	#define SPEAR1310_GPT64_SYNC_ENB_SHIFT		31
+	#define SPEAR1310_SSP1_CS_SEL_CS0		0
+	#define SPEAR1310_SSP1_CS_SEL_CS1		1
+	#define SPEAR1310_SSP1_CS_SEL_MASK		3
+	#define SPEAR1310_SSP1_CS_SEL_SHIFT		30
Quoted 8 lines

arch/arm/mach-spear13xx/include/mach/irqs.h

Quoted 4 lines
arch/arm/mach-spear13xx/include/mach/irqs.h new file +4 -0
+	#define SPEAR1310_SSP1_CS_VAL_MASK		1
+	#define SPEAR1310_SSP1_CS_VAL_SHIFT		28
+	#define SPEAR1310_SSP1_CS_CTL_HW		0
+	#define SPEAR1310_SSP1_CS_CTL_SW		1

Why are the RAS control registers in a global header? It looks like you only use them from the clock driver, so they can be moved into a local header file there.

Actually registers serves many different features. Clock, software controlled chip selects for spi, etc. So really can't move to clock drivers.

I didn't wanted half part of a register in one file and other half in other. So kept them here, so that these are accessible from all users.

--
viresh

#4 lore raw

PATCH 1/9 SPEAr13xx: Add header files

Quoted 20 lines · viresh kumar
Quoted 10 lines · Arnd Bergmann
Quoted 9 lines · Viresh Kumar
arch/arm/mach-spear13xx/include/mach/spear.h new file +9 -0
+/* RAS Area Control Register */
+#define SPEAR1310_RAS_CTRL_REG0			(VA_SPEAR1310_RAS_BASE + 0x000)
+	#define SPEAR1310_GPT64_SYNC_ENB		0
+	#define SPEAR1310_GPT64_SYNC_ENB_MASK		1
+	#define SPEAR1310_GPT64_SYNC_ENB_SHIFT		31
+	#define SPEAR1310_SSP1_CS_SEL_CS0		0
+	#define SPEAR1310_SSP1_CS_SEL_CS1		1
+	#define SPEAR1310_SSP1_CS_SEL_MASK		3
+	#define SPEAR1310_SSP1_CS_SEL_SHIFT		30
Quoted 8 lines

arch/arm/mach-spear13xx/include/mach/spear.h line 81

Quoted 4 lines
arch/arm/mach-spear13xx/include/mach/spear.h new file +4 -0
+	#define SPEAR1310_SSP1_CS_VAL_MASK		1
+	#define SPEAR1310_SSP1_CS_VAL_SHIFT		28
+	#define SPEAR1310_SSP1_CS_CTL_HW		0
+	#define SPEAR1310_SSP1_CS_CTL_SW		1

Why are the RAS control registers in a global header? It looks like you only use them from the clock driver, so they can be moved into a local header file there.

Quoted 5 lines

Actually registers serves many different features. Clock, software controlled chip selects for spi, etc. So really can't move to clock drivers.

I didn't wanted half part of a register in one file and other half in other. So kept them here, so that these are accessible from all users.

It's still really ugly to have that in a global header file, including the hardcoded register addresses.

What I'd suggest you do instead here is export a function to access the registers from device drivers and add a new header file that contains only this interface, the register offsets and the register definitions. Then you can use proper of_iomap calls to get the area from the device tree in the machine init code and it will be clear which drivers use the interface because they have to explicitly include that header.

Arnd

#5 lore raw

PATCH 1/9 SPEAr13xx: Add header files

Quoted 2 lines · Arnd Bergmann

It's still really ugly to have that in a global header file, including the hardcoded register addresses.

I will check if i can move this to clock.c for now, to move things quicker. :)

--
viresh

#6 lore raw

PATCH 1/9 SPEAr13xx: Add header files

Quoted 7 lines · viresh kumar
Quoted 3 lines · Arnd Bergmann

It's still really ugly to have that in a global header file, including the
hardcoded register addresses.

I will check if i can move this to clock.c for now, to move things quicker. :)

Will squash following with this patch in my pull request, if i don't need to send V3:

From: Viresh Kumar <[email protected]>
Date: Mon, 23 Apr 2012 17:35:36 +0530
Subject: [PATCH 1/2] fixup! SPEAr13xx: Add header files

Remove 1310 specific register declarations from spear.h

---
 arch/arm/mach-spear13xx/include/mach/spear.h |   99 --------------------------
 1 files changed, 0 insertions(+), 99 deletions(-)
(quoted diff) +0 -0

b/arch/arm/mach-spear13xx/include/mach/spear.h
index 57fb960..30c57ef 100644

arch/arm/mach-spear13xx/include/mach/spear.h +0 -99

103 lines not on this page · raw message

#7 lore raw

PATCH 2/9 SPEAr13xx: Add source files

In reply to Viresh Kumar

This patch adds source files for SPEAr13xx Machines.

---
 arch/arm/mach-spear13xx/Kconfig       |   18 +++
 arch/arm/mach-spear13xx/Makefile      |   10 ++
 arch/arm/mach-spear13xx/Makefile.boot |    6 +
 arch/arm/mach-spear13xx/headsmp.S     |   47 ++++++++
 arch/arm/mach-spear13xx/hotplug.c     |  119 +++++++++++++++++++
 arch/arm/mach-spear13xx/platsmp.c     |  127 ++++++++++++++++++++
 arch/arm/mach-spear13xx/spear1310.c   |   88 ++++++++++++++
 arch/arm/mach-spear13xx/spear1340.c   |  192 ++++++++++++++++++++++++++++++
 arch/arm/mach-spear13xx/spear13xx.c   |  210 +++++++++++++++++++++++++++++++++
 arch/arm/plat-spear/restart.c         |    5 +
 10 files changed, 822 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-spear13xx/Kconfig
 create mode 100644 arch/arm/mach-spear13xx/Makefile
 create mode 100644 arch/arm/mach-spear13xx/Makefile.boot
 create mode 100644 arch/arm/mach-spear13xx/headsmp.S
 create mode 100644 arch/arm/mach-spear13xx/hotplug.c
 create mode 100644 arch/arm/mach-spear13xx/platsmp.c
 create mode 100644 arch/arm/mach-spear13xx/spear1310.c
 create mode 100644 arch/arm/mach-spear13xx/spear1340.c
 create mode 100644 arch/arm/mach-spear13xx/spear13xx.c
arch/arm/mach-spear13xx/Kconfig new file +18 -0
new file mode 100644
index 0000000..138e891
@@ -0,0 +1,18 @@
+#
+# SPEAr13XX Machine configuration file
+#
+
+if ARCH_SPEAR13XX
+
+menu "SPEAr13xx Implementations"
+config MACH_SPEAR1310
+	bool "SPEAr1310 Machine support with Device Tree"
+	help
+	  Supports ST SPEAr1310 machine configured via the device-tree
+
+config MACH_SPEAR1340
+	bool "SPEAr1340 Machine support with Device Tree"
+	help
+	  Supports ST SPEAr1340 machine configured via the device-tree
+endmenu
+endif #ARCH_SPEAR13XX
arch/arm/mach-spear13xx/Makefile new file +10 -0
new file mode 100644
index 0000000..3435ea7
@@ -0,0 +1,10 @@
+#
+# Makefile for SPEAr13XX machine series
+#
+
+obj-$(CONFIG_SMP)		+= headsmp.o platsmp.o
+obj-$(CONFIG_HOTPLUG_CPU)	+= hotplug.o
+
+obj-$(CONFIG_ARCH_SPEAR13XX)	+= spear13xx.o
+obj-$(CONFIG_MACH_SPEAR1310)	+= spear1310.o
+obj-$(CONFIG_MACH_SPEAR1340)	+= spear1340.o
arch/arm/mach-spear13xx/Makefile.boot new file +6 -0
new file mode 100644
index 0000000..403efd7
@@ -0,0 +1,6 @@
+zreladdr-y	+= 0x00008000
+params_phys-y	:= 0x00000100
+initrd_phys-y	:= 0x00800000
+
+dtb-$(CONFIG_MACH_SPEAR1310)	+= spear1310-evb.dtb
+dtb-$(CONFIG_MACH_SPEAR1340)	+= spear1340-evb.dtb
arch/arm/mach-spear13xx/headsmp.S new file +47 -0

47 lines not on this page · raw message

arch/arm/mach-spear13xx/hotplug.c new file +119 -0

119 lines not on this page · raw message

arch/arm/mach-spear13xx/platsmp.c new file +127 -0

127 lines not on this page · raw message

arch/arm/mach-spear13xx/spear1310.c new file +88 -0

88 lines not on this page · raw message

arch/arm/mach-spear13xx/spear1340.c new file +192 -0

192 lines not on this page · raw message

arch/arm/mach-spear13xx/spear13xx.c new file +210 -0

210 lines not on this page · raw message

arch/arm/plat-spear/restart.c +5 -0
index 4471a23..ea0a613 100644
@@ -16,6 +16,7 @@
 #include <mach/spear.h>
 #include <mach/generic.h>
 
+#define SPEAR13XX_SYS_SW_RES			(VA_MISC_BASE + 0x204)
 void spear_restart(char mode, const char *cmd)
 {
 	if (mode == 's') {
@@ -23,6 +24,10 @@ void spear_restart(char mode, const char *cmd)
 		soft_restart(0);
 	} else {
 		/* hardware reset, Use on-chip reset capability */
+#ifdef CONFIG_ARCH_SPEAR13XX
+		writel_relaxed(0x01, SPEAR13XX_SYS_SW_RES);
+#else
 		sysctl_soft_reset((void __iomem *)VA_SPEAR_SYS_CTRL_BASE);
+#endif
 	}
 }
Signature · 1 line
1.7.9
#8 lore raw

PATCH 2/9 SPEAr13xx: Add source files

Quoted 11 lines · Viresh Kumar
arch/arm/mach-spear13xx/spear1340.c new file +11 -0
+static struct dw_dma_slave uart1_dma_param[] = {
+	{
+		/* Tx */
+		.cfg_hi = DWC_CFGH_DST_PER(SPEAR1340_DMA_REQ_UART1_TX),
+		.cfg_lo = 0,
+		.src_master = DMA_MASTER_MEMORY,
+		.dst_master = SPEAR1340_DMA_MASTER_UART1,
+	}, {
+		/* Rx */
+		.cfg_hi = DWC_CFGH_SRC_PER(SPEAR1340_DMA_REQ_UART1_RX),
+		.cfg_lo = 0,

arch/arm/mach-spear13xx/spear1340.c line 101

Quoted 10 lines
arch/arm/mach-spear13xx/spear1340.c new file +10 -0
+		.src_master = SPEAR1340_DMA_MASTER_UART1,
+		.dst_master = DMA_MASTER_MEMORY,
+	}
+};
+
+static struct amba_pl011_data uart1_data = {
+	.dma_filter = dw_dma_filter,
+	.dma_tx_param = &uart1_dma_param[0],
+	.dma_rx_param = &uart1_dma_param[1],
+};

Again, I hope that we can remove this eventually when we have the DMA bindings, but it's ok for now.

Quoted 30 lines
arch/arm/mach-spear13xx/spear1340.c new file +30 -0
+/* SATA device registration */
+static int sata_miphy_init(struct device *dev, void __iomem *addr)
+{
+	writel(SPEAR1340_SATA_CFG_VAL, SPEAR1340_PCIE_SATA_CFG);
+	writel(SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK,
+			SPEAR1340_PCIE_MIPHY_CFG);
+	/* Switch on sata power domain */
+	writel((readl(SPEAR1340_PCM_CFG) | (0x800)), SPEAR1340_PCM_CFG);
+	msleep(20);
+	/* Disable PCIE SATA Controller reset */
+	writel((readl(SPEAR1340_PERIP1_SW_RST) & (~0x1000)),
+			SPEAR1340_PERIP1_SW_RST);
+	msleep(20);
+
+	return 0;
+}
+
+void sata_miphy_exit(struct device *dev)
+{
+	writel(0, SPEAR1340_PCIE_SATA_CFG);
+	writel(0, SPEAR1340_PCIE_MIPHY_CFG);
+
+	/* Enable PCIE SATA Controller reset */
+	writel((readl(SPEAR1340_PERIP1_SW_RST) | (0x1000)),
+			SPEAR1340_PERIP1_SW_RST);
+	msleep(20);
+	/* Switch off sata power domain */
+	writel((readl(SPEAR1340_PCM_CFG) & (~0x800)), SPEAR1340_PCM_CFG);
+	msleep(20);
+}

arch/arm/mach-spear13xx/spear1340.c line 142

Quoted 10 lines
arch/arm/mach-spear13xx/spear1340.c new file +10 -0
+
+int sata_suspend(struct device *dev)
+{
+	if (dev->power.power_state.event == PM_EVENT_FREEZE)
+		return 0;
+
+	sata_miphy_exit(dev);
+
+	return 0;
+}

I'd like to see this done differently, with a ahci_spear driver derived from ahci_platform that provides these functions in a modular driver that registers to a spear specific identifier string and is able to do the platform specific based on information it can find in the device tree. That would however require changes to the existing ahci_platform code and I'd first like to hear what Jeff and others have to say about this.

Arnd

#9 lore raw

PATCH 2/9 SPEAr13xx: Add source files

Quoted 6 lines · Arnd Bergmann

Review

Quoted 2 lines · Viresh Kumar
(quoted diff) +2 -0
+static struct dw_dma_slave uart1_dma_param[] = {
+	{

Again, I hope that we can remove this eventually when we have the DMA bindings, but it's ok for now.

Surely try do later, once those DT bindings are up.

Quoted 42 lines
Quoted 30 lines
arch/arm/mach-spear13xx/spear1340.c new file +30 -0
+/* SATA device registration */
+static int sata_miphy_init(struct device *dev, void __iomem *addr)
+{
+	writel(SPEAR1340_SATA_CFG_VAL, SPEAR1340_PCIE_SATA_CFG);
+	writel(SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK,
+			SPEAR1340_PCIE_MIPHY_CFG);
+	/* Switch on sata power domain */
+	writel((readl(SPEAR1340_PCM_CFG) | (0x800)), SPEAR1340_PCM_CFG);
+	msleep(20);
+	/* Disable PCIE SATA Controller reset */
+	writel((readl(SPEAR1340_PERIP1_SW_RST) & (~0x1000)),
+			SPEAR1340_PERIP1_SW_RST);
+	msleep(20);
+
+	return 0;
+}
+
+void sata_miphy_exit(struct device *dev)
+{
+	writel(0, SPEAR1340_PCIE_SATA_CFG);
+	writel(0, SPEAR1340_PCIE_MIPHY_CFG);
+
+	/* Enable PCIE SATA Controller reset */
+	writel((readl(SPEAR1340_PERIP1_SW_RST) | (0x1000)),
+			SPEAR1340_PERIP1_SW_RST);
+	msleep(20);
+	/* Switch off sata power domain */
+	writel((readl(SPEAR1340_PCM_CFG) & (~0x800)), SPEAR1340_PCM_CFG);
+	msleep(20);
+}

arch/arm/mach-spear13xx/spear1340.c line 142

Quoted 10 lines
arch/arm/mach-spear13xx/spear1340.c new file +10 -0
+
+int sata_suspend(struct device *dev)
+{
+	if (dev->power.power_state.event == PM_EVENT_FREEZE)
+		return 0;
+
+	sata_miphy_exit(dev);
+
+	return 0;
+}

I'd like to see this done differently, with a ahci_spear driver derived from

Quoted 8 lines

ahci_platform that provides these functions in a modular driver that registers
to a spear specific identifier string and is able to do the platform specific
based on information it can find in the device tree. That would however require
changes to the existing ahci_platform code and I'd first like to hear what Jeff and others have to say about this.

To get platform data for ahci with DT, we need to do as mentioned by you. But for now maybe we can accept this approach. Once somebody fix ahci DT support as you suggested, we could create such drivers.

--
viresh

#10 lore raw

PATCH 2/9 SPEAr13xx: Add source files

Quoted 12 lines · viresh kumar
Quoted 9 lines · Arnd Bergmann

I'd like to see this done differently, with a ahci_spear driver derived from ahci_platform that provides these functions in a modular driver that registers
to a spear specific identifier string and is able to do the platform specific
based on information it can find in the device tree. That would however require
changes to the existing ahci_platform code and I'd first like to hear what Jeff and others have to say about this.

Quoted 3 lines

To get platform data for ahci with DT, we need to do as mentioned by you. But for now maybe we can accept this approach. Once somebody fix ahci DT support as you suggested, we could create such drivers.

Ok, fair enough. Right now we have only four platforms using this (davinci, exynos, imx and now spear), but the code is still fairly well isolated.

Arnd

#11 lore raw

PATCH 3/9 SPEAr13xx: Add common clock framework support

In reply to Viresh Kumar

This patch adds SPEAr1310 and SPEAr1340's clock framework support. It is based on earlier support for SPEAr3xx family.

Cc Mike Turquette <[email protected]>

---
Mike,

This would be required to go through Arnd's tree. So would be great if i can have your comments/Ack here.

 drivers/clk/spear/Makefile          |    2 +
 drivers/clk/spear/spear1310_clock.c | 1051 +++++++++++++++++++++++++++++++++++
 drivers/clk/spear/spear1340_clock.c |  968 ++++++++++++++++++++++++++++++++
 3 files changed, 2021 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/spear/spear1310_clock.c
 create mode 100644 drivers/clk/spear/spear1340_clock.c
drivers/clk/spear/Makefile +2 -0
index b499da6..6728271 100644
@@ -6,3 +6,5 @@ obj-y	+= clk-aux-synth.o clk-frac-synth.o clk-gpt-synth.o clk-vco-pll.o
 
 obj-$(CONFIG_ARCH_SPEAR3XX)	+= spear3xx_clock.o
 obj-$(CONFIG_ARCH_SPEAR6XX)	+= spear6xx_clock.o
+obj-$(CONFIG_MACH_SPEAR1310)	+= spear1310_clock.o
+obj-$(CONFIG_MACH_SPEAR1340)	+= spear1340_clock.o
drivers/clk/spear/spear1310_clock.c new file +1051 -0

1,051 lines not on this page · raw message

drivers/clk/spear/spear1340_clock.c new file +968 -0

968 lines not on this page · raw message

Signature · 1 line
1.7.9
#12 lore raw

PATCH 3/9 SPEAr13xx: Add common clock framework support

Quoted 10 lines · Viresh Kumar

This patch adds SPEAr1310 and SPEAr1340's clock framework support. It is based on earlier support for SPEAr3xx family.

Cc Mike Turquette <[email protected]>

---
Mike,

This would be required to go through Arnd's tree. So would be great if i can have your comments/Ack here.

Most of this patch looks good to me accept for the two items below:

...

drivers/clk/spear/spear1310_clock.c

Quoted 6 lines
drivers/clk/spear/spear1310_clock.c new file +6 -0
+void __init spear1310_clk_init(void)
+{
+ ? ? ? struct clk *clk, *clk1;
+
+ ? ? ? clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
+ ? ? ? clk_register_clkdev(clk, "apb_pclk", NULL);

There is no exception handling at all in this function. Do you just expect to fail at some later point?

...

drivers/clk/spear/spear1340_clock.c

Quoted 6 lines
drivers/clk/spear/spear1340_clock.c new file +6 -0
+void __init spear1340_clk_init(void)
+{
+ ? ? ? struct clk *clk, *clk1;
+
+ ? ? ? clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
+ ? ? ? clk_register_clkdev(clk, "apb_pclk", NULL);

Ditto.

Regards,
Mike

#13 lore raw

PATCH 3/9 SPEAr13xx: Add common clock framework support

Quoted 8 lines · Mike
Quoted 6 lines

drivers/clk/spear/spear1310_clock.c line 320

Quoted 6 lines
drivers/clk/spear/spear1310_clock.c new file +6 -0
+void __init spear1310_clk_init(void)
+{
+       struct clk *clk, *clk1;
+
+       clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
+       clk_register_clkdev(clk, "apb_pclk", NULL);

There is no exception handling at all in this function. Do you just expect to fail at some later point?

This is what Russell suggested in his clkdev patch. We don't have to check clk * returned from clk_register_*(). This will be done in clk_register_clkdev(), clk lookup wouldn't be registered for failing clocks.

Signature · 1 line
viresh
#14 lore raw

PATCH 4/9 pinctrl: SPEAr: Create macro for declaring GPIO PINS

In reply to Viresh Kumar

Same GPIO pins declarations would be required for other SoCs and that will be a lot of lines of code. Its better to create common macros for it.

---
Linus,

This would be required to go through Arnd's tree. So would be great if i can have your comments/Ack here.

 drivers/pinctrl/spear/pinctrl-spear.h    |  105 ++++++++++++++++++++++++++++++
 drivers/pinctrl/spear/pinctrl-spear3xx.c |  103 +-----------------------------
 2 files changed, 106 insertions(+), 102 deletions(-)
drivers/pinctrl/spear/pinctrl-spear.h +105 -0
index 47a6b5b..1f51dc9 100644
@@ -139,4 +139,109 @@ void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg);
 int __devinit spear_pinctrl_probe(struct platform_device *pdev,
 		struct spear_pinctrl_machdata *machdata);
 int __devexit spear_pinctrl_remove(struct platform_device *pdev);
+
+#define SPEAR_PIN_0_TO_101		\
+	PINCTRL_PIN(0, "PLGPIO0"),	\
+	PINCTRL_PIN(1, "PLGPIO1"),	\
+	PINCTRL_PIN(2, "PLGPIO2"),	\
+	PINCTRL_PIN(3, "PLGPIO3"),	\
+	PINCTRL_PIN(4, "PLGPIO4"),	\
+	PINCTRL_PIN(5, "PLGPIO5"),	\
+	PINCTRL_PIN(6, "PLGPIO6"),	\
+	PINCTRL_PIN(7, "PLGPIO7"),	\
+	PINCTRL_PIN(8, "PLGPIO8"),	\
+	PINCTRL_PIN(9, "PLGPIO9"),	\
+	PINCTRL_PIN(10, "PLGPIO10"),	\
+	PINCTRL_PIN(11, "PLGPIO11"),	\
+	PINCTRL_PIN(12, "PLGPIO12"),	\
+	PINCTRL_PIN(13, "PLGPIO13"),	\
+	PINCTRL_PIN(14, "PLGPIO14"),	\
+	PINCTRL_PIN(15, "PLGPIO15"),	\
+	PINCTRL_PIN(16, "PLGPIO16"),	\
+	PINCTRL_PIN(17, "PLGPIO17"),	\
+	PINCTRL_PIN(18, "PLGPIO18"),	\
+	PINCTRL_PIN(19, "PLGPIO19"),	\
+	PINCTRL_PIN(20, "PLGPIO20"),	\
+	PINCTRL_PIN(21, "PLGPIO21"),	\
+	PINCTRL_PIN(22, "PLGPIO22"),	\
+	PINCTRL_PIN(23, "PLGPIO23"),	\
+	PINCTRL_PIN(24, "PLGPIO24"),	\
+	PINCTRL_PIN(25, "PLGPIO25"),	\
+	PINCTRL_PIN(26, "PLGPIO26"),	\
+	PINCTRL_PIN(27, "PLGPIO27"),	\
+	PINCTRL_PIN(28, "PLGPIO28"),	\
+	PINCTRL_PIN(29, "PLGPIO29"),	\
+	PINCTRL_PIN(30, "PLGPIO30"),	\
+	PINCTRL_PIN(31, "PLGPIO31"),	\
+	PINCTRL_PIN(32, "PLGPIO32"),	\
+	PINCTRL_PIN(33, "PLGPIO33"),	\
+	PINCTRL_PIN(34, "PLGPIO34"),	\
+	PINCTRL_PIN(35, "PLGPIO35"),	\
+	PINCTRL_PIN(36, "PLGPIO36"),	\
+	PINCTRL_PIN(37, "PLGPIO37"),	\
+	PINCTRL_PIN(38, "PLGPIO38"),	\
+	PINCTRL_PIN(39, "PLGPIO39"),	\
+	PINCTRL_PIN(40, "PLGPIO40"),	\
+	PINCTRL_PIN(41, "PLGPIO41"),	\
+	PINCTRL_PIN(42, "PLGPIO42"),	\
+	PINCTRL_PIN(43, "PLGPIO43"),	\
+	PINCTRL_PIN(44, "PLGPIO44"),	\
+	PINCTRL_PIN(45, "PLGPIO45"),	\
+	PINCTRL_PIN(46, "PLGPIO46"),	\
+	PINCTRL_PIN(47, "PLGPIO47"),	\
+	PINCTRL_PIN(48, "PLGPIO48"),	\
+	PINCTRL_PIN(49, "PLGPIO49"),	\
+	PINCTRL_PIN(50, "PLGPIO50"),	\
+	PINCTRL_PIN(51, "PLGPIO51"),	\
+	PINCTRL_PIN(52, "PLGPIO52"),	\
+	PINCTRL_PIN(53, "PLGPIO53"),	\
+	PINCTRL_PIN(54, "PLGPIO54"),	\
+	PINCTRL_PIN(55, "PLGPIO55"),	\
+	PINCTRL_PIN(56, "PLGPIO56"),	\
+	PINCTRL_PIN(57, "PLGPIO57"),	\
+	PINCTRL_PIN(58, "PLGPIO58"),	\
+	PINCTRL_PIN(59, "PLGPIO59"),	\
+	PINCTRL_PIN(60, "PLGPIO60"),	\
+	PINCTRL_PIN(61, "PLGPIO61"),	\
+	PINCTRL_PIN(62, "PLGPIO62"),	\
+	PINCTRL_PIN(63, "PLGPIO63"),	\
+	PINCTRL_PIN(64, "PLGPIO64"),	\
+	PINCTRL_PIN(65, "PLGPIO65"),	\
+	PINCTRL_PIN(66, "PLGPIO66"),	\
+	PINCTRL_PIN(67, "PLGPIO67"),	\
+	PINCTRL_PIN(68, "PLGPIO68"),	\
+	PINCTRL_PIN(69, "PLGPIO69"),	\
+	PINCTRL_PIN(70, "PLGPIO70"),	\
+	PINCTRL_PIN(71, "PLGPIO71"),	\
+	PINCTRL_PIN(72, "PLGPIO72"),	\
+	PINCTRL_PIN(73, "PLGPIO73"),	\
+	PINCTRL_PIN(74, "PLGPIO74"),	\
+	PINCTRL_PIN(75, "PLGPIO75"),	\
+	PINCTRL_PIN(76, "PLGPIO76"),	\
+	PINCTRL_PIN(77, "PLGPIO77"),	\
+	PINCTRL_PIN(78, "PLGPIO78"),	\
+	PINCTRL_PIN(79, "PLGPIO79"),	\
+	PINCTRL_PIN(80, "PLGPIO80"),	\
+	PINCTRL_PIN(81, "PLGPIO81"),	\
+	PINCTRL_PIN(82, "PLGPIO82"),	\
+	PINCTRL_PIN(83, "PLGPIO83"),	\
+	PINCTRL_PIN(84, "PLGPIO84"),	\
+	PINCTRL_PIN(85, "PLGPIO85"),	\
+	PINCTRL_PIN(86, "PLGPIO86"),	\
+	PINCTRL_PIN(87, "PLGPIO87"),	\
+	PINCTRL_PIN(88, "PLGPIO88"),	\
+	PINCTRL_PIN(89, "PLGPIO89"),	\
+	PINCTRL_PIN(90, "PLGPIO90"),	\
+	PINCTRL_PIN(91, "PLGPIO91"),	\
+	PINCTRL_PIN(92, "PLGPIO92"),	\
+	PINCTRL_PIN(93, "PLGPIO93"),	\
+	PINCTRL_PIN(94, "PLGPIO94"),	\
+	PINCTRL_PIN(95, "PLGPIO95"),	\
+	PINCTRL_PIN(96, "PLGPIO96"),	\
+	PINCTRL_PIN(97, "PLGPIO97"),	\
+	PINCTRL_PIN(98, "PLGPIO98"),	\
+	PINCTRL_PIN(99, "PLGPIO99"),	\
+	PINCTRL_PIN(100, "PLGPIO100"),	\
+	PINCTRL_PIN(101, "PLGPIO101")
+
 #endif /* __PINMUX_SPEAR_H__ */
drivers/pinctrl/spear/pinctrl-spear3xx.c +1 -102

109 lines not on this page · raw message

Signature · 1 line
1.7.9
#15 lore raw

PATCH 6/9 SPEAr13xx: Add dts and dtsi files

In reply to Viresh Kumar

This patch adds machines/boards dts{i} files for SPEAr1310 and SPEAr1340. Both are based on ARM, Cortex A9 processor family.

---
 arch/arm/boot/dts/spear1310-evb.dts |  267 ++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/spear1310.dtsi    |  184 ++++++++++++++++++++++
 arch/arm/boot/dts/spear1340-evb.dts |  291 +++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/spear1340.dtsi    |   56 +++++++
 arch/arm/boot/dts/spear13xx.dtsi    |  258 +++++++++++++++++++++++++++++++
 5 files changed, 1056 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/boot/dts/spear1310-evb.dts
 create mode 100644 arch/arm/boot/dts/spear1310.dtsi
 create mode 100644 arch/arm/boot/dts/spear1340-evb.dts
 create mode 100644 arch/arm/boot/dts/spear1340.dtsi
 create mode 100644 arch/arm/boot/dts/spear13xx.dtsi
arch/arm/boot/dts/spear1310-evb.dts new file +267 -0
new file mode 100644
index 0000000..1ffc46c
@@ -0,0 +1,267 @@
+/*
+ * DTS file for SPEAr1310 Evaluation Baord
+ *
+ * Copyright 2012 Viresh Kumar <[email protected]>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "spear1310.dtsi"
+
+/ {
+	model = "ST SPEAr1310 Evaluation Board";
+	compatible = "st,spear1310-evb", "st,spear1310";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	memory {
+		reg = <0 0x40000000>;
+	};
+
+	ahb {
+		pinmux at e0700000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&state_default>;
+
+			state_default: pinmux {
+				i2c0-pmx {
+					st,pins = "i2c0_grp";
+					st,function = "i2c0";
+				};
+				i2s1 {
+					st,pins = "i2s1_grp";
+					st,function = "i2s1";
+				};
+				gpio {
+					st,pins = "arm_gpio_grp";
+					st,function = "arm_gpio";
+				};
+				eth {
+					st,pins = "gmii_grp";
+					st,function = "gmii";
+				};
+				ssp0 {
+					st,pins = "ssp0_grp";
+					st,function = "ssp0";
+				};
+				kbd {
+					st,pins = "keyboard_6x6_grp";
+					st,function = "keyboard";
+				};
+				sdhci {
+					st,pins = "sdhci_grp";
+					st,function = "sdhci";
+				};
+				smi-pmx {
+					st,pins = "smi_2_chips_grp";
+					st,function = "smi";
+				};
+				uart0 {
+					st,pins = "uart0_grp";
+					st,function = "uart0";
+				};
+				rs485 {
+					st,pins = "rs485_0_1_tdm_0_1_grp";
+					st,function = "rs485_0_1_tdm_0_1";
+				};
+				i2c1_2 {
+					st,pins = "i2c_1_2_grp";
+					st,function = "i2c_1_2";
+				};
+				pci {
+					st,pins = "pcie0_grp","pcie1_grp",
+						"pcie2_grp";
+					st,function = "pci";
+				};
+				smii {
+					st,pins = "smii_0_1_2_grp";
+					st,function = "smii_0_1_2";
+				};
+				nand {
+					st,pins = "nand_8bit_grp",
+						"nand_16bit_grp";
+					st,function = "nand";
+				};
+			};
+		};
+
+		ahci at b1000000 {
+			status = "okay";
+		};
+
+		cf at b2800000 {
+			status = "okay";
+		};
+
+		dma at ea800000 {
+			status = "okay";
+		};
+
+		dma at eb000000 {
+			status = "okay";
+		};
+
+		fsmc: flash at b0000000 {
+			status = "okay";
+		};
+
+		gmac0: eth at e2000000 {
+			status = "okay";
+		};
+
+		sdhci at b3000000 {
+			status = "okay";
+		};
+
+		smi: flash at ea000000 {
+			status = "okay";
+		};
+
+		spi0: spi at e0100000 {
+			status = "okay";
+		};
+
+		ehci at e4800000 {
+			status = "okay";
+		};
+
+		ehci at e5800000 {
+			status = "okay";
+		};
+
+		ohci at e4000000 {
+			status = "okay";
+		};
+
+		ohci at e5000000 {
+			status = "okay";
+		};
+
+		apb {
+			adc at e0080000 {
+				status = "okay";
+			};
+
+			gpio0: gpio at e0600000 {
+			       status = "okay";
+			};
+
+			gpio1: gpio at e0680000 {
+			       status = "okay";
+			};
+
+			i2c0: i2c at e0280000 {
+			       status = "okay";
+			};
+
+			i2c1: i2c at 5cd00000 {
+			       status = "okay";
+			};
+
+			kbd at e0300000 {
+				linux,keymap = < 0x00000001
+						 0x00010002
+						 0x00020003
+						 0x00030004
+						 0x00040005
+						 0x00050006
+						 0x00060007
+						 0x00070008
+						 0x00080009
+						 0x0100000a
+						 0x0101000c
+						 0x0102000d
+						 0x0103000e
+						 0x0104000f
+						 0x01050010
+						 0x01060011
+						 0x01070012
+						 0x01080013
+						 0x02000014
+						 0x02010015
+						 0x02020016
+						 0x02030017
+						 0x02040018
+						 0x02050019
+						 0x0206001a
+						 0x0207001b
+						 0x0208001c
+						 0x0300001d
+						 0x0301001e
+						 0x0302001f
+						 0x03030020
+						 0x03040021
+						 0x03050022
+						 0x03060023
+						 0x03070024
+						 0x03080025
+						 0x04000026
+						 0x04010027
+						 0x04020028
+						 0x04030029
+						 0x0404002a
+						 0x0405002b
+						 0x0406002c
+						 0x0407002d
+						 0x0408002e
+						 0x0500002f
+						 0x05010030
+						 0x05020031
+						 0x05030032
+						 0x05040033
+						 0x05050034
+						 0x05060035
+						 0x05070036
+						 0x05080037
+						 0x06000038
+						 0x06010039
+						 0x0602003a
+						 0x0603003b
+						 0x0604003c
+						 0x0605003d
+						 0x0606003e
+						 0x0607003f
+						 0x06080040
+						 0x07000041
+						 0x07010042
+						 0x07020043
+						 0x07030044
+						 0x07040045
+						 0x07050046
+						 0x07060047
+						 0x07070048
+						 0x07080049
+						 0x0800004a
+						 0x0801004b
+						 0x0802004c
+						 0x0803004d
+						 0x0804004e
+						 0x0805004f
+						 0x08060050
+						 0x08070051
+						 0x08080052 >;
+			       autorepeat;
+			       st,mode = <0>;
+			       status = "okay";
+			};
+
+			rtc at e0580000 {
+			       status = "okay";
+			};
+
+			serial at e0000000 {
+			       status = "okay";
+			};
+
+			wdt at ec800620 {
+			       status = "okay";
+			};
+		};
+	};
+};
arch/arm/boot/dts/spear1310.dtsi new file +184 -0

184 lines not on this page · raw message

arch/arm/boot/dts/spear1340-evb.dts new file +291 -0

291 lines not on this page · raw message

arch/arm/boot/dts/spear1340.dtsi new file +56 -0

56 lines not on this page · raw message

arch/arm/boot/dts/spear13xx.dtsi new file +258 -0

258 lines not on this page · raw message

Signature · 1 line
1.7.9
#16 lore raw

PATCH 7/9 SPEAr13xx: Add compilation support

In reply to Viresh Kumar
---
 arch/arm/Makefile            |    2 ++
 arch/arm/plat-spear/Kconfig  |   12 ++++++++++++
 arch/arm/plat-spear/Makefile |    5 +++--
 3 files changed, 17 insertions(+), 2 deletions(-)
arch/arm/Makefile +2 -0
index a0c40a0..68d61ad 100644
@@ -190,6 +190,8 @@ machine-$(CONFIG_ARCH_VEXPRESS)		:= vexpress
 machine-$(CONFIG_ARCH_VT8500)		:= vt8500
 machine-$(CONFIG_ARCH_W90X900)		:= w90x900
 machine-$(CONFIG_FOOTBRIDGE)		:= footbridge
+machine-$(CONFIG_MACH_SPEAR1310)	:= spear13xx
+machine-$(CONFIG_MACH_SPEAR1340)	:= spear13xx
 machine-$(CONFIG_MACH_SPEAR300)		:= spear3xx
 machine-$(CONFIG_MACH_SPEAR310)		:= spear3xx
 machine-$(CONFIG_MACH_SPEAR320)		:= spear3xx
arch/arm/plat-spear/Kconfig +12 -0
index 387655b..4404f82 100644
@@ -8,6 +8,17 @@ choice
 	prompt "ST SPEAr Family"
 	default ARCH_SPEAR3XX
 
+config ARCH_SPEAR13XX
+	bool "ST SPEAr13xx with Device Tree"
+	select ARM_GIC
+	select CPU_V7
+	select USE_OF
+	select HAVE_SMP
+	select MIGHT_HAVE_CACHE_L2X0
+	select PINCTRL
+	help
+	  Supports for ARM's SPEAR13XX family
+
 config ARCH_SPEAR3XX
 	bool "ST SPEAr3xx with Device Tree"
 	select ARM_VIC
@@ -27,6 +38,7 @@ config ARCH_SPEAR6XX
 endchoice
 
 # Adding SPEAr machine specific configuration files
+source "arch/arm/mach-spear13xx/Kconfig"
 source "arch/arm/mach-spear3xx/Kconfig"
 source "arch/arm/mach-spear6xx/Kconfig"
 
arch/arm/plat-spear/Makefile +3 -2
index 38f1235..2607bd0 100644
@@ -3,6 +3,7 @@
 #
 
 # Common support
-obj-y	:= restart.o time.o pl080.o
+obj-y	:= restart.o time.o
 
-obj-$(CONFIG_ARCH_SPEAR3XX)	+= shirq.o
+obj-$(CONFIG_ARCH_SPEAR3XX)	+= pl080.o shirq.o
+obj-$(CONFIG_ARCH_SPEAR6XX)	+= pl080.o
Signature · 1 line
1.7.9
#17 lore raw

PATCH 8/9 SPEAr13xx: Add defconfig

In reply to Viresh Kumar
---
 arch/arm/configs/spear13xx_defconfig |   91 ++++++++++++++++++++++++++++++++++
 1 files changed, 91 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/configs/spear13xx_defconfig
arch/arm/configs/spear13xx_defconfig new file +91 -0
new file mode 100644
index 0000000..587d1f3
@@ -0,0 +1,91 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_PLAT_SPEAR=y
+CONFIG_ARCH_SPEAR13XX=y
+CONFIG_MACH_SPEAR1310=y
+CONFIG_MACH_SPEAR1340=y
+# CONFIG_SWP_EMULATE is not set
+CONFIG_SMP=y
+# CONFIG_SMP_ON_UP is not set
+# CONFIG_ARM_CPU_TOPOLOGY is not set
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_BINFMT_MISC=y
+CONFIG_NET=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_FSMC=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_ATA=y
+# CONFIG_SATA_PMP is not set
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_PATA_ARASAN_CF=y
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+CONFIG_STMMAC_ETH=y
+# CONFIG_WLAN is not set
+CONFIG_INPUT_FF_MEMLESS=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_SPEAR=y
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_RAW_DRIVER=y
+CONFIG_MAX_RAW_DEVS=8192
+CONFIG_I2C=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_PL061=y
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_MPCORE_WATCHDOG=y
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB=y
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SPEAR=y
+CONFIG_RTC_CLASS=y
+CONFIG_DMADEVICES=y
+CONFIG_DW_DMAC=y
+CONFIG_DMATEST=m
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_AUTOFS4_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+CONFIG_TMPFS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=m
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_INFO=y
Signature · 1 line
1.7.9
#18 lore raw

PATCH 9/9 SPEAr: Update MAINTAINERS and Documentation

In reply to Viresh Kumar

This patchset updates MAINTAINERS files, makes shiraz as second Maintainer for SPEAr SoCs.

It also updates Documentation mostly for SPEAr13xx.

---
 Documentation/arm/SPEAr/overview.txt            |   32 ++++++++++++----------
 Documentation/devicetree/bindings/arm/spear.txt |   14 +++++-----
 MAINTAINERS                                     |   13 +++++++++
 3 files changed, 37 insertions(+), 22 deletions(-)
Documentation/arm/SPEAr/overview.txt +17 -15
index 28a9af9..57aae77 100644
@@ -8,9 +8,8 @@ Introduction
   weblink : http://www.st.com/spear
 
   The ST Microelectronics SPEAr range of ARM9/CortexA9 System-on-Chip CPUs are
-  supported by the 'spear' platform of ARM Linux. Currently SPEAr300,
-  SPEAr310, SPEAr320 and SPEAr600 SOCs are supported. Support for the SPEAr13XX
-  series is in progress.
+  supported by the 'spear' platform of ARM Linux. Currently SPEAr1310,
+  SPEAr1340, SPEAr300, SPEAr310, SPEAr320 and SPEAr600 SOCs are supported.
 
   Hierarchy in SPEAr is as follows:
 
@@ -26,33 +25,36 @@ Introduction
 		- SPEAr600 (SOC)
 			- SPEAr600 Evaluation Board
 	- SPEAr13XX (13XX SOC series, based on ARM CORTEXA9)
-		- SPEAr1300 (SOC)
+		- SPEAr1310 (SOC)
+			- SPEAr1310 Evaluation Board
+		- SPEAr1340 (SOC)
+			- SPEAr1340 Evaluation Board
 
   Configuration
   -------------
 
   A generic configuration is provided for each machine, and can be used as the
   default by
-	make spear600_defconfig
-	make spear300_defconfig
-	make spear310_defconfig
-	make spear320_defconfig
+	make spear13xx_defconfig
+	make spear3xx_defconfig
+	make spear6xx_defconfig
 
   Layout
   ------
 
-  The common files for multiple machine families (SPEAr3XX, SPEAr6XX and
-  SPEAr13XX) are located in the platform code contained in arch/arm/plat-spear
+  The common files for multiple machine families (SPEAr3xx, SPEAr6xx and
+  SPEAr13xx) are located in the platform code contained in arch/arm/plat-spear
   with headers in plat/.
 
   Each machine series have a directory with name arch/arm/mach-spear followed by
   series name. Like mach-spear3xx, mach-spear6xx and mach-spear13xx.
 
-  Common file for machines of spear3xx family is mach-spear3xx/spear3xx.c and for
-  spear6xx is mach-spear6xx/spear6xx.c. mach-spear* also contain soc/machine
-  specific files, like spear300.c, spear310.c, spear320.c and spear600.c.
-  mach-spear* doesn't contains board specific files as they fully support
-  Flattened Device Tree.
+  Common file for machines of spear3xx family is mach-spear3xx/spear3xx.c, for
+  spear6xx is mach-spear6xx/spear6xx.c and for spear13xx family is
+  mach-spear13xx/spear13xx.c. mach-spear* also contain soc/machine specific
+  files, like spear1310.c, spear1340.c spear300.c, spear310.c, spear320.c and
+  spear600.c.  mach-spear* doesn't contains board specific files as they fully
+  support Flattened Device Tree.
 
 
   Document Author
Documentation/devicetree/bindings/arm/spear.txt +7 -7
index aa5f355..0d42949 100644
@@ -2,25 +2,25 @@ ST SPEAr Platforms Device Tree Bindings
 ---------------------------------------
 
 Boards with the ST SPEAr600 SoC shall have the following properties:
-
 Required root node property:
-
 compatible = "st,spear600";
 
 Boards with the ST SPEAr300 SoC shall have the following properties:
-
 Required root node property:
-
 compatible = "st,spear300";
 
 Boards with the ST SPEAr310 SoC shall have the following properties:
-
 Required root node property:
-
 compatible = "st,spear310";
 
 Boards with the ST SPEAr320 SoC shall have the following properties:
+Required root node property:
+compatible = "st,spear320";
 
+Boards with the ST SPEAr1310 SoC shall have the following properties:
 Required root node property:
+compatible = "st,spear1310";
 
-compatible = "st,spear320";
+Boards with the ST SPEAr1340 SoC shall have the following properties:
+Required root node property:
+compatible = "st,spear1340";
MAINTAINERS +13 -0
index 618d4fd..103d20a 100644
@@ -6285,14 +6285,25 @@ F:	include/linux/compiler.h
 
 SPEAR PLATFORM SUPPORT
 M:	Viresh Kumar <[email protected]>
+M:	Shiraz Hashim <[email protected]>
 L:	spear-devel at list.st.com
 L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
 W:	http://www.st.com/spear
 S:	Maintained
 F:	arch/arm/plat-spear/
 
+SPEAR13XX MACHINE SUPPORT
+M:	Viresh Kumar <[email protected]>
+M:	Shiraz Hashim <[email protected]>
+L:	spear-devel at list.st.com
+L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
+W:	http://www.st.com/spear
+S:	Maintained
+F:	arch/arm/mach-spear13xx/
+
 SPEAR3XX MACHINE SUPPORT
 M:	Viresh Kumar <[email protected]>
+M:	Shiraz Hashim <[email protected]>
 L:	spear-devel at list.st.com
 L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
 W:	http://www.st.com/spear
@@ -6301,6 +6312,8 @@ F:	arch/arm/mach-spear3xx/
 
 SPEAR6XX MACHINE SUPPORT
 M:	Rajeev Kumar <[email protected]>
+M:	Shiraz Hashim <[email protected]>
+M:	Viresh Kumar <[email protected]>
 L:	spear-devel at list.st.com
 L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
 W:	http://www.st.com/spear
Signature · 1 line
1.7.9
#19 lore raw

cover Add support for SPEAr13xx SoCs

In reply to Viresh Kumar
Quoted 7 lines · Viresh Kumar

Sorry for yet another patchset for you :(

This one adds in support for SPEAr1310 and SPEAr1340. It supports:
- DT probing
- pinctrl drivers
- common clock framework

Quoted 7 lines

All you requested to get this upstream. :)

I have CC-ed Linus and Mike for their patches and would ask them for their Acks, as this would evantually make through your ARM-SoC tree.

Few devices/drivers mentioned in dts files have their DT probing patches under review.

I've looked at all the platform specific bits and they look pretty good, great work! I have ignored the pinctrl and clock drivers and hope that the respective maintainers will be able to judge them well.

There are a few places where you still hardcode stuff that could be turned into device tree properties, but those are corner cases and you have an existing platform here that you've done a great amount of excellent cleanups to in the last weeks, so my feeling is that all the platform code can go in when you take care of the stuff that I've commented on, most of those things should be simple.

Arnd

#20 lore raw

cover Add support for SPEAr13xx SoCs

Quoted 10 lines · Arnd Bergmann

I've looked at all the platform specific bits and they look pretty good, great work! I have ignored the pinctrl and clock drivers and hope that the respective maintainers will be able to judge them well.

There are a few places where you still hardcode stuff that could be turned into device tree properties, but those are corner cases and you have an existing platform here that you've done a great amount of excellent cleanups to in the last weeks, so my feeling is that all the platform code can go in when you take care of the stuff that I've commented on, most of those things should be simple.

Have fixed most of stuff you pointed to. Check V2.

--
viresh

#21 lore raw

cover Add support for SPEAr13xx SoCs

Quoted 5 lines · viresh kumar
Quoted 4 lines · Arnd Bergmann

I've looked at all the platform specific bits and they look pretty good, great work! I have ignored the pinctrl and clock drivers and hope that the respective maintainers will be able to judge them well.

Quoted 9 lines
Quoted 6 lines

There are a few places where you still hardcode stuff that could be turned into device tree properties, but those are corner cases and you have an existing platform here that you've done a great amount of excellent cleanups to in the last weeks, so my feeling is that all the platform code can go in when you take care of the stuff that I've commented on, most of those things should be simple.

Have fixed most of stuff you pointed to. Check V2.

Wow, that was fast ;-)

Can you comment on the ones you did not address? In particular, I'd like to understand why you put the SPEAR1310_RAS_CTRL* register definitions into a globally visible header file.

Arnd

#22 lore raw

cover Add support for SPEAr13xx SoCs

Quoted 19 lines · Arnd Bergmann
Quoted 18 lines · viresh kumar
Quoted 16 lines · Arnd Bergmann

I've looked at all the platform specific bits and they look pretty good,
great work! I have ignored the pinctrl and clock drivers and hope that the
respective maintainers will be able to judge them well.

There are a few places where you still hardcode stuff that could be turned
into device tree properties, but those are corner cases and you have an existing platform here that you've done a great amount of excellent cleanups
to in the last weeks, so my feeling is that all the platform code can go in
when you take care of the stuff that I've commented on, most of those things
should be simple.

Quoted 4 lines
Quoted 2 lines

Have fixed most of stuff you pointed to. Check V2.

Wow, that was fast ;-)

Actually i should say it now:

Wow, that was too fast ;-)

Quoted 3 lines

Can you comment on the ones you did not address? In particular, I'd like to understand why you put the SPEAR1310_RAS_CTRL* register definitions into a globally visible header file.

I was replying to that mail only when you wrote this. Can check my reply there.

--
viresh