q35 qemu support
Subsystems (2)
v3 cover q35 qemu support
Hi,
Qemu bits for q35 support, I'm posting the seabios changes separately. The patches require '-M pc_q35' and -L 'seabios dir with q35 changes' on the qemu command line. Hopefully, we can make it the default for x86 at some future point when we feel comfortable with it.
The current patches have been tested with basic install testing and memory testing on f16, f17, windows 7 and windows 8. They can be run on the various BSD flavors by adding a 'piix4-ide' device to the pci bus. ie: -device piix4-ide. Patches have also been reported to work with a small dsdt change on OSX 10.6 as well.
I've dropped the ahci migration bits, which means q35 is not migratable at the moment. I simply haven't had time to make them more complete yet.
I'm hoping that we'll come to some agreement on the minimal functionality required for q35 to be merged.
Git trees:
git://github.com/jibaron/q35-qemu.gitgit://github.com/jibaron/q35-seabios.git
Notes:
I've dropped automatic load of the dsdt table on the piix for now. We can't pull this in until we have snapshot of the dsdt aml, and I wanted it to be done at a clean seabios freeze point (Although I guess that could be the current snapshot). I don't see the harm in pulling this in later though.
I've also gone to a model of the pci host being sparse:
00:00.0 Host bridge: Intel Corporation 82G33/G31/P35/P31 Express DRAM Controller
00:01.0 VGA compatible controller: Cirrus Logic GD 5446
00:02.0 Ethernet controller: Intel Corporation 82540EM Gigabit Ethernet Controller (rev 03) 00:1f.0 ISA bridge: Intel Corporation 82801IB (ICH9) LPC Interface Controller (rev 02) 00:1f.2 SATA controller: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller (rev 02) 00:1f.3 SMBus: Intel Corporation 82801I (ICH9 Family) SMBus Controller (rev 02)
The idea is only to populate the essential stuff at 1f, and have the rest filled out via command line options. In this way we have minimal bus configuration with 1 slot occupied as in piix. Should make things easier for libvirt. And this way user has complete control over things. For example, I have added support that when '-usb' is passed the usb controllers for ich9 are filled out.
Todo:
-add ahci migration back (need to cover more fields, but basically works) -add base addr for hpet in LPC device (for osx per agraf) -convert hotplug to use MemoryRegionPortio for hotplug (need an IsaDevice?)
Thanks,
-Jason
Changes from v2:
-Patch restructure (broke out ich9 chips + data structures separately) -added passthrough support
-add support for -usb to fill out host pci bus
-Dropped automatic load of dsdt table for piix
-cleanups
-dropped wmask on smbus (mst)
-sparse host bus
Changes from v1:
-Updated end of low mem from 0xe0000000 -> 0xb0000000 (Gerd Hoffmann)
-so 0xb000000-0xc000000 is memconfig
-0xc000000-0xfec00000 is 32-bit pci window -style/various cleanups
-introduced IF_AHCI
-introduced mach_if
-split dsdt out of bios, now passed for piix4 as well (Paolo, Gerd) -Removed add opaque argument to pci_map_irq_fn (Michael S. Tsirkin) -removed patches that were merged in v1
Isaku Yamahata (6):
pci: pci capability must be in PCI space
pci: introduce pci_swizzle_map_irq_fn() for standardized interrupt
pin swizzle
pc, pc_piix: split out pc nic initialization pc/piix_pci: factor out smram/pam logic
pci_ids: add intel 82801BA pci-to-pci bridge id
q35: Introduce q35 pc based chipset emulator
Jan Kiszka (5):
pci: Add class 0xc05 as 'SMBus'
q35: Suppress SMM BIOS initialization under KVM
q35: Fix non-PCI IRQ processing in ich9_lpc_update_apic
q35: smbus: Remove PCI_STATUS_SIG_SYSTEM_ERROR and
PCI_STATUS_DETECTED_PARITY from w1cmask
q35: Add kvmclock support
Jason Baron (15):
blockdev: Introduce a default machine blockdev interface field,
QEMUMachine->mach_if
blockdev: Introduce IF_AHCI
pc: Move ioapic_init() from pc_piix.c to pc.c
pcie: pass pcie window size to pcie_host_mmcfg_update()
pcie: Convert PCIExpressHost to use the QOM.
ich9: Add acpi support and definitions
ich9: Add the lpc chip
ich9: Add smbus
ich9: Add i82801b11 dmi-to-pci bridge
Add i21154 bridge chip.
Add a fallback bios file search, if -L fails.
q35: automatically load the q35 dsdt table
q35: add acpi-based pci hotplug.
q35: fill in usb pci slots with -usb
ich9: add support pci assignment
blockdev.c | 17 ++- blockdev.h | 21 ++ hw/Makefile.objs | 1 + hw/acpi_ich9.c | 492 +++++++++++++++++++++++++++++++++++++++++++ hw/acpi_ich9.h | 57 +++++ hw/boards.h | 2 +- hw/device-hotplug.c | 2 +- hw/highbank.c | 2 +- hw/i21154.c | 113 ++++++++++ hw/i21154.h | 9 + hw/i386/Makefile.objs | 2 + hw/i82801b11.c | 125 +++++++++++ hw/ich9.h | 211 +++++++++++++++++++ hw/ide.h | 6 + hw/ide/ahci.c | 18 ++ hw/ide/core.c | 23 ++- hw/leon3.c | 2 +- hw/lpc_ich9.c | 558 +++++++++++++++++++++++++++++++++++++++++++++++++ hw/mips_jazz.c | 4 +- hw/pam.c | 120 +++++++++++ hw/pam.h | 98 +++++++++ hw/pc.c | 58 +++++ hw/pc.h | 7 + hw/pc_piix.c | 38 +--- hw/pc_q35.c | 336 +++++++++++++++++++++++++++++ hw/pc_sysfw.c | 2 +- hw/pci.c | 25 ++- hw/pci.h | 2 + hw/pci_ids.h | 16 ++ hw/pcie_host.c | 35 +++- hw/pcie_host.h | 12 +- hw/piix_pci.c | 65 +----- hw/puv3.c | 2 +- hw/q35.c | 332 +++++++++++++++++++++++++++++ hw/q35.h | 161 ++++++++++++++ hw/realview.c | 6 +- hw/smbus_ich9.c | 163 ++++++++++++++ hw/spapr.c | 2 +- hw/sun4m.c | 24 +- hw/versatilepb.c | 4 +- hw/vexpress.c | 4 +- hw/xilinx_zynq.c | 2 +- vl.c | 56 ++++-- 43 files changed, 3074 insertions(+), 161 deletions(-) create mode 100644 hw/acpi_ich9.c create mode 100644 hw/acpi_ich9.h create mode 100644 hw/i21154.c create mode 100644 hw/i21154.h create mode 100644 hw/i82801b11.c create mode 100644 hw/ich9.h create mode 100644 hw/lpc_ich9.c create mode 100644 hw/pam.c create mode 100644 hw/pam.h create mode 100644 hw/pc_q35.c create mode 100644 hw/q35.c create mode 100644 hw/q35.h create mode 100644 hw/smbus_ich9.c
PATCH v3 1/26 blockdev: Introduce a default machine blockdev interface field, QEMUMachine->mach_if
From: Jason Baron <[email protected]>
The current QEMUMachine definition has a 'use_scsi' field to indicate if a machine type should use scsi by default. However, Q35 wants to use ahci by default. Thus, introdue a new field in the QEMUMachine defintion, mach_if.
This field should be initialized by the machine type to the default interface type which it wants to use (IF_SCSI, IF_AHCI, etc.). If no mach_if is defined, or it is set to 'IF_DEFAULT' or 'IF_NONE', we currently assume IF_IDE.
Please use 'static inline int get_mach_if(int mach_if)', when accesssing the new mach_if field.
--- blockdev.c | 4 ++-- blockdev.h | 19 +++++++++++++++++++ hw/boards.h | 2 +- hw/device-hotplug.c | 2 +- hw/highbank.c | 2 +- hw/leon3.c | 2 +- hw/mips_jazz.c | 4 ++-- hw/pc_sysfw.c | 2 +- hw/puv3.c | 2 +- hw/realview.c | 6 +++--- hw/spapr.c | 2 +- hw/sun4m.c | 24 ++++++++++++------------ hw/versatilepb.c | 4 ++-- hw/vexpress.c | 4 ++-- hw/xilinx_zynq.c | 2 +- vl.c | 20 +++++++++++--------- 16 files changed, 61 insertions(+), 40 deletions(-)
blockdev.c +2 -2
@@ -275,7 +275,7 @@ static bool do_check_io_limits(BlockIOLimit *io_limits)return true; } -DriveInfo *drive_init (QemuOpts *opts,int default_to_scsi) +DriveInfo *drive_init (QemuOpts *opts,int mach_if) {const char *buf;const char *file =NULL ;
@@ -325,7 +325,7 @@ DriveInfo *drive_init(QemuOpts *opts, int default_to_scsi)return NULL ; } }else { - type = default_to_scsi ?IF_SCSI :IF_IDE ; + type =get_mach_if (mach_if); } max_devs = if_max_devs[type];
blockdev.h +19 -0
@@ -40,6 +40,22 @@ struct DriveInfo {int refcount; }; +/* +* Each qemu machine type defines a mach_if field for its default +* interface type. If its unspecified, we set it to IF_IDE. +*/ +static inline int get_mach_if (int mach_if) +{ +assert (mach_if <IF_COUNT ); +assert (mach_if >=IF_DEFAULT ); + +if ((mach_if ==IF_NONE ) || (mach_if ==IF_DEFAULT )) { +return IF_IDE ; + } + +return mach_if; +} +DriveInfo *drive_get (BlockInterfaceType type,int bus,int unit);DriveInfo *drive_get_by_index (BlockInterfaceType type,int index);int drive_get_max_bus (BlockInterfaceType type);
@@ -61,4 +77,7 @@ void qmp_change_blockdev(const char *device, const char *filename, bool has_format, const char *format, Error **errp);void do_commit (Monitor *mon,const QDict *qdict);int do_drive_del (Monitor *mon,const QDict *qdict,QObject **ret_data); + + +#endif
hw/boards.h +1 -1
@@ -20,7 +20,7 @@ typedef struct QEMUMachine {const char *desc;QEMUMachineInitFunc *init;QEMUMachineResetFunc *reset; -int use_scsi; +int mach_if;int max_cpus; unsigned int no_serial:1, no_parallel:1,
hw/device-hotplug.c +1 -1
@@ -39,7 +39,7 @@ DriveInfo *add_init_drive(const char *optstr)if (!opts)return NULL ; - dinfo =drive_init (opts, current_machine->use_scsi); + dinfo =drive_init (opts, current_machine->mach_if);if (!dinfo) {qemu_opts_del (opts);return NULL ;
hw/highbank.c +1 -1
@@ -324,7 +324,7 @@ static QEMUMachine highbank_machine = { .name = "highbank", .desc = "Calxeda Highbank (ECX-1000)", .init = highbank_init, - .use_scsi = 1, + .mach_if = IF_SCSI, .max_cpus = 4, };
hw/leon3.c +1 -1
@@ -214,7 +214,7 @@ static QEMUMachine leon3_generic_machine = { .name = "leon3_generic", .desc = "Leon-3 generic", .init = leon3_generic_hw_init, - .use_scsi = 0, + .mach_if = IF_DEFAULT, };static void leon3_machine_init (void )
hw/mips_jazz.c +2 -2
@@ -325,14 +325,14 @@ static QEMUMachine mips_magnum_machine = { .name = "magnum", .desc = "MIPS Magnum", .init = mips_magnum_init, - .use_scsi = 1, + .mach_if = IF_SCSI, };static QEMUMachine mips_pica61_machine = { .name ="pica61" , .desc ="Acer Pica 61" , .init = mips_pica61_init, - .use_scsi =1 , + .mach_if =IF_SCSI , };static void mips_jazz_machine_init (void )
hw/pc_sysfw.c +1 -1
@@ -98,7 +98,7 @@ static void pc_fw_add_pflash_drv(void)return ; } -drive_init (opts, machine->use_scsi); +drive_init (opts, machine->mach_if); } static void pc_system_flash_init(MemoryRegion *rom_memory,
hw/puv3.c +1 -1
@@ -120,7 +120,7 @@ static QEMUMachine puv3_machine = { .desc = "PKUnity Version-3 based on UniCore32", .init = puv3_init, .is_default = 1, - .use_scsi = 0, + .mach_if = IF_DEFAULT, };static void puv3_machine_init (void )
hw/realview.c +3 -3
@@ -382,14 +382,14 @@ static QEMUMachine realview_eb_machine = { .name = "realview-eb", .desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)", .init = realview_eb_init, - .use_scsi = 1, + .mach_if = IF_SCSI, };static QEMUMachine realview_eb_mpcore_machine = { .name ="realview-eb-mpcore" , .desc ="ARM RealView Emulation Baseboard (ARM11MPCore)" , .init = realview_eb_mpcore_init, - .use_scsi =1 , + .mach_if =IF_SCSI , .max_cpus =4 , };
@@ -403,7 +403,7 @@ static QEMUMachine realview_pbx_a9_machine = { .name = "realview-pbx-a9", .desc = "ARM RealView Platform Baseboard Explore for Cortex-A9", .init = realview_pbx_a9_init, - .use_scsi = 1, + .mach_if = IF_SCSI, .max_cpus = 4, };
hw/spapr.c +1 -1
@@ -913,7 +913,7 @@ static QEMUMachine spapr_machine = { .reset = ppc_spapr_reset, .max_cpus = MAX_CPUS, .no_parallel = 1, - .use_scsi = 1, + .mach_if = IF_SCSI, };static void spapr_machine_init (void )
hw/sun4m.c +12 -12
@@ -1400,7 +1400,7 @@ static QEMUMachine ss5_machine = { .name = "SS-5", .desc = "Sun4m platform, SPARCstation 5", .init = ss5_init, - .use_scsi = 1, + .mach_if = IF_SCSI, .is_default = 1, };
@@ -1408,7 +1408,7 @@ static QEMUMachine ss10_machine = { .name = "SS-10", .desc = "Sun4m platform, SPARCstation 10", .init = ss10_init, - .use_scsi = 1, + .mach_if = IF_SCSI, .max_cpus = 4, };
@@ -1416,7 +1416,7 @@ static QEMUMachine ss600mp_machine = { .name = "SS-600MP", .desc = "Sun4m platform, SPARCserver 600MP", .init = ss600mp_init, - .use_scsi = 1, + .mach_if = IF_SCSI, .max_cpus = 4, };
@@ -1424,7 +1424,7 @@ static QEMUMachine ss20_machine = { .name = "SS-20", .desc = "Sun4m platform, SPARCstation 20", .init = ss20_init, - .use_scsi = 1, + .mach_if = IF_SCSI, .max_cpus = 4, };
@@ -1432,35 +1432,35 @@ static QEMUMachine voyager_machine = { .name = "Voyager", .desc = "Sun4m platform, SPARCstation Voyager", .init = vger_init, - .use_scsi = 1, + .mach_if = IF_SCSI, };static QEMUMachine ss_lx_machine = { .name ="LX" , .desc ="Sun4m platform, SPARCstation LX" , .init = ss_lx_init, - .use_scsi =1 , + .mach_if =IF_SCSI , };static QEMUMachine ss4_machine = { .name ="SS-4" , .desc ="Sun4m platform, SPARCstation 4" , .init = ss4_init, - .use_scsi =1 , + .mach_if =IF_SCSI , };static QEMUMachine scls_machine = { .name ="SPARCClassic" , .desc ="Sun4m platform, SPARCClassic" , .init = scls_init, - .use_scsi =1 , + .mach_if =IF_SCSI , };static QEMUMachine sbook_machine = { .name ="SPARCbook" , .desc ="Sun4m platform, SPARCbook" , .init = sbook_init, - .use_scsi =1 , + .mach_if =IF_SCSI , };static const struct sun4d_hwdef sun4d_hwdefs[] = {
@@ -1677,7 +1677,7 @@ static QEMUMachine ss1000_machine = { .name = "SS-1000", .desc = "Sun4d platform, SPARCserver 1000", .init = ss1000_init, - .use_scsi = 1, + .mach_if = IF_SCSI, .max_cpus = 8, };
@@ -1685,7 +1685,7 @@ static QEMUMachine ss2000_machine = { .name = "SS-2000", .desc = "Sun4d platform, SPARCcenter 2000", .init = ss2000_init, - .use_scsi = 1, + .mach_if = IF_SCSI, .max_cpus = 20, };
@@ -1861,7 +1861,7 @@ static QEMUMachine ss2_machine = { .name = "SS-2", .desc = "Sun4c platform, SPARCstation 2", .init = ss2_init, - .use_scsi = 1, + .mach_if = IF_SCSI, };static void sun4m_register_types (void )
hw/versatilepb.c +2 -2
@@ -374,14 +374,14 @@ static QEMUMachine versatilepb_machine = { .name = "versatilepb", .desc = "ARM Versatile/PB (ARM926EJ-S)", .init = vpb_init, - .use_scsi = 1, + .mach_if = IF_SCSI, };static QEMUMachine versatileab_machine = { .name ="versatileab" , .desc ="ARM Versatile/AB (ARM926EJ-S)" , .init = vab_init, - .use_scsi =1 , + .mach_if =IF_SCSI , };static void versatile_machine_init (void )
hw/vexpress.c +2 -2
@@ -495,7 +495,7 @@ static QEMUMachine vexpress_a9_machine = { .name = "vexpress-a9", .desc = "ARM Versatile Express for Cortex-A9", .init = vexpress_a9_init, - .use_scsi = 1, + .mach_if = IF_SCSI, .max_cpus = 4, };
@@ -503,7 +503,7 @@ static QEMUMachine vexpress_a15_machine = { .name = "vexpress-a15", .desc = "ARM Versatile Express for Cortex-A15", .init = vexpress_a15_init, - .use_scsi = 1, + .mach_if = IF_SCSI, .max_cpus = 4, };
hw/xilinx_zynq.c +1 -1
@@ -178,7 +178,7 @@ static QEMUMachine zynq_machine = { .name = "xilinx-zynq-a9", .desc = "Xilinx Zynq Platform Baseboard for Cortex-A9", .init = zynq_init, - .use_scsi = 1, + .if_default = IF_SCSI, .max_cpus = 1, .no_sdcard = 1 };
vl.c +11 -9
@@ -802,9 +802,9 @@ static int parse_sandbox(QemuOpts *opts, void *opaque)static int drive_init_func (QemuOpts *opts,void *opaque) { -int *use_scsi = opaque; +int *mach_if = opaque; -return drive_init (opts, *use_scsi) ==NULL ; +return drive_init (opts, *mach_if) ==NULL ; }static int drive_enable_snapshot (QemuOpts *opts,void *opaque)
@@ -815,14 +815,14 @@ static int drive_enable_snapshot(QemuOpts *opts, void *opaque)return 0 ; } -static void default_drive (int enable,int snapshot,int use_scsi, +static void default_drive (int enable,int snapshot,int mach_if,BlockInterfaceType type,int index,const char *optstr) {QemuOpts *opts;if (type ==IF_DEFAULT ) { - type = use_scsi ?IF_SCSI :IF_IDE ; + type =get_mach_if (mach_if); }if (!enable ||drive_get_by_index (type, index)) {
@@ -833,7 +833,7 @@ static void default_drive(int enable, int snapshot, int use_scsi,if (snapshot) {drive_enable_snapshot (opts,NULL ); } -if (!drive_init (opts, use_scsi)) { +if (!drive_init (opts, mach_if)) {exit (1 ); } }
@@ -3547,14 +3547,16 @@ int main(int argc, char **argv, char **envp)/* open the virtual block devices */ if (snapshot)qemu_opts_foreach (qemu_find_opts ("drive" ), drive_enable_snapshot,NULL ,0 ); -if (qemu_opts_foreach (qemu_find_opts ("drive" ), drive_init_func, &machine->use_scsi,1 ) !=0 ) +if (qemu_opts_foreach (qemu_find_opts ("drive" ), drive_init_func, + &machine->mach_if,1 ) !=0 ) {exit (1 ); + } -default_drive (default_cdrom, snapshot, machine->use_scsi, +default_drive (default_cdrom, snapshot, machine->mach_if,IF_DEFAULT ,2 ,CDROM_OPTS ); -default_drive (default_floppy, snapshot, machine->use_scsi, +default_drive (default_floppy, snapshot, machine->mach_if,IF_FLOPPY ,0 ,FD_OPTS ); -default_drive (default_sdcard, snapshot, machine->use_scsi, +default_drive (default_sdcard, snapshot, machine->mach_if,IF_SD ,0 ,SD_OPTS );register_savevm_live (NULL ,"ram" ,0 ,4 , &savevm_ram_handlers,NULL );
Signature · 1 line
1.7.1
Re: [Qemu-devel] [PATCH v3 01/26] blockdev: Introduce a default machine blockdev interface field, QEMUMachine->mach_if
Quoted 10 lines · Jason Baron
From: Jason Baron <[email protected]>
The current QEMUMachine definition has a '
use_scsi' field to indicate if a machine type should use scsi by default. However, Q35 wants to use ahci by default. Thus, introdue a new field in the QEMUMachine defintion,mach_if.This field should be initialized by the machine type to the default interface type which it wants to use (
IF_SCSI,IF_AHCI, etc.). If nomach_ifis defined, or it is set to 'IF_DEFAULT' or 'IF_NONE', we currently assumeIF_IDE.
Quoted 5 lines
Please use 'static inline int
get_mach_if(int mach_if)', when accesssing the newmach_iffield.Reviewed-by Paolo Bonzini <[email protected]>Signed-off-by Jason Baron <[email protected]>
Kevin, could you review/ack this patch pls?
Quoted 447 lines
--- blockdev.c | 4 ++-- blockdev.h | 19 +++++++++++++++++++ hw/boards.h | 2 +- hw/device-hotplug.c | 2 +- hw/highbank.c | 2 +- hw/leon3.c | 2 +- hw/mips_jazz.c | 4 ++-- hw/pc_sysfw.c | 2 +- hw/puv3.c | 2 +- hw/realview.c | 6 +++--- hw/spapr.c | 2 +- hw/sun4m.c | 24 ++++++++++++------------ hw/versatilepb.c | 4 ++-- hw/vexpress.c | 4 ++-- hw/xilinx_zynq.c | 2 +- vl.c | 20 +++++++++++--------- 16 files changed, 61 insertions(+), 40 deletions(-)blockdev.c +2
-2@@ -275,7 +275,7 @@ static bool do_check_io_limits(BlockIOLimit *io_limits)return true; } -DriveInfo *drive_init (QemuOpts *opts,int default_to_scsi) +DriveInfo *drive_init (QemuOpts *opts,int mach_if) {const char *buf;const char *file =NULL ;@@ -325,7 +325,7 @@ DriveInfo *drive_init(QemuOpts *opts, int default_to_scsi)return NULL ; } }else { - type = default_to_scsi ?IF_SCSI :IF_IDE ; + type =get_mach_if (mach_if); } max_devs = if_max_devs[type];blockdev.h +19
-0@@ -40,6 +40,22 @@ struct DriveInfo {int refcount; }; +/* +* Each qemu machine type defines a mach_if field for its default +* interface type. If its unspecified, we set it to IF_IDE. +*/ +static inline int get_mach_if (int mach_if) +{ +assert (mach_if <IF_COUNT ); +assert (mach_if >=IF_DEFAULT ); + +if ((mach_if ==IF_NONE ) || (mach_if ==IF_DEFAULT )) { +return IF_IDE ; + } + +return mach_if; +} +DriveInfo *drive_get (BlockInterfaceType type,int bus,int unit);DriveInfo *drive_get_by_index (BlockInterfaceType type,int index);int drive_get_max_bus (BlockInterfaceType type);@@ -61,4 +77,7 @@ void qmp_change_blockdev(const char *device, const char *filename, bool has_format, const char *format, Error **errp);void do_commit (Monitor *mon,const QDict *qdict);int do_drive_del (Monitor *mon,const QDict *qdict,QObject **ret_data); + + +#endif hw/boards.h +1
-1@@ -20,7 +20,7 @@ typedef struct QEMUMachine {const char *desc;QEMUMachineInitFunc *init;QEMUMachineResetFunc *reset; -int use_scsi; +int mach_if;int max_cpus; unsigned int no_serial:1, no_parallel:1,hw/device-hotplug.c +1
-1@@ -39,7 +39,7 @@ DriveInfo *add_init_drive(const char *optstr)if (!opts)return NULL ; - dinfo =drive_init (opts, current_machine->use_scsi); + dinfo =drive_init (opts, current_machine->mach_if);if (!dinfo) {qemu_opts_del (opts);return NULL ;hw/highbank.c +1
-1@@ -324,7 +324,7 @@ static QEMUMachine highbank_machine = { .name = "highbank", .desc = "Calxeda Highbank (ECX-1000)", .init = highbank_init, - .use_scsi = 1, + .mach_if = IF_SCSI, .max_cpus = 4, };hw/leon3.c +1
-1@@ -214,7 +214,7 @@ static QEMUMachine leon3_generic_machine = { .name = "leon3_generic", .desc = "Leon-3 generic", .init = leon3_generic_hw_init, - .use_scsi = 0, + .mach_if = IF_DEFAULT, };static void leon3_machine_init (void )hw/mips_jazz.c +2
-2@@ -325,14 +325,14 @@ static QEMUMachine mips_magnum_machine = { .name = "magnum", .desc = "MIPS Magnum", .init = mips_magnum_init, - .use_scsi = 1, + .mach_if = IF_SCSI, };static QEMUMachine mips_pica61_machine = { .name ="pica61" , .desc ="Acer Pica 61" , .init = mips_pica61_init, - .use_scsi =1 , + .mach_if =IF_SCSI , };static void mips_jazz_machine_init (void )hw/pc_sysfw.c +1
-1@@ -98,7 +98,7 @@ static void pc_fw_add_pflash_drv(void)return ; } -drive_init (opts, machine->use_scsi); +drive_init (opts, machine->mach_if); } static void pc_system_flash_init(MemoryRegion *rom_memory,hw/puv3.c +1
-1@@ -120,7 +120,7 @@ static QEMUMachine puv3_machine = { .desc = "PKUnity Version-3 based on UniCore32", .init = puv3_init, .is_default = 1, - .use_scsi = 0, + .mach_if = IF_DEFAULT, };static void puv3_machine_init (void )hw/realview.c +3
-3@@ -382,14 +382,14 @@ static QEMUMachine realview_eb_machine = { .name = "realview-eb", .desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)", .init = realview_eb_init, - .use_scsi = 1, + .mach_if = IF_SCSI, };static QEMUMachine realview_eb_mpcore_machine = { .name ="realview-eb-mpcore" , .desc ="ARM RealView Emulation Baseboard (ARM11MPCore)" , .init = realview_eb_mpcore_init, - .use_scsi =1 , + .mach_if =IF_SCSI , .max_cpus =4 , };@@ -403,7 +403,7 @@ static QEMUMachine realview_pbx_a9_machine = { .name = "realview-pbx-a9", .desc = "ARM RealView Platform Baseboard Explore for Cortex-A9", .init = realview_pbx_a9_init, - .use_scsi = 1, + .mach_if = IF_SCSI, .max_cpus = 4, };hw/spapr.c +1
-1@@ -913,7 +913,7 @@ static QEMUMachine spapr_machine = { .reset = ppc_spapr_reset, .max_cpus = MAX_CPUS, .no_parallel = 1, - .use_scsi = 1, + .mach_if = IF_SCSI, };static void spapr_machine_init (void )hw/sun4m.c +12
-12@@ -1400,7 +1400,7 @@ static QEMUMachine ss5_machine = { .name = "SS-5", .desc = "Sun4m platform, SPARCstation 5", .init = ss5_init, - .use_scsi = 1, + .mach_if = IF_SCSI, .is_default = 1, };@@ -1408,7 +1408,7 @@ static QEMUMachine ss10_machine = { .name = "SS-10", .desc = "Sun4m platform, SPARCstation 10", .init = ss10_init, - .use_scsi = 1, + .mach_if = IF_SCSI, .max_cpus = 4, };@@ -1416,7 +1416,7 @@ static QEMUMachine ss600mp_machine = { .name = "SS-600MP", .desc = "Sun4m platform, SPARCserver 600MP", .init = ss600mp_init, - .use_scsi = 1, + .mach_if = IF_SCSI, .max_cpus = 4, };@@ -1424,7 +1424,7 @@ static QEMUMachine ss20_machine = { .name = "SS-20", .desc = "Sun4m platform, SPARCstation 20", .init = ss20_init, - .use_scsi = 1, + .mach_if = IF_SCSI, .max_cpus = 4, };@@ -1432,35 +1432,35 @@ static QEMUMachine voyager_machine = { .name = "Voyager", .desc = "Sun4m platform, SPARCstation Voyager", .init = vger_init, - .use_scsi = 1, + .mach_if = IF_SCSI, };static QEMUMachine ss_lx_machine = { .name ="LX" , .desc ="Sun4m platform, SPARCstation LX" , .init = ss_lx_init, - .use_scsi =1 , + .mach_if =IF_SCSI , };static QEMUMachine ss4_machine = { .name ="SS-4" , .desc ="Sun4m platform, SPARCstation 4" , .init = ss4_init, - .use_scsi =1 , + .mach_if =IF_SCSI , };static QEMUMachine scls_machine = { .name ="SPARCClassic" , .desc ="Sun4m platform, SPARCClassic" , .init = scls_init, - .use_scsi =1 , + .mach_if =IF_SCSI , };static QEMUMachine sbook_machine = { .name ="SPARCbook" , .desc ="Sun4m platform, SPARCbook" , .init = sbook_init, - .use_scsi =1 , + .mach_if =IF_SCSI , };static const struct sun4d_hwdef sun4d_hwdefs[] = {@@ -1677,7 +1677,7 @@ static QEMUMachine ss1000_machine = { .name = "SS-1000", .desc = "Sun4d platform, SPARCserver 1000", .init = ss1000_init, - .use_scsi = 1, + .mach_if = IF_SCSI, .max_cpus = 8, };@@ -1685,7 +1685,7 @@ static QEMUMachine ss2000_machine = { .name = "SS-2000", .desc = "Sun4d platform, SPARCcenter 2000", .init = ss2000_init, - .use_scsi = 1, + .mach_if = IF_SCSI, .max_cpus = 20, };@@ -1861,7 +1861,7 @@ static QEMUMachine ss2_machine = { .name = "SS-2", .desc = "Sun4c platform, SPARCstation 2", .init = ss2_init, - .use_scsi = 1, + .mach_if = IF_SCSI, };static void sun4m_register_types (void )hw/versatilepb.c +2
-2@@ -374,14 +374,14 @@ static QEMUMachine versatilepb_machine = { .name = "versatilepb", .desc = "ARM Versatile/PB (ARM926EJ-S)", .init = vpb_init, - .use_scsi = 1, + .mach_if = IF_SCSI, };static QEMUMachine versatileab_machine = { .name ="versatileab" , .desc ="ARM Versatile/AB (ARM926EJ-S)" , .init = vab_init, - .use_scsi =1 , + .mach_if =IF_SCSI , };static void versatile_machine_init (void )hw/vexpress.c +2
-2@@ -495,7 +495,7 @@ static QEMUMachine vexpress_a9_machine = { .name = "vexpress-a9", .desc = "ARM Versatile Express for Cortex-A9", .init = vexpress_a9_init, - .use_scsi = 1, + .mach_if = IF_SCSI, .max_cpus = 4, };@@ -503,7 +503,7 @@ static QEMUMachine vexpress_a15_machine = { .name = "vexpress-a15", .desc = "ARM Versatile Express for Cortex-A15", .init = vexpress_a15_init, - .use_scsi = 1, + .mach_if = IF_SCSI, .max_cpus = 4, };hw/xilinx_zynq.c +1
-1@@ -178,7 +178,7 @@ static QEMUMachine zynq_machine = { .name = "xilinx-zynq-a9", .desc = "Xilinx Zynq Platform Baseboard for Cortex-A9", .init = zynq_init, - .use_scsi = 1, + .if_default = IF_SCSI, .max_cpus = 1, .no_sdcard = 1 };vl.c +11
-9@@ -802,9 +802,9 @@ static int parse_sandbox(QemuOpts *opts, void *opaque)static int drive_init_func (QemuOpts *opts,void *opaque) { -int *use_scsi = opaque; +int *mach_if = opaque; -return drive_init (opts, *use_scsi) ==NULL ; +return drive_init (opts, *mach_if) ==NULL ; }static int drive_enable_snapshot (QemuOpts *opts,void *opaque)@@ -815,14 +815,14 @@ static int drive_enable_snapshot(QemuOpts *opts, void *opaque)return 0 ; } -static void default_drive (int enable,int snapshot,int use_scsi, +static void default_drive (int enable,int snapshot,int mach_if,BlockInterfaceType type,int index,const char *optstr) {QemuOpts *opts;if (type ==IF_DEFAULT ) { - type = use_scsi ?IF_SCSI :IF_IDE ; + type =get_mach_if (mach_if); }if (!enable ||drive_get_by_index (type, index)) {@@ -833,7 +833,7 @@ static void default_drive(int enable, int snapshot, int use_scsi,if (snapshot) {drive_enable_snapshot (opts,NULL ); } -if (!drive_init (opts, use_scsi)) { +if (!drive_init (opts, mach_if)) {exit (1 ); } }@@ -3547,14 +3547,16 @@ int main(int argc, char **argv, char **envp)/* open the virtual block devices */ if (snapshot)qemu_opts_foreach (qemu_find_opts ("drive" ), drive_enable_snapshot,NULL ,0 ); -if (qemu_opts_foreach (qemu_find_opts ("drive" ), drive_init_func, &machine->use_scsi,1 ) !=0 ) +if (qemu_opts_foreach (qemu_find_opts ("drive" ), drive_init_func, + &machine->mach_if,1 ) !=0 ) {exit (1 ); + } -default_drive (default_cdrom, snapshot, machine->use_scsi, +default_drive (default_cdrom, snapshot, machine->mach_if,IF_DEFAULT ,2 ,CDROM_OPTS ); -default_drive (default_floppy, snapshot, machine->use_scsi, +default_drive (default_floppy, snapshot, machine->mach_if,IF_FLOPPY ,0 ,FD_OPTS ); -default_drive (default_sdcard, snapshot, machine->use_scsi, +default_drive (default_sdcard, snapshot, machine->mach_if,IF_SD ,0 ,SD_OPTS );register_savevm_live (NULL ,"ram" ,0 ,4 , &savevm_ram_handlers,NULL );Signature · 1 line
1.7.1
Re: [Qemu-devel] [PATCH v3 01/26] blockdev: Introduce a default machine blockdev interface field, QEMUMachine->mach_if
Am 22.10.2012 12:47, schrieb Michael S. Tsirkin:
Quoted 10 lines · Jason Baron
Quoted 9 lines
From: Jason Baron <[email protected]>
The current QEMUMachine definition has a '
use_scsi' field to indicate if a machine type should use scsi by default. However, Q35 wants to use ahci by default. Thus, introdue a new field in the QEMUMachine defintion,mach_if.This field should be initialized by the machine type to the default interface type which it wants to use (
IF_SCSI,IF_AHCI, etc.). If nomach_ifis defined, or it is set to 'IF_DEFAULT' or 'IF_NONE', we currently assumeIF_IDE.
Is this default mechanism necessary? Can't we make sure that each machine does define its preferred interface, and doesn't define it as IF_DEFAULT (which would be the same as an explicit IF_IDE anyway)?
Also, 'mach_if' isn't a very descriptive name. Something like 'default_drive_if' would be better.
Quoted 35 lines
Quoted 5 lines
Please use 'static inline int
get_mach_if(int mach_if)', when accesssing the newmach_iffield.Reviewed-by Paolo Bonzini <[email protected]>Signed-off-by Jason Baron <[email protected]>Kevin, could you review/ack this patch pls?
Quoted 27 lines
--- blockdev.c | 4 ++-- blockdev.h | 19 +++++++++++++++++++ hw/boards.h | 2 +- hw/device-hotplug.c | 2 +- hw/highbank.c | 2 +- hw/leon3.c | 2 +- hw/mips_jazz.c | 4 ++-- hw/pc_sysfw.c | 2 +- hw/puv3.c | 2 +- hw/realview.c | 6 +++--- hw/spapr.c | 2 +- hw/sun4m.c | 24 ++++++++++++------------ hw/versatilepb.c | 4 ++-- hw/vexpress.c | 4 ++-- hw/xilinx_zynq.c | 2 +- vl.c | 20 +++++++++++--------- 16 files changed, 61 insertions(+), 40 deletions(-)blockdev.c +0
-0@@ -275,7 +275,7 @@ static bool do_check_io_limits(BlockIOLimit *io_limits)return true; }
Quoted 2 lines
blockdev.c static bool do_check_io_limits(BlockIOLimit *io_limits) · line 278
Quoted 2 lines
blockdev.c +1
-1-DriveInfo *drive_init (QemuOpts *opts,int default_to_scsi) +DriveInfo *drive_init (QemuOpts *opts,int mach_if)
BlockInterfaceType, not int.
Quoted 49 lines
Quoted 49 lines
blockdev.c +1
-1{const char *buf;const char *file =NULL ;@@ -325,7 +325,7 @@ DriveInfo *drive_init(QemuOpts *opts, int default_to_scsi)return NULL ; } }else { - type = default_to_scsi ?IF_SCSI :IF_IDE ; + type =get_mach_if (mach_if); } max_devs = if_max_devs[type];blockdev.h +19
-0@@ -40,6 +40,22 @@ struct DriveInfo {int refcount; }; +/* +* Each qemu machine type defines a mach_if field for its default +* interface type. If its unspecified, we set it to IF_IDE. +*/ +static inline int get_mach_if (int mach_if) +{ +assert (mach_if <IF_COUNT ); +assert (mach_if >=IF_DEFAULT ); + +if ((mach_if ==IF_NONE ) || (mach_if ==IF_DEFAULT )) { +return IF_IDE ; + } + +return mach_if; +} +DriveInfo *drive_get (BlockInterfaceType type,int bus,int unit);DriveInfo *drive_get_by_index (BlockInterfaceType type,int index);int drive_get_max_bus (BlockInterfaceType type);@@ -61,4 +77,7 @@ void qmp_change_blockdev(const char *device, const char *filename, bool has_format, const char *format, Error **errp);void do_commit (Monitor *mon,const QDict *qdict);int do_drive_del (Monitor *mon,const QDict *qdict,QObject **ret_data); + + +#endif hw/boards.h +0
-0
Quoted 8 lines
hw/boards.h typedef struct QEMUMachine { · line 23
Quoted 8 lines
hw/boards.h +1
-1@@ -20,7 +20,7 @@ typedef struct QEMUMachine {const char *desc;QEMUMachineInitFunc *init;QEMUMachineResetFunc *reset; -int use_scsi; +int mach_if;
Same here.
Kevin
Re: [Qemu-devel] [PATCH v3 01/26] blockdev: Introduce a default machine blockdev interface field, QEMUMachine->mach_if
Quoted 8 lines · Kevin Wolf
Am 22.10.2012 12:47, schrieb Michael S. Tsirkin:
Quoted 7 lines · Jason Baron
Quoted 6 lines
From: Jason Baron <[email protected]>
The current QEMUMachine definition has a '
use_scsi' field to indicate if a machine type should use scsi by default. However, Q35 wants to use ahci by default. Thus, introdue a new field in the QEMUMachine defintion,mach_if.
Quoted 8 lines
Quoted 3 lines
Quoted 3 lines
This field should be initialized by the machine type to the default interface type which it wants to use (
IF_SCSI,IF_AHCI, etc.). If nomach_ifis defined, or it is set to 'IF_DEFAULT' or 'IF_NONE', we currently assumeIF_IDE.Is this default mechanism necessary? Can't we make sure that each machine does define its preferred interface, and doesn't define it as
IF_DEFAULT(which would be the same as an explicitIF_IDEanyway)?
IF_NONE is currently defined as 0, so I wanted to make sure that any machine types that didn't explicity define the 'mach_if' field would be mapped to IF_IDE. If you don't like having 'IF_DEFAULT' there, I can simply drop 2 'IF_DEFAULT' settings that I had. Would that be ok with you?
Quoted 3 lines
Also, '
mach_if' isn't a very descriptive name. Something like 'default_drive_if' would be better.
ok, will update.
Quoted 35 lines
Quoted 35 lines
Quoted 5 lines
Please use 'static inline int
get_mach_if(int mach_if)', when accesssing the newmach_iffield.Reviewed-by Paolo Bonzini <[email protected]>Signed-off-by Jason Baron <[email protected]>Kevin, could you review/ack this patch pls?
Quoted 27 lines
--- blockdev.c | 4 ++-- blockdev.h | 19 +++++++++++++++++++ hw/boards.h | 2 +- hw/device-hotplug.c | 2 +- hw/highbank.c | 2 +- hw/leon3.c | 2 +- hw/mips_jazz.c | 4 ++-- hw/pc_sysfw.c | 2 +- hw/puv3.c | 2 +- hw/realview.c | 6 +++--- hw/spapr.c | 2 +- hw/sun4m.c | 24 ++++++++++++------------ hw/versatilepb.c | 4 ++-- hw/vexpress.c | 4 ++-- hw/xilinx_zynq.c | 2 +- vl.c | 20 +++++++++++--------- 16 files changed, 61 insertions(+), 40 deletions(-)blockdev.c +0
-0@@ -275,7 +275,7 @@ static bool do_check_io_limits(BlockIOLimit *io_limits)return true; }
Quoted 5 lines
Quoted 2 lines
blockdev.c static bool do_check_io_limits(BlockIOLimit *io_limits) · line 278
Quoted 2 lines
blockdev.c +1
-1-DriveInfo *drive_init (QemuOpts *opts,int default_to_scsi) +DriveInfo *drive_init (QemuOpts *opts,int mach_if)BlockInterfaceType, not int.
ok.
Quoted 60 lines
Quoted 49 lines
Quoted 49 lines
blockdev.c +1
-1{const char *buf;const char *file =NULL ;@@ -325,7 +325,7 @@ DriveInfo *drive_init(QemuOpts *opts, int default_to_scsi)return NULL ; } }else { - type = default_to_scsi ?IF_SCSI :IF_IDE ; + type =get_mach_if (mach_if); } max_devs = if_max_devs[type];blockdev.h +19
-0@@ -40,6 +40,22 @@ struct DriveInfo {int refcount; }; +/* +* Each qemu machine type defines a mach_if field for its default +* interface type. If its unspecified, we set it to IF_IDE. +*/ +static inline int get_mach_if (int mach_if) +{ +assert (mach_if <IF_COUNT ); +assert (mach_if >=IF_DEFAULT ); + +if ((mach_if ==IF_NONE ) || (mach_if ==IF_DEFAULT )) { +return IF_IDE ; + } + +return mach_if; +} +DriveInfo *drive_get (BlockInterfaceType type,int bus,int unit);DriveInfo *drive_get_by_index (BlockInterfaceType type,int index);int drive_get_max_bus (BlockInterfaceType type);@@ -61,4 +77,7 @@ void qmp_change_blockdev(const char *device, const char *filename, bool has_format, const char *format, Error **errp);void do_commit (Monitor *mon,const QDict *qdict);int do_drive_del (Monitor *mon,const QDict *qdict,QObject **ret_data); + + +#endif hw/boards.h +0
-0Quoted 8 lines
hw/boards.h typedef struct QEMUMachine { · line 23
Quoted 8 lines
hw/boards.h +1
-1@@ -20,7 +20,7 @@ typedef struct QEMUMachine {const char *desc;QEMUMachineInitFunc *init;QEMUMachineResetFunc *reset; -int use_scsi; +int mach_if;Same here.
Quoted 1 line
Kevin
ok.
Thanks,
-Jason
Re: [Qemu-devel] [PATCH v3 01/26] blockdev: Introduce a default machine blockdev interface field, QEMUMachine->mach_if
In reply to Jason BaronQuoted 5 lines · Jason Baron
From: Jason Baron <[email protected]>
The current QEMUMachine definition has a '
use_scsi' field to indicate if a machine type should use scsi by default. However, Q35 wants to use ahci by default. Thus, introdue a new field in the QEMUMachine defintion,mach_if.
Even though q35's desire to default to IF_AHCI is driving this patch, generalizing the default interface type makes sense on its own. Even if we IF_AHCI should turn out to need more discussion.
Quoted 33 lines
This field should be initialized by the machine type to the default interface type which it wants to use (
IF_SCSI,IF_AHCI, etc.). If nomach_ifis defined, or it is set to 'IF_DEFAULT' or 'IF_NONE', we currently assumeIF_IDE.Please use 'static inline int
get_mach_if(int mach_if)', when accesssing the newmach_iffield.Reviewed-by Paolo Bonzini <[email protected]>Signed-off-by Jason Baron <[email protected]>--- blockdev.c | 4 ++-- blockdev.h | 19 +++++++++++++++++++ hw/boards.h | 2 +- hw/device-hotplug.c | 2 +- hw/highbank.c | 2 +- hw/leon3.c | 2 +- hw/mips_jazz.c | 4 ++-- hw/pc_sysfw.c | 2 +- hw/puv3.c | 2 +- hw/realview.c | 6 +++--- hw/spapr.c | 2 +- hw/sun4m.c | 24 ++++++++++++------------ hw/versatilepb.c | 4 ++-- hw/vexpress.c | 4 ++-- hw/xilinx_zynq.c | 2 +- vl.c | 20 +++++++++++--------- 16 files changed, 61 insertions(+), 40 deletions(-)blockdev.c +0
-0
blockdev.c static bool do_check_io_limits(BlockIOLimit *io_limits) · line 278
Quoted 5 lines
blockdev.c +1
-1@@ -275,7 +275,7 @@ static bool do_check_io_limits(BlockIOLimit *io_limits)return true; } -DriveInfo *drive_init (QemuOpts *opts,int default_to_scsi) +DriveInfo *drive_init (QemuOpts *opts,int mach_if)
BlockInterfaceType mach_if
Suggest to rename mach_if to something more descriptive. Kevin's default_drive_if works for me.
Quoted 17 lines
blockdev.c +1
-1{const char *buf;const char *file =NULL ;@@ -325,7 +325,7 @@ DriveInfo *drive_init(QemuOpts *opts, int default_to_scsi)return NULL ; } }else { - type = default_to_scsi ?IF_SCSI :IF_IDE ; + type =get_mach_if (mach_if); } max_devs = if_max_devs[type];blockdev.h +0
-0
blockdev.h struct DriveInfo { · line 47
Quoted 8 lines
blockdev.h +5
-0@@ -40,6 +40,22 @@ struct DriveInfo {int refcount; }; +/* +* Each qemu machine type defines a mach_if field for its default +* interface type. If its unspecified, we set it to IF_IDE. +*/ +static inline int get_mach_if (int mach_if)
BlockInterfaceType mach_if, and return type.
blockdev.h struct DriveInfo { · line 58
Quoted 11 lines
blockdev.h +11
-0+{ +assert (mach_if <IF_COUNT ); +assert (mach_if >=IF_DEFAULT ); + +if ((mach_if ==IF_NONE ) || (mach_if ==IF_DEFAULT )) { +return IF_IDE ; + } + +return mach_if; +} +
I'm not sure we should map IF_NONE to IF_IDE.
get_mach_if() should return an interface type the board supports. In theory, we could have a board that doesn't define any controllers, but still lets the user define some with -device (say because the board sports a PCI bus). Then IF_NONE would be the only interface type that makes any sense, and therefore the only sensible value of get_mach_if().
If we drop the magic mapping of IF_NONE, only IF_DEFAULT is left, and that one's clearly marked "for use with drive_add() only". No real need for magic mapping then. Could drop get_mach_if() and use mach_if directly.
blockdev.h void qmp_change_blockdev(const char *device, const char *filename, · line 83
Quoted 11 lines
blockdev.h +3
-0DriveInfo *drive_get (BlockInterfaceType type,int bus,int unit);DriveInfo *drive_get_by_index (BlockInterfaceType type,int index);int drive_get_max_bus (BlockInterfaceType type);@@ -61,4 +77,7 @@ void qmp_change_blockdev(const char *device, const char *filename, bool has_format, const char *format, Error **errp);void do_commit (Monitor *mon,const QDict *qdict);int do_drive_del (Monitor *mon,const QDict *qdict,QObject **ret_data); + + +#endif
Unnecessary whitespace change, suggest to drop hunk.
hw/boards.h typedef struct QEMUMachine { · line 23
Quoted 10 lines
hw/boards.h +1
-1@@ -20,7 +20,7 @@ typedef struct QEMUMachine {const char *desc;QEMUMachineInitFunc *init;QEMUMachineResetFunc *reset; -int use_scsi; +int mach_if;
BlockInterfaceType mach_if
Quoted 288 lines
hw/boards.h +0
-0int max_cpus; unsigned int no_serial:1, no_parallel:1,hw/device-hotplug.c +1
-1@@ -39,7 +39,7 @@ DriveInfo *add_init_drive(const char *optstr)if (!opts)return NULL ; - dinfo =drive_init (opts, current_machine->use_scsi); + dinfo =drive_init (opts, current_machine->mach_if);if (!dinfo) {qemu_opts_del (opts);return NULL ;hw/highbank.c +1
-1@@ -324,7 +324,7 @@ static QEMUMachine highbank_machine = { .name = "highbank", .desc = "Calxeda Highbank (ECX-1000)", .init = highbank_init, - .use_scsi = 1, + .mach_if = IF_SCSI, .max_cpus = 4, };hw/leon3.c +1
-1@@ -214,7 +214,7 @@ static QEMUMachine leon3_generic_machine = { .name = "leon3_generic", .desc = "Leon-3 generic", .init = leon3_generic_hw_init, - .use_scsi = 0, + .mach_if = IF_DEFAULT, };static void leon3_machine_init (void )hw/mips_jazz.c +2
-2@@ -325,14 +325,14 @@ static QEMUMachine mips_magnum_machine = { .name = "magnum", .desc = "MIPS Magnum", .init = mips_magnum_init, - .use_scsi = 1, + .mach_if = IF_SCSI, };static QEMUMachine mips_pica61_machine = { .name ="pica61" , .desc ="Acer Pica 61" , .init = mips_pica61_init, - .use_scsi =1 , + .mach_if =IF_SCSI , };static void mips_jazz_machine_init (void )hw/pc_sysfw.c +1
-1@@ -98,7 +98,7 @@ static void pc_fw_add_pflash_drv(void)return ; } -drive_init (opts, machine->use_scsi); +drive_init (opts, machine->mach_if); } static void pc_system_flash_init(MemoryRegion *rom_memory,hw/puv3.c +1
-1@@ -120,7 +120,7 @@ static QEMUMachine puv3_machine = { .desc = "PKUnity Version-3 based on UniCore32", .init = puv3_init, .is_default = 1, - .use_scsi = 0, + .mach_if = IF_DEFAULT, };static void puv3_machine_init (void )hw/realview.c +3
-3@@ -382,14 +382,14 @@ static QEMUMachine realview_eb_machine = { .name = "realview-eb", .desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)", .init = realview_eb_init, - .use_scsi = 1, + .mach_if = IF_SCSI, };static QEMUMachine realview_eb_mpcore_machine = { .name ="realview-eb-mpcore" , .desc ="ARM RealView Emulation Baseboard (ARM11MPCore)" , .init = realview_eb_mpcore_init, - .use_scsi =1 , + .mach_if =IF_SCSI , .max_cpus =4 , };@@ -403,7 +403,7 @@ static QEMUMachine realview_pbx_a9_machine = { .name = "realview-pbx-a9", .desc = "ARM RealView Platform Baseboard Explore for Cortex-A9", .init = realview_pbx_a9_init, - .use_scsi = 1, + .mach_if = IF_SCSI, .max_cpus = 4, };hw/spapr.c +1
-1@@ -913,7 +913,7 @@ static QEMUMachine spapr_machine = { .reset = ppc_spapr_reset, .max_cpus = MAX_CPUS, .no_parallel = 1, - .use_scsi = 1, + .mach_if = IF_SCSI, };static void spapr_machine_init (void )hw/sun4m.c +12
-12@@ -1400,7 +1400,7 @@ static QEMUMachine ss5_machine = { .name = "SS-5", .desc = "Sun4m platform, SPARCstation 5", .init = ss5_init, - .use_scsi = 1, + .mach_if = IF_SCSI, .is_default = 1, };@@ -1408,7 +1408,7 @@ static QEMUMachine ss10_machine = { .name = "SS-10", .desc = "Sun4m platform, SPARCstation 10", .init = ss10_init, - .use_scsi = 1, + .mach_if = IF_SCSI, .max_cpus = 4, };@@ -1416,7 +1416,7 @@ static QEMUMachine ss600mp_machine = { .name = "SS-600MP", .desc = "Sun4m platform, SPARCserver 600MP", .init = ss600mp_init, - .use_scsi = 1, + .mach_if = IF_SCSI, .max_cpus = 4, };@@ -1424,7 +1424,7 @@ static QEMUMachine ss20_machine = { .name = "SS-20", .desc = "Sun4m platform, SPARCstation 20", .init = ss20_init, - .use_scsi = 1, + .mach_if = IF_SCSI, .max_cpus = 4, };@@ -1432,35 +1432,35 @@ static QEMUMachine voyager_machine = { .name = "Voyager", .desc = "Sun4m platform, SPARCstation Voyager", .init = vger_init, - .use_scsi = 1, + .mach_if = IF_SCSI, };static QEMUMachine ss_lx_machine = { .name ="LX" , .desc ="Sun4m platform, SPARCstation LX" , .init = ss_lx_init, - .use_scsi =1 , + .mach_if =IF_SCSI , };static QEMUMachine ss4_machine = { .name ="SS-4" , .desc ="Sun4m platform, SPARCstation 4" , .init = ss4_init, - .use_scsi =1 , + .mach_if =IF_SCSI , };static QEMUMachine scls_machine = { .name ="SPARCClassic" , .desc ="Sun4m platform, SPARCClassic" , .init = scls_init, - .use_scsi =1 , + .mach_if =IF_SCSI , };static QEMUMachine sbook_machine = { .name ="SPARCbook" , .desc ="Sun4m platform, SPARCbook" , .init = sbook_init, - .use_scsi =1 , + .mach_if =IF_SCSI , };static const struct sun4d_hwdef sun4d_hwdefs[] = {@@ -1677,7 +1677,7 @@ static QEMUMachine ss1000_machine = { .name = "SS-1000", .desc = "Sun4d platform, SPARCserver 1000", .init = ss1000_init, - .use_scsi = 1, + .mach_if = IF_SCSI, .max_cpus = 8, };@@ -1685,7 +1685,7 @@ static QEMUMachine ss2000_machine = { .name = "SS-2000", .desc = "Sun4d platform, SPARCcenter 2000", .init = ss2000_init, - .use_scsi = 1, + .mach_if = IF_SCSI, .max_cpus = 20, };@@ -1861,7 +1861,7 @@ static QEMUMachine ss2_machine = { .name = "SS-2", .desc = "Sun4c platform, SPARCstation 2", .init = ss2_init, - .use_scsi = 1, + .mach_if = IF_SCSI, };static void sun4m_register_types (void )hw/versatilepb.c +2
-2@@ -374,14 +374,14 @@ static QEMUMachine versatilepb_machine = { .name = "versatilepb", .desc = "ARM Versatile/PB (ARM926EJ-S)", .init = vpb_init, - .use_scsi = 1, + .mach_if = IF_SCSI, };static QEMUMachine versatileab_machine = { .name ="versatileab" , .desc ="ARM Versatile/AB (ARM926EJ-S)" , .init = vab_init, - .use_scsi =1 , + .mach_if =IF_SCSI , };static void versatile_machine_init (void )hw/vexpress.c +2
-2@@ -495,7 +495,7 @@ static QEMUMachine vexpress_a9_machine = { .name = "vexpress-a9", .desc = "ARM Versatile Express for Cortex-A9", .init = vexpress_a9_init, - .use_scsi = 1, + .mach_if = IF_SCSI, .max_cpus = 4, };@@ -503,7 +503,7 @@ static QEMUMachine vexpress_a15_machine = { .name = "vexpress-a15", .desc = "ARM Versatile Express for Cortex-A15", .init = vexpress_a15_init, - .use_scsi = 1, + .mach_if = IF_SCSI, .max_cpus = 4, };hw/xilinx_zynq.c +0
-0
hw/xilinx_zynq.c static QEMUMachine zynq_machine = { · line 184
Quoted 8 lines
hw/xilinx_zynq.c +1
-1@@ -178,7 +178,7 @@ static QEMUMachine zynq_machine = { .name = "xilinx-zynq-a9", .desc = "Xilinx Zynq Platform Baseboard for Cortex-A9", .init = zynq_init, - .use_scsi = 1, + .if_default = IF_SCSI, .max_cpus = 1, .no_sdcard = 1 };
Didn't check you covered all boards.
vl.c static int parse_sandbox(QemuOpts *opts, void *opaque) · line 805
Quoted 10 lines
vl.c +1
-1@@ -802,9 +802,9 @@ static int parse_sandbox(QemuOpts *opts, void *opaque)static int drive_init_func (QemuOpts *opts,void *opaque) { -int *use_scsi = opaque; +int *mach_if = opaque;
BlockInterfaceType *mach_if
vl.c static int drive_enable_snapshot(QemuOpts *opts, void *opaque) · line 818
Quoted 12 lines
vl.c +2
-2-return drive_init (opts, *use_scsi) ==NULL ; +return drive_init (opts, *mach_if) ==NULL ; }static int drive_enable_snapshot (QemuOpts *opts,void *opaque)@@ -815,14 +815,14 @@ static int drive_enable_snapshot(QemuOpts *opts, void *opaque)return 0 ; } -static void default_drive(int enable, int snapshot, int use_scsi, +static void default_drive(int enable, int snapshot, int mach_if,
BlockInterfaceType mach_if
Quoted 41 lines
vl.c +8
-6BlockInterfaceType type, int index, const char *optstr) { QemuOpts *opts;if (type ==IF_DEFAULT ) { - type = use_scsi ?IF_SCSI :IF_IDE ; + type =get_mach_if (mach_if); }if (!enable ||drive_get_by_index (type, index)) {@@ -833,7 +833,7 @@ static void default_drive(int enable, int snapshot, int use_scsi,if (snapshot) {drive_enable_snapshot (opts,NULL ); } -if (!drive_init (opts, use_scsi)) { +if (!drive_init (opts, mach_if)) {exit (1 ); } }@@ -3547,14 +3547,16 @@ int main(int argc, char **argv, char **envp)/* open the virtual block devices */ if (snapshot)qemu_opts_foreach (qemu_find_opts ("drive" ), drive_enable_snapshot,NULL ,0 ); -if (qemu_opts_foreach (qemu_find_opts ("drive" ), drive_init_func, &machine->use_scsi,1 ) !=0 ) +if (qemu_opts_foreach (qemu_find_opts ("drive" ), drive_init_func, + &machine->mach_if,1 ) !=0 ) {exit (1 ); + } -default_drive (default_cdrom, snapshot, machine->use_scsi, +default_drive (default_cdrom, snapshot, machine->mach_if,IF_DEFAULT ,2 ,CDROM_OPTS ); -default_drive (default_floppy, snapshot, machine->use_scsi, +default_drive (default_floppy, snapshot, machine->mach_if,IF_FLOPPY ,0 ,FD_OPTS ); -default_drive (default_sdcard, snapshot, machine->use_scsi, +default_drive (default_sdcard, snapshot, machine->mach_if,IF_SD ,0 ,SD_OPTS );register_savevm_live (NULL ,"ram" ,0 ,4 , &savevm_ram_handlers,NULL );
Re: [Qemu-devel] [PATCH v3 01/26] blockdev: Introduce a default machine blockdev interface field, QEMUMachine->mach_if
Quoted 48 lines · Markus Armbruster
Quoted 5 lines · Jason Baron
From: Jason Baron <[email protected]>
The current QEMUMachine definition has a '
use_scsi' field to indicate if a machine type should use scsi by default. However, Q35 wants to use ahci by default. Thus, introdue a new field in the QEMUMachine defintion,mach_if.Even though q35's desire to default to
IF_AHCIis driving this patch, generalizing the default interface type makes sense on its own. Even if weIF_AHCIshould turn out to need more discussion.Quoted 36 lines
This field should be initialized by the machine type to the default interface type which it wants to use (
IF_SCSI,IF_AHCI, etc.). If nomach_ifis defined, or it is set to 'IF_DEFAULT' or 'IF_NONE', we currently assumeIF_IDE.Please use 'static inline int
get_mach_if(int mach_if)', when accesssing the newmach_iffield.Reviewed-by Paolo Bonzini <[email protected]>Signed-off-by Jason Baron <[email protected]>--- blockdev.c | 4 ++-- blockdev.h | 19 +++++++++++++++++++ hw/boards.h | 2 +- hw/device-hotplug.c | 2 +- hw/highbank.c | 2 +- hw/leon3.c | 2 +- hw/mips_jazz.c | 4 ++-- hw/pc_sysfw.c | 2 +- hw/puv3.c | 2 +- hw/realview.c | 6 +++--- hw/spapr.c | 2 +- hw/sun4m.c | 24 ++++++++++++------------ hw/versatilepb.c | 4 ++-- hw/vexpress.c | 4 ++-- hw/xilinx_zynq.c | 2 +- vl.c | 20 +++++++++++--------- 16 files changed, 61 insertions(+), 40 deletions(-)blockdev.c +0
-0@@ -275,7 +275,7 @@ static bool do_check_io_limits(BlockIOLimit *io_limits)return true; }
Quoted 8 lines
blockdev.c static bool do_check_io_limits(BlockIOLimit *io_limits) · line 278
Quoted 2 lines
blockdev.c +1
-1-DriveInfo *drive_init (QemuOpts *opts,int default_to_scsi) +DriveInfo *drive_init (QemuOpts *opts,int mach_if)BlockInterfaceType
mach_ifSuggest to rename
mach_ifto something more descriptive. Kevin'sdefault_drive_ifworks for me.
ok.
Quoted 43 lines
Quoted 18 lines
blockdev.c +1
-1{const char *buf;const char *file =NULL ;@@ -325,7 +325,7 @@ DriveInfo *drive_init(QemuOpts *opts, int default_to_scsi)return NULL ; } }else { - type = default_to_scsi ?IF_SCSI :IF_IDE ; + type =get_mach_if (mach_if); } max_devs = if_max_devs[type];blockdev.h +0
-0blockdev.h struct DriveInfo { · line 47
Quoted 8 lines
blockdev.h +5
-0@@ -40,6 +40,22 @@ struct DriveInfo {int refcount; }; +/* +* Each qemu machine type defines a mach_if field for its default +* interface type. If its unspecified, we set it to IF_IDE. +*/ +static inline int get_mach_if (int mach_if)BlockInterfaceType
mach_if, and return type.blockdev.h struct DriveInfo { · line 58
Quoted 11 lines
blockdev.h +11
-0+{ +assert (mach_if <IF_COUNT ); +assert (mach_if >=IF_DEFAULT ); + +if ((mach_if ==IF_NONE ) || (mach_if ==IF_DEFAULT )) { +return IF_IDE ; + } + +return mach_if; +} +I'm not sure we should map
IF_NONEtoIF_IDE.
Quoted 6 lines
get_mach_if()should return an interface type the board supports. In theory, we could have a board that doesn't define any controllers, but still lets the user define some with -device (say because the board sports a PCI bus). ThenIF_NONEwould be the only interface type that makes any sense, and therefore the only sensible value ofget_mach_if().
Ok, but no boards use IF_NONE in that sense currently. But planning for the future is good :)
Quoted 4 lines
If we drop the magic mapping of
IF_NONE, onlyIF_DEFAULTis left, and that one's clearly marked "for use withdrive_add()only". No real need for magic mapping then. Could dropget_mach_if()and usemach_ifdirectly.
Meaning explicity set mach_if or default_drive_if to IF_IDE for all machine types that are currently either IF_NONE, IF_DEFAULT, or not explicitly defined?
Thanks,
-Jason
Re: [Qemu-devel] [PATCH v3 01/26] blockdev: Introduce a default machine blockdev interface field, QEMUMachine->mach_if
Quoted 113 lines · Jason Baron
Quoted 48 lines · Markus Armbruster
Quoted 5 lines · Jason Baron
From: Jason Baron <[email protected]>
The current QEMUMachine definition has a '
use_scsi' field to indicate if a machine type should use scsi by default. However, Q35 wants to use ahci by default. Thus, introdue a new field in the QEMUMachine defintion,mach_if.Even though q35's desire to default to
IF_AHCIis driving this patch, generalizing the default interface type makes sense on its own. Even if weIF_AHCIshould turn out to need more discussion.Quoted 36 lines
This field should be initialized by the machine type to the default interface type which it wants to use (
IF_SCSI,IF_AHCI, etc.). If nomach_ifis defined, or it is set to 'IF_DEFAULT' or 'IF_NONE', we currently assumeIF_IDE.Please use 'static inline int
get_mach_if(int mach_if)', when accesssing the newmach_iffield.Reviewed-by Paolo Bonzini <[email protected]>Signed-off-by Jason Baron <[email protected]>--- blockdev.c | 4 ++-- blockdev.h | 19 +++++++++++++++++++ hw/boards.h | 2 +- hw/device-hotplug.c | 2 +- hw/highbank.c | 2 +- hw/leon3.c | 2 +- hw/mips_jazz.c | 4 ++-- hw/pc_sysfw.c | 2 +- hw/puv3.c | 2 +- hw/realview.c | 6 +++--- hw/spapr.c | 2 +- hw/sun4m.c | 24 ++++++++++++------------ hw/versatilepb.c | 4 ++-- hw/vexpress.c | 4 ++-- hw/xilinx_zynq.c | 2 +- vl.c | 20 +++++++++++--------- 16 files changed, 61 insertions(+), 40 deletions(-)blockdev.c +0
-0@@ -275,7 +275,7 @@ static bool do_check_io_limits(BlockIOLimit *io_limits)return true; }Quoted 8 lines
blockdev.c static bool do_check_io_limits(BlockIOLimit *io_limits) · line 278
Quoted 2 lines
blockdev.c +1
-1-DriveInfo *drive_init (QemuOpts *opts,int default_to_scsi) +DriveInfo *drive_init (QemuOpts *opts,int mach_if)BlockInterfaceType
mach_ifSuggest to rename
mach_ifto something more descriptive. Kevin'sdefault_drive_ifworks for me.ok.
Quoted 43 lines
Quoted 18 lines
blockdev.c +1
-1{const char *buf;const char *file =NULL ;@@ -325,7 +325,7 @@ DriveInfo *drive_init(QemuOpts *opts, int default_to_scsi)return NULL ; } }else { - type = default_to_scsi ?IF_SCSI :IF_IDE ; + type =get_mach_if (mach_if); } max_devs = if_max_devs[type];blockdev.h +0
-0blockdev.h struct DriveInfo { · line 47
Quoted 8 lines
blockdev.h +5
-0@@ -40,6 +40,22 @@ struct DriveInfo {int refcount; }; +/* +* Each qemu machine type defines a mach_if field for its default +* interface type. If its unspecified, we set it to IF_IDE. +*/ +static inline int get_mach_if (int mach_if)BlockInterfaceType
mach_if, and return type.blockdev.h struct DriveInfo { · line 58
Quoted 11 lines
blockdev.h +11
-0+{ +assert (mach_if <IF_COUNT ); +assert (mach_if >=IF_DEFAULT ); + +if ((mach_if ==IF_NONE ) || (mach_if ==IF_DEFAULT )) { +return IF_IDE ; + } + +return mach_if; +} +I'm not sure we should map
IF_NONEtoIF_IDE.Quoted 6 lines
get_mach_if()should return an interface type the board supports. In theory, we could have a board that doesn't define any controllers, but still lets the user define some with -device (say because the board sports a PCI bus). ThenIF_NONEwould be the only interface type that makes any sense, and therefore the only sensible value ofget_mach_if().Ok, but no boards use
IF_NONEin that sense currently. But planning for the future is good :)
Quoted 8 lines
Quoted 4 lines
If we drop the magic mapping of
IF_NONE, onlyIF_DEFAULTis left, and that one's clearly marked "for use withdrive_add()only". No real need for magic mapping then. Could dropget_mach_if()and usemach_ifdirectly.Meaning explicity set
mach_ifordefault_drive_iftoIF_IDEfor all machine types that are currently eitherIF_NONE,IF_DEFAULT, or not explicitly defined?
Yes.
I count 97 machine types. 24 have .use_scsi = 1. Two have explicit .use_scsi = 0, and the remaining 71 have it implicitly. I very much doubt these 73 all sport IDE controllers. Last time I checked[*], 41 machine types supported CD-ROM drives. Makes me estimate we have ~55 machine types that have neither onboard SCSI nor IDE.
What happens when .use_scsi = 0 and the board doesn't provide IDE? -drive without if= defines a block backend, but no frontend. Just like if=none, except for the (misleading) default ID. Likewise, when .use_scsi = 1 and the board doesn't provide SCSI.
You convert the 24 .use_scsi = 1 to .mach_if = IF_SCSI. Fair enough. But I think it should be changed to a more suitable value for machine types that don't actually provide SCSI. Suspect highbank is an example. Can be done as followup patch; your choice.
You convert the two explicit .use_scsi = 0 (leon3_generic and puv3.c) to IF_DEFAULT, effectively IF_IDE. In both cases, the machine doesn't actually provide an IDE controller as far as I can tell. Again, changing it to a more suitable value would make sense. Followup patch, or drop the .use_scsi = 0 in a preparatory patch, or convert to "no initializer" to fold this case into the next one, or whatever else works for you.
You leave the 71 without a .use_scsi initializer alone, which results in IF_NONE, effectively IF_IDE. Fair enough. Again, it should be changed to a more suitable value for the machine types that don't provide IDE. If you drop the magic mapping, IF_NONE means IF_NONE, which may be a more suitable value for the ones that don't provide IDE. So you'd have to add .mach_if = IF_IDE only to the minority that does provide IDE, and leave the remaining ~55 ones alone.
Not so bad, isn't it?
[*] http://lists.nongnu.org/archive/html/qemu-devel/2012-08/msg02993.html
Re: [Qemu-devel] [PATCH v3 01/26] blockdev: Introduce a default machine blockdev interface field, QEMUMachine->mach_if
In reply to Jason BaronQuoted 12 lines · Jason Baron
From: Jason Baron <[email protected]>
The current QEMUMachine definition has a '
use_scsi' field to indicate if a machine type should use scsi by default. However, Q35 wants to use ahci by default. Thus, introdue a new field in the QEMUMachine defintion,mach_if.This field should be initialized by the machine type to the default interface type which it wants to use (
IF_SCSI,IF_AHCI, etc.). If nomach_ifis defined, or it is set to 'IF_DEFAULT' or 'IF_NONE', we currently assumeIF_IDE.Please use 'static inline int
get_mach_if(int mach_if)', when accesssing the newmach_iffield.
[...]
Quoted 13 lines
hw/boards.h +1
-1@@ -20,7 +20,7 @@ typedef struct QEMUMachine {const char *desc;QEMUMachineInitFunc *init;QEMUMachineResetFunc *reset; -int use_scsi; +int mach_if;int max_cpus; unsigned int no_serial:1, no_parallel:1,
[...]
hw/xilinx_zynq.c static QEMUMachine zynq_machine = { · line 181
Quoted 10 lines
hw/xilinx_zynq.c +1
-1@@ -178,7 +178,7 @@ static QEMUMachine zynq_machine = { .name = "xilinx-zynq-a9", .desc = "Xilinx Zynq Platform Baseboard for Cortex-A9", .init = zynq_init, - .use_scsi = 1, + .if_default = IF_SCSI,
I doubt this compiles, and if it does, the compiler is mean to you :)
Quoted 3 lines
hw/xilinx_zynq.c +0
-0.max_cpus = 1, .no_sdcard = 1 };
[...]
PATCH v3 2/26 blockdev: Introduce IF_AHCI
In reply to Jason BaronFrom: Jason Baron <[email protected]>
Introduce IF_AHCI so that q35 can differentiate between ide and ahci disks. This allows q35 to specify its default disk type. It also allows q35 to differentiate between ahci and ide disks, such that -drive if=ide does not result in the creating of an ahci disk. This is important, since we don't want to have the meaning of if=ide changing once q35 is introduced. Thus, its important for this to be applied before we introduce q35.
This patch also adds:
pci_ahci_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table)
Which provides a convient way of attaching ahci drives to an ahci controller.
--- blockdev.c | 13 ++++++++++++- blockdev.h | 2 ++ hw/ide.h | 6 ++++++ hw/ide/ahci.c | 18 ++++++++++++++++++ hw/ide/core.c | 23 ++++++++++++++++++----- 5 files changed, 56 insertions(+), 6 deletions(-)
blockdev.c +12 -1
@@ -33,6 +33,7 @@ static const char *const if_name[IF_COUNT] = { [IF_SD] = "sd", [IF_VIRTIO] = "virtio", [IF_XEN] = "xen", + [IF_AHCI] = "ahci", };static const int if_max_devs[IF_COUNT ] = {
@@ -52,8 +53,17 @@ static const int if_max_devs[IF_COUNT] = {*/ [IF_IDE] = 2, [IF_SCSI] = 7, + [IF_AHCI] = 6, }; +int get_if_max_devs (BlockInterfaceType if_type) +{ +assert (if_type <IF_COUNT ); +assert (if_type >=IF_DEFAULT ); + +return if_max_devs[if_type]; +} +/* * We automatically delete the drive when a device using it gets * unplugged. Questionable feature, but we can't just drop it.
@@ -518,7 +528,7 @@ DriveInfo *drive_init(QemuOpts *opts, int mach_if) }else {/* no id supplied -> create one */ dinfo->id =g_malloc0 (32 ); -if (type ==IF_IDE || type ==IF_SCSI ) +if (type ==IF_IDE || type ==IF_SCSI || type ==IF_AHCI ) mediastr = (media ==MEDIA_CDROM ) ?"-cd" :"-hd" ;if (max_devs) snprintf(dinfo->id, 32, "%s%i%s%i",
@@ -550,6 +560,7 @@ DriveInfo *drive_init(QemuOpts *opts, int mach_if)switch (type) {case IF_IDE : +case IF_AHCI :case IF_SCSI :case IF_XEN :case IF_NONE :
blockdev.h +2 -0
@@ -21,6 +21,7 @@ typedef enum {IF_DEFAULT =-1 ,/* for use with drive_add() only */ IF_NONE ,IF_IDE ,IF_SCSI ,IF_FLOPPY ,IF_PFLASH ,IF_MTD ,IF_SD ,IF_VIRTIO ,IF_XEN , +IF_AHCI , IF_COUNT } BlockInterfaceType;
@@ -56,6 +57,7 @@ static inline int get_mach_if(int mach_if)return mach_if; } +int get_if_max_devs (BlockInterfaceType if_type);DriveInfo *drive_get (BlockInterfaceType type,int bus,int unit);DriveInfo *drive_get_by_index (BlockInterfaceType type,int index);int drive_get_max_bus (BlockInterfaceType type);
hw/ide.h +6 -0
@@ -4,6 +4,7 @@#include "isa.h" #include "pci.h" #include "memory.h" +#include "blockdev.h" #define MAX_IDE_DEVS 2
@@ -34,6 +35,11 @@ int ide_get_geometry(BusState *bus, int unit,int ide_get_bios_chs_trans (BusState *bus,int unit);/* ide/core.c */ +void ata_drive_get (DriveInfo **hd,int max_bus,BlockInterfaceType type);void ide_drive_get (DriveInfo **hd,int max_bus); +void ahci_drive_get (DriveInfo **hd,int max_bus); + +/* ide/ahci.c */ +void pci_ahci_create_devs (PCIDevice *pci_dev,DriveInfo **hd_table);#endif /* HW_IDE_H */
hw/ide/ahci.c +18 -0
@@ -26,6 +26,7 @@#include <hw/pc.h> #include <hw/pci.h> #include <hw/sysbus.h> +#include <blockdev.h> #include "monitor.h" #include "dma.h"
@@ -1260,3 +1261,20 @@ static void sysbus_ahci_register_types(void) }type_init (sysbus_ahci_register_types) + +void pci_ahci_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table) +{ + struct AHCIPCIState *dev = DO_UPCAST(struct AHCIPCIState, card, pci_dev); +int i; +DriveInfo *drive; + +for (i =0 ; i < dev->ahci.ports; i++) { +if (hd_table[i] ==NULL ) { +continue ; + } + drive = hd_table[i]; +assert (drive->type ==IF_AHCI ); +ide_create_drive (&dev->ahci.dev[i].port,0 , + hd_table[i]); + } +}
hw/ide/core.c +18 -5
@@ -2341,16 +2341,29 @@ const VMStateDescription vmstate_ide_bus = { } }; -void ide_drive_get (DriveInfo **hd,int max_bus) +void ata_drive_get (DriveInfo **hd,int max_bus,BlockInterfaceType type) {int i; +int max_devs; + +assert ((type ==IF_IDE ) || type ==IF_AHCI ); -if (drive_get_max_bus (IF_IDE ) >= max_bus) { +if (drive_get_max_bus (type) >= max_bus) {fprintf (stderr,"qemu: too many IDE bus: %d\n" , max_bus);exit (1 ); } - -for (i =0 ; i < max_bus *MAX_IDE_DEVS ; i++) { - hd[i] =drive_get (IF_IDE , i /MAX_IDE_DEVS , i %MAX_IDE_DEVS ); + max_devs =get_if_max_devs (type); +for (i =0 ; i < max_bus * max_devs; i++) { + hd[i] =drive_get (type, i / max_devs, i % max_devs); } } + +void ide_drive_get (DriveInfo **hd,int max_bus) +{ +ata_drive_get (hd, max_bus,IF_IDE ); +} + +void ahci_drive_get (DriveInfo **hd,int max_bus) +{ +ata_drive_get (hd, max_bus,IF_AHCI ); +}
Signature · 1 line
1.7.1
Re: [Qemu-devel] [PATCH v3 02/26] blockdev: Introduce IF_AHCI
Quoted 11 lines · Jason Baron
From: Jason Baron <[email protected]>
Introduce
IF_AHCIso that q35 can differentiate between ide and ahci disks. This allows q35 to specify its default disk type. It also allows q35 to differentiate between ahci and ide disks, such that -drive if=ide does not result in the creating of an ahci disk. This is important, since we don't want to have the meaning of if=ide changing once q35 is introduced. Thus, its important for this to be applied before we introduce q35.This patch also adds:
Quoted 8 lines
pci_ahci_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table)Which provides a convient way of attaching ahci drives to an ahci controller.
Reviewed-by Paolo Bonzini <[email protected]>Signed-off-by Jason Baron <[email protected]>---
Kevin, could you review/ack this patch pls?
Quoted 172 lines
blockdev.c | 13 ++++++++++++- blockdev.h | 2 ++ hw/ide.h | 6 ++++++ hw/ide/ahci.c | 18 ++++++++++++++++++ hw/ide/core.c | 23 ++++++++++++++++++----- 5 files changed, 56 insertions(+), 6 deletions(-)blockdev.c +12
-1@@ -33,6 +33,7 @@ static const char *const if_name[IF_COUNT] = { [IF_SD] = "sd", [IF_VIRTIO] = "virtio", [IF_XEN] = "xen", + [IF_AHCI] = "ahci", };static const int if_max_devs[IF_COUNT ] = {@@ -52,8 +53,17 @@ static const int if_max_devs[IF_COUNT] = {*/ [IF_IDE] = 2, [IF_SCSI] = 7, + [IF_AHCI] = 6, }; +int get_if_max_devs (BlockInterfaceType if_type) +{ +assert (if_type <IF_COUNT ); +assert (if_type >=IF_DEFAULT ); + +return if_max_devs[if_type]; +} +/* * We automatically delete the drive when a device using it gets * unplugged. Questionable feature, but we can't just drop it. @@ -518,7 +528,7 @@ DriveInfo *drive_init(QemuOpts *opts, int mach_if) }else {/* no id supplied -> create one */ dinfo->id =g_malloc0 (32 ); -if (type ==IF_IDE || type ==IF_SCSI ) +if (type ==IF_IDE || type ==IF_SCSI || type ==IF_AHCI ) mediastr = (media ==MEDIA_CDROM ) ?"-cd" :"-hd" ;if (max_devs) snprintf(dinfo->id, 32, "%s%i%s%i",@@ -550,6 +560,7 @@ DriveInfo *drive_init(QemuOpts *opts, int mach_if)switch (type) {case IF_IDE : +case IF_AHCI :case IF_SCSI :case IF_XEN :case IF_NONE :blockdev.h +2
-0@@ -21,6 +21,7 @@ typedef enum {IF_DEFAULT =-1 ,/* for use with drive_add() only */ IF_NONE ,IF_IDE ,IF_SCSI ,IF_FLOPPY ,IF_PFLASH ,IF_MTD ,IF_SD ,IF_VIRTIO ,IF_XEN , +IF_AHCI , IF_COUNT } BlockInterfaceType;@@ -56,6 +57,7 @@ static inline int get_mach_if(int mach_if)return mach_if; } +int get_if_max_devs (BlockInterfaceType if_type);DriveInfo *drive_get (BlockInterfaceType type,int bus,int unit);DriveInfo *drive_get_by_index (BlockInterfaceType type,int index);int drive_get_max_bus (BlockInterfaceType type);hw/ide.h +6
-0@@ -4,6 +4,7 @@#include "isa.h" #include "pci.h" #include "memory.h" +#include "blockdev.h" #define MAX_IDE_DEVS 2@@ -34,6 +35,11 @@ int ide_get_geometry(BusState *bus, int unit,int ide_get_bios_chs_trans (BusState *bus,int unit);/* ide/core.c */ +void ata_drive_get (DriveInfo **hd,int max_bus,BlockInterfaceType type);void ide_drive_get (DriveInfo **hd,int max_bus); +void ahci_drive_get (DriveInfo **hd,int max_bus); + +/* ide/ahci.c */ +void pci_ahci_create_devs (PCIDevice *pci_dev,DriveInfo **hd_table);#endif /* HW_IDE_H */ hw/ide/ahci.c +18
-0@@ -26,6 +26,7 @@#include <hw/pc.h> #include <hw/pci.h> #include <hw/sysbus.h> +#include <blockdev.h> #include "monitor.h" #include "dma.h" @@ -1260,3 +1261,20 @@ static void sysbus_ahci_register_types(void) }type_init (sysbus_ahci_register_types) + +void pci_ahci_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table) +{ + struct AHCIPCIState *dev = DO_UPCAST(struct AHCIPCIState, card, pci_dev); +int i; +DriveInfo *drive; + +for (i =0 ; i < dev->ahci.ports; i++) { +if (hd_table[i] ==NULL ) { +continue ; + } + drive = hd_table[i]; +assert (drive->type ==IF_AHCI ); +ide_create_drive (&dev->ahci.dev[i].port,0 , + hd_table[i]); + } +}hw/ide/core.c +18
-5@@ -2341,16 +2341,29 @@ const VMStateDescription vmstate_ide_bus = { } }; -void ide_drive_get (DriveInfo **hd,int max_bus) +void ata_drive_get (DriveInfo **hd,int max_bus,BlockInterfaceType type) {int i; +int max_devs; + +assert ((type ==IF_IDE ) || type ==IF_AHCI ); -if (drive_get_max_bus (IF_IDE ) >= max_bus) { +if (drive_get_max_bus (type) >= max_bus) {fprintf (stderr,"qemu: too many IDE bus: %d\n" , max_bus);exit (1 ); } - -for (i =0 ; i < max_bus *MAX_IDE_DEVS ; i++) { - hd[i] =drive_get (IF_IDE , i /MAX_IDE_DEVS , i %MAX_IDE_DEVS ); + max_devs =get_if_max_devs (type); +for (i =0 ; i < max_bus * max_devs; i++) { + hd[i] =drive_get (type, i / max_devs, i % max_devs); } } + +void ide_drive_get (DriveInfo **hd,int max_bus) +{ +ata_drive_get (hd, max_bus,IF_IDE ); +} + +void ahci_drive_get (DriveInfo **hd,int max_bus) +{ +ata_drive_get (hd, max_bus,IF_AHCI ); +}Signature · 1 line
1.7.1
Re: [Qemu-devel] [PATCH v3 02/26] blockdev: Introduce IF_AHCI
Am 22.10.2012 12:48, schrieb Michael S. Tsirkin:
Quoted 41 lines · Jason Baron
Quoted 11 lines
From: Jason Baron <[email protected]>
Introduce
IF_AHCIso that q35 can differentiate between ide and ahci disks. This allows q35 to specify its default disk type. It also allows q35 to differentiate between ahci and ide disks, such that -drive if=ide does not result in the creating of an ahci disk. This is important, since we don't want to have the meaning of if=ide changing once q35 is introduced. Thus, its important for this to be applied before we introduce q35.This patch also adds:
Quoted 8 lines
pci_ahci_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table)Which provides a convient way of attaching ahci drives to an ahci controller.
Reviewed-by Paolo Bonzini <[email protected]>Signed-off-by Jason Baron <[email protected]>---
Kevin, could you review/ack this patch pls?
Quoted 18 lines
blockdev.c | 13 ++++++++++++- blockdev.h | 2 ++ hw/ide.h | 6 ++++++ hw/ide/ahci.c | 18 ++++++++++++++++++ hw/ide/core.c | 23 ++++++++++++++++++----- 5 files changed, 56 insertions(+), 6 deletions(-)blockdev.c +1
-0@@ -33,6 +33,7 @@ static const char *const if_name[IF_COUNT] = { [IF_SD] = "sd", [IF_VIRTIO] = "virtio", [IF_XEN] = "xen", + [IF_AHCI] = "ahci", };
Quoted 7 lines
blockdev.c static const int if_max_devs[IF_COUNT] = { · line 57
Quoted 7 lines
blockdev.c +1
-0static const int if_max_devs[IF_COUNT ] = {@@ -52,8 +53,17 @@ static const int if_max_devs[IF_COUNT] = { */ [IF_IDE] = 2, [IF_SCSI] = 7, + [IF_AHCI] = 6, };
What are the implications of this if we decided to add another AHCI controller which had a different number of ports? I suspect that a controller with less than 6 ports breaks when you add more drives than a single controller can handle, and one with more than 6 ports doesn't use up all of its ports before it adds another controller.
Markus?
Quoted 7 lines
blockdev.c static const int if_max_devs[IF_COUNT] = { · line 65
Quoted 7 lines
blockdev.c +7
-0+int get_if_max_devs (BlockInterfaceType if_type) +{ +assert (if_type <IF_COUNT ); +assert (if_type >=IF_DEFAULT ); + +return if_max_devs[if_type]; +}
if_max_devs has a specific obvious meaning within blockdev.c, but outside it's not as obvious. So this function could use a rename.
Quoted 105 lines
Quoted 105 lines
blockdev.c +2
-1/* * We automatically delete the drive when a device using it gets * unplugged. Questionable feature, but we can't just drop it. @@ -518,7 +528,7 @@ DriveInfo *drive_init(QemuOpts *opts, int mach_if) }else {/* no id supplied -> create one */ dinfo->id =g_malloc0 (32 ); -if (type ==IF_IDE || type ==IF_SCSI ) +if (type ==IF_IDE || type ==IF_SCSI || type ==IF_AHCI ) mediastr = (media ==MEDIA_CDROM ) ?"-cd" :"-hd" ;if (max_devs) snprintf(dinfo->id, 32, "%s%i%s%i",@@ -550,6 +560,7 @@ DriveInfo *drive_init(QemuOpts *opts, int mach_if)switch (type) {case IF_IDE : +case IF_AHCI :case IF_SCSI :case IF_XEN :case IF_NONE :blockdev.h +2
-0@@ -21,6 +21,7 @@ typedef enum {IF_DEFAULT =-1 ,/* for use with drive_add() only */ IF_NONE ,IF_IDE ,IF_SCSI ,IF_FLOPPY ,IF_PFLASH ,IF_MTD ,IF_SD ,IF_VIRTIO ,IF_XEN , +IF_AHCI , IF_COUNT } BlockInterfaceType;@@ -56,6 +57,7 @@ static inline int get_mach_if(int mach_if)return mach_if; } +int get_if_max_devs (BlockInterfaceType if_type);DriveInfo *drive_get (BlockInterfaceType type,int bus,int unit);DriveInfo *drive_get_by_index (BlockInterfaceType type,int index);int drive_get_max_bus (BlockInterfaceType type);hw/ide.h +6
-0@@ -4,6 +4,7 @@#include "isa.h" #include "pci.h" #include "memory.h" +#include "blockdev.h" #define MAX_IDE_DEVS 2@@ -34,6 +35,11 @@ int ide_get_geometry(BusState *bus, int unit,int ide_get_bios_chs_trans (BusState *bus,int unit);/* ide/core.c */ +void ata_drive_get (DriveInfo **hd,int max_bus,BlockInterfaceType type);void ide_drive_get (DriveInfo **hd,int max_bus); +void ahci_drive_get (DriveInfo **hd,int max_bus); + +/* ide/ahci.c */ +void pci_ahci_create_devs (PCIDevice *pci_dev,DriveInfo **hd_table);#endif /* HW_IDE_H */ hw/ide/ahci.c +18
-0@@ -26,6 +26,7 @@#include <hw/pc.h> #include <hw/pci.h> #include <hw/sysbus.h> +#include <blockdev.h> #include "monitor.h" #include "dma.h" @@ -1260,3 +1261,20 @@ static void sysbus_ahci_register_types(void) }type_init (sysbus_ahci_register_types) + +void pci_ahci_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table) +{ + struct AHCIPCIState *dev = DO_UPCAST(struct AHCIPCIState, card, pci_dev); +int i; +DriveInfo *drive; + +for (i =0 ; i < dev->ahci.ports; i++) { +if (hd_table[i] ==NULL ) { +continue ; + } + drive = hd_table[i]; +assert (drive->type ==IF_AHCI ); +ide_create_drive (&dev->ahci.dev[i].port,0 , + hd_table[i]); + } +}hw/ide/core.c +0
-0@@ -2341,16 +2341,29 @@ const VMStateDescription vmstate_ide_bus = { } };
Quoted 2 lines
hw/ide/core.c const VMStateDescription vmstate_ide_bus = { · line 2344
Quoted 2 lines
hw/ide/core.c +1
-1-void ide_drive_get (DriveInfo **hd,int max_bus) +void ata_drive_get (DriveInfo **hd,int max_bus,BlockInterfaceType type)
Could be static?
Quoted 5 lines
hw/ide/core.c const VMStateDescription vmstate_ide_bus = { · line 2349
Quoted 5 lines
hw/ide/core.c +3
-0{int i; +int max_devs; + +assert ((type ==IF_IDE ) || type ==IF_AHCI );
Interesting use of brackets.
Quoted 4 lines
hw/ide/core.c const VMStateDescription vmstate_ide_bus = { · line 2352
Quoted 4 lines
hw/ide/core.c +1
-1-if (drive_get_max_bus (IF_IDE ) >= max_bus) { +if (drive_get_max_bus (type) >= max_bus) {fprintf (stderr,"qemu: too many IDE bus: %d\n" , max_bus);
"Too many %s buses", type == IF_IDE ? "IDE" : "AHCI"
Quoted 12 lines
Quoted 12 lines
hw/ide/core.c +5
-3exit (1 ); } - -for (i =0 ; i < max_bus *MAX_IDE_DEVS ; i++) { - hd[i] =drive_get (IF_IDE , i /MAX_IDE_DEVS , i %MAX_IDE_DEVS ); + max_devs =get_if_max_devs (type); +for (i =0 ; i < max_bus * max_devs; i++) { + hd[i] =drive_get (type, i / max_devs, i % max_devs); } } + +void ide_drive_get (DriveInfo **hd,int max_bus)
Quoted 8 lines
hw/ide/core.c const VMStateDescription vmstate_ide_bus = { · line 2369
Quoted 8 lines
hw/ide/core.c +8
-0+{ +ata_drive_get (hd, max_bus,IF_IDE ); +} + +void ahci_drive_get (DriveInfo **hd,int max_bus) +{ +ata_drive_get (hd, max_bus,IF_AHCI ); +}
Kevin
Re: [Qemu-devel] [PATCH v3 02/26] blockdev: Introduce IF_AHCI
Quoted 54 lines · Kevin Wolf
Quoted 40 lines
Quoted 11 lines
From: Jason Baron <[email protected]>
Introduce
IF_AHCIso that q35 can differentiate between ide and ahci disks. This allows q35 to specify its default disk type. It also allows q35 to differentiate between ahci and ide disks, such that -drive if=ide does not result in the creating of an ahci disk. This is important, since we don't want to have the meaning of if=ide changing once q35 is introduced. Thus, its important for this to be applied before we introduce q35.This patch also adds:
Quoted 8 lines
pci_ahci_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table)Which provides a convient way of attaching ahci drives to an ahci controller.
Reviewed-by Paolo Bonzini <[email protected]>Signed-off-by Jason Baron <[email protected]>---
Kevin, could you review/ack this patch pls?
Quoted 18 lines
blockdev.c | 13 ++++++++++++- blockdev.h | 2 ++ hw/ide.h | 6 ++++++ hw/ide/ahci.c | 18 ++++++++++++++++++ hw/ide/core.c | 23 ++++++++++++++++++----- 5 files changed, 56 insertions(+), 6 deletions(-)blockdev.c +1
-0@@ -33,6 +33,7 @@ static const char *const if_name[IF_COUNT] = { [IF_SD] = "sd", [IF_VIRTIO] = "virtio", [IF_XEN] = "xen", + [IF_AHCI] = "ahci", };Quoted 7 lines
blockdev.c static const int if_max_devs[IF_COUNT] = { · line 57
Quoted 7 lines
blockdev.c +1
-0static const int if_max_devs[IF_COUNT ] = {@@ -52,8 +53,17 @@ static const int if_max_devs[IF_COUNT] = { */ [IF_IDE] = 2, [IF_SCSI] = 7, + [IF_AHCI] = 6, };What are the implications of this if we decided to add another AHCI controller which had a different number of ports? I suspect that a controller with less than 6 ports breaks when you add more drives than a single controller can handle, and one with more than 6 ports doesn't use up all of its ports before it adds another controller.
Quoted 2 lines
Markus?
My plan was to make this field, machine dependent if/when we wanted a different size. I don't think it breaks anything to make this change at a later point. But please correct me, if I am wrong.
Quoted 10 lines
Quoted 7 lines
blockdev.c static const int if_max_devs[IF_COUNT] = { · line 65
Quoted 7 lines
blockdev.c +7
-0+int get_if_max_devs (BlockInterfaceType if_type) +{ +assert (if_type <IF_COUNT ); +assert (if_type >=IF_DEFAULT ); + +return if_max_devs[if_type]; +}
if_max_devshas a specific obvious meaning withinblockdev.c, but outside it's not as obvious. So this function could use a rename.
ok.
Quoted 106 lines
Quoted 106 lines
Quoted 106 lines
blockdev.c +2
-1/* * We automatically delete the drive when a device using it gets * unplugged. Questionable feature, but we can't just drop it. @@ -518,7 +528,7 @@ DriveInfo *drive_init(QemuOpts *opts, int mach_if) }else {/* no id supplied -> create one */ dinfo->id =g_malloc0 (32 ); -if (type ==IF_IDE || type ==IF_SCSI ) +if (type ==IF_IDE || type ==IF_SCSI || type ==IF_AHCI ) mediastr = (media ==MEDIA_CDROM ) ?"-cd" :"-hd" ;if (max_devs) snprintf(dinfo->id, 32, "%s%i%s%i",@@ -550,6 +560,7 @@ DriveInfo *drive_init(QemuOpts *opts, int mach_if)switch (type) {case IF_IDE : +case IF_AHCI :case IF_SCSI :case IF_XEN :case IF_NONE :blockdev.h +2
-0@@ -21,6 +21,7 @@ typedef enum {IF_DEFAULT =-1 ,/* for use with drive_add() only */ IF_NONE ,IF_IDE ,IF_SCSI ,IF_FLOPPY ,IF_PFLASH ,IF_MTD ,IF_SD ,IF_VIRTIO ,IF_XEN , +IF_AHCI , IF_COUNT } BlockInterfaceType;@@ -56,6 +57,7 @@ static inline int get_mach_if(int mach_if)return mach_if; } +int get_if_max_devs (BlockInterfaceType if_type);DriveInfo *drive_get (BlockInterfaceType type,int bus,int unit);DriveInfo *drive_get_by_index (BlockInterfaceType type,int index);int drive_get_max_bus (BlockInterfaceType type);hw/ide.h +6
-0@@ -4,6 +4,7 @@#include "isa.h" #include "pci.h" #include "memory.h" +#include "blockdev.h" #define MAX_IDE_DEVS 2@@ -34,6 +35,11 @@ int ide_get_geometry(BusState *bus, int unit,int ide_get_bios_chs_trans (BusState *bus,int unit);/* ide/core.c */ +void ata_drive_get (DriveInfo **hd,int max_bus,BlockInterfaceType type);void ide_drive_get (DriveInfo **hd,int max_bus); +void ahci_drive_get (DriveInfo **hd,int max_bus); + +/* ide/ahci.c */ +void pci_ahci_create_devs (PCIDevice *pci_dev,DriveInfo **hd_table);#endif /* HW_IDE_H */ hw/ide/ahci.c +18
-0@@ -26,6 +26,7 @@#include <hw/pc.h> #include <hw/pci.h> #include <hw/sysbus.h> +#include <blockdev.h> #include "monitor.h" #include "dma.h" @@ -1260,3 +1261,20 @@ static void sysbus_ahci_register_types(void) }type_init (sysbus_ahci_register_types) + +void pci_ahci_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table) +{ + struct AHCIPCIState *dev = DO_UPCAST(struct AHCIPCIState, card, pci_dev); +int i; +DriveInfo *drive; + +for (i =0 ; i < dev->ahci.ports; i++) { +if (hd_table[i] ==NULL ) { +continue ; + } + drive = hd_table[i]; +assert (drive->type ==IF_AHCI ); +ide_create_drive (&dev->ahci.dev[i].port,0 , + hd_table[i]); + } +}hw/ide/core.c +0
-0@@ -2341,16 +2341,29 @@ const VMStateDescription vmstate_ide_bus = { } };
Quoted 5 lines
Quoted 2 lines
hw/ide/core.c const VMStateDescription vmstate_ide_bus = { · line 2344
Quoted 2 lines
hw/ide/core.c +1
-1-void ide_drive_get (DriveInfo **hd,int max_bus) +void ata_drive_get (DriveInfo **hd,int max_bus,BlockInterfaceType type)Could be static?
Yes.
Quoted 7 lines
Quoted 5 lines
hw/ide/core.c const VMStateDescription vmstate_ide_bus = { · line 2349
Quoted 5 lines
hw/ide/core.c +3
-0{int i; +int max_devs; + +assert ((type ==IF_IDE ) || type ==IF_AHCI );Interesting use of brackets.
oops.
Quoted 7 lines
Quoted 5 lines
hw/ide/core.c const VMStateDescription vmstate_ide_bus = { · line 2352
Quoted 5 lines
hw/ide/core.c +1
-1-if (drive_get_max_bus (IF_IDE ) >= max_bus) { +if (drive_get_max_bus (type) >= max_bus) {fprintf (stderr,"qemu: too many IDE bus: %d\n" , max_bus);"Too many %s buses", type ==
IF_IDE? "IDE" : "AHCI"
ok.
Quoted 15 lines
Quoted 15 lines
Quoted 15 lines
hw/ide/core.c +7
-3exit (1 ); } - -for (i =0 ; i < max_bus *MAX_IDE_DEVS ; i++) { - hd[i] =drive_get (IF_IDE , i /MAX_IDE_DEVS , i %MAX_IDE_DEVS ); + max_devs =get_if_max_devs (type); +for (i =0 ; i < max_bus * max_devs; i++) { + hd[i] =drive_get (type, i / max_devs, i % max_devs); } } + +void ide_drive_get (DriveInfo **hd,int max_bus) +{ +ata_drive_get (hd, max_bus,IF_IDE );
Quoted 8 lines
Quoted 6 lines
hw/ide/core.c const VMStateDescription vmstate_ide_bus = { · line 2369
Quoted 6 lines
hw/ide/core.c +6
-0+} + +void ahci_drive_get (DriveInfo **hd,int max_bus) +{ +ata_drive_get (hd, max_bus,IF_AHCI ); +}Kevin
Thanks,
-Jason
Re: [Qemu-devel] [PATCH v3 02/26] blockdev: Introduce IF_AHCI
Quoted 10 lines · Jason Baron
Quoted 9 lines · Kevin Wolf
Quoted 9 lines
Quoted 9 lines
From: Jason Baron <[email protected]>
Introduce
IF_AHCIso that q35 can differentiate between ide and ahci disks. This allows q35 to specify its default disk type. It also allows q35 to differentiate between ahci and ide disks, such that -drive if=ide does not result in the creating of an ahci disk. This is important, since we don't want
to have the meaning of if=ide changing once q35 is introduced. Thus, its important for this to be applied before we introduce q35.
This isn't the real argument for IF_AHCI. The real argument is that the (bus, unit) namespace for if=ide makes no sense for AHCI.
A board can have any number of IDE controllers. Each IDE controller provides one or two buses, and each bus takes up to two units. Together, we get a a board-specific number of buses, where each bus takes up to two units.
A board can have any number of AHCI controllers. Each AHCI controller provides a device-specific number of ports. Together, we get a board-specific number of buses, where each bus can takes a bus-specific number of units.
Plain q35 doesn't really need to differentiate between IDE and AHCI; it has only AHCI. What it needs is a "one bus with six units" namespace.
We could fix this by relaxing if=ide's rigid "two units per bus" for new machine types.
You fix it by introducing if=ahci. Probably simpler. But what's the plan for the next generation of controller? Yet another interface type?
Note that SCSI suffers from similar rigidity: seven units per bus. That's fine for SCSI-1, but not for some of the other variants.
"Differentiate" comes into play when a board sports both AHCI and IDE controllers. Which q35 doesn't, does it?
Then, the new if=ahci lets users select the kind of controller more easily than bus numbers would.
Drawback: existing command lines upgrade from pc to plain q35 gracefully only if they don't specify if=ide explicitly. Upgrading to some q35 variant with IDE controller on board is even worse: it works, but performance sucks. Some regard this as a feature.
Quoted 31 lines
Quoted 31 lines
Quoted 31 lines
Quoted 10 lines
This patch also adds:
pci_ahci_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table)Which provides a convient way of attaching ahci drives to an ahci controller.
Reviewed-by Paolo Bonzini <[email protected]>Signed-off-by Jason Baron <[email protected]>---
Kevin, could you review/ack this patch pls?
Quoted 18 lines
blockdev.c | 13 ++++++++++++- blockdev.h | 2 ++ hw/ide.h | 6 ++++++ hw/ide/ahci.c | 18 ++++++++++++++++++ hw/ide/core.c | 23 ++++++++++++++++++----- 5 files changed, 56 insertions(+), 6 deletions(-)blockdev.c +1
-0@@ -33,6 +33,7 @@ static const char *const if_name[IF_COUNT] = { [IF_SD] = "sd", [IF_VIRTIO] = "virtio", [IF_XEN] = "xen", + [IF_AHCI] = "ahci", };
Quoted 2 lines
Quoted 2 lines
Quoted 2 lines
blockdev.c static const int if_max_devs[IF_COUNT] = {
Quoted 2 lines
blockdev.c +0
-0static const int if_max_devs[IF_COUNT ] = {@@ -52,8 +53,17 @@ static const int if_max_devs[IF_COUNT] = {
/*
* Do not change these numbers! They govern how drive option
* index maps to unit and bus. That mapping is ABI. *
* All controllers used to imlement if=T drives need to support
* if_max_devs[T] units, for any T with if_max_devs[T] != 0.
* Otherwise, some index values map to "impossible" bus, unit
* values.
*
* For instance, if you change [IF_SCSI] to 255, -drive
* if=scsi,index=12 no longer means bus=1,unit=5, but
* bus=0,unit=12. With an lsi53c895a controller (7 units max),
* the drive can't be set up. Regression.
Quoted 12 lines
Quoted 12 lines
Quoted 5 lines
blockdev.c static const int if_max_devs[IF_COUNT] = { · line 57
Quoted 5 lines
blockdev.c +1
-0*/ [IF_IDE] = 2, [IF_SCSI] = 7, + [IF_AHCI] = 6, };What are the implications of this if we decided to add another AHCI controller which had a different number of ports? I suspect that a controller with less than 6 ports breaks when you add more drives than a single controller can handle, and one with more than 6 ports doesn't use up all of its ports before it adds another controller.
Quoted 6 lines
Quoted 2 lines
Markus?
My plan was to make this field, machine dependent if/when we wanted a different size. I don't think it breaks anything to make this change at a later point. But please correct me, if I am wrong.
I'm afraid you are. See the comment immediately above, and commit 27d6bf40.
As far as I can see, the least bad solution is leaving if_max_devs[IF_AHCI] zero. Makes index=N an alias for unit=N,bus=0, and leaves rejecting invalid (bus,unit) to the board.
Quoted 11 lines
Quoted 10 lines
Quoted 7 lines
blockdev.c static const int if_max_devs[IF_COUNT] = { · line 65
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blockdev.c +7
-0+int get_if_max_devs (BlockInterfaceType if_type) +{ +assert (if_type <IF_COUNT ); +assert (if_type >=IF_DEFAULT ); + +return if_max_devs[if_type]; +}
if_max_devshas a specific obvious meaning withinblockdev.c, but outside it's not as obvious. So this function could use a rename.
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ok.
No, get rid of it. if_max_devs[]'s purpose is mapping between index and (bus, unit), no more. See below.
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blockdev.c +2
-1/* * We automatically delete the drive when a device using it gets * unplugged. Questionable feature, but we can't just drop it. @@ -518,7 +528,7 @@ DriveInfo *drive_init(QemuOpts *opts, int mach_if) }else {/* no id supplied -> create one */ dinfo->id =g_malloc0 (32 ); -if (type ==IF_IDE || type ==IF_SCSI ) +if (type ==IF_IDE || type ==IF_SCSI || type ==IF_AHCI ) mediastr = (media ==MEDIA_CDROM ) ?"-cd" :"-hd" ;if (max_devs) snprintf(dinfo->id, 32, "%s%i%s%i",@@ -550,6 +560,7 @@ DriveInfo *drive_init(QemuOpts *opts, int mach_if)switch (type) {case IF_IDE : +case IF_AHCI :case IF_SCSI :case IF_XEN :case IF_NONE :blockdev.h +2
-0@@ -21,6 +21,7 @@ typedef enum {IF_DEFAULT =-1 ,/* for use with drive_add() only */ IF_NONE ,IF_IDE ,IF_SCSI ,IF_FLOPPY ,IF_PFLASH ,IF_MTD ,IF_SD ,IF_VIRTIO ,IF_XEN , +IF_AHCI , IF_COUNT } BlockInterfaceType;@@ -56,6 +57,7 @@ static inline int get_mach_if(int mach_if)return mach_if; } +int get_if_max_devs (BlockInterfaceType if_type);DriveInfo *drive_get (BlockInterfaceType type,int bus,int unit);DriveInfo *drive_get_by_index (BlockInterfaceType type,int index);int drive_get_max_bus (BlockInterfaceType type);hw/ide.h +1
-0@@ -4,6 +4,7 @@#include "isa.h" #include "pci.h" #include "memory.h" +#include "blockdev.h" #define MAX_IDE_DEVS 2@@ -34,6 +35,11 @@ int ide_get_geometry(BusState *bus, int unit,int ide_get_bios_chs_trans (BusState *bus,int unit);
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hw/ide.h int ide_get_geometry(BusState *bus, int unit, · line 43
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hw/ide.h +5
-0/* ide/core.c */ +void ata_drive_get (DriveInfo **hd,int max_bus,BlockInterfaceType type);void ide_drive_get (DriveInfo **hd,int max_bus); +void ahci_drive_get (DriveInfo **hd,int max_bus); + +/* ide/ahci.c */ +void pci_ahci_create_devs (PCIDevice *pci_dev,DriveInfo **hd_table);
Shouldn't this go next to pci_ide_create_devs()'s declaration? Currently in hw/ide/pci.h.
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hw/ide.h +0
-0#endif /* HW_IDE_H */ hw/ide/ahci.c +10
-0@@ -26,6 +26,7 @@#include <hw/pc.h> #include <hw/pci.h> #include <hw/sysbus.h> +#include <blockdev.h> #include "monitor.h" #include "dma.h" @@ -1260,3 +1261,20 @@ static void sysbus_ahci_register_types(void) }type_init (sysbus_ahci_register_types) + +void pci_ahci_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table) +{ + struct AHCIPCIState *dev = DO_UPCAST(struct AHCIPCIState, card, pci_dev); +int i; +DriveInfo *drive; + +for (i =0 ; i < dev->ahci.ports; i++) { +if (hd_table[i] ==NULL ) {
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hw/ide/ahci.c static void sysbus_ahci_register_types(void) · line 1280
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hw/ide/ahci.c +8
-0+continue ; + } + drive = hd_table[i]; +assert (drive->type ==IF_AHCI ); +ide_create_drive (&dev->ahci.dev[i].port,0 , + hd_table[i]); + } +}
Shouldn't this go next to pci_ide_create_devs()'s definition? Currently in hw/ide/pci.c.
Consider adding a parameter for the number of elements in hd_table[], for robustness. As is, the caller has to ensure hd_table[] has at least dev->ahci.ports elements, which is not obvious from the function signature.
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hw/ide/core.c +0
-0@@ -2341,16 +2341,29 @@ const VMStateDescription vmstate_ide_bus = { } };Quoted 5 lines
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hw/ide/core.c const VMStateDescription vmstate_ide_bus = { · line 2344
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hw/ide/core.c +1
-1-void ide_drive_get (DriveInfo **hd,int max_bus) +void ata_drive_get (DriveInfo **hd,int max_bus,BlockInterfaceType type)Could be static?
Yes.
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hw/ide/core.c const VMStateDescription vmstate_ide_bus = { · line 2349
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hw/ide/core.c +3
-0{int i; +int max_devs; + +assert ((type ==IF_IDE ) || type ==IF_AHCI );Interesting use of brackets.
oops.
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hw/ide/core.c const VMStateDescription vmstate_ide_bus = { · line 2352
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hw/ide/core.c +1
-1-if (drive_get_max_bus (IF_IDE ) >= max_bus) { +if (drive_get_max_bus (type) >= max_bus) {fprintf (stderr,"qemu: too many IDE bus: %d\n" , max_bus);"Too many %s buses", type ==
IF_IDE? "IDE" : "AHCI"ok.
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hw/ide/core.c +5
-3exit (1 ); } - -for (i =0 ; i < max_bus *MAX_IDE_DEVS ; i++) { - hd[i] =drive_get (IF_IDE , i /MAX_IDE_DEVS , i %MAX_IDE_DEVS ); + max_devs =get_if_max_devs (type); +for (i =0 ; i < max_bus * max_devs; i++) { + hd[i] =drive_get (type, i / max_devs, i % max_devs); } } + +void ide_drive_get (DriveInfo **hd,int max_bus)
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hw/ide/core.c const VMStateDescription vmstate_ide_bus = { · line 2369
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hw/ide/core.c +8
-0+{ +ata_drive_get (hd, max_bus,IF_IDE ); +} + +void ahci_drive_get (DriveInfo **hd,int max_bus) +{ +ata_drive_get (hd, max_bus,IF_AHCI ); +}
For IDE, we always have two devices per bus. The boards number of buses varies in theory, and is always two in practice. Thus we have "#define MAX_IDE_DEVS 2" in ide.h, and "#define MAX_IDE_BUS 2" in all the <board>.c. The latter is passed to ide_drive_get() as parameter. Getting the well-known MAX_IDE_DEVS from get_if_max_devs() buys us nothing.
For AHCI, I figure we have a device-specific number of ports per device, and a board-specific number of devices (typically one). If there are multiple devices, they don't necessarily sport the same number of ports. Thus, a nested loop does not work.
Suggest
void ahci_drive_get(DriveInfo **hd, int bus, int max_ports)
which the board can call once for each device, with the device's true number of ports as argument. Look ma, no get_if_max_devs()!
Re: [Qemu-devel] [PATCH v3 02/26] blockdev: Introduce IF_AHCI
Quoted 26 lines · Markus Armbruster
Quoted 10 lines · Jason Baron
Quoted 9 lines · Kevin Wolf
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From: Jason Baron <[email protected]>
Introduce
IF_AHCIso that q35 can differentiate between ide and ahci disks. This allows q35 to specify its default disk type. It also allows q35 to differentiate between ahci and ide disks, such that -drive if=ide does not result in the creating of an ahci disk. This is important, since we don't want
to have the meaning of if=ide changing once q35 is introduced. Thus, its important for this to be applied before we introduce q35.This isn't the real argument for
IF_AHCI. The real argument is that the (bus, unit) namespace for if=ide makes no sense for AHCI.A board can have any number of IDE controllers. Each IDE controller provides one or two buses, and each bus takes up to two units. Together, we get a a board-specific number of buses, where each bus takes up to two units.
A board can have any number of AHCI controllers. Each AHCI controller provides a device-specific number of ports. Together, we get a board-specific number of buses, where each bus can takes a bus-specific number of units.
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Plain q35 doesn't really need to differentiate between IDE and AHCI; it has only AHCI. What it needs is a "one bus with six units" namespace.
We could fix this by relaxing if=ide's rigid "two units per bus" for new machine types.
You fix it by introducing if=ahci. Probably simpler. But what's the plan for the next generation of controller? Yet another interface type?
Next generation might require a new interface type. But taking you're suggestions, if=ahci is now machine dependent, so it shouldn't be so bad (see incremental patch at end).
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Note that SCSI suffers from similar rigidity: seven units per bus. That's fine for SCSI-1, but not for some of the other variants.
"Differentiate" comes into play when a board sports both AHCI and IDE controllers. Which q35 doesn't, does it?
Yes, there is no ide controller by default. That said i've used the piix-ide controller to install windows xp, for example, on q35.
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Then, the new if=ahci lets users select the kind of controller more easily than bus numbers would.
Drawback: existing command lines upgrade from pc to plain q35 gracefully only if they don't specify if=ide explicitly. Upgrading to some q35 variant with IDE controller on board is even worse: it works, but performance sucks. Some regard this as a feature.
well if=ide could give a warning on q35, suggesting using if=ahci, if we're not going to create an ide controller for if=ide (which I wasn't intending).
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This patch also adds:
pci_ahci_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table)Which provides a convient way of attaching ahci drives to an ahci controller.
Reviewed-by Paolo Bonzini <[email protected]>Signed-off-by Jason Baron <[email protected]>---
Kevin, could you review/ack this patch pls?
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blockdev.c | 13 ++++++++++++- blockdev.h | 2 ++ hw/ide.h | 6 ++++++ hw/ide/ahci.c | 18 ++++++++++++++++++ hw/ide/core.c | 23 ++++++++++++++++++----- 5 files changed, 56 insertions(+), 6 deletions(-)blockdev.c +1
-0@@ -33,6 +33,7 @@ static const char *const if_name[IF_COUNT] = { [IF_SD] = "sd", [IF_VIRTIO] = "virtio", [IF_XEN] = "xen", + [IF_AHCI] = "ahci", };Quoted 2 lines
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blockdev.c static const int if_max_devs[IF_COUNT] = {
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blockdev.c +0
-0static const int if_max_devs[IF_COUNT ] = {@@ -52,8 +53,17 @@ static const int if_max_devs[IF_COUNT] = {/*
* Do not change these numbers! They govern how drive option
* index maps to unit and bus. That mapping is ABI. *
* All controllers used to imlement if=T drives need to support
* if_max_devs[T] units, for any T with if_max_devs[T] != 0.
* Otherwise, some index values map to "impossible" bus, unit
* values.
*
* For instance, if you change [IF_SCSI] to 255, -drive
* if=scsi,index=12 no longer means bus=1,unit=5, but
* bus=0,unit=12. With an lsi53c895a controller (7 units max),
* the drive can't be set up. Regression.Quoted 12 lines
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blockdev.c static const int if_max_devs[IF_COUNT] = { · line 57
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blockdev.c +1
-0*/ [IF_IDE] = 2, [IF_SCSI] = 7, + [IF_AHCI] = 6, };What are the implications of this if we decided to add another AHCI controller which had a different number of ports? I suspect that a controller with less than 6 ports breaks when you add more drives than a single controller can handle, and one with more than 6 ports doesn't use up all of its ports before it adds another controller.
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Markus?
My plan was to make this field, machine dependent if/when we wanted a different size. I don't think it breaks anything to make this change at a later point. But please correct me, if I am wrong.
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I'm afraid you are. See the comment immediately above, and commit
27d6bf40.As far as I can see, the least bad solution is leaving if_max_devs[IF_AHCI] zero. Makes index=N an alias for unit=N,bus=0, and leaves rejecting invalid (bus,unit) to the board.
Ok. I've done that. And it makes if=ahci machine dependent.
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blockdev.c static const int if_max_devs[IF_COUNT] = { · line 64
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blockdev.c +7
-0+int get_if_max_devs (BlockInterfaceType if_type) +{ +assert (if_type <IF_COUNT ); +assert (if_type >=IF_DEFAULT ); + +return if_max_devs[if_type]; +}
if_max_devshas a specific obvious meaning withinblockdev.c, but outside it's not as obvious. So this function could use a rename.
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ok.
No, get rid of it. if_max_devs[]'s purpose is mapping between index and (bus, unit), no more. See below.
done.
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blockdev.c +2
-1/* * We automatically delete the drive when a device using it gets * unplugged. Questionable feature, but we can't just drop it. @@ -518,7 +528,7 @@ DriveInfo *drive_init(QemuOpts *opts, int mach_if) }else {/* no id supplied -> create one */ dinfo->id =g_malloc0 (32 ); -if (type ==IF_IDE || type ==IF_SCSI ) +if (type ==IF_IDE || type ==IF_SCSI || type ==IF_AHCI ) mediastr = (media ==MEDIA_CDROM ) ?"-cd" :"-hd" ;if (max_devs) snprintf(dinfo->id, 32, "%s%i%s%i",@@ -550,6 +560,7 @@ DriveInfo *drive_init(QemuOpts *opts, int mach_if)switch (type) {case IF_IDE : +case IF_AHCI :case IF_SCSI :case IF_XEN :case IF_NONE :blockdev.h +2
-0@@ -21,6 +21,7 @@ typedef enum {IF_DEFAULT =-1 ,/* for use with drive_add() only */ IF_NONE ,IF_IDE ,IF_SCSI ,IF_FLOPPY ,IF_PFLASH ,IF_MTD ,IF_SD ,IF_VIRTIO ,IF_XEN , +IF_AHCI , IF_COUNT } BlockInterfaceType;@@ -56,6 +57,7 @@ static inline int get_mach_if(int mach_if)return mach_if; } +int get_if_max_devs (BlockInterfaceType if_type);DriveInfo *drive_get (BlockInterfaceType type,int bus,int unit);DriveInfo *drive_get_by_index (BlockInterfaceType type,int index);int drive_get_max_bus (BlockInterfaceType type);hw/ide.h +1
-0@@ -4,6 +4,7 @@#include "isa.h" #include "pci.h" #include "memory.h" +#include "blockdev.h" #define MAX_IDE_DEVS 2@@ -34,6 +35,11 @@ int ide_get_geometry(BusState *bus, int unit,int ide_get_bios_chs_trans (BusState *bus,int unit);
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hw/ide.h int ide_get_geometry(BusState *bus, int unit, · line 43
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hw/ide.h +5
-0/* ide/core.c */ +void ata_drive_get (DriveInfo **hd,int max_bus,BlockInterfaceType type);void ide_drive_get (DriveInfo **hd,int max_bus); +void ahci_drive_get (DriveInfo **hd,int max_bus); + +/* ide/ahci.c */ +void pci_ahci_create_devs (PCIDevice *pci_dev,DriveInfo **hd_table);Shouldn't this go next to pci_ide_create_devs()'s declaration? Currently in
hw/ide/pci.h.
done.
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hw/ide.h +0
-0#endif /* HW_IDE_H */ hw/ide/ahci.c +10
-0@@ -26,6 +26,7 @@#include <hw/pc.h> #include <hw/pci.h> #include <hw/sysbus.h> +#include <blockdev.h> #include "monitor.h" #include "dma.h" @@ -1260,3 +1261,20 @@ static void sysbus_ahci_register_types(void) }type_init (sysbus_ahci_register_types) + +void pci_ahci_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table) +{ + struct AHCIPCIState *dev = DO_UPCAST(struct AHCIPCIState, card, pci_dev); +int i; +DriveInfo *drive; + +for (i =0 ; i < dev->ahci.ports; i++) { +if (hd_table[i] ==NULL ) {Quoted 8 lines
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hw/ide/ahci.c static void sysbus_ahci_register_types(void) · line 1280
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hw/ide/ahci.c +8
-0+continue ; + } + drive = hd_table[i]; +assert (drive->type ==IF_AHCI ); +ide_create_drive (&dev->ahci.dev[i].port,0 , + hd_table[i]); + } +}Shouldn't this go next to pci_ide_create_devs()'s definition? Currently in
hw/ide/pci.c.Consider adding a parameter for the number of elements in hd_table[], for robustness. As is, the caller has to ensure hd_table[] has at least
dev->ahci.portselements, which is not obvious from the function signature.Quoted 49 lines
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hw/ide/core.c +0
-0@@ -2341,16 +2341,29 @@ const VMStateDescription vmstate_ide_bus = { } };Quoted 5 lines
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hw/ide/core.c const VMStateDescription vmstate_ide_bus = { · line 2344
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hw/ide/core.c +1
-1-void ide_drive_get (DriveInfo **hd,int max_bus) +void ata_drive_get (DriveInfo **hd,int max_bus,BlockInterfaceType type)Could be static?
Yes.
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hw/ide/core.c const VMStateDescription vmstate_ide_bus = { · line 2349
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hw/ide/core.c +3
-0{int i; +int max_devs; + +assert ((type ==IF_IDE ) || type ==IF_AHCI );Interesting use of brackets.
oops.
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hw/ide/core.c const VMStateDescription vmstate_ide_bus = { · line 2351
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hw/ide/core.c +1
-1-if (drive_get_max_bus (IF_IDE ) >= max_bus) { +if (drive_get_max_bus (type) >= max_bus) {fprintf (stderr,"qemu: too many IDE bus: %d\n" , max_bus);"Too many %s buses", type ==
IF_IDE? "IDE" : "AHCI"ok.
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hw/ide/core.c +5
-3exit (1 ); } - -for (i =0 ; i < max_bus *MAX_IDE_DEVS ; i++) { - hd[i] =drive_get (IF_IDE , i /MAX_IDE_DEVS , i %MAX_IDE_DEVS ); + max_devs =get_if_max_devs (type); +for (i =0 ; i < max_bus * max_devs; i++) { + hd[i] =drive_get (type, i / max_devs, i % max_devs); } } + +void ide_drive_get (DriveInfo **hd,int max_bus)Quoted 8 lines
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hw/ide/core.c const VMStateDescription vmstate_ide_bus = { · line 2368
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hw/ide/core.c +8
-0+{ +ata_drive_get (hd, max_bus,IF_IDE ); +} + +void ahci_drive_get (DriveInfo **hd,int max_bus) +{ +ata_drive_get (hd, max_bus,IF_AHCI ); +}For IDE, we always have two devices per bus. The boards number of buses varies in theory, and is always two in practice. Thus we have "#define
MAX_IDE_DEVS2" inide.h, and "#defineMAX_IDE_BUS2" in all the <board>.c. The latter is passed toide_drive_get()as parameter. Getting the well-knownMAX_IDE_DEVSfromget_if_max_devs()buys us nothing.For AHCI, I figure we have a device-specific number of ports per device, and a board-specific number of devices (typically one). If there are multiple devices, they don't necessarily sport the same number of ports. Thus, a nested loop does not work.
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Suggest
void
ahci_drive_get(DriveInfo **hd, int bus, int max_ports)which the board can call once for each device, with the device's true number of ports as argument. Look ma, no
get_if_max_devs()!
Agreed.
So here is an incremental patch. If its too hard to read I'll send a full diff - I'd like to include something like this in my next q35 series. thoughts?
Thanks,
-Jason
blockdev.c +15 -9
@@ -53,17 +53,9 @@ static const int if_max_devs[IF_COUNT] = { */ [IF_IDE] = 2, [IF_SCSI] = 7, - [IF_AHCI] = 6, + [IF_AHCI] = 0, }; -int get_if_max_devs (BlockInterfaceType if_type) -{ -assert (if_type <IF_COUNT ); -assert (if_type >=IF_DEFAULT ); - -return if_max_devs[if_type]; -} -/* * We automatically delete the drive when a device using it gets * unplugged. Questionable feature, but we can't just drop it.
@@ -168,6 +160,20 @@ int drive_get_max_bus(BlockInterfaceType type)return max_bus; } +int drive_get_max_unit (BlockInterfaceType type) +{ +int max_unit; +DriveInfo *dinfo; + + max_unit =-1 ; + QTAILQ_FOREACH(dinfo, &drives, next) { +if (dinfo->type == type && + dinfo->unit > max_unit) + max_unit = dinfo->unit; + } +return max_unit; +} +/* Get a block device. This should only be used for single-drive devices (e.g. SD/Floppy/MTD). Multi-disk devices (scsi/ide) should use the appropriate bus. */
blockdev.h +1 -0
@@ -61,6 +61,7 @@ int get_if_max_devs(BlockInterfaceType if_type);DriveInfo *drive_get (BlockInterfaceType type,int bus,int unit);DriveInfo *drive_get_by_index (BlockInterfaceType type,int index);int drive_get_max_bus (BlockInterfaceType type); +int drive_get_max_unit (BlockInterfaceType type);DriveInfo *drive_get_next (BlockInterfaceType type);void drive_get_ref (DriveInfo *dinfo);void drive_put_ref (DriveInfo *dinfo);
hw/ide.h +1 -5
@@ -35,11 +35,7 @@ int ide_get_geometry(BusState *bus, int unit,int ide_get_bios_chs_trans (BusState *bus,int unit);/* ide/core.c */ -void ata_drive_get (DriveInfo **hd,int max_bus,BlockInterfaceType type);void ide_drive_get (DriveInfo **hd,int max_bus); -void ahci_drive_get (DriveInfo **hd,int max_bus); - -/* ide/ahci.c */ -void pci_ahci_create_devs (PCIDevice *pci_dev,DriveInfo **hd_table); +void ahci_drive_get (DriveInfo **hd,int max_bus,int max_ports);#endif /* HW_IDE_H */
hw/ide/ahci.c +0 -17
@@ -1261,20 +1261,3 @@ static void sysbus_ahci_register_types(void) }type_init (sysbus_ahci_register_types) - -void pci_ahci_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table) -{ - struct AHCIPCIState *dev = DO_UPCAST(struct AHCIPCIState, card, pci_dev); -int i; -DriveInfo *drive; - -for (i =0 ; i < dev->ahci.ports; i++) { -if (hd_table[i] ==NULL ) { -continue ; - } - drive = hd_table[i]; -assert (drive->type ==IF_AHCI ); -ide_create_drive (&dev->ahci.dev[i].port,0 , - hd_table[i]); - } -}
hw/ide/core.c +7 -8
@@ -2341,18 +2341,17 @@ const VMStateDescription vmstate_ide_bus = { } }; -void ata_drive_get (DriveInfo **hd,int max_bus,BlockInterfaceType type) +static void ata_drive_get (DriveInfo **hd,int max_bus,int max_devs, +BlockInterfaceType type) {int i; -int max_devs; -assert ((type ==IF_IDE ) || type ==IF_AHCI ); +assert ((type ==IF_IDE ) || (type ==IF_AHCI )); -if (drive_get_max_bus (type) >= max_bus) { +if ((type ==IF_IDE ) && (drive_get_max_bus (type) >= max_bus)) {fprintf (stderr,"qemu: too many IDE bus: %d\n" , max_bus);exit (1 ); } - max_devs =get_if_max_devs (type);for (i =0 ; i < max_bus * max_devs; i++) { hd[i] =drive_get (type, i / max_devs, i % max_devs); }
@@ -2360,10 +2359,10 @@ void ata_drive_get(DriveInfo **hd, int max_bus, BlockInterfaceType type)void ide_drive_get (DriveInfo **hd,int max_bus) { -ata_drive_get (hd, max_bus,IF_IDE ); +ata_drive_get (hd, max_bus,MAX_IDE_DEVS ,IF_IDE ); } -void ahci_drive_get (DriveInfo **hd,int max_bus) +void ahci_drive_get (DriveInfo **hd,int max_bus,int max_ports) { -ata_drive_get (hd, max_bus,IF_AHCI ); +ata_drive_get (hd, max_bus, max_ports,IF_AHCI ); }
hw/ide/pci.c +19 -0
@@ -30,6 +30,7 @@#include "dma.h" #include <hw/ide/pci.h> +#include <hw/ide/ahci.h> #define BMDMA_PAGE_SIZE 4096
@@ -504,6 +505,24 @@ void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table) } } + +void pci_ahci_create_devs (PCIDevice *pci_dev,DriveInfo **hd_table,int table_size) +{ + struct AHCIPCIState *dev = DO_UPCAST(struct AHCIPCIState, card, pci_dev); +int i; +DriveInfo *drive; + +for (i =0 ; i < table_size; i++) { +if (hd_table[i] ==NULL ) { +continue ; + } + drive = hd_table[i]; +assert (drive->type ==IF_AHCI ); +ide_create_drive (&dev->ahci.dev[i].port,0 , + hd_table[i]); + } +} +static const struct IDEDMAOps bmdma_ops = { .start_dma = bmdma_start_dma, .start_transfer = bmdma_start_transfer,
hw/ide/pci.h +2 -0
@@ -58,6 +58,8 @@ void bmdma_init(IDEBus *bus, BMDMAState *bm, PCIIDEState *d);void bmdma_cmd_writeb (BMDMAState *bm,uint32_t val);extern MemoryRegionOps bmdma_addr_ioport_ops;void pci_ide_create_devs (PCIDevice *dev,DriveInfo **hd_table); +void pci_ahci_create_devs (PCIDevice *pci_dev,DriveInfo **hd_table,int table_size); +extern const VMStateDescription vmstate_ide_pci;#endif
Re: [Qemu-devel] [PATCH v3 02/26] blockdev: Introduce IF_AHCI
Quoted 43 lines · Jason Baron
Quoted 28 lines · Markus Armbruster
Quoted 12 lines · Jason Baron
Quoted 11 lines · Kevin Wolf
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From: Jason Baron <[email protected]>
Introduce
IF_AHCIso that q35 can differentiate between ide and ahci disks.
This allows q35 to specify its default disk type. It also allows q35 to differentiate between ahci and ide disks, such that -drive if=ide does not
result in the creating of an ahci disk. This is important, since we don't want
to have the meaning of if=ide changing once q35 is introduced. Thus, its important for this to be applied before we introduce q35.This isn't the real argument for
IF_AHCI. The real argument is that the (bus, unit) namespace for if=ide makes no sense for AHCI.A board can have any number of IDE controllers. Each IDE controller provides one or two buses, and each bus takes up to two units. Together, we get a a board-specific number of buses, where each bus takes up to two units.
A board can have any number of AHCI controllers. Each AHCI controller provides a device-specific number of ports. Together, we get a board-specific number of buses, where each bus can takes a bus-specific number of units.
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Plain q35 doesn't really need to differentiate between IDE and AHCI; it has only AHCI. What it needs is a "one bus with six units" namespace.
We could fix this by relaxing if=ide's rigid "two units per bus" for new machine types.
You fix it by introducing if=ahci. Probably simpler. But what's the plan for the next generation of controller? Yet another interface type?
Next generation might require a new interface type. But taking you're suggestions, if=ahci is now machine dependent, so it shouldn't be so bad (see incremental patch at end).
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Note that SCSI suffers from similar rigidity: seven units per bus. That's fine for SCSI-1, but not for some of the other variants.
"Differentiate" comes into play when a board sports both AHCI and IDE controllers. Which q35 doesn't, does it?
Yes, there is no ide controller by default. That said i've used the piix-ide controller to install windows xp, for example, on q35.
Sure, but only default controllers matter when it comes to -drive with if!=none.
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Then, the new if=ahci lets users select the kind of controller more easily than bus numbers would.
Drawback: existing command lines upgrade from pc to plain q35 gracefully only if they don't specify if=ide explicitly. Upgrading to some q35 variant with IDE controller on board is even worse: it works, but performance sucks. Some regard this as a feature.
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well if=ide could give a warning on q35, suggesting using if=ahci, if we're not going to create an ide controller for if=ide (which I wasn't intending).
Sounds helpful.
We should find warn about -drive with if!=none the board doesn't use in general. Extra points for a special warning for pointing to if=ahci in cases where it makes sense.
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This patch also adds:
pci_ahci_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table)Which provides a convient way of attaching ahci drives to an ahci controller.
Reviewed-by Paolo Bonzini <[email protected]>Signed-off-by Jason Baron <[email protected]>---
Kevin, could you review/ack this patch pls?
Quoted 18 lines
blockdev.c | 13 ++++++++++++- blockdev.h | 2 ++ hw/ide.h | 6 ++++++ hw/ide/ahci.c | 18 ++++++++++++++++++ hw/ide/core.c | 23 ++++++++++++++++++----- 5 files changed, 56 insertions(+), 6 deletions(-)blockdev.c +1
-0@@ -33,6 +33,7 @@ static const char *const if_name[IF_COUNT] = { [IF_SD] = "sd", [IF_VIRTIO] = "virtio", [IF_XEN] = "xen", + [IF_AHCI] = "ahci", };Quoted 2 lines
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blockdev.c static const int if_max_devs[IF_COUNT] = {
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blockdev.c +0
-0static const int if_max_devs[IF_COUNT ] = {@@ -52,8 +53,17 @@ static const int if_max_devs[IF_COUNT] = {/*
* Do not change these numbers! They govern how drive option
* index maps to unit and bus. That mapping is ABI. *
* All controllers used to imlement if=T drives need to support
* if_max_devs[T] units, for any T with if_max_devs[T] != 0.
* Otherwise, some index values map to "impossible" bus, unit
* values.
*
* For instance, if you change [IF_SCSI] to 255, -drive
* if=scsi,index=12 no longer means bus=1,unit=5, but
* bus=0,unit=12. With an lsi53c895a controller (7 units max),
* the drive can't be set up. Regression.Quoted 12 lines
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blockdev.c static const int if_max_devs[IF_COUNT] = { · line 57
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blockdev.c +1
-0*/ [IF_IDE] = 2, [IF_SCSI] = 7, + [IF_AHCI] = 6, };What are the implications of this if we decided to add another AHCI controller which had a different number of ports? I suspect that a controller with less than 6 ports breaks when you add more drives than a single controller can handle, and one with more than 6 ports doesn't use up all of its ports before it adds another controller.
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Markus?
My plan was to make this field, machine dependent if/when we wanted a different
size. I don't think it breaks anything to make this change at a later point. But please correct me, if I am wrong.I'm afraid you are. See the comment immediately above, and commit
27d6bf40.
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As far as I can see, the least bad solution is leaving if_max_devs[IF_AHCI] zero. Makes index=N an alias for unit=N,bus=0, and leaves rejecting invalid (bus,unit) to the board.
Ok. I've done that. And it makes if=ahci machine dependent.
Uh, in what sense?
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blockdev.c static const int if_max_devs[IF_COUNT] = { · line 64
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blockdev.c +7
-0+int get_if_max_devs (BlockInterfaceType if_type) +{ +assert (if_type <IF_COUNT ); +assert (if_type >=IF_DEFAULT ); + +return if_max_devs[if_type]; +}
if_max_devshas a specific obvious meaning withinblockdev.c, but outside it's not as obvious. So this function could use a rename.Quoted 5 lines
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ok.
No, get rid of it. if_max_devs[]'s purpose is mapping between index and (bus, unit), no more. See below.
done.
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blockdev.c +2
-1/* * We automatically delete the drive when a device using it gets * unplugged. Questionable feature, but we can't just drop it. @@ -518,7 +528,7 @@ DriveInfo *drive_init(QemuOpts *opts, int mach_if) }else {/* no id supplied -> create one */ dinfo->id =g_malloc0 (32 ); -if (type ==IF_IDE || type ==IF_SCSI ) +if (type ==IF_IDE || type ==IF_SCSI || type ==IF_AHCI ) mediastr = (media ==MEDIA_CDROM ) ?"-cd" :"-hd" ;if (max_devs) snprintf(dinfo->id, 32, "%s%i%s%i",@@ -550,6 +560,7 @@ DriveInfo *drive_init(QemuOpts *opts, int mach_if)switch (type) {case IF_IDE : +case IF_AHCI :case IF_SCSI :case IF_XEN :case IF_NONE :blockdev.h +2
-0@@ -21,6 +21,7 @@ typedef enum {IF_DEFAULT =-1 ,/* for use with drive_add() only */ IF_NONE ,IF_IDE ,IF_SCSI ,IF_FLOPPY ,IF_PFLASH ,IF_MTD ,IF_SD ,IF_VIRTIO ,IF_XEN , +IF_AHCI , IF_COUNT } BlockInterfaceType;@@ -56,6 +57,7 @@ static inline int get_mach_if(int mach_if)return mach_if; } +int get_if_max_devs (BlockInterfaceType if_type);DriveInfo *drive_get (BlockInterfaceType type,int bus,int unit);DriveInfo *drive_get_by_index (BlockInterfaceType type,int index);int drive_get_max_bus (BlockInterfaceType type);hw/ide.h +1
-0@@ -4,6 +4,7 @@#include "isa.h" #include "pci.h" #include "memory.h" +#include "blockdev.h" #define MAX_IDE_DEVS 2@@ -34,6 +35,11 @@ int ide_get_geometry(BusState *bus, int unit,int ide_get_bios_chs_trans (BusState *bus,int unit);Quoted 11 lines
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hw/ide.h int ide_get_geometry(BusState *bus, int unit, · line 43
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hw/ide.h +5
-0/* ide/core.c */ +void ata_drive_get (DriveInfo **hd,int max_bus,BlockInterfaceType type);void ide_drive_get (DriveInfo **hd,int max_bus); +void ahci_drive_get (DriveInfo **hd,int max_bus); + +/* ide/ahci.c */ +void pci_ahci_create_devs (PCIDevice *pci_dev,DriveInfo **hd_table);Shouldn't this go next to pci_ide_create_devs()'s declaration? Currently in
hw/ide/pci.h.done.
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hw/ide.h +0
-0#endif /* HW_IDE_H */ hw/ide/ahci.c +5
-0@@ -26,6 +26,7 @@#include <hw/pc.h> #include <hw/pci.h> #include <hw/sysbus.h> +#include <blockdev.h> #include "monitor.h" #include "dma.h" @@ -1260,3 +1261,20 @@ static void sysbus_ahci_register_types(void) }type_init (sysbus_ahci_register_types) + +void pci_ahci_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table) +{ + struct AHCIPCIState *dev = DO_UPCAST(struct AHCIPCIState,card,
pci_dev);hw/ide/ahci.c +5
-0+int i; +DriveInfo *drive; + +for (i =0 ; i < dev->ahci.ports; i++) { +if (hd_table[i] ==NULL ) {Quoted 8 lines
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hw/ide/ahci.c
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hw/ide/ahci.c +8
-0+continue ; + } + drive = hd_table[i]; +assert (drive->type ==IF_AHCI ); +ide_create_drive (&dev->ahci.dev[i].port,0 , + hd_table[i]); + } +}Shouldn't this go next to pci_ide_create_devs()'s definition? Currently in
hw/ide/pci.c.Consider adding a parameter for the number of elements in hd_table[], for robustness. As is, the caller has to ensure hd_table[] has at least
dev->ahci.portselements, which is not obvious from the function signature.Quoted 49 lines
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hw/ide/core.c +0
-0@@ -2341,16 +2341,29 @@ const VMStateDescription vmstate_ide_bus = { } };Quoted 5 lines
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hw/ide/core.c const VMStateDescription vmstate_ide_bus = { · line 2344
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hw/ide/core.c +1
-1-void ide_drive_get (DriveInfo **hd,int max_bus) +void ata_drive_get (DriveInfo **hd,int max_bus,BlockInterfaceType type)Could be static?
Yes.
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hw/ide/core.c const VMStateDescription vmstate_ide_bus = { · line 2349
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hw/ide/core.c +3
-0{int i; +int max_devs; + +assert ((type ==IF_IDE ) || type ==IF_AHCI );Interesting use of brackets.
oops.
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hw/ide/core.c const VMStateDescription vmstate_ide_bus = { · line 2351
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hw/ide/core.c +1
-1-if (drive_get_max_bus (IF_IDE ) >= max_bus) { +if (drive_get_max_bus (type) >= max_bus) {fprintf (stderr,"qemu: too many IDE bus: %d\n" , max_bus);"Too many %s buses", type ==
IF_IDE? "IDE" : "AHCI"ok.
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hw/ide/core.c +5
-3exit (1 ); } - -for (i =0 ; i < max_bus *MAX_IDE_DEVS ; i++) { - hd[i] =drive_get (IF_IDE , i /MAX_IDE_DEVS , i %MAX_IDE_DEVS ); + max_devs =get_if_max_devs (type); +for (i =0 ; i < max_bus * max_devs; i++) { + hd[i] =drive_get (type, i / max_devs, i % max_devs); } } + +void ide_drive_get (DriveInfo **hd,int max_bus)Quoted 8 lines
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hw/ide/core.c const VMStateDescription vmstate_ide_bus = { · line 2368
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hw/ide/core.c +8
-0+{ +ata_drive_get (hd, max_bus,IF_IDE ); +} + +void ahci_drive_get (DriveInfo **hd,int max_bus) +{ +ata_drive_get (hd, max_bus,IF_AHCI ); +}For IDE, we always have two devices per bus. The boards number of buses varies in theory, and is always two in practice. Thus we have "#define
MAX_IDE_DEVS2" inide.h, and "#defineMAX_IDE_BUS2" in all the <board>.c. The latter is passed toide_drive_get()as parameter. Getting the well-knownMAX_IDE_DEVSfromget_if_max_devs()buys us nothing.For AHCI, I figure we have a device-specific number of ports per device, and a board-specific number of devices (typically one). If there are multiple devices, they don't necessarily sport the same number of ports. Thus, a nested loop does not work.
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Suggest
void
ahci_drive_get(DriveInfo **hd, int bus, int max_ports)which the board can call once for each device, with the device's true number of ports as argument. Look ma, no
get_if_max_devs()!Agreed.
So here is an incremental patch. If its too hard to read I'll send a full diff - I'd like to include something like this in my next q35 series. thoughts?
Thanks,
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-1-Jasonblockdev.c +0
-0
blockdev.c static const int if_max_devs[IF_COUNT] = { · line 57
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blockdev.c +1
-1@@ -53,17 +53,9 @@ static const int if_max_devs[IF_COUNT] = { */ [IF_IDE] = 2, [IF_SCSI] = 7, - [IF_AHCI] = 6, + [IF_AHCI] = 0, };
Consider dropping the IF_AHCI line, for consistency with the other interface types that want zero value here.
Quoted 20 lines
blockdev.c +4
-8-int get_if_max_devs (BlockInterfaceType if_type) -{ -assert (if_type <IF_COUNT ); -assert (if_type >=IF_DEFAULT ); - -return if_max_devs[if_type]; -} -/* * We automatically delete the drive when a device using it gets * unplugged. Questionable feature, but we can't just drop it. @@ -168,6 +160,20 @@ int drive_get_max_bus(BlockInterfaceType type)return max_bus; } +int drive_get_max_unit (BlockInterfaceType type) +{ +int max_unit; +DriveInfo *dinfo;
blockdev.c int drive_get_max_bus(BlockInterfaceType type) · line 176
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blockdev.c +10
-0+ + max_unit =-1 ; + QTAILQ_FOREACH(dinfo, &drives, next) { +if (dinfo->type == type && + dinfo->unit > max_unit) + max_unit = dinfo->unit; + } +return max_unit; +} +
This returns the largest unit number on any bus. Wouldn't a function to return the largest unit number on a specific bus (given by parameter int bus) be more useful?
Anyway, there's so caller, yet. Suggest to drop until it's needed.
Oh, maybe you need it to call your ahci_drive_get(). Patch doesn't include that part.
hw/ide.h
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blockdev.c +0
-0/* Get a block device. This should only be used for single-drive devices (e.g. SD/Floppy/MTD). Multi-disk devices (scsi/ide) should use the appropriate bus. */ blockdev.h +1
-0@@ -61,6 +61,7 @@ int get_if_max_devs(BlockInterfaceType if_type);DriveInfo *drive_get (BlockInterfaceType type,int bus,int unit);DriveInfo *drive_get_by_index (BlockInterfaceType type,int index);int drive_get_max_bus (BlockInterfaceType type); +int drive_get_max_unit (BlockInterfaceType type);DriveInfo *drive_get_next (BlockInterfaceType type);void drive_get_ref (DriveInfo *dinfo);void drive_put_ref (DriveInfo *dinfo);hw/ide.h +0
-0
Suspect you can also back out he hunk adding #include "blockdev.h".
Quoted 69 lines
hw/ide.h +1
-5@@ -35,11 +35,7 @@ int ide_get_geometry(BusState *bus, int unit,int ide_get_bios_chs_trans (BusState *bus,int unit);/* ide/core.c */ -void ata_drive_get (DriveInfo **hd,int max_bus,BlockInterfaceType type);void ide_drive_get (DriveInfo **hd,int max_bus); -void ahci_drive_get (DriveInfo **hd,int max_bus); - -/* ide/ahci.c */ -void pci_ahci_create_devs (PCIDevice *pci_dev,DriveInfo **hd_table); +void ahci_drive_get (DriveInfo **hd,int max_bus,int max_ports);#endif /* HW_IDE_H */ hw/ide/ahci.c +0
-17@@ -1261,20 +1261,3 @@ static void sysbus_ahci_register_types(void) }type_init (sysbus_ahci_register_types) - -void pci_ahci_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table) -{ - struct AHCIPCIState *dev = DO_UPCAST(struct AHCIPCIState, card, pci_dev); -int i; -DriveInfo *drive; - -for (i =0 ; i < dev->ahci.ports; i++) { -if (hd_table[i] ==NULL ) { -continue ; - } - drive = hd_table[i]; -assert (drive->type ==IF_AHCI ); -ide_create_drive (&dev->ahci.dev[i].port,0 , - hd_table[i]); - } -}hw/ide/core.c +4
-5@@ -2341,18 +2341,17 @@ const VMStateDescription vmstate_ide_bus = { } }; -void ata_drive_get (DriveInfo **hd,int max_bus,BlockInterfaceType type) +static void ata_drive_get (DriveInfo **hd,int max_bus,int max_devs, +BlockInterfaceType type) {int i; -int max_devs; -assert ((type ==IF_IDE ) || type ==IF_AHCI ); +assert ((type ==IF_IDE ) || (type ==IF_AHCI )); -if (drive_get_max_bus (type) >= max_bus) { +if ((type ==IF_IDE ) && (drive_get_max_bus (type) >= max_bus)) {fprintf (stderr,"qemu: too many IDE bus: %d\n" , max_bus);exit (1 ); } - max_devs =get_if_max_devs (type);for (i =0 ; i < max_bus * max_devs; i++) { hd[i] =drive_get (type, i / max_devs, i % max_devs); }@@ -2360,10 +2359,10 @@ void ata_drive_get(DriveInfo **hd, int max_bus, BlockInterfaceType type)void ide_drive_get (DriveInfo **hd,int max_bus) {
hw/ide/core.c void ata_drive_get(DriveInfo **hd, int max_bus, BlockInterfaceType type) · line 2368
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hw/ide/core.c +3
-3-ata_drive_get (hd, max_bus,IF_IDE ); +ata_drive_get (hd, max_bus,MAX_IDE_DEVS ,IF_IDE ); } -void ahci_drive_get (DriveInfo **hd,int max_bus) +void ahci_drive_get (DriveInfo **hd,int max_bus,int max_ports) { -ata_drive_get (hd, max_bus,IF_AHCI ); +ata_drive_get (hd, max_bus, max_ports,IF_AHCI ); }
Looks like this now:
static void ata_drive_get(DriveInfo **hd, int max_bus, int max_devs,
BlockInterfaceType type)
{
int i;
assert((type == IF_IDE) || (type == IF_AHCI));
if ((type == IF_IDE) && (drive_get_max_bus(type) >= max_bus)) {
fprintf(stderr, "qemu: too many IDE bus: %d\n", max_bus);
exit(1);
}
for (i = 0; i < max_bus * max_devs; i++) {
hd[i] = drive_get(type, i / max_devs, i % max_devs);
}
}void ide_drive_get(DriveInfo **hd, int max_bus)
{
ata_drive_get(hd, max_bus, MAX_IDE_DEVS, IF_IDE);
}void ahci_drive_get(DriveInfo **hd, int max_bus, int max_ports)
{
ata_drive_get(hd, max_bus, max_ports, IF_AHCI);
}What I had in mind is this:
void ide_drive_get(DriveInfo **hd, int max_bus)
{
int i;
if (drive_get_max_bus(IF_IDE) >= max_bus) {
fprintf(stderr, "qemu: too many IDE bus: %d\n", max_bus);
exit(1);
}
for(i = 0; i < max_bus * MAX_IDE_DEVS; i++) {
hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
}
}void ahci_drive_get(DriveInfo **hd, int bus, int nports)
{
for(i = 0; i < nports; i++) {
hd[i] = drive_get(IF_IDE, bus, i);
}
}ide_drive_get() is unchanged.
The board knows exactly how many AHCI controllers it creates, and how many ports they have. Say it creates two, one with 6 ports, the other with eight. It can get the drives like this:
DriveInfo *hd0[6], *hd1[8];
ahci_drive_get(hd0, 0, ARRAY_SIZE(hd0));
ahci_drive_get(hd1, 1, ARRAY_SIZE(hd1));Quoted 21 lines
hw/ide/pci.c +6
-0@@ -30,6 +30,7 @@#include "dma.h" #include <hw/ide/pci.h> +#include <hw/ide/ahci.h> #define BMDMA_PAGE_SIZE 4096@@ -504,6 +505,24 @@ void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table) } } + +void pci_ahci_create_devs (PCIDevice *pci_dev,DriveInfo **hd_table,int table_size) +{ + struct AHCIPCIState *dev = DO_UPCAST(struct AHCIPCIState, card, pci_dev); +int i;
hw/ide/pci.c void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table) · line 522
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hw/ide/pci.c +10
-0+DriveInfo *drive; + +for (i =0 ; i < table_size; i++) { +if (hd_table[i] ==NULL ) { +continue ; + } + drive = hd_table[i]; +assert (drive->type ==IF_AHCI ); +ide_create_drive (&dev->ahci.dev[i].port,0 , + hd_table[i]);
Note that the drive with bus=b,unit=u is connected to the b-th AHCI controller's u-th IDE bus. I'm *not* objecting to that, because I think -drive makes little sense, and improving it is a lost cause.
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hw/ide/pci.c +3
-0+ } +} +static const struct IDEDMAOps bmdma_ops = { .start_dma = bmdma_start_dma, .start_transfer = bmdma_start_transfer,hw/ide/pci.h +2
-0@@ -58,6 +58,8 @@ void bmdma_init(IDEBus *bus, BMDMAState *bm, PCIIDEState *d);void bmdma_cmd_writeb (BMDMAState *bm,uint32_t val);extern MemoryRegionOps bmdma_addr_ioport_ops;void pci_ide_create_devs (PCIDevice *dev,DriveInfo **hd_table); +void pci_ahci_create_devs (PCIDevice *pci_dev,DriveInfo **hd_table,int table_size); +extern const VMStateDescription vmstate_ide_pci;#endif
PATCH v3 3/26 pci: pci capability must be in PCI space
In reply to Jason BaronFrom: Isaku Yamahata <[email protected]>
pci capability must be in PCI space.
It can't lay in PCIe extended config space.
--- hw/pci.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-)
hw/pci.c +3 -3
@@ -1644,16 +1644,16 @@ PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)return pci_create_simple_multifunction (bus, devfn, false, name); } -static int pci_find_space (PCIDevice *pdev,uint8_t size) +static uint8_t pci_find_space (PCIDevice *pdev,uint8_t size) { -int config_size =pci_config_size (pdev);int offset =PCI_CONFIG_HEADER_SIZE ;int i; -for (i =PCI_CONFIG_HEADER_SIZE ; i < config_size; ++i) +for (i =PCI_CONFIG_HEADER_SIZE ; i <PCI_CONFIG_SPACE_SIZE ; ++i) {if (pdev->used[i]) offset = i +1 ;else if (i - offset +1 == size)return offset; + }return 0 ; }
Signature · 1 line
1.7.1
Michael S. Tsirkin
AppliedRe: [Qemu-devel] [PATCH v3 03/26] pci: pci capability must be in PCI space
Quoted 8 lines · Jason Baron
From: Isaku Yamahata <[email protected]>
pci capability must be in PCI space.
It can't lay in PCIe extended config space.Reviewed-by Paolo Bonzini <[email protected]>Signed-off-by Isaku Yamahata <[email protected]>Signed-off-by Jason Baron <[email protected]>
Applied, thanks!
Quoted 30 lines
--- hw/pci.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-)hw/pci.c +3
-3@@ -1644,16 +1644,16 @@ PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)return pci_create_simple_multifunction (bus, devfn, false, name); } -static int pci_find_space (PCIDevice *pdev,uint8_t size) +static uint8_t pci_find_space (PCIDevice *pdev,uint8_t size) { -int config_size =pci_config_size (pdev);int offset =PCI_CONFIG_HEADER_SIZE ;int i; -for (i =PCI_CONFIG_HEADER_SIZE ; i < config_size; ++i) +for (i =PCI_CONFIG_HEADER_SIZE ; i <PCI_CONFIG_SPACE_SIZE ; ++i) {if (pdev->used[i]) offset = i +1 ;else if (i - offset +1 == size)return offset; + }return 0 ; }Signature · 1 line
1.7.1
PATCH v3 4/26 pci: introduce pci_swizzle_map_irq_fn() for standardized interrupt pin swizzle
In reply to Jason BaronFrom: Isaku Yamahata <[email protected]>
Introduce pci_swizzle_map_irq_fn() for interrupt pin swizzle which is standardized. PCI bridge swizzle is common logic, by introducing this function duplicated swizzle logic will be avoided later.
--- hw/pci.c | 18 ++++++++++++++++++ hw/pci.h | 2 ++ 2 files changed, 20 insertions(+), 0 deletions(-)
hw/pci.c +18 -0
@@ -1121,6 +1121,24 @@ void pci_device_set_intx_routing_notifier(PCIDevice *dev, dev->intx_routing_notifier = notifier; } +/* +* PCI-to-PCI bridge specification +* 9.1: Interrupt routing. Table 9-1 +* +* the PCI Express Base Specification, Revision 2.1 +* 2.2.8.1: INTx interrutp signaling - Rules +* the Implementation Note +* Table 2-20 +*/ +/* +* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD +* 0-origin unlike PCI interrupt pin register. +*/ +int pci_swizzle_map_irq_fn (PCIDevice *pci_dev,int pin) +{ +return (pin +PCI_SLOT (pci_dev->devfn)) %PCI_NUM_PINS ; +} +/***********************************************************/ /* monitor info on PCI */
hw/pci.h +2 -0
@@ -316,6 +316,8 @@ void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, void *irq_opaque, int nirq);int pci_bus_get_irq_level (PCIBus *bus,int irq_num);void pci_bus_hotplug (PCIBus *bus,pci_hotplug_fn hotplug,DeviceState *dev); +/* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */ +int pci_swizzle_map_irq_fn (PCIDevice *pci_dev,int pin); PCIBus *pci_register_bus(DeviceState *parent, const char *name, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, void *irq_opaque,
Signature · 1 line
1.7.1
Michael S. Tsirkin
AppliedRe: [Qemu-devel] [PATCH v3 04/26] pci: introduce pci_swizzle_map_irq_fn() for standardized interrupt pin swizzle
Quoted 10 lines · Jason Baron
From: Isaku Yamahata <[email protected]>
Introduce
pci_swizzle_map_irq_fn()for interrupt pin swizzle which is standardized. PCI bridge swizzle is common logic, by introducing this function duplicated swizzle logic will be avoided later.[[email protected]: drop opaque argument]Reviewed-by Paolo Bonzini <[email protected]>Signed-off-by Isaku Yamahata <[email protected]>Signed-off-by Jason Baron <[email protected]>
Applied, thanks.
Quoted 49 lines
--- hw/pci.c | 18 ++++++++++++++++++ hw/pci.h | 2 ++ 2 files changed, 20 insertions(+), 0 deletions(-)hw/pci.c +18
-0@@ -1121,6 +1121,24 @@ void pci_device_set_intx_routing_notifier(PCIDevice *dev, dev->intx_routing_notifier = notifier; } +/* +* PCI-to-PCI bridge specification +* 9.1: Interrupt routing. Table 9-1 +* +* the PCI Express Base Specification, Revision 2.1 +* 2.2.8.1: INTx interrutp signaling - Rules +* the Implementation Note +* Table 2-20 +*/ +/* +* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD +* 0-origin unlike PCI interrupt pin register. +*/ +int pci_swizzle_map_irq_fn (PCIDevice *pci_dev,int pin) +{ +return (pin +PCI_SLOT (pci_dev->devfn)) %PCI_NUM_PINS ; +} +/***********************************************************/ /* monitor info on PCI */ hw/pci.h +2
-0@@ -316,6 +316,8 @@ void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, void *irq_opaque, int nirq);int pci_bus_get_irq_level (PCIBus *bus,int irq_num);void pci_bus_hotplug (PCIBus *bus,pci_hotplug_fn hotplug,DeviceState *dev); +/* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */ +int pci_swizzle_map_irq_fn (PCIDevice *pci_dev,int pin); PCIBus *pci_register_bus(DeviceState *parent, const char *name, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, void *irq_opaque,Signature · 1 line
1.7.1
PATCH v3 5/26 pc, pc_piix: split out pc nic initialization
In reply to Jason BaronFrom: Isaku Yamahata <[email protected]>
Factor out pc nic initialization.
This simplifies the pc initialization and will reduce the code duplication of q35 pc initialization.
--- hw/pc.c | 15 +++++++++++++++ hw/pc.h | 1 + hw/pc_piix.c | 9 +-------- 3 files changed, 17 insertions(+), 8 deletions(-)
hw/pc.c +15 -0
@@ -1100,6 +1100,21 @@ void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, *floppy =fdctrl_init_isa (isa_bus, fd); } +void pc_nic_init (ISABus *isa_bus,PCIBus *pci_bus) +{ +int i; + +for (i =0 ; i < nb_nics; i++) { +NICInfo *nd = &nd_table[i]; + +if (!pci_bus || (nd->model &&strcmp (nd->model,"ne2k_isa" ) ==0 )) { +pc_init_ne2k_isa (isa_bus, nd); + }else { +pci_nic_init_nofail (nd,"e1000" ,NULL ); + } + } +} +void pc_pci_device_init (PCIBus *pci_bus) {int max_bus;
hw/pc.h +1 -0
@@ -125,6 +125,7 @@ void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,const char *boot_device, ISADevice *floppy, BusState *ide0, BusState *ide1, ISADevice *s); +void pc_nic_init (ISABus *isa_bus,PCIBus *pci_bus);void pc_pci_device_init (PCIBus *pci_bus);typedef void (*cpu_set_smm_t )(int smm,void *arg);
hw/pc_piix.c +1 -8
@@ -233,14 +233,7 @@ static void pc_init1(MemoryRegion *system_memory,/* init basic PC hardware */ pc_basic_device_init (isa_bus, gsi, &rtc_state, &floppy,xen_enabled ()); -for (i =0 ; i < nb_nics; i++) { -NICInfo *nd = &nd_table[i]; - -if (!pci_enabled || (nd->model &&strcmp (nd->model,"ne2k_isa" ) ==0 )) -pc_init_ne2k_isa (isa_bus, nd); -else -pci_nic_init_nofail (nd,"e1000" ,NULL ); - } +pc_nic_init (isa_bus, pci_bus);ide_drive_get (hd,MAX_IDE_BUS );if (pci_enabled) {
Signature · 1 line
1.7.1
Re: [Qemu-devel] [PATCH v3 05/26] pc, pc_piix: split out pc nic initialization
Quoted 9 lines · Jason Baron
From: Isaku Yamahata <[email protected]>
Factor out pc nic initialization.
This simplifies the pc initialization and will reduce the code duplication of q35 pc initialization.Reviewed-by Paolo Bonzini <[email protected]>Signed-off-by Isaku Yamahata <[email protected]>Signed-off-by Jason Baron <[email protected]>
Anthony could you pls review/ack this patch?
Quoted 66 lines
--- hw/pc.c | 15 +++++++++++++++ hw/pc.h | 1 + hw/pc_piix.c | 9 +-------- 3 files changed, 17 insertions(+), 8 deletions(-)hw/pc.c +15
-0@@ -1100,6 +1100,21 @@ void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, *floppy =fdctrl_init_isa (isa_bus, fd); } +void pc_nic_init (ISABus *isa_bus,PCIBus *pci_bus) +{ +int i; + +for (i =0 ; i < nb_nics; i++) { +NICInfo *nd = &nd_table[i]; + +if (!pci_bus || (nd->model &&strcmp (nd->model,"ne2k_isa" ) ==0 )) { +pc_init_ne2k_isa (isa_bus, nd); + }else { +pci_nic_init_nofail (nd,"e1000" ,NULL ); + } + } +} +void pc_pci_device_init (PCIBus *pci_bus) {int max_bus;hw/pc.h +1
-0@@ -125,6 +125,7 @@ void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,const char *boot_device, ISADevice *floppy, BusState *ide0, BusState *ide1, ISADevice *s); +void pc_nic_init (ISABus *isa_bus,PCIBus *pci_bus);void pc_pci_device_init (PCIBus *pci_bus);typedef void (*cpu_set_smm_t )(int smm,void *arg);hw/pc_piix.c +1
-8@@ -233,14 +233,7 @@ static void pc_init1(MemoryRegion *system_memory,/* init basic PC hardware */ pc_basic_device_init (isa_bus, gsi, &rtc_state, &floppy,xen_enabled ()); -for (i =0 ; i < nb_nics; i++) { -NICInfo *nd = &nd_table[i]; - -if (!pci_enabled || (nd->model &&strcmp (nd->model,"ne2k_isa" ) ==0 )) -pc_init_ne2k_isa (isa_bus, nd); -else -pci_nic_init_nofail (nd,"e1000" ,NULL ); - } +pc_nic_init (isa_bus, pci_bus);ide_drive_get (hd,MAX_IDE_BUS );if (pci_enabled) {Signature · 1 line
1.7.1
PATCH v3 6/26 pc: Move ioapic_init() from pc_piix.c to pc.c
In reply to Jason BaronFrom: Jason Baron <[email protected]>
Move ioapic_init from pc_piix.c to pc.c, to make it a common function. Rename ioapic_init -> ioapic_init_gsi.
--- hw/pc.c | 24 ++++++++++++++++++++++++ hw/pc.h | 2 ++ hw/pc_piix.c | 25 +------------------------ 3 files changed, 27 insertions(+), 24 deletions(-)
hw/pc.c +24 -0
@@ -1125,3 +1125,27 @@ void pc_pci_device_init(PCIBus *pci_bus)pci_create_simple (pci_bus,-1 ,"lsi53c895a" ); } } + +void ioapic_init_gsi (GSIState *gsi_state,const char *parent_name) +{ +DeviceState *dev; +SysBusDevice *d; +unsigned int i; + +if (kvm_irqchip_in_kernel ()) { + dev =qdev_create (NULL ,"kvm-ioapic" ); + }else { + dev =qdev_create (NULL ,"ioapic" ); + } +if (parent_name) { +object_property_add_child (object_resolve_path (parent_name,NULL ), +"ioapic" ,OBJECT (dev),NULL ); + } +qdev_init_nofail (dev); + d =sysbus_from_qdev (dev); +sysbus_mmio_map (d,0 ,0xfec00000 ); + +for (i =0 ; i <IOAPIC_NUM_PINS ; i++) { + gsi_state->ioapic_irq[i] =qdev_get_gpio_in (dev, i); + } +}
hw/pc.h +2 -0
@@ -131,6 +131,8 @@ void pc_pci_device_init(PCIBus *pci_bus);typedef void (*cpu_set_smm_t )(int smm,void *arg);void cpu_smm_register (cpu_set_smm_t callback,void *arg); +void ioapic_init_gsi (GSIState *gsi_state,const char *parent_name); +/* acpi.c */ extern int acpi_enabled;extern char *acpi_tables;
hw/pc_piix.c +1 -24
@@ -94,29 +94,6 @@ static void kvm_piix3_gsi_handler(void *opaque, int n, int level) } } -static void ioapic_init (GSIState *gsi_state) -{ -DeviceState *dev; -SysBusDevice *d; -unsigned int i; - -if (kvm_irqchip_in_kernel ()) { - dev =qdev_create (NULL ,"kvm-ioapic" ); - }else { - dev =qdev_create (NULL ,"ioapic" ); - } -/* FIXME: this should be under the piix3. */ -object_property_add_child (object_resolve_path ("i440fx" ,NULL ), -"ioapic" ,OBJECT (dev),NULL ); -qdev_init_nofail (dev); - d =sysbus_from_qdev (dev); -sysbus_mmio_map (d,0 ,0xfec00000 ); - -for (i =0 ; i <IOAPIC_NUM_PINS ; i++) { - gsi_state->ioapic_irq[i] =qdev_get_gpio_in (dev, i); - } -} -/* PC hardware initialisation */ static void pc_init1(MemoryRegion *system_memory, MemoryRegion *system_io,
@@ -220,7 +197,7 @@ static void pc_init1(MemoryRegion *system_memory, gsi_state->i8259_irq[i] = i8259[i]; }if (pci_enabled) { -ioapic_init (gsi_state); +ioapic_init_gsi (gsi_state,"i440fx" ); }pc_register_ferr_irq (gsi[13 ]);
Signature · 1 line
1.7.1
Re: [Qemu-devel] [PATCH v3 06/26] pc: Move ioapic_init() from pc_piix.c to pc.c
Quoted 7 lines · Jason Baron
From: Jason Baron <[email protected]>
Move
ioapic_initfrompc_piix.ctopc.c, to make it a common function. Renameioapic_init->ioapic_init_gsi.Reviewed-by Paolo Bonzini <[email protected]>Signed-off-by Jason Baron <[email protected]>
Anthony, could you pls review/ack this patch?
Quoted 96 lines
--- hw/pc.c | 24 ++++++++++++++++++++++++ hw/pc.h | 2 ++ hw/pc_piix.c | 25 +------------------------ 3 files changed, 27 insertions(+), 24 deletions(-)hw/pc.c +24
-0@@ -1125,3 +1125,27 @@ void pc_pci_device_init(PCIBus *pci_bus)pci_create_simple (pci_bus,-1 ,"lsi53c895a" ); } } + +void ioapic_init_gsi (GSIState *gsi_state,const char *parent_name) +{ +DeviceState *dev; +SysBusDevice *d; +unsigned int i; + +if (kvm_irqchip_in_kernel ()) { + dev =qdev_create (NULL ,"kvm-ioapic" ); + }else { + dev =qdev_create (NULL ,"ioapic" ); + } +if (parent_name) { +object_property_add_child (object_resolve_path (parent_name,NULL ), +"ioapic" ,OBJECT (dev),NULL ); + } +qdev_init_nofail (dev); + d =sysbus_from_qdev (dev); +sysbus_mmio_map (d,0 ,0xfec00000 ); + +for (i =0 ; i <IOAPIC_NUM_PINS ; i++) { + gsi_state->ioapic_irq[i] =qdev_get_gpio_in (dev, i); + } +}hw/pc.h +2
-0@@ -131,6 +131,8 @@ void pc_pci_device_init(PCIBus *pci_bus);typedef void (*cpu_set_smm_t )(int smm,void *arg);void cpu_smm_register (cpu_set_smm_t callback,void *arg); +void ioapic_init_gsi (GSIState *gsi_state,const char *parent_name); +/* acpi.c */ extern int acpi_enabled;extern char *acpi_tables;hw/pc_piix.c +1
-24@@ -94,29 +94,6 @@ static void kvm_piix3_gsi_handler(void *opaque, int n, int level) } } -static void ioapic_init (GSIState *gsi_state) -{ -DeviceState *dev; -SysBusDevice *d; -unsigned int i; - -if (kvm_irqchip_in_kernel ()) { - dev =qdev_create (NULL ,"kvm-ioapic" ); - }else { - dev =qdev_create (NULL ,"ioapic" ); - } -/* FIXME: this should be under the piix3. */ -object_property_add_child (object_resolve_path ("i440fx" ,NULL ), -"ioapic" ,OBJECT (dev),NULL ); -qdev_init_nofail (dev); - d =sysbus_from_qdev (dev); -sysbus_mmio_map (d,0 ,0xfec00000 ); - -for (i =0 ; i <IOAPIC_NUM_PINS ; i++) { - gsi_state->ioapic_irq[i] =qdev_get_gpio_in (dev, i); - } -} -/* PC hardware initialisation */ static void pc_init1(MemoryRegion *system_memory, MemoryRegion *system_io,@@ -220,7 +197,7 @@ static void pc_init1(MemoryRegion *system_memory, gsi_state->i8259_irq[i] = i8259[i]; }if (pci_enabled) { -ioapic_init (gsi_state); +ioapic_init_gsi (gsi_state,"i440fx" ); }pc_register_ferr_irq (gsi[13 ]);Signature · 1 line
1.7.1
PATCH v3 7/26 pc/piix_pci: factor out smram/pam logic
In reply to Jason BaronFrom: Isaku Yamahata <[email protected]>
Factor out smram/pam logic for later use.
Which will be used by q35 too.
--- hw/i386/Makefile.objs | 1 + hw/pam.c | 120 +++++++++++++++++++++++++++++++++++++++++++++++++ hw/pam.h | 98 ++++++++++++++++++++++++++++++++++++++++ hw/piix_pci.c | 65 ++++---------------------- 4 files changed, 229 insertions(+), 55 deletions(-) create mode 100644 hw/pam.c create mode 100644 hw/pam.h
hw/i386/Makefile.objs +1 -0
@@ -6,6 +6,7 @@ obj-y += pci-hotplug.o smbios.o wdt_ib700.o obj-y += debugcon.o multiboot.o obj-y += pc_piix.o obj-y += pc_sysfw.o +obj-y += pam.o obj-$(CONFIG_XEN) += xen_platform.o xen_apic.o obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen-host-pci-device.o obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pt.o xen_pt_config_init.o xen_pt_msi.o
hw/pam.c new file +120 -0
120 lines not on this page · raw message
hw/pam.h new file +98 -0
98 lines not on this page · raw message
hw/piix_pci.c +10 -55
94 lines not on this page · raw message
Signature · 1 line
1.7.1
Michael S. Tsirkin
AppliedRe: [Qemu-devel] [PATCH v3 07/26] pc/piix_pci: factor out smram/pam logic
Quoted 9 lines · Jason Baron
From: Isaku Yamahata <[email protected]>
Factor out smram/pam logic for later use.
Which will be used by q35 too.Reviewed-by Paolo Bonzini <[email protected]>[[email protected]: changes for updated memory API]Signed-off-by Isaku Yamahata <[email protected]>Signed-off-by Jason Baron <[email protected]>
Applied, thanks.
Quoted 355 lines
--- hw/i386/Makefile.objs | 1 + hw/pam.c | 120 +++++++++++++++++++++++++++++++++++++++++++++++++ hw/pam.h | 98 ++++++++++++++++++++++++++++++++++++++++ hw/piix_pci.c | 65 ++++---------------------- 4 files changed, 229 insertions(+), 55 deletions(-) create mode 100644 hw/pam.c create mode 100644 hw/pam.hhw/i386/Makefile.objs +1
-0@@ -6,6 +6,7 @@ obj-y += pci-hotplug.o smbios.o wdt_ib700.o obj-y += debugcon.o multiboot.o obj-y += pc_piix.o obj-y += pc_sysfw.o +obj-y += pam.o obj-$(CONFIG_XEN) += xen_platform.o xen_apic.o obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen-host-pci-device.o obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pt.o xen_pt_config_init.o xen_pt_msi.ohw/pam.c new file +120
-0@@ -0,0 +1,120 @@ +/* +* QEMU i440FX/PIIX3 PCI Bridge Emulation +* +* Copyright (c) 2006 Fabrice Bellard +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +* THE SOFTWARE. +* +* Split out from piix_pci.c +* Copyright (c) 2011 Isaku Yamahata <yamahata at valinux co jp> +* VA Linux Systems Japan K.K. +* Copyright (c) 2012 Jason Baron <[email protected]> +* +*/ + +#include "sysemu.h" +#include "pam.h" + +void smram_update (MemoryRegion *smram_region,uint8_t smram, +uint8_t smm_enabled) +{ +bool smram_enabled; + + smram_enabled = ((smm_enabled && (smram &SMRAM_G_SMRAME )) || + (smram &SMRAM_D_OPEN )); +memory_region_set_enabled (smram_region, !smram_enabled); +} + +void smram_set_smm (uint8_t *host_smm_enabled,int smm,uint8_t smram, +MemoryRegion *smram_region) +{ +uint8_t smm_enabled = (smm !=0 ); +if (*host_smm_enabled != smm_enabled) { + *host_smm_enabled = smm_enabled; +smram_update (smram_region, smram, *host_smm_enabled); + } +} + +static void pam_update_seg (PAMMemoryRegion *mem,uint32_t start,uint32_t size, +MemoryRegion *ram_memory, +MemoryRegion *pci_address_space, +MemoryRegion *system_memory,uint8_t attr) +{ +if (mem->initialized) { +memory_region_del_subregion (system_memory, &mem->mem); +memory_region_destroy (&mem->mem); + } + +switch (attr) { +case PAM_ATTR_WE |PAM_ATTR_RE : +/* RAM */ +memory_region_init_alias (&mem->mem,"pam-ram" , ram_memory, + start, size); +break ; +case PAM_ATTR_RE : +/* ROM (XXX: not quite correct) */ +memory_region_init_alias (&mem->mem,"pam-rom" , ram_memory, + start, size); +memory_region_set_readonly (&mem->mem, true); +break ; +case PAM_ATTR_WE : +case 0 : +/* XXX: should distinguish read/write cases */ +memory_region_init_alias (&mem->mem,"pam-pci" , pci_address_space, + start, size); +break ; +default : +abort (); +break ; + } +memory_region_add_subregion_overlap (system_memory, start, &mem->mem,1 ); + mem->initialized = true; + +} + +static uint8_t pam_attr (uint8_t val,int hi) +{ +return (val >> ((!!hi) *4 )) &PAM_ATTR_MASK ; +} + +void pam_update (PAMMemoryRegion *mem,int idx,uint8_t val, +MemoryRegion *ram_memory,MemoryRegion *pci_address_space, +MemoryRegion *system_memory) +{ +uint32_t phys_addr; +int map_idx; + +assert (0 <= idx && idx <=PAM_IDX_MAX ); + +if (idx ==0 ) { +pam_update_seg (&mem[0 ],PAM_BIOS_BASE ,PAM_BIOS_SIZE , ram_memory, + pci_address_space, system_memory,pam_attr (val,1 )); +return ; + } + + map_idx = (idx -1 ) *2 ; + + phys_addr =PAM_EXPAN_BASE +PAM_EXPAN_SIZE * map_idx; +pam_update_seg (&mem[map_idx +1 ], phys_addr,PAM_EXPAN_SIZE , ram_memory, + pci_address_space, system_memory,pam_attr (val,0 )); + + phys_addr +=PAM_EXPAN_SIZE ; +pam_update_seg (&mem[map_idx +2 ], phys_addr,PAM_EXPAN_SIZE , ram_memory, + pci_address_space, system_memory,pam_attr (val,1 )); +}hw/pam.h new file +98
-0@@ -0,0 +1,98 @@ +#ifndef QEMU_PAM_H +#define QEMU_PAM_H + +/* +* Copyright (c) 2006 Fabrice Bellard +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +* THE SOFTWARE. +*/ +/* +* Split out from piix_pci.c +* Copyright (c) 2011 Isaku Yamahata <yamahata at valinux co jp> +* VA Linux Systems Japan K.K. +* Copyright (c) 2012 Jason Baron <[email protected]> +* +* SMRAM memory area and PAM memory area in Legacy address range for PC. +* PAM: Programmable Attribute Map registers +* +* 0xa0000 - 0xbffff compatible SMRAM +* +* 0xc0000 - 0xc3fff Expansion area memory segments +* 0xc4000 - 0xc7fff +* 0xc8000 - 0xcbfff +* 0xcc000 - 0xcffff +* 0xd0000 - 0xd7fff +* 0xd8000 - 0xdbfff +* 0xdc000 - 0xdffff +* 0xe0000 - 0xe3fff Extended System BIOS Area Memory Segments +* 0xe4000 - 0xe7fff +* 0xe8000 - 0xebfff +* 0xec000 - 0xeffff +* +* 0xf0000 - 0xfffff System BIOS Area Memory Segments +*/ + +#include "qemu-common.h" +#include "memory.h" + +#define SMRAM_C_BASE 0xa0000 +#define SMRAM_C_END 0xc0000 +#define SMRAM_C_SIZE 0x20000 + + +#define PAM_EXPAN_BASE 0xc0000 +#define PAM_EXPAN_SIZE 0x04000 + +#define PAM_EXBIOS_BASE 0xe0000 +#define PAM_EXBIOS_SIZE 0x04000 + +#define PAM_BIOS_BASE 0xf0000 +#define PAM_BIOS_END 0xfffff +/* 64KB: Intel 3 series express chipset family p. 58*/ +#define PAM_BIOS_SIZE 0x10000 + +/* PAM registers: log nibble and high nibble*/ +#define PAM_ATTR_WE ((uint8_t)2) +#define PAM_ATTR_RE ((uint8_t)1) +#define PAM_ATTR_MASK ((uint8_t)3) + +#define PAM_IDX_MAX 6/* pam0 - pam6 */ + +/* SMRAM register */ +#define SMRAM_D_OPEN ((uint8_t)(1 << 6)) +#define SMRAM_D_CLS ((uint8_t)(1 << 5)) +#define SMRAM_D_LCK ((uint8_t)(1 << 4)) +#define SMRAM_G_SMRAME ((uint8_t)(1 << 3)) +#define SMRAM_C_BASE_SEG_MASK ((uint8_t)0x7) +#define SMRAM_C_BASE_SEG ((uint8_t)0x2)/* hardwired to b010 */ + +typedef struct PAMMemoryRegion { +MemoryRegion mem; +bool initialized; +}PAMMemoryRegion ; + +void smram_update (MemoryRegion *smram_region,uint8_t smram, +uint8_t smm_enabled); +void smram_set_smm (uint8_t *host_smm_enabled,int smm,uint8_t smram, +MemoryRegion *smram_region); +void pam_update (PAMMemoryRegion *mem,int idx,uint8_t val, +MemoryRegion *ram_memory,MemoryRegion *pci_address_space, +MemoryRegion *system_memory); + +#endif /* QEMU_PAM_H */ hw/piix_pci.c +10
-55@@ -30,6 +30,7 @@#include "sysbus.h" #include "range.h" #include "xen.h" +#include "pam.h" /* * I440FX chipset data sheet. @@ -68,11 +69,6 @@ typedef struct PIIX3State {int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS ]; } PIIX3State; -typedef struct PAMMemoryRegion { -MemoryRegion mem; -bool initialized; -}PAMMemoryRegion ; -struct PCII440FXState {PCIDevice dev;MemoryRegion *system_memory;@@ -105,56 +101,16 @@ static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)return (pci_intx + slot_addend) &3 ; } -static void update_pam (PCII440FXState *d,uint32_t start,uint32_t end,int r, -PAMMemoryRegion *mem) -{ -if (mem->initialized) { -memory_region_del_subregion (d->system_memory, &mem->mem); -memory_region_destroy (&mem->mem); - } - -// printf("ISA mapping %08x-0x%08x: %d\n", start, end, r); -switch (r) { -case 3 : -/* RAM */ -memory_region_init_alias (&mem->mem,"pam-ram" , d->ram_memory, - start, end - start); -break ; -case 1 : -/* ROM (XXX: not quite correct) */ -memory_region_init_alias (&mem->mem,"pam-rom" , d->ram_memory, - start, end - start); -memory_region_set_readonly (&mem->mem, true); -break ; -case 2 : -case 0 : -/* XXX: should distinguish read/write cases */ -memory_region_init_alias (&mem->mem,"pam-pci" , d->pci_address_space, - start, end - start); -break ; - } -memory_region_add_subregion_overlap (d->system_memory, - start, &mem->mem,1 ); - mem->initialized = true; -} -static void i440fx_update_memory_mappings (PCII440FXState *d) { -int i, r; -uint32_t smram; -bool smram_enabled; +int i;memory_region_transaction_begin (); -update_pam (d,0xf0000 ,0x100000 , (d->dev.config[I440FX_PAM ] >>4 ) &3 , - &d->pam_regions[0 ]); -for (i =0 ; i <12 ; i++) { - r = (d->dev.config[(i >>1 ) + (I440FX_PAM +1 )] >> ((i &1 ) *4 )) &3 ; -update_pam (d,0xc0000 +0x4000 * i,0xc0000 +0x4000 * (i +1 ), r, - &d->pam_regions[i+1 ]); +for (i =0 ; i <=PAM_IDX_MAX ; i++) { +pam_update (&d->pam_regions[0 ], i, d->dev.config[I440FX_PAM + i], + d->ram_memory, d->pci_address_space, d->system_memory); } - smram = d->dev.config[I440FX_SMRAM ]; - smram_enabled = (d->smm_enabled && (smram &0x08 )) || (smram &0x40 ); -memory_region_set_enabled (&d->smram_region, !smram_enabled); +smram_update (&d->smram_region, d->dev.config[I440FX_SMRAM ], d->smm_enabled);memory_region_transaction_commit (); }@@ -162,11 +118,10 @@ static void i440fx_set_smm(int val, void *arg) {PCII440FXState *d = arg; - val = (val !=0 ); -if (d->smm_enabled != val) { - d->smm_enabled = val; -i440fx_update_memory_mappings (d); - } +memory_region_transaction_begin (); +smram_set_smm (&d->smm_enabled, val, d->dev.config[I440FX_SMRAM ], + &d->smram_region); +memory_region_transaction_commit (); }Signature · 1 line
1.7.1
Re: [Qemu-devel] [PATCH v3 07/26] pc/piix_pci: factor out smram/pam logic
In reply to Jason BaronQuoted 9 lines · Jason Baron
From: Isaku Yamahata <[email protected]>
Factor out smram/pam logic for later use.
Which will be used by q35 too.Reviewed-by Paolo Bonzini <[email protected]>[[email protected]: changes for updated memory API]Signed-off-by Isaku Yamahata <[email protected]>Signed-off-by Jason Baron <[email protected]>
I dropped this patch from pci branch for now as it needs to be rebased. Can you do this pls?
Quoted 355 lines
--- hw/i386/Makefile.objs | 1 + hw/pam.c | 120 +++++++++++++++++++++++++++++++++++++++++++++++++ hw/pam.h | 98 ++++++++++++++++++++++++++++++++++++++++ hw/piix_pci.c | 65 ++++---------------------- 4 files changed, 229 insertions(+), 55 deletions(-) create mode 100644 hw/pam.c create mode 100644 hw/pam.hhw/i386/Makefile.objs +1
-0@@ -6,6 +6,7 @@ obj-y += pci-hotplug.o smbios.o wdt_ib700.o obj-y += debugcon.o multiboot.o obj-y += pc_piix.o obj-y += pc_sysfw.o +obj-y += pam.o obj-$(CONFIG_XEN) += xen_platform.o xen_apic.o obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen-host-pci-device.o obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pt.o xen_pt_config_init.o xen_pt_msi.ohw/pam.c new file +120
-0@@ -0,0 +1,120 @@ +/* +* QEMU i440FX/PIIX3 PCI Bridge Emulation +* +* Copyright (c) 2006 Fabrice Bellard +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +* THE SOFTWARE. +* +* Split out from piix_pci.c +* Copyright (c) 2011 Isaku Yamahata <yamahata at valinux co jp> +* VA Linux Systems Japan K.K. +* Copyright (c) 2012 Jason Baron <[email protected]> +* +*/ + +#include "sysemu.h" +#include "pam.h" + +void smram_update (MemoryRegion *smram_region,uint8_t smram, +uint8_t smm_enabled) +{ +bool smram_enabled; + + smram_enabled = ((smm_enabled && (smram &SMRAM_G_SMRAME )) || + (smram &SMRAM_D_OPEN )); +memory_region_set_enabled (smram_region, !smram_enabled); +} + +void smram_set_smm (uint8_t *host_smm_enabled,int smm,uint8_t smram, +MemoryRegion *smram_region) +{ +uint8_t smm_enabled = (smm !=0 ); +if (*host_smm_enabled != smm_enabled) { + *host_smm_enabled = smm_enabled; +smram_update (smram_region, smram, *host_smm_enabled); + } +} + +static void pam_update_seg (PAMMemoryRegion *mem,uint32_t start,uint32_t size, +MemoryRegion *ram_memory, +MemoryRegion *pci_address_space, +MemoryRegion *system_memory,uint8_t attr) +{ +if (mem->initialized) { +memory_region_del_subregion (system_memory, &mem->mem); +memory_region_destroy (&mem->mem); + } + +switch (attr) { +case PAM_ATTR_WE |PAM_ATTR_RE : +/* RAM */ +memory_region_init_alias (&mem->mem,"pam-ram" , ram_memory, + start, size); +break ; +case PAM_ATTR_RE : +/* ROM (XXX: not quite correct) */ +memory_region_init_alias (&mem->mem,"pam-rom" , ram_memory, + start, size); +memory_region_set_readonly (&mem->mem, true); +break ; +case PAM_ATTR_WE : +case 0 : +/* XXX: should distinguish read/write cases */ +memory_region_init_alias (&mem->mem,"pam-pci" , pci_address_space, + start, size); +break ; +default : +abort (); +break ; + } +memory_region_add_subregion_overlap (system_memory, start, &mem->mem,1 ); + mem->initialized = true; + +} + +static uint8_t pam_attr (uint8_t val,int hi) +{ +return (val >> ((!!hi) *4 )) &PAM_ATTR_MASK ; +} + +void pam_update (PAMMemoryRegion *mem,int idx,uint8_t val, +MemoryRegion *ram_memory,MemoryRegion *pci_address_space, +MemoryRegion *system_memory) +{ +uint32_t phys_addr; +int map_idx; + +assert (0 <= idx && idx <=PAM_IDX_MAX ); + +if (idx ==0 ) { +pam_update_seg (&mem[0 ],PAM_BIOS_BASE ,PAM_BIOS_SIZE , ram_memory, + pci_address_space, system_memory,pam_attr (val,1 )); +return ; + } + + map_idx = (idx -1 ) *2 ; + + phys_addr =PAM_EXPAN_BASE +PAM_EXPAN_SIZE * map_idx; +pam_update_seg (&mem[map_idx +1 ], phys_addr,PAM_EXPAN_SIZE , ram_memory, + pci_address_space, system_memory,pam_attr (val,0 )); + + phys_addr +=PAM_EXPAN_SIZE ; +pam_update_seg (&mem[map_idx +2 ], phys_addr,PAM_EXPAN_SIZE , ram_memory, + pci_address_space, system_memory,pam_attr (val,1 )); +}hw/pam.h new file +98
-0@@ -0,0 +1,98 @@ +#ifndef QEMU_PAM_H +#define QEMU_PAM_H + +/* +* Copyright (c) 2006 Fabrice Bellard +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +* THE SOFTWARE. +*/ +/* +* Split out from piix_pci.c +* Copyright (c) 2011 Isaku Yamahata <yamahata at valinux co jp> +* VA Linux Systems Japan K.K. +* Copyright (c) 2012 Jason Baron <[email protected]> +* +* SMRAM memory area and PAM memory area in Legacy address range for PC. +* PAM: Programmable Attribute Map registers +* +* 0xa0000 - 0xbffff compatible SMRAM +* +* 0xc0000 - 0xc3fff Expansion area memory segments +* 0xc4000 - 0xc7fff +* 0xc8000 - 0xcbfff +* 0xcc000 - 0xcffff +* 0xd0000 - 0xd7fff +* 0xd8000 - 0xdbfff +* 0xdc000 - 0xdffff +* 0xe0000 - 0xe3fff Extended System BIOS Area Memory Segments +* 0xe4000 - 0xe7fff +* 0xe8000 - 0xebfff +* 0xec000 - 0xeffff +* +* 0xf0000 - 0xfffff System BIOS Area Memory Segments +*/ + +#include "qemu-common.h" +#include "memory.h" + +#define SMRAM_C_BASE 0xa0000 +#define SMRAM_C_END 0xc0000 +#define SMRAM_C_SIZE 0x20000 + + +#define PAM_EXPAN_BASE 0xc0000 +#define PAM_EXPAN_SIZE 0x04000 + +#define PAM_EXBIOS_BASE 0xe0000 +#define PAM_EXBIOS_SIZE 0x04000 + +#define PAM_BIOS_BASE 0xf0000 +#define PAM_BIOS_END 0xfffff +/* 64KB: Intel 3 series express chipset family p. 58*/ +#define PAM_BIOS_SIZE 0x10000 + +/* PAM registers: log nibble and high nibble*/ +#define PAM_ATTR_WE ((uint8_t)2) +#define PAM_ATTR_RE ((uint8_t)1) +#define PAM_ATTR_MASK ((uint8_t)3) + +#define PAM_IDX_MAX 6/* pam0 - pam6 */ + +/* SMRAM register */ +#define SMRAM_D_OPEN ((uint8_t)(1 << 6)) +#define SMRAM_D_CLS ((uint8_t)(1 << 5)) +#define SMRAM_D_LCK ((uint8_t)(1 << 4)) +#define SMRAM_G_SMRAME ((uint8_t)(1 << 3)) +#define SMRAM_C_BASE_SEG_MASK ((uint8_t)0x7) +#define SMRAM_C_BASE_SEG ((uint8_t)0x2)/* hardwired to b010 */ + +typedef struct PAMMemoryRegion { +MemoryRegion mem; +bool initialized; +}PAMMemoryRegion ; + +void smram_update (MemoryRegion *smram_region,uint8_t smram, +uint8_t smm_enabled); +void smram_set_smm (uint8_t *host_smm_enabled,int smm,uint8_t smram, +MemoryRegion *smram_region); +void pam_update (PAMMemoryRegion *mem,int idx,uint8_t val, +MemoryRegion *ram_memory,MemoryRegion *pci_address_space, +MemoryRegion *system_memory); + +#endif /* QEMU_PAM_H */ hw/piix_pci.c +10
-55@@ -30,6 +30,7 @@#include "sysbus.h" #include "range.h" #include "xen.h" +#include "pam.h" /* * I440FX chipset data sheet. @@ -68,11 +69,6 @@ typedef struct PIIX3State {int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS ]; } PIIX3State; -typedef struct PAMMemoryRegion { -MemoryRegion mem; -bool initialized; -}PAMMemoryRegion ; -struct PCII440FXState {PCIDevice dev;MemoryRegion *system_memory;@@ -105,56 +101,16 @@ static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)return (pci_intx + slot_addend) &3 ; } -static void update_pam (PCII440FXState *d,uint32_t start,uint32_t end,int r, -PAMMemoryRegion *mem) -{ -if (mem->initialized) { -memory_region_del_subregion (d->system_memory, &mem->mem); -memory_region_destroy (&mem->mem); - } - -// printf("ISA mapping %08x-0x%08x: %d\n", start, end, r); -switch (r) { -case 3 : -/* RAM */ -memory_region_init_alias (&mem->mem,"pam-ram" , d->ram_memory, - start, end - start); -break ; -case 1 : -/* ROM (XXX: not quite correct) */ -memory_region_init_alias (&mem->mem,"pam-rom" , d->ram_memory, - start, end - start); -memory_region_set_readonly (&mem->mem, true); -break ; -case 2 : -case 0 : -/* XXX: should distinguish read/write cases */ -memory_region_init_alias (&mem->mem,"pam-pci" , d->pci_address_space, - start, end - start); -break ; - } -memory_region_add_subregion_overlap (d->system_memory, - start, &mem->mem,1 ); - mem->initialized = true; -} -static void i440fx_update_memory_mappings (PCII440FXState *d) { -int i, r; -uint32_t smram; -bool smram_enabled; +int i;memory_region_transaction_begin (); -update_pam (d,0xf0000 ,0x100000 , (d->dev.config[I440FX_PAM ] >>4 ) &3 , - &d->pam_regions[0 ]); -for (i =0 ; i <12 ; i++) { - r = (d->dev.config[(i >>1 ) + (I440FX_PAM +1 )] >> ((i &1 ) *4 )) &3 ; -update_pam (d,0xc0000 +0x4000 * i,0xc0000 +0x4000 * (i +1 ), r, - &d->pam_regions[i+1 ]); +for (i =0 ; i <=PAM_IDX_MAX ; i++) { +pam_update (&d->pam_regions[0 ], i, d->dev.config[I440FX_PAM + i], + d->ram_memory, d->pci_address_space, d->system_memory); } - smram = d->dev.config[I440FX_SMRAM ]; - smram_enabled = (d->smm_enabled && (smram &0x08 )) || (smram &0x40 ); -memory_region_set_enabled (&d->smram_region, !smram_enabled); +smram_update (&d->smram_region, d->dev.config[I440FX_SMRAM ], d->smm_enabled);memory_region_transaction_commit (); }@@ -162,11 +118,10 @@ static void i440fx_set_smm(int val, void *arg) {PCII440FXState *d = arg; - val = (val !=0 ); -if (d->smm_enabled != val) { - d->smm_enabled = val; -i440fx_update_memory_mappings (d); - } +memory_region_transaction_begin (); +smram_set_smm (&d->smm_enabled, val, d->dev.config[I440FX_SMRAM ], + &d->smram_region); +memory_region_transaction_commit (); }Signature · 1 line
1.7.1
PATCH v3 8/26 pci_ids: add intel 82801BA pci-to-pci bridge id
In reply to Jason BaronFrom: Isaku Yamahata <[email protected]>
Adds pci id constants which will be used by q35.
--- hw/pci_ids.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)
hw/pci_ids.h +1 -0
@@ -104,6 +104,7 @@#define PCI_DEVICE_ID_INTEL_82378 0x0484#define PCI_DEVICE_ID_INTEL_82441 0x1237#define PCI_DEVICE_ID_INTEL_82801AA_5 0x2415 +#define PCI_DEVICE_ID_INTEL_82801BA_11 0x244e#define PCI_DEVICE_ID_INTEL_82801D 0x24CD#define PCI_DEVICE_ID_INTEL_ESB_9 0x25ab#define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000
Signature · 1 line
1.7.1
Michael S. Tsirkin
AppliedRe: [Qemu-devel] [PATCH v3 08/26] pci_ids: add intel 82801BA pci-to-pci bridge id
Quoted 7 lines · Jason Baron
From: Isaku Yamahata <[email protected]>
Adds pci id constants which will be used by q35.
Reviewed-by Paolo Bonzini <[email protected]>Signed-off-by Isaku Yamahata <[email protected]>Signed-off-by Jason Baron <[email protected]>
Applied, thanks
Quoted 18 lines
--- hw/pci_ids.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)hw/pci_ids.h +1
-0@@ -104,6 +104,7 @@#define PCI_DEVICE_ID_INTEL_82378 0x0484#define PCI_DEVICE_ID_INTEL_82441 0x1237#define PCI_DEVICE_ID_INTEL_82801AA_5 0x2415 +#define PCI_DEVICE_ID_INTEL_82801BA_11 0x244e#define PCI_DEVICE_ID_INTEL_82801D 0x24CD#define PCI_DEVICE_ID_INTEL_ESB_9 0x25ab#define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000Signature · 1 line
1.7.1
PATCH v3 9/26 pci: Add class 0xc05 as 'SMBus'
In reply to Jason BaronFrom: Jan Kiszka <[email protected]>
--- hw/pci.c | 1 + hw/pci_ids.h | 1 + 2 files changed, 2 insertions(+), 0 deletions(-)
hw/pci.c +1 -0
@@ -1203,6 +1203,7 @@ static const pci_class_desc pci_class_descriptions[] = { 0x0c02, "SSA controller", "ssa"}, { 0x0c03, "USB controller", "usb"}, { 0x0c04, "Fibre channel controller", "fibre-channel"}, + { 0x0c05, "SMBus"}, { 0, NULL} };
hw/pci_ids.h +1 -0
@@ -31,6 +31,7 @@#define PCI_CLASS_SYSTEM_OTHER 0x0880#define PCI_CLASS_SERIAL_USB 0x0c03 +#define PCI_CLASS_SERIAL_SMBUS 0x0c05#define PCI_CLASS_BRIDGE_HOST 0x0600#define PCI_CLASS_BRIDGE_ISA 0x0601
Signature · 1 line
1.7.1
Michael S. Tsirkin
AppliedRe: [Qemu-devel] [PATCH v3 09/26] pci: Add class 0xc05 as 'SMBus'
Quoted 6 lines · Jason Baron
From: Jan Kiszka <[email protected]>
[[email protected]: add PCI_CLASS_SERIAL_SMBUS definition]Reviewed-by Paolo Bonzini <[email protected]>Signed-off-by Jan Kiszka <[email protected]>Signed-off-by Jason Baron <[email protected]>
Applied, thanks.
Quoted 31 lines
--- hw/pci.c | 1 + hw/pci_ids.h | 1 + 2 files changed, 2 insertions(+), 0 deletions(-)hw/pci.c +1
-0@@ -1203,6 +1203,7 @@ static const pci_class_desc pci_class_descriptions[] = { 0x0c02, "SSA controller", "ssa"}, { 0x0c03, "USB controller", "usb"}, { 0x0c04, "Fibre channel controller", "fibre-channel"}, + { 0x0c05, "SMBus"}, { 0, NULL} };hw/pci_ids.h +1
-0@@ -31,6 +31,7 @@#define PCI_CLASS_SYSTEM_OTHER 0x0880#define PCI_CLASS_SERIAL_USB 0x0c03 +#define PCI_CLASS_SERIAL_SMBUS 0x0c05#define PCI_CLASS_BRIDGE_HOST 0x0600#define PCI_CLASS_BRIDGE_ISA 0x0601Signature · 1 line
1.7.1
PATCH v3 10/26 pcie: pass pcie window size to pcie_host_mmcfg_update()
In reply to Jason BaronFrom: Jason Baron <[email protected]>
This allows q35 to pass/set the size of the pcie window in its update routine.
--- hw/pcie_host.c | 21 ++++++++++++--------- hw/pcie_host.h | 8 +++++--- 2 files changed, 17 insertions(+), 12 deletions(-)
hw/pcie_host.c +12 -9
@@ -107,14 +107,9 @@ static const MemoryRegionOps pcie_mmcfg_ops = {/* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */ #define PCIE_BASE_ADDR_UNMAPPED ((target_phys_addr_t)-1ULL) -int pcie_host_init (PCIExpressHost *e,uint32_t size) +int pcie_host_init (PCIExpressHost *e) { -assert (!(size & (size -1 )));/* power of 2 */ -assert (size >=PCIE_MMCFG_SIZE_MIN ); -assert (size <=PCIE_MMCFG_SIZE_MAX ); e->base_addr =PCIE_BASE_ADDR_UNMAPPED ; - e->size = size; -memory_region_init_io (&e->mmio, &pcie_mmcfg_ops, e,"pcie-mmcfg" , e->size);return 0 ; }
@@ -123,22 +118,30 @@ void pcie_host_mmcfg_unmap(PCIExpressHost *e) {if (e->base_addr !=PCIE_BASE_ADDR_UNMAPPED ) {memory_region_del_subregion (get_system_memory (), &e->mmio); +memory_region_destroy (&e->mmio); e->base_addr =PCIE_BASE_ADDR_UNMAPPED ; } } -void pcie_host_mmcfg_map (PCIExpressHost *e,target_phys_addr_t addr) +void pcie_host_mmcfg_map (PCIExpressHost *e,target_phys_addr_t addr, +uint32_t size) { +assert (!(size & (size -1 )));/* power of 2 */ +assert (size >=PCIE_MMCFG_SIZE_MIN ); +assert (size <=PCIE_MMCFG_SIZE_MAX ); + e->size = size; +memory_region_init_io (&e->mmio, &pcie_mmcfg_ops, e,"pcie-mmcfg" , e->size); e->base_addr = addr;memory_region_add_subregion (get_system_memory (), e->base_addr, &e->mmio); }void pcie_host_mmcfg_update (PCIExpressHost *e,int enable, -target_phys_addr_t addr) +target_phys_addr_t addr, +uint32_t size) {pcie_host_mmcfg_unmap (e);if (enable) { -pcie_host_mmcfg_map (e, addr); +pcie_host_mmcfg_map (e, addr, size); } }
hw/pcie_host.h +5 -3
@@ -39,11 +39,13 @@ struct PCIExpressHost { MemoryRegion mmio; }; -int pcie_host_init (PCIExpressHost *e,uint32_t size); +int pcie_host_init (PCIExpressHost *e);void pcie_host_mmcfg_unmap (PCIExpressHost *e); -void pcie_host_mmcfg_map (PCIExpressHost *e,target_phys_addr_t addr); +void pcie_host_mmcfg_map (PCIExpressHost *e,target_phys_addr_t addr, +uint32_t size);void pcie_host_mmcfg_update (PCIExpressHost *e,int enable, -target_phys_addr_t addr); +target_phys_addr_t addr, +uint32_t size);#endif /* PCIE_HOST_H */
Signature · 1 line
1.7.1
Michael S. Tsirkin
AppliedRe: [Qemu-devel] [PATCH v3 10/26] pcie: pass pcie window size to pcie_host_mmcfg_update()
Quoted 6 lines · Jason Baron
From: Jason Baron <[email protected]>
This allows q35 to pass/set the size of the pcie window in its update routine.
Reviewed-by Paolo Bonzini <[email protected]>Signed-off-by Jason Baron <[email protected]>
Applied, thanks.
Quoted 82 lines
--- hw/pcie_host.c | 21 ++++++++++++--------- hw/pcie_host.h | 8 +++++--- 2 files changed, 17 insertions(+), 12 deletions(-)hw/pcie_host.c +12
-9@@ -107,14 +107,9 @@ static const MemoryRegionOps pcie_mmcfg_ops = {/* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */ #define PCIE_BASE_ADDR_UNMAPPED ((target_phys_addr_t)-1ULL) -int pcie_host_init (PCIExpressHost *e,uint32_t size) +int pcie_host_init (PCIExpressHost *e) { -assert (!(size & (size -1 )));/* power of 2 */ -assert (size >=PCIE_MMCFG_SIZE_MIN ); -assert (size <=PCIE_MMCFG_SIZE_MAX ); e->base_addr =PCIE_BASE_ADDR_UNMAPPED ; - e->size = size; -memory_region_init_io (&e->mmio, &pcie_mmcfg_ops, e,"pcie-mmcfg" , e->size);return 0 ; }@@ -123,22 +118,30 @@ void pcie_host_mmcfg_unmap(PCIExpressHost *e) {if (e->base_addr !=PCIE_BASE_ADDR_UNMAPPED ) {memory_region_del_subregion (get_system_memory (), &e->mmio); +memory_region_destroy (&e->mmio); e->base_addr =PCIE_BASE_ADDR_UNMAPPED ; } } -void pcie_host_mmcfg_map (PCIExpressHost *e,target_phys_addr_t addr) +void pcie_host_mmcfg_map (PCIExpressHost *e,target_phys_addr_t addr, +uint32_t size) { +assert (!(size & (size -1 )));/* power of 2 */ +assert (size >=PCIE_MMCFG_SIZE_MIN ); +assert (size <=PCIE_MMCFG_SIZE_MAX ); + e->size = size; +memory_region_init_io (&e->mmio, &pcie_mmcfg_ops, e,"pcie-mmcfg" , e->size); e->base_addr = addr;memory_region_add_subregion (get_system_memory (), e->base_addr, &e->mmio); }void pcie_host_mmcfg_update (PCIExpressHost *e,int enable, -target_phys_addr_t addr) +target_phys_addr_t addr, +uint32_t size) {pcie_host_mmcfg_unmap (e);if (enable) { -pcie_host_mmcfg_map (e, addr); +pcie_host_mmcfg_map (e, addr, size); } }hw/pcie_host.h +5
-3@@ -39,11 +39,13 @@ struct PCIExpressHost { MemoryRegion mmio; }; -int pcie_host_init (PCIExpressHost *e,uint32_t size); +int pcie_host_init (PCIExpressHost *e);void pcie_host_mmcfg_unmap (PCIExpressHost *e); -void pcie_host_mmcfg_map (PCIExpressHost *e,target_phys_addr_t addr); +void pcie_host_mmcfg_map (PCIExpressHost *e,target_phys_addr_t addr, +uint32_t size);void pcie_host_mmcfg_update (PCIExpressHost *e,int enable, -target_phys_addr_t addr); +target_phys_addr_t addr, +uint32_t size);#endif /* PCIE_HOST_H */ Signature · 1 line
1.7.1
PATCH v3 11/26 pcie: Convert PCIExpressHost to use the QOM.
In reply to Jason BaronFrom: Jason Baron <[email protected]>
Let's use PCIExpressHost with QOM.
--- hw/pcie_host.c | 14 ++++++++++++++ hw/pcie_host.h | 4 ++++ 2 files changed, 18 insertions(+), 0 deletions(-)
hw/pcie_host.c +14 -0
@@ -145,3 +145,17 @@ void pcie_host_mmcfg_update(PCIExpressHost *e,pcie_host_mmcfg_map (e, addr, size); } } + +static const TypeInfo pcie_host_type_info = { + .name =TYPE_PCIE_HOST_BRIDGE , + .parent =TYPE_PCI_HOST_BRIDGE , + .abstract = true, + .instance_size =sizeof (PCIExpressHost), +}; + +static void pcie_host_register_types (void ) +{ +type_register_static (&pcie_host_type_info); +} + +type_init (pcie_host_register_types)
hw/pcie_host.h +4 -0
@@ -24,6 +24,10 @@#include "pci_host.h" #include "memory.h" +#define TYPE_PCIE_HOST_BRIDGE "pcie-host-bridge" +#define PCIE_HOST_BRIDGE (obj) \ + OBJECT_CHECK(PCIExpressHost, (obj), TYPE_PCIE_HOST_BRIDGE) +struct PCIExpressHost {PCIHostState pci;
Signature · 1 line
1.7.1
Michael S. Tsirkin
AppliedRe: [Qemu-devel] [PATCH v3 11/26] pcie: Convert PCIExpressHost to use the QOM.
Quoted 7 lines · Jason Baron
From: Jason Baron <[email protected]>
Let's use PCIExpressHost with QOM.
Reviewed-by Paolo Bonzini <[email protected]>Acked-by Andreas Färber <[email protected]>Signed-off-by Jason Baron <[email protected]>
Applied, thanks.
Quoted 44 lines
--- hw/pcie_host.c | 14 ++++++++++++++ hw/pcie_host.h | 4 ++++ 2 files changed, 18 insertions(+), 0 deletions(-)hw/pcie_host.c +14
-0@@ -145,3 +145,17 @@ void pcie_host_mmcfg_update(PCIExpressHost *e,pcie_host_mmcfg_map (e, addr, size); } } + +static const TypeInfo pcie_host_type_info = { + .name =TYPE_PCIE_HOST_BRIDGE , + .parent =TYPE_PCI_HOST_BRIDGE , + .abstract = true, + .instance_size =sizeof (PCIExpressHost), +}; + +static void pcie_host_register_types (void ) +{ +type_register_static (&pcie_host_type_info); +} + +type_init (pcie_host_register_types)hw/pcie_host.h +4
-0@@ -24,6 +24,10 @@#include "pci_host.h" #include "memory.h" +#define TYPE_PCIE_HOST_BRIDGE "pcie-host-bridge" +#define PCIE_HOST_BRIDGE (obj) \ + OBJECT_CHECK(PCIExpressHost, (obj), TYPE_PCIE_HOST_BRIDGE) +struct PCIExpressHost {PCIHostState pci;Signature · 1 line
1.7.1
PATCH v3 12/26 ich9: Add acpi support and definitions
In reply to Jason BaronFrom: Jason Baron <[email protected]>
Lay the groundwork for subsequent ich9 support.
--- hw/acpi_ich9.c | 315 +++++++++++++++++++++++++++++++++++++++++++++++++ hw/acpi_ich9.h | 47 ++++++++ hw/i386/Makefile.objs | 1 + hw/ich9.h | 207 ++++++++++++++++++++++++++++++++ hw/pci_ids.h | 12 ++ 5 files changed, 582 insertions(+), 0 deletions(-) create mode 100644 hw/acpi_ich9.c create mode 100644 hw/acpi_ich9.h create mode 100644 hw/ich9.h
hw/acpi_ich9.c new file +315 -0
@@ -0,0 +1,315 @@ +/* +* ACPI implementation +* +* Copyright (c) 2006 Fabrice Bellard +* +* This library is free software; you can redistribute it and/or +* modify it under the terms of the GNU Lesser General Public +* License version 2 as published by the Free Software Foundation. +* +* This library is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +* Lesser General Public License for more details. +* +* You should have received a copy of the GNU Lesser General Public +* License along with this library; if not, see <http://www.gnu.org/licenses/> +*/ +/* +* Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp> +* VA Linux Systems Japan K.K. +* Copyright (C) 2012 Jason Baron <[email protected]> +* +* This is based on acpi.c. +*/ +#include "hw.h" +#include "pc.h" +#include "pci.h" +#include "qemu-timer.h" +#include "sysemu.h" +#include "acpi.h" + +#include "ich9.h" + +//#define DEBUG + +#ifdef DEBUG +#define ICH9_DEBUG (fmt, ...) \ +do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0) +#else +#define ICH9_DEBUG (fmt, ...) do { } while (0) +#endif + +static void pm_ioport_write_fallback (void *opaque,uint32_t addr,int len, +uint32_t val); +static uint32_t pm_ioport_read_fallback (void *opaque,uint32_t addr,int len); + +static void pm_update_sci (ICH9LPCPMRegs *pm) +{ +int sci_level, pm1a_sts; + + pm1a_sts =acpi_pm1_evt_get_sts (&pm->acpi_regs); + + sci_level = (((pm1a_sts & pm->acpi_regs.pm1.evt.en) & + (ACPI_BITMASK_RT_CLOCK_ENABLE | +ACPI_BITMASK_POWER_BUTTON_ENABLE | +ACPI_BITMASK_GLOBAL_LOCK_ENABLE | +ACPI_BITMASK_TIMER_ENABLE )) !=0 ); +qemu_set_irq (pm->irq, sci_level); + +/* schedule a timer interruption if needed */ +acpi_pm_tmr_update (&pm->acpi_regs, + (pm->acpi_regs.pm1.evt.en &ACPI_BITMASK_TIMER_ENABLE ) && + !(pm1a_sts &ACPI_BITMASK_TIMER_STATUS )); +} + +static void ich9_pm_update_sci_fn (ACPIREGS *regs) +{ +ICH9LPCPMRegs *pm =container_of (regs, ICH9LPCPMRegs, acpi_regs); +pm_update_sci (pm); +} + +static void pm_ioport_writeb (void *opaque,uint32_t addr,uint32_t val) +{ +ICH9LPCPMRegs *pm = opaque; + +switch (addr &ICH9_PMIO_MASK ) { + case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + ICH9_PMIO_GPE0_LEN - 1): +acpi_gpe_ioport_writeb (&pm->acpi_regs, addr, val); +break ; +default : +break ; + } + +ICH9_DEBUG ("port=0x%04x val=0x%04x\n" , addr, val); +} + +static uint32_t pm_ioport_readb (void *opaque,uint32_t addr) +{ +ICH9LPCPMRegs *pm = opaque; +uint32_t val =0 ; + +switch (addr &ICH9_PMIO_MASK ) { + case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + ICH9_PMIO_GPE0_LEN - 1): + val =acpi_gpe_ioport_readb (&pm->acpi_regs, addr); +break ; +default : + val =0 ; +break ; + } +ICH9_DEBUG ("port=0x%04x val=0x%04x\n" , addr, val); +return val; +} + +static void pm_ioport_writew (void *opaque,uint32_t addr,uint32_t val) +{ +ICH9LPCPMRegs *pm = opaque; + +switch (addr &ICH9_PMIO_MASK ) { +case ICH9_PMIO_PM1_STS : +acpi_pm1_evt_write_sts (&pm->acpi_regs, val); +pm_update_sci (pm); +break ; +case ICH9_PMIO_PM1_EN : + pm->acpi_regs.pm1.evt.en = val; +pm_update_sci (pm); +break ; +case ICH9_PMIO_PM1_CNT : +acpi_pm1_cnt_write (&pm->acpi_regs, val,0 ); +break ; +default : +pm_ioport_write_fallback (opaque, addr,2 , val); +break ; + } +ICH9_DEBUG ("port=0x%04x val=0x%04x\n" , addr, val); +} + +static uint32_t pm_ioport_readw (void *opaque,uint32_t addr) +{ +ICH9LPCPMRegs *pm = opaque; +uint32_t val; + +switch (addr &ICH9_PMIO_MASK ) { +case ICH9_PMIO_PM1_STS : + val =acpi_pm1_evt_get_sts (&pm->acpi_regs); +break ; +case ICH9_PMIO_PM1_EN : + val = pm->acpi_regs.pm1.evt.en; +break ; +case ICH9_PMIO_PM1_CNT : + val = pm->acpi_regs.pm1.cnt.cnt; +break ; +default : + val =pm_ioport_read_fallback (opaque, addr,2 ); +break ; + } +ICH9_DEBUG ("port=0x%04x val=0x%04x\n" , addr, val); +return val; +} + +static void pm_ioport_writel (void *opaque,uint32_t addr,uint32_t val) +{ +ICH9LPCPMRegs *pm = opaque; + +switch (addr &ICH9_PMIO_MASK ) { +case ICH9_PMIO_SMI_EN : + pm->smi_en = val; +break ; +default : +pm_ioport_write_fallback (opaque, addr,4 , val); +break ; + } +ICH9_DEBUG ("port=0x%04x val=0x%08x\n" , addr, val); +} + +static uint32_t pm_ioport_readl (void *opaque,uint32_t addr) +{ +ICH9LPCPMRegs *pm = opaque; +uint32_t val; + +switch (addr &ICH9_PMIO_MASK ) { +case ICH9_PMIO_PM1_TMR : + val =acpi_pm_tmr_get (&pm->acpi_regs); +break ; +case ICH9_PMIO_SMI_EN : + val = pm->smi_en; +break ; + +default : + val =pm_ioport_read_fallback (opaque, addr,4 ); +break ; + } +ICH9_DEBUG ("port=0x%04x val=0x%08x\n" , addr, val); +return val; +} + +static void pm_ioport_write_fallback (void *opaque,uint32_t addr,int len, +uint32_t val) + { +int subsize = (len ==4 ) ?2 :1 ; +IOPortWriteFunc *ioport_write = + (subsize ==2 ) ? pm_ioport_writew : pm_ioport_writeb; + +int i; + +for (i =0 ; i < len; i += subsize) { +ioport_write (opaque, addr, val); + val >>=8 * subsize; + } +} + +static uint32_t pm_ioport_read_fallback (void *opaque,uint32_t addr,int len) +{ +int subsize = (len ==4 ) ?2 :1 ; +IOPortReadFunc *ioport_read = + (subsize ==2 ) ? pm_ioport_readw : pm_ioport_readb; + +uint32_t val; +int i; + + val =0 ; +for (i =0 ; i < len; i += subsize) { + val <<=8 * subsize; + val |=ioport_read (opaque, addr); + } + +return val; +} + +void ich9_pm_iospace_update (ICH9LPCPMRegs *pm,uint32_t pm_io_base) +{ +ICH9_DEBUG ("to 0x%x\n" , pm_io_base); + +assert ((pm_io_base &ICH9_PMIO_MASK ) ==0 ); + +if (pm->pm_io_base !=0 ) { +isa_unassign_ioport (pm->pm_io_base,ICH9_PMIO_SIZE ); + } + +/* don't map at 0 */ +if (pm_io_base ==0 ) { +return ; + } + +register_ioport_write (pm_io_base,ICH9_PMIO_SIZE ,1 , pm_ioport_writeb, pm); +register_ioport_read (pm_io_base,ICH9_PMIO_SIZE ,1 , pm_ioport_readb, pm); +register_ioport_write (pm_io_base,ICH9_PMIO_SIZE ,2 , pm_ioport_writew, pm); +register_ioport_read (pm_io_base,ICH9_PMIO_SIZE ,2 , pm_ioport_readw, pm); +register_ioport_write (pm_io_base,ICH9_PMIO_SIZE ,4 , pm_ioport_writel, pm); +register_ioport_read (pm_io_base,ICH9_PMIO_SIZE ,4 , pm_ioport_readl, pm); + + pm->pm_io_base = pm_io_base; +acpi_gpe_blk (&pm->acpi_regs, pm_io_base +ICH9_PMIO_GPE0_STS ); +} + +static int ich9_pm_post_load (void *opaque,int version_id) +{ +ICH9LPCPMRegs *pm = opaque; +uint32_t pm_io_base = pm->pm_io_base; + pm->pm_io_base =0 ; +ich9_pm_iospace_update (pm, pm_io_base); +return 0 ; +} + +#define VMSTATE_GPE_ARRAY (_field, _state) \ + { \ + .name = (stringify(_field)), \ + .version_id = 0, \ + .num = ICH9_PMIO_GPE0_LEN, \ + .info = &vmstate_info_uint8, \ + .size = sizeof(uint8_t), \ + .flags = VMS_ARRAY | VMS_POINTER, \ + .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ + } + +const VMStateDescription vmstate_ich9_pm = { + .name ="ich9_pm" , + .version_id =1 , + .minimum_version_id =1 , + .minimum_version_id_old =1 , + .post_load = ich9_pm_post_load, + .fields = (VMStateField []) { +VMSTATE_UINT16 (acpi_regs.pm1.evt.sts, ICH9LPCPMRegs), +VMSTATE_UINT16 (acpi_regs.pm1.evt.en, ICH9LPCPMRegs), +VMSTATE_UINT16 (acpi_regs.pm1.cnt.cnt, ICH9LPCPMRegs), +VMSTATE_TIMER (acpi_regs.tmr.timer, ICH9LPCPMRegs), +VMSTATE_INT64 (acpi_regs.tmr.overflow_time, ICH9LPCPMRegs), +VMSTATE_GPE_ARRAY (acpi_regs.gpe.sts, ICH9LPCPMRegs), +VMSTATE_GPE_ARRAY (acpi_regs.gpe.en, ICH9LPCPMRegs), +VMSTATE_UINT32 (smi_en, ICH9LPCPMRegs), +VMSTATE_UINT32 (smi_sts, ICH9LPCPMRegs), +VMSTATE_END_OF_LIST () + } +}; + +static void pm_reset (void *opaque) +{ +ICH9LPCPMRegs *pm = opaque; +ich9_pm_iospace_update (pm,0 ); + +acpi_pm1_evt_reset (&pm->acpi_regs); +acpi_pm1_cnt_reset (&pm->acpi_regs); +acpi_pm_tmr_reset (&pm->acpi_regs); +acpi_gpe_reset (&pm->acpi_regs); + +pm_update_sci (pm); +} + +static void pm_powerdown_req (Notifier *n,void *opaque) +{ +ICH9LPCPMRegs *pm =container_of (n, ICH9LPCPMRegs, powerdown_notifier); + +acpi_pm1_evt_power_down (&pm->acpi_regs); +} + +void ich9_pm_init (ICH9LPCPMRegs *pm,qemu_irq sci_irq,qemu_irq cmos_s3) +{ +acpi_pm_tmr_init (&pm->acpi_regs, ich9_pm_update_sci_fn); +acpi_pm1_cnt_init (&pm->acpi_regs); +acpi_gpe_init (&pm->acpi_regs,ICH9_PMIO_GPE0_LEN ); + + pm->irq = sci_irq; +qemu_register_reset (pm_reset, pm); + pm->powerdown_notifier.notify = pm_powerdown_req; +qemu_register_powerdown_notifier (&pm->powerdown_notifier); +}
hw/acpi_ich9.h new file +47 -0
47 lines not on this page · raw message
hw/i386/Makefile.objs +1 -0
@@ -7,6 +7,7 @@ obj-y += debugcon.o multiboot.o obj-y += pc_piix.o obj-y += pc_sysfw.o obj-y += pam.o +obj-y += acpi_ich9.o obj-$(CONFIG_XEN) += xen_platform.o xen_apic.o obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen-host-pci-device.o obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pt.o xen_pt_config_init.o xen_pt_msi.o
hw/ich9.h new file +207 -0
207 lines not on this page · raw message
hw/pci_ids.h +12 -0
@@ -36,6 +36,7 @@#define PCI_CLASS_BRIDGE_HOST 0x0600#define PCI_CLASS_BRIDGE_ISA 0x0601#define PCI_CLASS_BRIDGE_PCI 0x0604 +#define PCI_CLASS_BRDIGE_PCI_INF_SUB 0x01#define PCI_CLASS_BRIDGE_OTHER 0x0680#define PCI_CLASS_COMMUNICATION_OTHER 0x0780
@@ -115,6 +116,17 @@#define PCI_DEVICE_ID_INTEL_82371AB 0x7111#define PCI_DEVICE_ID_INTEL_82371AB_2 0x7112#define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113 + +#define PCI_DEVICE_ID_INTEL_ICH9_0 0x2910 +#define PCI_DEVICE_ID_INTEL_ICH9_1 0x2917 +#define PCI_DEVICE_ID_INTEL_ICH9_2 0x2912 +#define PCI_DEVICE_ID_INTEL_ICH9_3 0x2913 +#define PCI_DEVICE_ID_INTEL_ICH9_4 0x2914 +#define PCI_DEVICE_ID_INTEL_ICH9_5 0x2919 +#define PCI_DEVICE_ID_INTEL_ICH9_6 0x2930 +#define PCI_DEVICE_ID_INTEL_ICH9_7 0x2916 +#define PCI_DEVICE_ID_INTEL_ICH9_8 0x2918 +#define PCI_DEVICE_ID_INTEL_82801I_UHCI1 0x2934#define PCI_DEVICE_ID_INTEL_82801I_UHCI2 0x2935#define PCI_DEVICE_ID_INTEL_82801I_UHCI3 0x2936
Signature · 1 line
1.7.1
Re: [Qemu-devel] [PATCH v3 12/26] ich9: Add acpi support and definitions
Quoted 6 lines · Jason Baron
From: Jason Baron <[email protected]>
Lay the groundwork for subsequent ich9 support.
Signed-off-by Isaku Yamahata <[email protected]>Signed-off-by Jason Baron <[email protected]>
Applied with one exception, see below.
Quoted 615 lines
--- hw/acpi_ich9.c | 315 +++++++++++++++++++++++++++++++++++++++++++++++++ hw/acpi_ich9.h | 47 ++++++++ hw/i386/Makefile.objs | 1 + hw/ich9.h | 207 ++++++++++++++++++++++++++++++++ hw/pci_ids.h | 12 ++ 5 files changed, 582 insertions(+), 0 deletions(-) create mode 100644 hw/acpi_ich9.c create mode 100644 hw/acpi_ich9.h create mode 100644 hw/ich9.hhw/acpi_ich9.c new file +315
-0@@ -0,0 +1,315 @@ +/* +* ACPI implementation +* +* Copyright (c) 2006 Fabrice Bellard +* +* This library is free software; you can redistribute it and/or +* modify it under the terms of the GNU Lesser General Public +* License version 2 as published by the Free Software Foundation. +* +* This library is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +* Lesser General Public License for more details. +* +* You should have received a copy of the GNU Lesser General Public +* License along with this library; if not, see <http://www.gnu.org/licenses/> +*/ +/* +* Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp> +* VA Linux Systems Japan K.K. +* Copyright (C) 2012 Jason Baron <[email protected]> +* +* This is based on acpi.c. +*/ +#include "hw.h" +#include "pc.h" +#include "pci.h" +#include "qemu-timer.h" +#include "sysemu.h" +#include "acpi.h" + +#include "ich9.h" + +//#define DEBUG + +#ifdef DEBUG +#define ICH9_DEBUG (fmt, ...) \ +do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0) +#else +#define ICH9_DEBUG (fmt, ...) do { } while (0) +#endif + +static void pm_ioport_write_fallback (void *opaque,uint32_t addr,int len, +uint32_t val); +static uint32_t pm_ioport_read_fallback (void *opaque,uint32_t addr,int len); + +static void pm_update_sci (ICH9LPCPMRegs *pm) +{ +int sci_level, pm1a_sts; + + pm1a_sts =acpi_pm1_evt_get_sts (&pm->acpi_regs); + + sci_level = (((pm1a_sts & pm->acpi_regs.pm1.evt.en) & + (ACPI_BITMASK_RT_CLOCK_ENABLE | +ACPI_BITMASK_POWER_BUTTON_ENABLE | +ACPI_BITMASK_GLOBAL_LOCK_ENABLE | +ACPI_BITMASK_TIMER_ENABLE )) !=0 ); +qemu_set_irq (pm->irq, sci_level); + +/* schedule a timer interruption if needed */ +acpi_pm_tmr_update (&pm->acpi_regs, + (pm->acpi_regs.pm1.evt.en &ACPI_BITMASK_TIMER_ENABLE ) && + !(pm1a_sts &ACPI_BITMASK_TIMER_STATUS )); +} + +static void ich9_pm_update_sci_fn (ACPIREGS *regs) +{ +ICH9LPCPMRegs *pm =container_of (regs, ICH9LPCPMRegs, acpi_regs); +pm_update_sci (pm); +} + +static void pm_ioport_writeb (void *opaque,uint32_t addr,uint32_t val) +{ +ICH9LPCPMRegs *pm = opaque; + +switch (addr &ICH9_PMIO_MASK ) { + case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + ICH9_PMIO_GPE0_LEN - 1): +acpi_gpe_ioport_writeb (&pm->acpi_regs, addr, val); +break ; +default : +break ; + } + +ICH9_DEBUG ("port=0x%04x val=0x%04x\n" , addr, val); +} + +static uint32_t pm_ioport_readb (void *opaque,uint32_t addr) +{ +ICH9LPCPMRegs *pm = opaque; +uint32_t val =0 ; + +switch (addr &ICH9_PMIO_MASK ) { + case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + ICH9_PMIO_GPE0_LEN - 1): + val =acpi_gpe_ioport_readb (&pm->acpi_regs, addr); +break ; +default : + val =0 ; +break ; + } +ICH9_DEBUG ("port=0x%04x val=0x%04x\n" , addr, val); +return val; +} + +static void pm_ioport_writew (void *opaque,uint32_t addr,uint32_t val) +{ +ICH9LPCPMRegs *pm = opaque; + +switch (addr &ICH9_PMIO_MASK ) { +case ICH9_PMIO_PM1_STS : +acpi_pm1_evt_write_sts (&pm->acpi_regs, val); +pm_update_sci (pm); +break ; +case ICH9_PMIO_PM1_EN : + pm->acpi_regs.pm1.evt.en = val; +pm_update_sci (pm); +break ; +case ICH9_PMIO_PM1_CNT : +acpi_pm1_cnt_write (&pm->acpi_regs, val,0 ); +break ; +default : +pm_ioport_write_fallback (opaque, addr,2 , val); +break ; + } +ICH9_DEBUG ("port=0x%04x val=0x%04x\n" , addr, val); +} + +static uint32_t pm_ioport_readw (void *opaque,uint32_t addr) +{ +ICH9LPCPMRegs *pm = opaque; +uint32_t val; + +switch (addr &ICH9_PMIO_MASK ) { +case ICH9_PMIO_PM1_STS : + val =acpi_pm1_evt_get_sts (&pm->acpi_regs); +break ; +case ICH9_PMIO_PM1_EN : + val = pm->acpi_regs.pm1.evt.en; +break ; +case ICH9_PMIO_PM1_CNT : + val = pm->acpi_regs.pm1.cnt.cnt; +break ; +default : + val =pm_ioport_read_fallback (opaque, addr,2 ); +break ; + } +ICH9_DEBUG ("port=0x%04x val=0x%04x\n" , addr, val); +return val; +} + +static void pm_ioport_writel (void *opaque,uint32_t addr,uint32_t val) +{ +ICH9LPCPMRegs *pm = opaque; + +switch (addr &ICH9_PMIO_MASK ) { +case ICH9_PMIO_SMI_EN : + pm->smi_en = val; +break ; +default : +pm_ioport_write_fallback (opaque, addr,4 , val); +break ; + } +ICH9_DEBUG ("port=0x%04x val=0x%08x\n" , addr, val); +} + +static uint32_t pm_ioport_readl (void *opaque,uint32_t addr) +{ +ICH9LPCPMRegs *pm = opaque; +uint32_t val; + +switch (addr &ICH9_PMIO_MASK ) { +case ICH9_PMIO_PM1_TMR : + val =acpi_pm_tmr_get (&pm->acpi_regs); +break ; +case ICH9_PMIO_SMI_EN : + val = pm->smi_en; +break ; + +default : + val =pm_ioport_read_fallback (opaque, addr,4 ); +break ; + } +ICH9_DEBUG ("port=0x%04x val=0x%08x\n" , addr, val); +return val; +} + +static void pm_ioport_write_fallback (void *opaque,uint32_t addr,int len, +uint32_t val) + { +int subsize = (len ==4 ) ?2 :1 ; +IOPortWriteFunc *ioport_write = + (subsize ==2 ) ? pm_ioport_writew : pm_ioport_writeb; + +int i; + +for (i =0 ; i < len; i += subsize) { +ioport_write (opaque, addr, val); + val >>=8 * subsize; + } +} + +static uint32_t pm_ioport_read_fallback (void *opaque,uint32_t addr,int len) +{ +int subsize = (len ==4 ) ?2 :1 ; +IOPortReadFunc *ioport_read = + (subsize ==2 ) ? pm_ioport_readw : pm_ioport_readb; + +uint32_t val; +int i; + + val =0 ; +for (i =0 ; i < len; i += subsize) { + val <<=8 * subsize; + val |=ioport_read (opaque, addr); + } + +return val; +} + +void ich9_pm_iospace_update (ICH9LPCPMRegs *pm,uint32_t pm_io_base) +{ +ICH9_DEBUG ("to 0x%x\n" , pm_io_base); + +assert ((pm_io_base &ICH9_PMIO_MASK ) ==0 ); + +if (pm->pm_io_base !=0 ) { +isa_unassign_ioport (pm->pm_io_base,ICH9_PMIO_SIZE ); + } + +/* don't map at 0 */ +if (pm_io_base ==0 ) { +return ; + } + +register_ioport_write (pm_io_base,ICH9_PMIO_SIZE ,1 , pm_ioport_writeb, pm); +register_ioport_read (pm_io_base,ICH9_PMIO_SIZE ,1 , pm_ioport_readb, pm); +register_ioport_write (pm_io_base,ICH9_PMIO_SIZE ,2 , pm_ioport_writew, pm); +register_ioport_read (pm_io_base,ICH9_PMIO_SIZE ,2 , pm_ioport_readw, pm); +register_ioport_write (pm_io_base,ICH9_PMIO_SIZE ,4 , pm_ioport_writel, pm); +register_ioport_read (pm_io_base,ICH9_PMIO_SIZE ,4 , pm_ioport_readl, pm); + + pm->pm_io_base = pm_io_base; +acpi_gpe_blk (&pm->acpi_regs, pm_io_base +ICH9_PMIO_GPE0_STS ); +} + +static int ich9_pm_post_load (void *opaque,int version_id) +{ +ICH9LPCPMRegs *pm = opaque; +uint32_t pm_io_base = pm->pm_io_base; + pm->pm_io_base =0 ; +ich9_pm_iospace_update (pm, pm_io_base); +return 0 ; +} + +#define VMSTATE_GPE_ARRAY (_field, _state) \ + { \ + .name = (stringify(_field)), \ + .version_id = 0, \ + .num = ICH9_PMIO_GPE0_LEN, \ + .info = &vmstate_info_uint8, \ + .size = sizeof(uint8_t), \ + .flags = VMS_ARRAY | VMS_POINTER, \ + .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ + } + +const VMStateDescription vmstate_ich9_pm = { + .name ="ich9_pm" , + .version_id =1 , + .minimum_version_id =1 , + .minimum_version_id_old =1 , + .post_load = ich9_pm_post_load, + .fields = (VMStateField []) { +VMSTATE_UINT16 (acpi_regs.pm1.evt.sts, ICH9LPCPMRegs), +VMSTATE_UINT16 (acpi_regs.pm1.evt.en, ICH9LPCPMRegs), +VMSTATE_UINT16 (acpi_regs.pm1.cnt.cnt, ICH9LPCPMRegs), +VMSTATE_TIMER (acpi_regs.tmr.timer, ICH9LPCPMRegs), +VMSTATE_INT64 (acpi_regs.tmr.overflow_time, ICH9LPCPMRegs), +VMSTATE_GPE_ARRAY (acpi_regs.gpe.sts, ICH9LPCPMRegs), +VMSTATE_GPE_ARRAY (acpi_regs.gpe.en, ICH9LPCPMRegs), +VMSTATE_UINT32 (smi_en, ICH9LPCPMRegs), +VMSTATE_UINT32 (smi_sts, ICH9LPCPMRegs), +VMSTATE_END_OF_LIST () + } +}; + +static void pm_reset (void *opaque) +{ +ICH9LPCPMRegs *pm = opaque; +ich9_pm_iospace_update (pm,0 ); + +acpi_pm1_evt_reset (&pm->acpi_regs); +acpi_pm1_cnt_reset (&pm->acpi_regs); +acpi_pm_tmr_reset (&pm->acpi_regs); +acpi_gpe_reset (&pm->acpi_regs); + +pm_update_sci (pm); +} + +static void pm_powerdown_req (Notifier *n,void *opaque) +{ +ICH9LPCPMRegs *pm =container_of (n, ICH9LPCPMRegs, powerdown_notifier); + +acpi_pm1_evt_power_down (&pm->acpi_regs); +} + +void ich9_pm_init (ICH9LPCPMRegs *pm,qemu_irq sci_irq,qemu_irq cmos_s3) +{ +acpi_pm_tmr_init (&pm->acpi_regs, ich9_pm_update_sci_fn); +acpi_pm1_cnt_init (&pm->acpi_regs); +acpi_gpe_init (&pm->acpi_regs,ICH9_PMIO_GPE0_LEN ); + + pm->irq = sci_irq; +qemu_register_reset (pm_reset, pm); + pm->powerdown_notifier.notify = pm_powerdown_req; +qemu_register_powerdown_notifier (&pm->powerdown_notifier); +}hw/acpi_ich9.h new file +47
-0@@ -0,0 +1,47 @@ +/* +* QEMU GMCH/ICH9 LPC PM Emulation +* +* Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp> +* VA Linux Systems Japan K.K. +* +* This library is free software; you can redistribute it and/or +* modify it under the terms of the GNU Lesser General Public +* License as published by the Free Software Foundation; either +* version 2 of the License, or (at your option) any later version. +* +* This library is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +* Lesser General Public License for more details. +* +* You should have received a copy of the GNU Lesser General Public +* License along with this library; if not, see <http://www.gnu.org/licenses/> +*/ + +#ifndef HW_ACPI_ICH9_H +#define HW_ACPI_ICH9_H + +#include "acpi.h" + +typedef struct ICH9LPCPMRegs { +/* +* In ich9 spec says that pm1_cnt register is 32bit width and +* that the upper 16bits are reserved and unused. +* PM1a_CNT_BLK = 2 in FADT so it is defined as uint16_t. +*/ +ACPIREGS acpi_regs; +uint32_t smi_en; +uint32_t smi_sts; + +qemu_irq irq;/* SCI */ + +uint32_t pm_io_base; +Notifier powerdown_notifier; +}ICH9LPCPMRegs ; + +void ich9_pm_init (ICH9LPCPMRegs *pm, +qemu_irq sci_irq,qemu_irq cmos_s3_resume); +void ich9_pm_iospace_update (ICH9LPCPMRegs *pm,uint32_t pm_io_base); +extern const VMStateDescription vmstate_ich9_pm; + +#endif /* HW_ACPI_ICH9_H */ hw/i386/Makefile.objs +1
-0@@ -7,6 +7,7 @@ obj-y += debugcon.o multiboot.o obj-y += pc_piix.o obj-y += pc_sysfw.o obj-y += pam.o +obj-y += acpi_ich9.o obj-$(CONFIG_XEN) += xen_platform.o xen_apic.o obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen-host-pci-device.o obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pt.o xen_pt_config_init.o xen_pt_msi.ohw/ich9.h new file +207
-0@@ -0,0 +1,207 @@ +#ifndef HW_ICH9_H +#define HW_ICH9_H + +#include "hw.h" +#include "range.h" +#include "isa.h" +#include "sysbus.h" +#include "pc.h" +#include "apm.h" +#include "ioapic.h" +#include "pci.h" +#include "pcie_host.h" +#include "pci_bridge.h" +#include "acpi.h" +#include "acpi_ich9.h" +#include "pam.h" +#include "pci_internals.h" + +void ich9_lpc_set_irq (void *opaque,int irq_num,int level); +int ich9_lpc_map_irq (PCIDevice *pci_dev,int intx); +void ich9_lpc_pm_init (PCIDevice *pci_lpc,qemu_irq cmos_s3); +PCIBus *ich9_d2pbr_init (PCIBus *bus,int devfn,int sec_bus); +i2c_bus *ich9_smb_init (PCIBus *bus,int devfn,uint32_t smb_io_base); + +#define ICH9_CC_SIZE (16 * 1024)/* 16KB */ + +#define TYPE_ICH9_LPC_DEVICE "ICH9 LPC" +#define ICH9_LPC_DEVICE (obj) \ + OBJECT_CHECK(ICH9LPCState, (obj), TYPE_ICH9_LPC_DEVICE) + +typedef struct ICH9LPCState { +/* ICH9 LPC PCI to ISA bridge */ +PCIDevice d; + +/* (pci device, intx) -> pirq +* In real chipset case, the unused slots are never used +* as ICH9 supports only D25-D32 irq routing. +* On the other hand in qemu case, any slot/function can be populated +* via command line option. +* So fallback interrupt routing for any devices in any slots is necessary. +*/ +uint8_t irr[PCI_SLOT_MAX ][PCI_NUM_PINS ]; + +APMState apm; +ICH9LPCPMRegs pm; +uint32_t sci_level;/* track sci level */ + +/* 10.1 Chipset Configuration registers(Memory Space) +which is pointed by RCBA */ +uint8_t chip_config[ICH9_CC_SIZE ]; +/* isa bus */ +ISABus *isa_bus; +MemoryRegion rbca_mem; + +qemu_irq *pic; +qemu_irq *ioapic; +}ICH9LPCState ; + +#define Q35_MASK (bit, ms_bit, ls_bit) \ +((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1))) + +/* ICH9: Chipset Configuration Registers */ +#define ICH9_CC_ADDR_MASK (ICH9_CC_SIZE - 1) + +#define ICH9_CC +#define ICH9_CC_D28IP 0x310C +#define ICH9_CC_D28IP_SHIFT 4 +#define ICH9_CC_D28IP_MASK 0xf +#define ICH9_CC_D28IP_DEFAULT 0x00214321 +#define ICH9_CC_D31IR 0x3140 +#define ICH9_CC_D30IR 0x3142 +#define ICH9_CC_D29IR 0x3144 +#define ICH9_CC_D28IR 0x3146 +#define ICH9_CC_D27IR 0x3148 +#define ICH9_CC_D26IR 0x314C +#define ICH9_CC_D25IR 0x3150 +#define ICH9_CC_DIR_DEFAULT 0x3210 +#define ICH9_CC_D30IR_DEFAULT 0x0 +#define ICH9_CC_DIR_SHIFT 4 +#define ICH9_CC_DIR_MASK 0x7 +#define ICH9_CC_OIC 0x31FF +#define ICH9_CC_OIC_AEN 0x1 + +/* D28:F[0-5] */ +#define ICH9_PCIE_DEV 28 +#define ICH9_PCIE_FUNC_MAX 6 + + +/* D29:F0 USB UHCI Controller #1 */ +#define ICH9_USB_UHCI1_DEV 29 +#define ICH9_USB_UHCI1_FUNC 0 + +/* D30:F0 DMI-to-PCI brdige */ +#define ICH9_D2P_BRIDGE "ICH9 D2P BRIDGE" +#define ICH9_D2P_BRIDGE_SAVEVM_VERSION 0 + +#define ICH9_D2P_BRIDGE_DEV 30 +#define ICH9_D2P_BRIDGE_FUNC 0 + +#define ICH9_D2P_SECONDARY_DEFAULT (256 - 8) + +#define ICH9_D2P_A2_REVISION 0x92 + + +/* D31:F1 LPC controller */ +#define ICH9_A2_LPC "ICH9 A2 LPC" +#define ICH9_A2_LPC_SAVEVM_VERSION 0 + +#define ICH9_LPC_DEV 31 +#define ICH9_LPC_FUNC 0 + +#define ICH9_A2_LPC_REVISION 0x2 +#define ICH9_LPC_NB_PIRQS 8/* PCI A-H */ + +#define ICH9_LPC_PMBASE 0x40 +#define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK Q35_MASK(32, 15, 7) +#define ICH9_LPC_PMBASE_RTE 0x1 +#define ICH9_LPC_PMBASE_DEFAULT 0x1 +#define ICH9_LPC_ACPI_CTRL 0x44 +#define ICH9_LPC_ACPI_CTRL_ACPI_EN 0x80 +#define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK Q35_MASK(8, 2, 0) +#define ICH9_LPC_ACPI_CTRL_9 0x0 +#define ICH9_LPC_ACPI_CTRL_10 0x1 +#define ICH9_LPC_ACPI_CTRL_11 0x2 +#define ICH9_LPC_ACPI_CTRL_20 0x4 +#define ICH9_LPC_ACPI_CTRL_21 0x5 +#define ICH9_LPC_ACPI_CTRL_DEFAULT 0x0 + +#define ICH9_LPC_PIRQA_ROUT 0x60 +#define ICH9_LPC_PIRQB_ROUT 0x61 +#define ICH9_LPC_PIRQC_ROUT 0x62 +#define ICH9_LPC_PIRQD_ROUT 0x63 + +#define ICH9_LPC_PIRQE_ROUT 0x68 +#define ICH9_LPC_PIRQF_ROUT 0x69 +#define ICH9_LPC_PIRQG_ROUT 0x6a +#define ICH9_LPC_PIRQH_ROUT 0x6b + +#define ICH9_LPC_PIRQ_ROUT_IRQEN 0x80 +#define ICH9_LPC_PIRQ_ROUT_MASK Q35_MASK(8, 3, 0) +#define ICH9_LPC_PIRQ_ROUT_DEFAULT 0x80 + +#define ICH9_LPC_RCBA 0xf0 +#define ICH9_LPC_RCBA_BA_MASK Q35_MASK(32, 31, 14) +#define ICH9_LPC_RCBA_EN 0x1 +#define ICH9_LPC_RCBA_DEFAULT 0x0 + +#define ICH9_LPC_PIC_NUM_PINS 16 +#define ICH9_LPC_IOAPIC_NUM_PINS 24 + +/* D31:F2 SATA Controller #1 */ +#define ICH9_SATA1_DEV 31 +#define ICH9_SATA1_FUNC 2 + +/* D30:F1 power management I/O registers +offset from the address ICH9_LPC_PMBASE */ + +/* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */ +#define ICH9_PMIO_SIZE 128 +#define ICH9_PMIO_MASK (ICH9_PMIO_SIZE - 1) + +#define ICH9_PMIO_PM1_STS 0x00 +#define ICH9_PMIO_PM1_EN 0x02 +#define ICH9_PMIO_PM1_CNT 0x04 +#define ICH9_PMIO_PM1_TMR 0x08 +#define ICH9_PMIO_GPE0_STS 0x20 +#define ICH9_PMIO_GPE0_EN 0x28 +#define ICH9_PMIO_GPE0_LEN 16 +#define ICH9_PMIO_SMI_EN 0x30 +#define ICH9_PMIO_SMI_EN_APMC_EN (1 << 5) +#define ICH9_PMIO_SMI_STS 0x34 + +/* FADT ACPI_ENABLE/ACPI_DISABLE */ +#define ICH9_APM_ACPI_ENABLE 0x2 +#define ICH9_APM_ACPI_DISABLE 0x3 + + +/* D31:F3 SMBus controller */ +#define ICH9_A2_SMB_REVISION 0x02 +#define ICH9_SMB_PI 0x00 + +#define ICH9_SMB_SMBMBAR0 0x10 +#define ICH9_SMB_SMBMBAR1 0x14 +#define ICH9_SMB_SMBM_BAR 0 +#define ICH9_SMB_SMBM_SIZE (1 << 8) +#define ICH9_SMB_SMB_BASE 0x20 +#define ICH9_SMB_SMB_BASE_BAR 4 +#define ICH9_SMB_SMB_BASE_SIZE (1 << 5) +#define ICH9_SMB_HOSTC 0x40 +#define ICH9_SMB_HOSTC_SSRESET ((uint8_t)(1 << 3)) +#define ICH9_SMB_HOSTC_I2C_EN ((uint8_t)(1 << 2)) +#define ICH9_SMB_HOSTC_SMB_SMI_EN ((uint8_t)(1 << 1)) +#define ICH9_SMB_HOSTC_HST_EN ((uint8_t)(1 << 0)) + +/* D31:F3 SMBus I/O and memory mapped I/O registers */ +#define ICH9_SMB_DEV 31 +#define ICH9_SMB_FUNC 3 + +#define ICH9_SMB_HST_STS 0x00 +#define ICH9_SMB_HST_CNT 0x02 +#define ICH9_SMB_HST_CMD 0x03 +#define ICH9_SMB_XMIT_SLVA 0x04 +#define ICH9_SMB_HST_D0 0x05 +#define ICH9_SMB_HST_D1 0x06 +#define ICH9_SMB_HOST_BLOCK_DB 0x07 + +#endif /* HW_ICH9_H */ hw/pci_ids.h +0
-0
hw/pci_ids.h line 39
Quoted 4 lines
hw/pci_ids.h +1
-0@@ -36,6 +36,7 @@#define PCI_CLASS_BRIDGE_HOST 0x0600#define PCI_CLASS_BRIDGE_ISA 0x0601#define PCI_CLASS_BRIDGE_PCI 0x0604 +#define PCI_CLASS_BRDIGE_PCI_INF_SUB 0x01
This bit has several problems:
- it's not in linux pci_ids to which we try to stick
- name is mistyped
- whitespace is damaged
As it's unused by this patch I dropped this chunk for now, and applied the rest of the patch.
Quoted 23 lines
hw/pci_ids.h +11
-0#define PCI_CLASS_BRIDGE_OTHER 0x0680#define PCI_CLASS_COMMUNICATION_OTHER 0x0780@@ -115,6 +116,17 @@#define PCI_DEVICE_ID_INTEL_82371AB 0x7111#define PCI_DEVICE_ID_INTEL_82371AB_2 0x7112#define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113 + +#define PCI_DEVICE_ID_INTEL_ICH9_0 0x2910 +#define PCI_DEVICE_ID_INTEL_ICH9_1 0x2917 +#define PCI_DEVICE_ID_INTEL_ICH9_2 0x2912 +#define PCI_DEVICE_ID_INTEL_ICH9_3 0x2913 +#define PCI_DEVICE_ID_INTEL_ICH9_4 0x2914 +#define PCI_DEVICE_ID_INTEL_ICH9_5 0x2919 +#define PCI_DEVICE_ID_INTEL_ICH9_6 0x2930 +#define PCI_DEVICE_ID_INTEL_ICH9_7 0x2916 +#define PCI_DEVICE_ID_INTEL_ICH9_8 0x2918 +#define PCI_DEVICE_ID_INTEL_82801I_UHCI1 0x2934#define PCI_DEVICE_ID_INTEL_82801I_UHCI2 0x2935#define PCI_DEVICE_ID_INTEL_82801I_UHCI3 0x2936Signature · 1 line
1.7.1
Re: [Qemu-devel] [PATCH v3 12/26] ich9: Add acpi support and definitions
In reply to Jason BaronQuoted 37 lines · Jason Baron
From: Jason Baron <[email protected]>
Lay the groundwork for subsequent ich9 support.
Signed-off-by Isaku Yamahata <[email protected]>Signed-off-by Jason Baron <[email protected]>--- hw/acpi_ich9.c | 315 +++++++++++++++++++++++++++++++++++++++++++++++++ hw/acpi_ich9.h | 47 ++++++++ hw/i386/Makefile.objs | 1 + hw/ich9.h | 207 ++++++++++++++++++++++++++++++++ hw/pci_ids.h | 12 ++ 5 files changed, 582 insertions(+), 0 deletions(-) create mode 100644 hw/acpi_ich9.c create mode 100644 hw/acpi_ich9.h create mode 100644 hw/ich9.hhw/acpi_ich9.c new file +14
-0@@ -0,0 +1,315 @@ +/* +* ACPI implementation +* +* Copyright (c) 2006 Fabrice Bellard +* +* This library is free software; you can redistribute it and/or +* modify it under the terms of the GNU Lesser General Public +* License version 2 as published by the Free Software Foundation. +* +* This library is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +* Lesser General Public License for more details. +*
hw/acpi_ich9.c line 24
Quoted 10 lines
hw/acpi_ich9.c new file +10
-0+* You should have received a copy of the GNU Lesser General Public +* License along with this library; if not, see <http://www.gnu.org/licenses/> +*/ +/* +* Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp> +* VA Linux Systems Japan K.K. +* Copyright (C) 2012 Jason Baron <[email protected]> +* +* This is based on acpi.c. +*/
Anthony, acpi.c header says:
* Contributions after 2012-01-13 are licensed under the terms of the
* GNU GPL, version 2 or (at your option) any later version.
I am guessing it would be hard to guess which parts of this patch are original and which are derivative.
Signature · 1 line
MST
Re: [Qemu-devel] [PATCH v3 12/26] ich9: Add acpi support and definitions
In reply to Jason BaronQuoted 415 lines · Jason Baron
From: Jason Baron <[email protected]>
Lay the groundwork for subsequent ich9 support.
Signed-off-by Isaku Yamahata <[email protected]>Signed-off-by Jason Baron <[email protected]>--- hw/acpi_ich9.c | 315 +++++++++++++++++++++++++++++++++++++++++++++++++ hw/acpi_ich9.h | 47 ++++++++ hw/i386/Makefile.objs | 1 + hw/ich9.h | 207 ++++++++++++++++++++++++++++++++ hw/pci_ids.h | 12 ++ 5 files changed, 582 insertions(+), 0 deletions(-) create mode 100644 hw/acpi_ich9.c create mode 100644 hw/acpi_ich9.h create mode 100644 hw/ich9.hhw/acpi_ich9.c new file +315
-0@@ -0,0 +1,315 @@ +/* +* ACPI implementation +* +* Copyright (c) 2006 Fabrice Bellard +* +* This library is free software; you can redistribute it and/or +* modify it under the terms of the GNU Lesser General Public +* License version 2 as published by the Free Software Foundation. +* +* This library is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +* Lesser General Public License for more details. +* +* You should have received a copy of the GNU Lesser General Public +* License along with this library; if not, see <http://www.gnu.org/licenses/> +*/ +/* +* Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp> +* VA Linux Systems Japan K.K. +* Copyright (C) 2012 Jason Baron <[email protected]> +* +* This is based on acpi.c. +*/ +#include "hw.h" +#include "pc.h" +#include "pci.h" +#include "qemu-timer.h" +#include "sysemu.h" +#include "acpi.h" + +#include "ich9.h" + +//#define DEBUG + +#ifdef DEBUG +#define ICH9_DEBUG (fmt, ...) \ +do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0) +#else +#define ICH9_DEBUG (fmt, ...) do { } while (0) +#endif + +static void pm_ioport_write_fallback (void *opaque,uint32_t addr,int len, +uint32_t val); +static uint32_t pm_ioport_read_fallback (void *opaque,uint32_t addr,int len); + +static void pm_update_sci (ICH9LPCPMRegs *pm) +{ +int sci_level, pm1a_sts; + + pm1a_sts =acpi_pm1_evt_get_sts (&pm->acpi_regs); + + sci_level = (((pm1a_sts & pm->acpi_regs.pm1.evt.en) & + (ACPI_BITMASK_RT_CLOCK_ENABLE | +ACPI_BITMASK_POWER_BUTTON_ENABLE | +ACPI_BITMASK_GLOBAL_LOCK_ENABLE | +ACPI_BITMASK_TIMER_ENABLE )) !=0 ); +qemu_set_irq (pm->irq, sci_level); + +/* schedule a timer interruption if needed */ +acpi_pm_tmr_update (&pm->acpi_regs, + (pm->acpi_regs.pm1.evt.en &ACPI_BITMASK_TIMER_ENABLE ) && + !(pm1a_sts &ACPI_BITMASK_TIMER_STATUS )); +} + +static void ich9_pm_update_sci_fn (ACPIREGS *regs) +{ +ICH9LPCPMRegs *pm =container_of (regs, ICH9LPCPMRegs, acpi_regs); +pm_update_sci (pm); +} + +static void pm_ioport_writeb (void *opaque,uint32_t addr,uint32_t val) +{ +ICH9LPCPMRegs *pm = opaque; + +switch (addr &ICH9_PMIO_MASK ) { + case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + ICH9_PMIO_GPE0_LEN - 1): +acpi_gpe_ioport_writeb (&pm->acpi_regs, addr, val); +break ; +default : +break ; + } + +ICH9_DEBUG ("port=0x%04x val=0x%04x\n" , addr, val); +} + +static uint32_t pm_ioport_readb (void *opaque,uint32_t addr) +{ +ICH9LPCPMRegs *pm = opaque; +uint32_t val =0 ; + +switch (addr &ICH9_PMIO_MASK ) { + case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + ICH9_PMIO_GPE0_LEN - 1): + val =acpi_gpe_ioport_readb (&pm->acpi_regs, addr); +break ; +default : + val =0 ; +break ; + } +ICH9_DEBUG ("port=0x%04x val=0x%04x\n" , addr, val); +return val; +} + +static void pm_ioport_writew (void *opaque,uint32_t addr,uint32_t val) +{ +ICH9LPCPMRegs *pm = opaque; + +switch (addr &ICH9_PMIO_MASK ) { +case ICH9_PMIO_PM1_STS : +acpi_pm1_evt_write_sts (&pm->acpi_regs, val); +pm_update_sci (pm); +break ; +case ICH9_PMIO_PM1_EN : + pm->acpi_regs.pm1.evt.en = val; +pm_update_sci (pm); +break ; +case ICH9_PMIO_PM1_CNT : +acpi_pm1_cnt_write (&pm->acpi_regs, val,0 ); +break ; +default : +pm_ioport_write_fallback (opaque, addr,2 , val); +break ; + } +ICH9_DEBUG ("port=0x%04x val=0x%04x\n" , addr, val); +} + +static uint32_t pm_ioport_readw (void *opaque,uint32_t addr) +{ +ICH9LPCPMRegs *pm = opaque; +uint32_t val; + +switch (addr &ICH9_PMIO_MASK ) { +case ICH9_PMIO_PM1_STS : + val =acpi_pm1_evt_get_sts (&pm->acpi_regs); +break ; +case ICH9_PMIO_PM1_EN : + val = pm->acpi_regs.pm1.evt.en; +break ; +case ICH9_PMIO_PM1_CNT : + val = pm->acpi_regs.pm1.cnt.cnt; +break ; +default : + val =pm_ioport_read_fallback (opaque, addr,2 ); +break ; + } +ICH9_DEBUG ("port=0x%04x val=0x%04x\n" , addr, val); +return val; +} + +static void pm_ioport_writel (void *opaque,uint32_t addr,uint32_t val) +{ +ICH9LPCPMRegs *pm = opaque; + +switch (addr &ICH9_PMIO_MASK ) { +case ICH9_PMIO_SMI_EN : + pm->smi_en = val; +break ; +default : +pm_ioport_write_fallback (opaque, addr,4 , val); +break ; + } +ICH9_DEBUG ("port=0x%04x val=0x%08x\n" , addr, val); +} + +static uint32_t pm_ioport_readl (void *opaque,uint32_t addr) +{ +ICH9LPCPMRegs *pm = opaque; +uint32_t val; + +switch (addr &ICH9_PMIO_MASK ) { +case ICH9_PMIO_PM1_TMR : + val =acpi_pm_tmr_get (&pm->acpi_regs); +break ; +case ICH9_PMIO_SMI_EN : + val = pm->smi_en; +break ; + +default : + val =pm_ioport_read_fallback (opaque, addr,4 ); +break ; + } +ICH9_DEBUG ("port=0x%04x val=0x%08x\n" , addr, val); +return val; +} + +static void pm_ioport_write_fallback (void *opaque,uint32_t addr,int len, +uint32_t val) + { +int subsize = (len ==4 ) ?2 :1 ; +IOPortWriteFunc *ioport_write = + (subsize ==2 ) ? pm_ioport_writew : pm_ioport_writeb; + +int i; + +for (i =0 ; i < len; i += subsize) { +ioport_write (opaque, addr, val); + val >>=8 * subsize; + } +} + +static uint32_t pm_ioport_read_fallback (void *opaque,uint32_t addr,int len) +{ +int subsize = (len ==4 ) ?2 :1 ; +IOPortReadFunc *ioport_read = + (subsize ==2 ) ? pm_ioport_readw : pm_ioport_readb; + +uint32_t val; +int i; + + val =0 ; +for (i =0 ; i < len; i += subsize) { + val <<=8 * subsize; + val |=ioport_read (opaque, addr); + } + +return val; +} + +void ich9_pm_iospace_update (ICH9LPCPMRegs *pm,uint32_t pm_io_base) +{ +ICH9_DEBUG ("to 0x%x\n" , pm_io_base); + +assert ((pm_io_base &ICH9_PMIO_MASK ) ==0 ); + +if (pm->pm_io_base !=0 ) { +isa_unassign_ioport (pm->pm_io_base,ICH9_PMIO_SIZE ); + } + +/* don't map at 0 */ +if (pm_io_base ==0 ) { +return ; + } + +register_ioport_write (pm_io_base,ICH9_PMIO_SIZE ,1 , pm_ioport_writeb, pm); +register_ioport_read (pm_io_base,ICH9_PMIO_SIZE ,1 , pm_ioport_readb, pm); +register_ioport_write (pm_io_base,ICH9_PMIO_SIZE ,2 , pm_ioport_writew, pm); +register_ioport_read (pm_io_base,ICH9_PMIO_SIZE ,2 , pm_ioport_readw, pm); +register_ioport_write (pm_io_base,ICH9_PMIO_SIZE ,4 , pm_ioport_writel, pm); +register_ioport_read (pm_io_base,ICH9_PMIO_SIZE ,4 , pm_ioport_readl, pm); + + pm->pm_io_base = pm_io_base; +acpi_gpe_blk (&pm->acpi_regs, pm_io_base +ICH9_PMIO_GPE0_STS ); +} + +static int ich9_pm_post_load (void *opaque,int version_id) +{ +ICH9LPCPMRegs *pm = opaque; +uint32_t pm_io_base = pm->pm_io_base; + pm->pm_io_base =0 ; +ich9_pm_iospace_update (pm, pm_io_base); +return 0 ; +} + +#define VMSTATE_GPE_ARRAY (_field, _state) \ + { \ + .name = (stringify(_field)), \ + .version_id = 0, \ + .num = ICH9_PMIO_GPE0_LEN, \ + .info = &vmstate_info_uint8, \ + .size = sizeof(uint8_t), \ + .flags = VMS_ARRAY | VMS_POINTER, \ + .offset = vmstate_offset_pointer(_state, _field, uint8_t), \ + } + +const VMStateDescription vmstate_ich9_pm = { + .name ="ich9_pm" , + .version_id =1 , + .minimum_version_id =1 , + .minimum_version_id_old =1 , + .post_load = ich9_pm_post_load, + .fields = (VMStateField []) { +VMSTATE_UINT16 (acpi_regs.pm1.evt.sts, ICH9LPCPMRegs), +VMSTATE_UINT16 (acpi_regs.pm1.evt.en, ICH9LPCPMRegs), +VMSTATE_UINT16 (acpi_regs.pm1.cnt.cnt, ICH9LPCPMRegs), +VMSTATE_TIMER (acpi_regs.tmr.timer, ICH9LPCPMRegs), +VMSTATE_INT64 (acpi_regs.tmr.overflow_time, ICH9LPCPMRegs), +VMSTATE_GPE_ARRAY (acpi_regs.gpe.sts, ICH9LPCPMRegs), +VMSTATE_GPE_ARRAY (acpi_regs.gpe.en, ICH9LPCPMRegs), +VMSTATE_UINT32 (smi_en, ICH9LPCPMRegs), +VMSTATE_UINT32 (smi_sts, ICH9LPCPMRegs), +VMSTATE_END_OF_LIST () + } +}; + +static void pm_reset (void *opaque) +{ +ICH9LPCPMRegs *pm = opaque; +ich9_pm_iospace_update (pm,0 ); + +acpi_pm1_evt_reset (&pm->acpi_regs); +acpi_pm1_cnt_reset (&pm->acpi_regs); +acpi_pm_tmr_reset (&pm->acpi_regs); +acpi_gpe_reset (&pm->acpi_regs); + +pm_update_sci (pm); +} + +static void pm_powerdown_req (Notifier *n,void *opaque) +{ +ICH9LPCPMRegs *pm =container_of (n, ICH9LPCPMRegs, powerdown_notifier); + +acpi_pm1_evt_power_down (&pm->acpi_regs); +} + +void ich9_pm_init (ICH9LPCPMRegs *pm,qemu_irq sci_irq,qemu_irq cmos_s3) +{ +acpi_pm_tmr_init (&pm->acpi_regs, ich9_pm_update_sci_fn); +acpi_pm1_cnt_init (&pm->acpi_regs); +acpi_gpe_init (&pm->acpi_regs,ICH9_PMIO_GPE0_LEN ); + + pm->irq = sci_irq; +qemu_register_reset (pm_reset, pm); + pm->powerdown_notifier.notify = pm_powerdown_req; +qemu_register_powerdown_notifier (&pm->powerdown_notifier); +}hw/acpi_ich9.h new file +47
-0@@ -0,0 +1,47 @@ +/* +* QEMU GMCH/ICH9 LPC PM Emulation +* +* Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp> +* VA Linux Systems Japan K.K. +* +* This library is free software; you can redistribute it and/or +* modify it under the terms of the GNU Lesser General Public +* License as published by the Free Software Foundation; either +* version 2 of the License, or (at your option) any later version. +* +* This library is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +* Lesser General Public License for more details. +* +* You should have received a copy of the GNU Lesser General Public +* License along with this library; if not, see <http://www.gnu.org/licenses/> +*/ + +#ifndef HW_ACPI_ICH9_H +#define HW_ACPI_ICH9_H + +#include "acpi.h" + +typedef struct ICH9LPCPMRegs { +/* +* In ich9 spec says that pm1_cnt register is 32bit width and +* that the upper 16bits are reserved and unused. +* PM1a_CNT_BLK = 2 in FADT so it is defined as uint16_t. +*/ +ACPIREGS acpi_regs; +uint32_t smi_en; +uint32_t smi_sts; + +qemu_irq irq;/* SCI */ + +uint32_t pm_io_base; +Notifier powerdown_notifier; +}ICH9LPCPMRegs ; + +void ich9_pm_init (ICH9LPCPMRegs *pm, +qemu_irq sci_irq,qemu_irq cmos_s3_resume); +void ich9_pm_iospace_update (ICH9LPCPMRegs *pm,uint32_t pm_io_base); +extern const VMStateDescription vmstate_ich9_pm; + +#endif /* HW_ACPI_ICH9_H */ hw/i386/Makefile.objs +1
-0@@ -7,6 +7,7 @@ obj-y += debugcon.o multiboot.o obj-y += pc_piix.o obj-y += pc_sysfw.o obj-y += pam.o +obj-y += acpi_ich9.o obj-$(CONFIG_XEN) += xen_platform.o xen_apic.o obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen-host-pci-device.o obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pt.o xen_pt_config_init.o xen_pt_msi.ohw/ich9.h new file +6
-0@@ -0,0 +1,207 @@ +#ifndef HW_ICH9_H +#define HW_ICH9_H + +#include "hw.h" +#include "range.h" +#include "isa.h"
hw/ich9.h line 16
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hw/ich9.h new file +10
-0+#include "sysbus.h" +#include "pc.h" +#include "apm.h" +#include "ioapic.h" +#include "pci.h" +#include "pcie_host.h" +#include "pci_bridge.h" +#include "acpi.h" +#include "acpi_ich9.h" +#include "pam.h"
Here too pam.h is not needed.
Quoted 223 lines
hw/ich9.h new file +191
-0+#include "pci_internals.h" + +void ich9_lpc_set_irq (void *opaque,int irq_num,int level); +int ich9_lpc_map_irq (PCIDevice *pci_dev,int intx); +void ich9_lpc_pm_init (PCIDevice *pci_lpc,qemu_irq cmos_s3); +PCIBus *ich9_d2pbr_init (PCIBus *bus,int devfn,int sec_bus); +i2c_bus *ich9_smb_init (PCIBus *bus,int devfn,uint32_t smb_io_base); + +#define ICH9_CC_SIZE (16 * 1024)/* 16KB */ + +#define TYPE_ICH9_LPC_DEVICE "ICH9 LPC" +#define ICH9_LPC_DEVICE (obj) \ + OBJECT_CHECK(ICH9LPCState, (obj), TYPE_ICH9_LPC_DEVICE) + +typedef struct ICH9LPCState { +/* ICH9 LPC PCI to ISA bridge */ +PCIDevice d; + +/* (pci device, intx) -> pirq +* In real chipset case, the unused slots are never used +* as ICH9 supports only D25-D32 irq routing. +* On the other hand in qemu case, any slot/function can be populated +* via command line option. +* So fallback interrupt routing for any devices in any slots is necessary. +*/ +uint8_t irr[PCI_SLOT_MAX ][PCI_NUM_PINS ]; + +APMState apm; +ICH9LPCPMRegs pm; +uint32_t sci_level;/* track sci level */ + +/* 10.1 Chipset Configuration registers(Memory Space) +which is pointed by RCBA */ +uint8_t chip_config[ICH9_CC_SIZE ]; +/* isa bus */ +ISABus *isa_bus; +MemoryRegion rbca_mem; + +qemu_irq *pic; +qemu_irq *ioapic; +}ICH9LPCState ; + +#define Q35_MASK (bit, ms_bit, ls_bit) \ +((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1))) + +/* ICH9: Chipset Configuration Registers */ +#define ICH9_CC_ADDR_MASK (ICH9_CC_SIZE - 1) + +#define ICH9_CC +#define ICH9_CC_D28IP 0x310C +#define ICH9_CC_D28IP_SHIFT 4 +#define ICH9_CC_D28IP_MASK 0xf +#define ICH9_CC_D28IP_DEFAULT 0x00214321 +#define ICH9_CC_D31IR 0x3140 +#define ICH9_CC_D30IR 0x3142 +#define ICH9_CC_D29IR 0x3144 +#define ICH9_CC_D28IR 0x3146 +#define ICH9_CC_D27IR 0x3148 +#define ICH9_CC_D26IR 0x314C +#define ICH9_CC_D25IR 0x3150 +#define ICH9_CC_DIR_DEFAULT 0x3210 +#define ICH9_CC_D30IR_DEFAULT 0x0 +#define ICH9_CC_DIR_SHIFT 4 +#define ICH9_CC_DIR_MASK 0x7 +#define ICH9_CC_OIC 0x31FF +#define ICH9_CC_OIC_AEN 0x1 + +/* D28:F[0-5] */ +#define ICH9_PCIE_DEV 28 +#define ICH9_PCIE_FUNC_MAX 6 + + +/* D29:F0 USB UHCI Controller #1 */ +#define ICH9_USB_UHCI1_DEV 29 +#define ICH9_USB_UHCI1_FUNC 0 + +/* D30:F0 DMI-to-PCI brdige */ +#define ICH9_D2P_BRIDGE "ICH9 D2P BRIDGE" +#define ICH9_D2P_BRIDGE_SAVEVM_VERSION 0 + +#define ICH9_D2P_BRIDGE_DEV 30 +#define ICH9_D2P_BRIDGE_FUNC 0 + +#define ICH9_D2P_SECONDARY_DEFAULT (256 - 8) + +#define ICH9_D2P_A2_REVISION 0x92 + + +/* D31:F1 LPC controller */ +#define ICH9_A2_LPC "ICH9 A2 LPC" +#define ICH9_A2_LPC_SAVEVM_VERSION 0 + +#define ICH9_LPC_DEV 31 +#define ICH9_LPC_FUNC 0 + +#define ICH9_A2_LPC_REVISION 0x2 +#define ICH9_LPC_NB_PIRQS 8/* PCI A-H */ + +#define ICH9_LPC_PMBASE 0x40 +#define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK Q35_MASK(32, 15, 7) +#define ICH9_LPC_PMBASE_RTE 0x1 +#define ICH9_LPC_PMBASE_DEFAULT 0x1 +#define ICH9_LPC_ACPI_CTRL 0x44 +#define ICH9_LPC_ACPI_CTRL_ACPI_EN 0x80 +#define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK Q35_MASK(8, 2, 0) +#define ICH9_LPC_ACPI_CTRL_9 0x0 +#define ICH9_LPC_ACPI_CTRL_10 0x1 +#define ICH9_LPC_ACPI_CTRL_11 0x2 +#define ICH9_LPC_ACPI_CTRL_20 0x4 +#define ICH9_LPC_ACPI_CTRL_21 0x5 +#define ICH9_LPC_ACPI_CTRL_DEFAULT 0x0 + +#define ICH9_LPC_PIRQA_ROUT 0x60 +#define ICH9_LPC_PIRQB_ROUT 0x61 +#define ICH9_LPC_PIRQC_ROUT 0x62 +#define ICH9_LPC_PIRQD_ROUT 0x63 + +#define ICH9_LPC_PIRQE_ROUT 0x68 +#define ICH9_LPC_PIRQF_ROUT 0x69 +#define ICH9_LPC_PIRQG_ROUT 0x6a +#define ICH9_LPC_PIRQH_ROUT 0x6b + +#define ICH9_LPC_PIRQ_ROUT_IRQEN 0x80 +#define ICH9_LPC_PIRQ_ROUT_MASK Q35_MASK(8, 3, 0) +#define ICH9_LPC_PIRQ_ROUT_DEFAULT 0x80 + +#define ICH9_LPC_RCBA 0xf0 +#define ICH9_LPC_RCBA_BA_MASK Q35_MASK(32, 31, 14) +#define ICH9_LPC_RCBA_EN 0x1 +#define ICH9_LPC_RCBA_DEFAULT 0x0 + +#define ICH9_LPC_PIC_NUM_PINS 16 +#define ICH9_LPC_IOAPIC_NUM_PINS 24 + +/* D31:F2 SATA Controller #1 */ +#define ICH9_SATA1_DEV 31 +#define ICH9_SATA1_FUNC 2 + +/* D30:F1 power management I/O registers +offset from the address ICH9_LPC_PMBASE */ + +/* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */ +#define ICH9_PMIO_SIZE 128 +#define ICH9_PMIO_MASK (ICH9_PMIO_SIZE - 1) + +#define ICH9_PMIO_PM1_STS 0x00 +#define ICH9_PMIO_PM1_EN 0x02 +#define ICH9_PMIO_PM1_CNT 0x04 +#define ICH9_PMIO_PM1_TMR 0x08 +#define ICH9_PMIO_GPE0_STS 0x20 +#define ICH9_PMIO_GPE0_EN 0x28 +#define ICH9_PMIO_GPE0_LEN 16 +#define ICH9_PMIO_SMI_EN 0x30 +#define ICH9_PMIO_SMI_EN_APMC_EN (1 << 5) +#define ICH9_PMIO_SMI_STS 0x34 + +/* FADT ACPI_ENABLE/ACPI_DISABLE */ +#define ICH9_APM_ACPI_ENABLE 0x2 +#define ICH9_APM_ACPI_DISABLE 0x3 + + +/* D31:F3 SMBus controller */ +#define ICH9_A2_SMB_REVISION 0x02 +#define ICH9_SMB_PI 0x00 + +#define ICH9_SMB_SMBMBAR0 0x10 +#define ICH9_SMB_SMBMBAR1 0x14 +#define ICH9_SMB_SMBM_BAR 0 +#define ICH9_SMB_SMBM_SIZE (1 << 8) +#define ICH9_SMB_SMB_BASE 0x20 +#define ICH9_SMB_SMB_BASE_BAR 4 +#define ICH9_SMB_SMB_BASE_SIZE (1 << 5) +#define ICH9_SMB_HOSTC 0x40 +#define ICH9_SMB_HOSTC_SSRESET ((uint8_t)(1 << 3)) +#define ICH9_SMB_HOSTC_I2C_EN ((uint8_t)(1 << 2)) +#define ICH9_SMB_HOSTC_SMB_SMI_EN ((uint8_t)(1 << 1)) +#define ICH9_SMB_HOSTC_HST_EN ((uint8_t)(1 << 0)) + +/* D31:F3 SMBus I/O and memory mapped I/O registers */ +#define ICH9_SMB_DEV 31 +#define ICH9_SMB_FUNC 3 + +#define ICH9_SMB_HST_STS 0x00 +#define ICH9_SMB_HST_CNT 0x02 +#define ICH9_SMB_HST_CMD 0x03 +#define ICH9_SMB_XMIT_SLVA 0x04 +#define ICH9_SMB_HST_D0 0x05 +#define ICH9_SMB_HST_D1 0x06 +#define ICH9_SMB_HOST_BLOCK_DB 0x07 + +#endif /* HW_ICH9_H */ hw/pci_ids.h +12
-0@@ -36,6 +36,7 @@#define PCI_CLASS_BRIDGE_HOST 0x0600#define PCI_CLASS_BRIDGE_ISA 0x0601#define PCI_CLASS_BRIDGE_PCI 0x0604 +#define PCI_CLASS_BRDIGE_PCI_INF_SUB 0x01#define PCI_CLASS_BRIDGE_OTHER 0x0680#define PCI_CLASS_COMMUNICATION_OTHER 0x0780@@ -115,6 +116,17 @@#define PCI_DEVICE_ID_INTEL_82371AB 0x7111#define PCI_DEVICE_ID_INTEL_82371AB_2 0x7112#define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113 + +#define PCI_DEVICE_ID_INTEL_ICH9_0 0x2910 +#define PCI_DEVICE_ID_INTEL_ICH9_1 0x2917 +#define PCI_DEVICE_ID_INTEL_ICH9_2 0x2912 +#define PCI_DEVICE_ID_INTEL_ICH9_3 0x2913 +#define PCI_DEVICE_ID_INTEL_ICH9_4 0x2914 +#define PCI_DEVICE_ID_INTEL_ICH9_5 0x2919 +#define PCI_DEVICE_ID_INTEL_ICH9_6 0x2930 +#define PCI_DEVICE_ID_INTEL_ICH9_7 0x2916 +#define PCI_DEVICE_ID_INTEL_ICH9_8 0x2918 +#define PCI_DEVICE_ID_INTEL_82801I_UHCI1 0x2934#define PCI_DEVICE_ID_INTEL_82801I_UHCI2 0x2935#define PCI_DEVICE_ID_INTEL_82801I_UHCI3 0x2936Signature · 1 line
1.7.1
PATCH v3 13/26 ich9: Add the lpc chip
In reply to Jason BaronFrom: Jason Baron <[email protected]>
Add support for the ich9 LPC chip.
--- hw/i386/Makefile.objs | 2 +- hw/lpc_ich9.c | 523 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 524 insertions(+), 1 deletions(-) create mode 100644 hw/lpc_ich9.c
hw/i386/Makefile.objs +1 -1
@@ -7,7 +7,7 @@ obj-y += debugcon.o multiboot.o obj-y += pc_piix.o obj-y += pc_sysfw.o obj-y += pam.o -obj-y += acpi_ich9.o +obj-y += acpi_ich9.o lpc_ich9.o obj-$(CONFIG_XEN) += xen_platform.o xen_apic.o obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen-host-pci-device.o obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pt.o xen_pt_config_init.o xen_pt_msi.o
hw/lpc_ich9.c new file +523 -0
523 lines not on this page · raw message
Signature · 1 line
1.7.1
Michael S. Tsirkin
AppliedRe: [Qemu-devel] [PATCH v3 13/26] ich9: Add the lpc chip
Quoted 6 lines · Jason Baron
From: Jason Baron <[email protected]>
Add support for the ich9 LPC chip.
Signed-off-by Isaku Yamahata <[email protected]>Signed-off-by Jason Baron <[email protected]>
Applied, thanks.
Quoted 550 lines
--- hw/i386/Makefile.objs | 2 +- hw/lpc_ich9.c | 523 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 524 insertions(+), 1 deletions(-) create mode 100644 hw/lpc_ich9.chw/i386/Makefile.objs +1
-1@@ -7,7 +7,7 @@ obj-y += debugcon.o multiboot.o obj-y += pc_piix.o obj-y += pc_sysfw.o obj-y += pam.o -obj-y += acpi_ich9.o +obj-y += acpi_ich9.o lpc_ich9.o obj-$(CONFIG_XEN) += xen_platform.o xen_apic.o obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen-host-pci-device.o obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pt.o xen_pt_config_init.o xen_pt_msi.ohw/lpc_ich9.c new file +523
-0@@ -0,0 +1,523 @@ +/* +* Copyright (c) 2006 Fabrice Bellard +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +* THE SOFTWARE. +*/ +/* +* QEMU ICH9 Emulation +* +* Copyright (c) 2009, 2010, 2011 +* Isaku Yamahata <yamahata at valinux co jp> +* VA Linux Systems Japan K.K. +* Copyright (C) 2012 Jason Baron <[email protected]> +* +* This is based on piix_pci.c, but heavily modified. +* +* This library is free software; you can redistribute it and/or +* modify it under the terms of the GNU Lesser General Public +* License as published by the Free Software Foundation; either +* version 2 of the License, or (at your option) any later version. +* +* This library is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +* Lesser General Public License for more details. +* +* You should have received a copy of the GNU Lesser General Public +* License along with this library; if not, see <http://www.gnu.org/licenses/> +*/ + +#include "qemu-common.h" +#include "hw.h" +#include "range.h" +#include "isa.h" +#include "sysbus.h" +#include "pc.h" +#include "apm.h" +#include "ioapic.h" +#include "pci.h" +#include "pcie_host.h" +#include "pci_bridge.h" +#include "ich9.h" +#include "acpi.h" +#include "acpi_ich9.h" +#include "pam.h" +#include "pci_internals.h" +#include "exec-memory.h" + +static int ich9_lpc_sci_irq (ICH9LPCState *lpc); + +/*****************************************************************************/ +/* ICH9 LPC PCI to ISA bridge */ + +static void ich9_lpc_reset (DeviceState *qdev); + +/* chipset configuration register +* to access chipset configuration registers, pci_[sg]et_{byte, word, long} +* are used. +* Although it's not pci configuration space, it's little endian as Intel. +*/ + +static void ich9_cc_update_ir (uint8_t irr[PCI_NUM_PINS ],uint16_t ir) +{ +int intx; +for (intx =0 ; intx <PCI_NUM_PINS ; intx++) { + irr[intx] = (ir >> (intx *ICH9_CC_DIR_SHIFT )) &ICH9_CC_DIR_MASK ; + } +} + +static void ich9_cc_update (ICH9LPCState *lpc) +{ +int slot; +int pci_intx; + +const int reg_offsets[] = { +ICH9_CC_D25IR , +ICH9_CC_D26IR , +ICH9_CC_D27IR , +ICH9_CC_D28IR , +ICH9_CC_D29IR , +ICH9_CC_D30IR , +ICH9_CC_D31IR , + }; +const int *offset; + +/* D{25 - 31}IR, but D30IR is read only to 0. */ +for (slot =25 , offset = reg_offsets; slot <32 ; slot++, offset++) { +if (slot ==30 ) { +continue ; + } +ich9_cc_update_ir (lpc->irr[slot], +pci_get_word (lpc->chip_config + *offset)); + } + +/* +* D30: DMI2PCI bridge +* It is arbitrarily decided how INTx lines of PCI devicesbehind the bridge +* are connected to pirq lines. Our choice is PIRQ[E-H]. +* INT[A-D] are connected to PIRQ[E-H] +*/ +for (pci_intx =0 ; pci_intx <PCI_NUM_PINS ; pci_intx++) { + lpc->irr[30 ][pci_intx] = pci_intx +4 ; + } +} + +static void ich9_cc_init (ICH9LPCState *lpc) +{ +int slot; +int intx; + +/* the default irq routing is arbitrary as long as it matches with +* acpi irq routing table. +* The one that is incompatible with piix_pci(= bochs) one is +* intentionally chosen to let the users know that the different +* board is used. +* +* int[A-D] -> pirq[E-F] +* avoid pirq A-D because they are used for pci express port +*/ +for (slot =0 ; slot <PCI_SLOT_MAX ; slot++) { +for (intx =0 ; intx <PCI_NUM_PINS ; intx++) { + lpc->irr[slot][intx] = (slot + intx) %4 +4 ; + } + } +ich9_cc_update (lpc); +} + +static void ich9_cc_reset (ICH9LPCState *lpc) +{ +uint8_t *c = lpc->chip_config; + +memset (lpc->chip_config,0 ,sizeof (lpc->chip_config)); + +pci_set_long (c +ICH9_CC_D31IR ,ICH9_CC_DIR_DEFAULT ); +pci_set_long (c +ICH9_CC_D30IR ,ICH9_CC_D30IR_DEFAULT ); +pci_set_long (c +ICH9_CC_D29IR ,ICH9_CC_DIR_DEFAULT ); +pci_set_long (c +ICH9_CC_D28IR ,ICH9_CC_DIR_DEFAULT ); +pci_set_long (c +ICH9_CC_D27IR ,ICH9_CC_DIR_DEFAULT ); +pci_set_long (c +ICH9_CC_D26IR ,ICH9_CC_DIR_DEFAULT ); +pci_set_long (c +ICH9_CC_D25IR ,ICH9_CC_DIR_DEFAULT ); + +ich9_cc_update (lpc); +} + +static void ich9_cc_addr_len (uint64_t *addr,unsigned *len) +{ + *addr &=ICH9_CC_ADDR_MASK ; +if (*addr + *len >=ICH9_CC_SIZE ) { + *len =ICH9_CC_SIZE - *addr; + } +} + +/* val: little endian */ +static void ich9_cc_write (void *opaque,target_phys_addr_t addr, +uint64_t val,unsigned len) +{ +ICH9LPCState *lpc = (ICH9LPCState *)opaque; + +ich9_cc_addr_len (&addr, &len); +memcpy (lpc->chip_config + addr, &val, len); +ich9_cc_update (lpc); +} + +/* return value: little endian */ +static uint64_t ich9_cc_read (void *opaque,target_phys_addr_t addr, +unsigned len) +{ +ICH9LPCState *lpc = (ICH9LPCState *)opaque; + +uint32_t val =0 ; +ich9_cc_addr_len (&addr, &len); +memcpy (&val, lpc->chip_config + addr, len); +return val; +} + +/* IRQ routing */ +/* */ +static void ich9_lpc_rout (uint8_t pirq_rout,int *pic_irq,int *pic_dis) +{ + *pic_irq = pirq_rout &ICH9_LPC_PIRQ_ROUT_MASK ; + *pic_dis = pirq_rout &ICH9_LPC_PIRQ_ROUT_IRQEN ; +} + +static void ich9_lpc_pic_irq (ICH9LPCState *lpc,int pirq_num, +int *pic_irq,int *pic_dis) +{ +switch (pirq_num) { + case 0 ... 3: /* A-D */ +ich9_lpc_rout (lpc->d.config[ICH9_LPC_PIRQA_ROUT + pirq_num], + pic_irq, pic_dis); +return ; + case 4 ... 7: /* E-H */ +ich9_lpc_rout (lpc->d.config[ICH9_LPC_PIRQE_ROUT + (pirq_num -4 )], + pic_irq, pic_dis); +return ; +default : +break ; + } +abort (); +} + +/* pic_irq: i8254 irq 0-15 */ +static void ich9_lpc_update_pic (ICH9LPCState *lpc,int pic_irq) +{ +int i, pic_level; + +/* The pic level is the logical OR of all the PCI irqs mapped to it */ + pic_level =0 ; +for (i =0 ; i <ICH9_LPC_NB_PIRQS ; i++) { +int tmp_irq; +int tmp_dis; +ich9_lpc_pic_irq (lpc, i, &tmp_irq, &tmp_dis); +if (!tmp_dis && pic_irq == tmp_irq) { + pic_level |=pci_bus_get_irq_level (lpc->d.bus, i); + } + } +if (pic_irq ==ich9_lpc_sci_irq (lpc)) { + pic_level |= lpc->sci_level; + } + +qemu_set_irq (lpc->pic[pic_irq], pic_level); +} + +/* pirq: pirq[A-H] 0-7*/ +static void ich9_lpc_update_by_pirq (ICH9LPCState *lpc,int pirq) +{ +int pic_irq; +int pic_dis; + +ich9_lpc_pic_irq (lpc, pirq, &pic_irq, &pic_dis); +assert (pic_irq <ICH9_LPC_PIC_NUM_PINS ); +if (pic_dis) { +return ; + } + +ich9_lpc_update_pic (lpc, pic_irq); +} + +/* APIC mode: GSIx: PIRQ[A-H] -> GSI 16, ... no pirq shares same APIC pins. */ +static int ich9_pirq_to_gsi (int pirq) +{ +return pirq +ICH9_LPC_PIC_NUM_PINS ; +} + +static int ich9_gsi_to_pirq (int gsi) +{ +return gsi -ICH9_LPC_PIC_NUM_PINS ; +} + +static void ich9_lpc_update_apic (ICH9LPCState *lpc,int gsi) +{ +int level; + + level =pci_bus_get_irq_level (lpc->d.bus,ich9_gsi_to_pirq (gsi)); +if (gsi ==ich9_lpc_sci_irq (lpc)) { + level |= lpc->sci_level; + } + +qemu_set_irq (lpc->ioapic[gsi], level); +} + +void ich9_lpc_set_irq (void *opaque,int pirq,int level) +{ +ICH9LPCState *lpc = opaque; + +assert (0 <= pirq); +assert (pirq <ICH9_LPC_NB_PIRQS ); + +ich9_lpc_update_apic (lpc,ich9_pirq_to_gsi (pirq)); +ich9_lpc_update_by_pirq (lpc, pirq); +} + +/* return the pirq number (PIRQ[A-H]:0-7) corresponding to +* a given device irq pin. +*/ +int ich9_lpc_map_irq (PCIDevice *pci_dev,int intx) +{ +BusState *bus =qdev_get_parent_bus (&pci_dev->qdev); +PCIBus *pci_bus =PCI_BUS (bus); +PCIDevice *lpc_pdev = + pci_bus->devices[PCI_DEVFN (ICH9_LPC_DEV ,ICH9_LPC_FUNC )]; +ICH9LPCState *lpc =ICH9_LPC_DEVICE (lpc_pdev); + +return lpc->irr[PCI_SLOT (pci_dev->devfn)][intx]; +} + +static int ich9_lpc_sci_irq (ICH9LPCState *lpc) +{ +switch (lpc->d.config[ICH9_LPC_ACPI_CTRL ] & +ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK ) { +case ICH9_LPC_ACPI_CTRL_9 : +return 9 ; +case ICH9_LPC_ACPI_CTRL_10 : +return 10 ; +case ICH9_LPC_ACPI_CTRL_11 : +return 11 ; +case ICH9_LPC_ACPI_CTRL_20 : +return 20 ; +case ICH9_LPC_ACPI_CTRL_21 : +return 21 ; +default : +/* reserved */ +break ; + } +return -1 ; +} + +static void ich9_set_sci (void *opaque,int irq_num,int level) +{ +ICH9LPCState *lpc = opaque; +int irq; + +assert (irq_num ==0 ); + level = !!level; +if (level == lpc->sci_level) { +return ; + } + lpc->sci_level = level; + + irq =ich9_lpc_sci_irq (lpc); +if (irq <0 ) { +return ; + } + +ich9_lpc_update_apic (lpc, irq); +if (irq <ICH9_LPC_PIC_NUM_PINS ) { +ich9_lpc_update_pic (lpc, irq); + } +} + +void ich9_lpc_pm_init (PCIDevice *lpc_pci,qemu_irq cmos_s3) +{ +ICH9LPCState *lpc =ICH9_LPC_DEVICE (lpc_pci); +qemu_irq *sci_irq; + + sci_irq =qemu_allocate_irqs (ich9_set_sci, lpc,1 ); +ich9_pm_init (&lpc->pm, sci_irq[0 ], cmos_s3); + +ich9_lpc_reset (&lpc->d.qdev); +} + +/* APM */ + +static void ich9_apm_ctrl_changed (uint32_t val,void *arg) +{ +ICH9LPCState *lpc = arg; + +/* ACPI specs 3.0, 4.7.2.5 */ +acpi_pm1_cnt_update (&lpc->pm.acpi_regs, + val ==ICH9_APM_ACPI_ENABLE , + val ==ICH9_APM_ACPI_DISABLE ); + +/* SMI_EN = PMBASE + 30. SMI control and enable register */ +if (lpc->pm.smi_en &ICH9_PMIO_SMI_EN_APMC_EN ) { +cpu_interrupt (first_cpu,CPU_INTERRUPT_SMI ); + } +} + +/* config:PMBASE */ +static void +ich9_lpc_pmbase_update (ICH9LPCState *lpc) +{ +uint32_t pm_io_base =pci_get_long (lpc->d.config +ICH9_LPC_PMBASE ); + pm_io_base &=ICH9_LPC_PMBASE_BASE_ADDRESS_MASK ; + +ich9_pm_iospace_update (&lpc->pm, pm_io_base); +} + +/* config:RBCA */ +static void ich9_lpc_rcba_update (ICH9LPCState *lpc,uint32_t rbca_old) +{ +uint32_t rbca =pci_get_long (lpc->d.config +ICH9_LPC_RCBA ); + +if (rbca_old &ICH9_LPC_RCBA_EN ) { +memory_region_del_subregion (get_system_memory (), &lpc->rbca_mem); + } +if (rbca &ICH9_LPC_RCBA_EN ) { +memory_region_add_subregion_overlap (get_system_memory (), + rbca &ICH9_LPC_RCBA_BA_MASK , + &lpc->rbca_mem,1 ); + } +} + +static int ich9_lpc_post_load (void *opaque,int version_id) +{ +ICH9LPCState *lpc = opaque; + +ich9_lpc_pmbase_update (lpc); +ich9_lpc_rcba_update (lpc,0 /* disabled ICH9_LPC_RBCA_EN */ ); +return 0 ; +} + +static void ich9_lpc_config_write (PCIDevice *d, +uint32_t addr,uint32_t val,int len) +{ +ICH9LPCState *lpc =ICH9_LPC_DEVICE (d); +uint32_t rbca_old =pci_get_long (d->config +ICH9_LPC_RCBA ); + +pci_default_write_config (d, addr, val, len); +if (ranges_overlap (addr, len,ICH9_LPC_PMBASE ,4 )) { +ich9_lpc_pmbase_update (lpc); + } +if (ranges_overlap (addr, len,ICH9_LPC_RCBA ,4 )) { +ich9_lpc_rcba_update (lpc, rbca_old); + } +} + +static void ich9_lpc_reset (DeviceState *qdev) +{ +PCIDevice *d =PCI_DEVICE (qdev); +ICH9LPCState *lpc =ICH9_LPC_DEVICE (d); +uint32_t rbca_old =pci_get_long (d->config +ICH9_LPC_RCBA ); +int i; + +for (i =0 ; i <4 ; i++) { +pci_set_byte (d->config +ICH9_LPC_PIRQA_ROUT + i, +ICH9_LPC_PIRQ_ROUT_DEFAULT ); + } +for (i =0 ; i <4 ; i++) { +pci_set_byte (d->config +ICH9_LPC_PIRQE_ROUT + i, +ICH9_LPC_PIRQ_ROUT_DEFAULT ); + } +pci_set_byte (d->config +ICH9_LPC_ACPI_CTRL ,ICH9_LPC_ACPI_CTRL_DEFAULT ); + +pci_set_long (d->config +ICH9_LPC_PMBASE ,ICH9_LPC_PMBASE_DEFAULT ); +pci_set_long (d->config +ICH9_LPC_RCBA ,ICH9_LPC_RCBA_DEFAULT ); + +ich9_cc_reset (lpc); + +ich9_lpc_pmbase_update (lpc); +ich9_lpc_rcba_update (lpc, rbca_old); + + lpc->sci_level =0 ; +} + +static const MemoryRegionOps rbca_mmio_ops = { + .read = ich9_cc_read, + .write = ich9_cc_write, + .endianness =DEVICE_LITTLE_ENDIAN , +}; + +static int ich9_lpc_initfn (PCIDevice *d) +{ +ICH9LPCState *lpc =ICH9_LPC_DEVICE (d); +ISABus *isa_bus; + + isa_bus =isa_bus_new (&d->qdev,get_system_io ()); + +pci_set_long (d->wmask +ICH9_LPC_PMBASE , +ICH9_LPC_PMBASE_BASE_ADDRESS_MASK ); + +memory_region_init_io (&lpc->rbca_mem, &rbca_mmio_ops, lpc, +"lpc-rbca-mmio" ,ICH9_CC_SIZE ); + + lpc->isa_bus = isa_bus; + +ich9_cc_init (lpc); +apm_init (&lpc->apm, ich9_apm_ctrl_changed, lpc); +return 0 ; +} + +static const VMStateDescription vmstate_ich9_lpc = { + .name ="ICH9LPC" , + .version_id =1 , + .minimum_version_id =1 , + .minimum_version_id_old =1 , + .post_load = ich9_lpc_post_load, + .fields = (VMStateField []) { +VMSTATE_PCI_DEVICE (d, ICH9LPCState), +VMSTATE_STRUCT (apm, ICH9LPCState,0 , vmstate_apm, APMState), +VMSTATE_STRUCT (pm, ICH9LPCState,0 , vmstate_ich9_pm, ICH9LPCPMRegs), +VMSTATE_UINT8_ARRAY (chip_config, ICH9LPCState,ICH9_CC_SIZE ), +VMSTATE_UINT32 (sci_level, ICH9LPCState), +VMSTATE_END_OF_LIST () + } +}; + +static void ich9_lpc_class_init (ObjectClass *klass,void *data) +{ +DeviceClass *dc =DEVICE_CLASS (klass); +PCIDeviceClass *k =PCI_DEVICE_CLASS (klass); + + dc->reset = ich9_lpc_reset; + k->init = ich9_lpc_initfn; + dc->vmsd = &vmstate_ich9_lpc; + dc->no_user =1 ; + k->config_write = ich9_lpc_config_write; + dc->desc ="ICH9 LPC bridge" ; + k->vendor_id =PCI_VENDOR_ID_INTEL ; + k->device_id =PCI_DEVICE_ID_INTEL_ICH9_8 ; + k->revision =ICH9_A2_LPC_REVISION ; + k->class_id =PCI_CLASS_BRIDGE_ISA ; + +} + +static const TypeInfo ich9_lpc_info = { + .name =TYPE_ICH9_LPC_DEVICE , + .parent =TYPE_PCI_DEVICE , + .instance_size =sizeof (struct ICH9LPCState ), + .class_init = ich9_lpc_class_init, +}; + +static void ich9_lpc_register (void ) +{ +type_register_static (&ich9_lpc_info); +} + +type_init (ich9_lpc_register);Signature · 1 line
1.7.1
Re: [Qemu-devel] [PATCH v3 13/26] ich9: Add the lpc chip
In reply to Jason BaronQuoted 42 lines · Jason Baron
From: Jason Baron <[email protected]>
Add support for the ich9 LPC chip.
Signed-off-by Isaku Yamahata <[email protected]>Signed-off-by Jason Baron <[email protected]>--- hw/i386/Makefile.objs | 2 +- hw/lpc_ich9.c | 523 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 524 insertions(+), 1 deletions(-) create mode 100644 hw/lpc_ich9.chw/i386/Makefile.objs +1
-1@@ -7,7 +7,7 @@ obj-y += debugcon.o multiboot.o obj-y += pc_piix.o obj-y += pc_sysfw.o obj-y += pam.o -obj-y += acpi_ich9.o +obj-y += acpi_ich9.o lpc_ich9.o obj-$(CONFIG_XEN) += xen_platform.o xen_apic.o obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen-host-pci-device.o obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pt.o xen_pt_config_init.o xen_pt_msi.ohw/lpc_ich9.c new file +11
-0@@ -0,0 +1,523 @@ +/* +* Copyright (c) 2006 Fabrice Bellard +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in
hw/lpc_ich9.c line 21
Quoted 10 lines
hw/lpc_ich9.c new file +10
-0+* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +* THE SOFTWARE. +*/
Above is confusing until one notices the below "this is based on piix_pci.c" and looks at that file.
I think it's best to just use copyright Fabrice selected for all of this file. Jason, Isaku, could you please both respond whether it's OK with you both?
Quoted 504 lines
hw/lpc_ich9.c new file +502
-0+/* +* QEMU ICH9 Emulation +* +* Copyright (c) 2009, 2010, 2011 +* Isaku Yamahata <yamahata at valinux co jp> +* VA Linux Systems Japan K.K. +* Copyright (C) 2012 Jason Baron <[email protected]> +* +* This is based on piix_pci.c, but heavily modified. +* +* This library is free software; you can redistribute it and/or +* modify it under the terms of the GNU Lesser General Public +* License as published by the Free Software Foundation; either +* version 2 of the License, or (at your option) any later version. +* +* This library is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +* Lesser General Public License for more details. +* +* You should have received a copy of the GNU Lesser General Public +* License along with this library; if not, see <http://www.gnu.org/licenses/> +*/ + +#include "qemu-common.h" +#include "hw.h" +#include "range.h" +#include "isa.h" +#include "sysbus.h" +#include "pc.h" +#include "apm.h" +#include "ioapic.h" +#include "pci.h" +#include "pcie_host.h" +#include "pci_bridge.h" +#include "ich9.h" +#include "acpi.h" +#include "acpi_ich9.h" +#include "pam.h" +#include "pci_internals.h" +#include "exec-memory.h" + +static int ich9_lpc_sci_irq (ICH9LPCState *lpc); + +/*****************************************************************************/ +/* ICH9 LPC PCI to ISA bridge */ + +static void ich9_lpc_reset (DeviceState *qdev); + +/* chipset configuration register +* to access chipset configuration registers, pci_[sg]et_{byte, word, long} +* are used. +* Although it's not pci configuration space, it's little endian as Intel. +*/ + +static void ich9_cc_update_ir (uint8_t irr[PCI_NUM_PINS ],uint16_t ir) +{ +int intx; +for (intx =0 ; intx <PCI_NUM_PINS ; intx++) { + irr[intx] = (ir >> (intx *ICH9_CC_DIR_SHIFT )) &ICH9_CC_DIR_MASK ; + } +} + +static void ich9_cc_update (ICH9LPCState *lpc) +{ +int slot; +int pci_intx; + +const int reg_offsets[] = { +ICH9_CC_D25IR , +ICH9_CC_D26IR , +ICH9_CC_D27IR , +ICH9_CC_D28IR , +ICH9_CC_D29IR , +ICH9_CC_D30IR , +ICH9_CC_D31IR , + }; +const int *offset; + +/* D{25 - 31}IR, but D30IR is read only to 0. */ +for (slot =25 , offset = reg_offsets; slot <32 ; slot++, offset++) { +if (slot ==30 ) { +continue ; + } +ich9_cc_update_ir (lpc->irr[slot], +pci_get_word (lpc->chip_config + *offset)); + } + +/* +* D30: DMI2PCI bridge +* It is arbitrarily decided how INTx lines of PCI devicesbehind the bridge +* are connected to pirq lines. Our choice is PIRQ[E-H]. +* INT[A-D] are connected to PIRQ[E-H] +*/ +for (pci_intx =0 ; pci_intx <PCI_NUM_PINS ; pci_intx++) { + lpc->irr[30 ][pci_intx] = pci_intx +4 ; + } +} + +static void ich9_cc_init (ICH9LPCState *lpc) +{ +int slot; +int intx; + +/* the default irq routing is arbitrary as long as it matches with +* acpi irq routing table. +* The one that is incompatible with piix_pci(= bochs) one is +* intentionally chosen to let the users know that the different +* board is used. +* +* int[A-D] -> pirq[E-F] +* avoid pirq A-D because they are used for pci express port +*/ +for (slot =0 ; slot <PCI_SLOT_MAX ; slot++) { +for (intx =0 ; intx <PCI_NUM_PINS ; intx++) { + lpc->irr[slot][intx] = (slot + intx) %4 +4 ; + } + } +ich9_cc_update (lpc); +} + +static void ich9_cc_reset (ICH9LPCState *lpc) +{ +uint8_t *c = lpc->chip_config; + +memset (lpc->chip_config,0 ,sizeof (lpc->chip_config)); + +pci_set_long (c +ICH9_CC_D31IR ,ICH9_CC_DIR_DEFAULT ); +pci_set_long (c +ICH9_CC_D30IR ,ICH9_CC_D30IR_DEFAULT ); +pci_set_long (c +ICH9_CC_D29IR ,ICH9_CC_DIR_DEFAULT ); +pci_set_long (c +ICH9_CC_D28IR ,ICH9_CC_DIR_DEFAULT ); +pci_set_long (c +ICH9_CC_D27IR ,ICH9_CC_DIR_DEFAULT ); +pci_set_long (c +ICH9_CC_D26IR ,ICH9_CC_DIR_DEFAULT ); +pci_set_long (c +ICH9_CC_D25IR ,ICH9_CC_DIR_DEFAULT ); + +ich9_cc_update (lpc); +} + +static void ich9_cc_addr_len (uint64_t *addr,unsigned *len) +{ + *addr &=ICH9_CC_ADDR_MASK ; +if (*addr + *len >=ICH9_CC_SIZE ) { + *len =ICH9_CC_SIZE - *addr; + } +} + +/* val: little endian */ +static void ich9_cc_write (void *opaque,target_phys_addr_t addr, +uint64_t val,unsigned len) +{ +ICH9LPCState *lpc = (ICH9LPCState *)opaque; + +ich9_cc_addr_len (&addr, &len); +memcpy (lpc->chip_config + addr, &val, len); +ich9_cc_update (lpc); +} + +/* return value: little endian */ +static uint64_t ich9_cc_read (void *opaque,target_phys_addr_t addr, +unsigned len) +{ +ICH9LPCState *lpc = (ICH9LPCState *)opaque; + +uint32_t val =0 ; +ich9_cc_addr_len (&addr, &len); +memcpy (&val, lpc->chip_config + addr, len); +return val; +} + +/* IRQ routing */ +/* */ +static void ich9_lpc_rout (uint8_t pirq_rout,int *pic_irq,int *pic_dis) +{ + *pic_irq = pirq_rout &ICH9_LPC_PIRQ_ROUT_MASK ; + *pic_dis = pirq_rout &ICH9_LPC_PIRQ_ROUT_IRQEN ; +} + +static void ich9_lpc_pic_irq (ICH9LPCState *lpc,int pirq_num, +int *pic_irq,int *pic_dis) +{ +switch (pirq_num) { + case 0 ... 3: /* A-D */ +ich9_lpc_rout (lpc->d.config[ICH9_LPC_PIRQA_ROUT + pirq_num], + pic_irq, pic_dis); +return ; + case 4 ... 7: /* E-H */ +ich9_lpc_rout (lpc->d.config[ICH9_LPC_PIRQE_ROUT + (pirq_num -4 )], + pic_irq, pic_dis); +return ; +default : +break ; + } +abort (); +} + +/* pic_irq: i8254 irq 0-15 */ +static void ich9_lpc_update_pic (ICH9LPCState *lpc,int pic_irq) +{ +int i, pic_level; + +/* The pic level is the logical OR of all the PCI irqs mapped to it */ + pic_level =0 ; +for (i =0 ; i <ICH9_LPC_NB_PIRQS ; i++) { +int tmp_irq; +int tmp_dis; +ich9_lpc_pic_irq (lpc, i, &tmp_irq, &tmp_dis); +if (!tmp_dis && pic_irq == tmp_irq) { + pic_level |=pci_bus_get_irq_level (lpc->d.bus, i); + } + } +if (pic_irq ==ich9_lpc_sci_irq (lpc)) { + pic_level |= lpc->sci_level; + } + +qemu_set_irq (lpc->pic[pic_irq], pic_level); +} + +/* pirq: pirq[A-H] 0-7*/ +static void ich9_lpc_update_by_pirq (ICH9LPCState *lpc,int pirq) +{ +int pic_irq; +int pic_dis; + +ich9_lpc_pic_irq (lpc, pirq, &pic_irq, &pic_dis); +assert (pic_irq <ICH9_LPC_PIC_NUM_PINS ); +if (pic_dis) { +return ; + } + +ich9_lpc_update_pic (lpc, pic_irq); +} + +/* APIC mode: GSIx: PIRQ[A-H] -> GSI 16, ... no pirq shares same APIC pins. */ +static int ich9_pirq_to_gsi (int pirq) +{ +return pirq +ICH9_LPC_PIC_NUM_PINS ; +} + +static int ich9_gsi_to_pirq (int gsi) +{ +return gsi -ICH9_LPC_PIC_NUM_PINS ; +} + +static void ich9_lpc_update_apic (ICH9LPCState *lpc,int gsi) +{ +int level; + + level =pci_bus_get_irq_level (lpc->d.bus,ich9_gsi_to_pirq (gsi)); +if (gsi ==ich9_lpc_sci_irq (lpc)) { + level |= lpc->sci_level; + } + +qemu_set_irq (lpc->ioapic[gsi], level); +} + +void ich9_lpc_set_irq (void *opaque,int pirq,int level) +{ +ICH9LPCState *lpc = opaque; + +assert (0 <= pirq); +assert (pirq <ICH9_LPC_NB_PIRQS ); + +ich9_lpc_update_apic (lpc,ich9_pirq_to_gsi (pirq)); +ich9_lpc_update_by_pirq (lpc, pirq); +} + +/* return the pirq number (PIRQ[A-H]:0-7) corresponding to +* a given device irq pin. +*/ +int ich9_lpc_map_irq (PCIDevice *pci_dev,int intx) +{ +BusState *bus =qdev_get_parent_bus (&pci_dev->qdev); +PCIBus *pci_bus =PCI_BUS (bus); +PCIDevice *lpc_pdev = + pci_bus->devices[PCI_DEVFN (ICH9_LPC_DEV ,ICH9_LPC_FUNC )]; +ICH9LPCState *lpc =ICH9_LPC_DEVICE (lpc_pdev); + +return lpc->irr[PCI_SLOT (pci_dev->devfn)][intx]; +} + +static int ich9_lpc_sci_irq (ICH9LPCState *lpc) +{ +switch (lpc->d.config[ICH9_LPC_ACPI_CTRL ] & +ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK ) { +case ICH9_LPC_ACPI_CTRL_9 : +return 9 ; +case ICH9_LPC_ACPI_CTRL_10 : +return 10 ; +case ICH9_LPC_ACPI_CTRL_11 : +return 11 ; +case ICH9_LPC_ACPI_CTRL_20 : +return 20 ; +case ICH9_LPC_ACPI_CTRL_21 : +return 21 ; +default : +/* reserved */ +break ; + } +return -1 ; +} + +static void ich9_set_sci (void *opaque,int irq_num,int level) +{ +ICH9LPCState *lpc = opaque; +int irq; + +assert (irq_num ==0 ); + level = !!level; +if (level == lpc->sci_level) { +return ; + } + lpc->sci_level = level; + + irq =ich9_lpc_sci_irq (lpc); +if (irq <0 ) { +return ; + } + +ich9_lpc_update_apic (lpc, irq); +if (irq <ICH9_LPC_PIC_NUM_PINS ) { +ich9_lpc_update_pic (lpc, irq); + } +} + +void ich9_lpc_pm_init (PCIDevice *lpc_pci,qemu_irq cmos_s3) +{ +ICH9LPCState *lpc =ICH9_LPC_DEVICE (lpc_pci); +qemu_irq *sci_irq; + + sci_irq =qemu_allocate_irqs (ich9_set_sci, lpc,1 ); +ich9_pm_init (&lpc->pm, sci_irq[0 ], cmos_s3); + +ich9_lpc_reset (&lpc->d.qdev); +} + +/* APM */ + +static void ich9_apm_ctrl_changed (uint32_t val,void *arg) +{ +ICH9LPCState *lpc = arg; + +/* ACPI specs 3.0, 4.7.2.5 */ +acpi_pm1_cnt_update (&lpc->pm.acpi_regs, + val ==ICH9_APM_ACPI_ENABLE , + val ==ICH9_APM_ACPI_DISABLE ); + +/* SMI_EN = PMBASE + 30. SMI control and enable register */ +if (lpc->pm.smi_en &ICH9_PMIO_SMI_EN_APMC_EN ) { +cpu_interrupt (first_cpu,CPU_INTERRUPT_SMI ); + } +} + +/* config:PMBASE */ +static void +ich9_lpc_pmbase_update (ICH9LPCState *lpc) +{ +uint32_t pm_io_base =pci_get_long (lpc->d.config +ICH9_LPC_PMBASE ); + pm_io_base &=ICH9_LPC_PMBASE_BASE_ADDRESS_MASK ; + +ich9_pm_iospace_update (&lpc->pm, pm_io_base); +} + +/* config:RBCA */ +static void ich9_lpc_rcba_update (ICH9LPCState *lpc,uint32_t rbca_old) +{ +uint32_t rbca =pci_get_long (lpc->d.config +ICH9_LPC_RCBA ); + +if (rbca_old &ICH9_LPC_RCBA_EN ) { +memory_region_del_subregion (get_system_memory (), &lpc->rbca_mem); + } +if (rbca &ICH9_LPC_RCBA_EN ) { +memory_region_add_subregion_overlap (get_system_memory (), + rbca &ICH9_LPC_RCBA_BA_MASK , + &lpc->rbca_mem,1 ); + } +} + +static int ich9_lpc_post_load (void *opaque,int version_id) +{ +ICH9LPCState *lpc = opaque; + +ich9_lpc_pmbase_update (lpc); +ich9_lpc_rcba_update (lpc,0 /* disabled ICH9_LPC_RBCA_EN */ ); +return 0 ; +} + +static void ich9_lpc_config_write (PCIDevice *d, +uint32_t addr,uint32_t val,int len) +{ +ICH9LPCState *lpc =ICH9_LPC_DEVICE (d); +uint32_t rbca_old =pci_get_long (d->config +ICH9_LPC_RCBA ); + +pci_default_write_config (d, addr, val, len); +if (ranges_overlap (addr, len,ICH9_LPC_PMBASE ,4 )) { +ich9_lpc_pmbase_update (lpc); + } +if (ranges_overlap (addr, len,ICH9_LPC_RCBA ,4 )) { +ich9_lpc_rcba_update (lpc, rbca_old); + } +} + +static void ich9_lpc_reset (DeviceState *qdev) +{ +PCIDevice *d =PCI_DEVICE (qdev); +ICH9LPCState *lpc =ICH9_LPC_DEVICE (d); +uint32_t rbca_old =pci_get_long (d->config +ICH9_LPC_RCBA ); +int i; + +for (i =0 ; i <4 ; i++) { +pci_set_byte (d->config +ICH9_LPC_PIRQA_ROUT + i, +ICH9_LPC_PIRQ_ROUT_DEFAULT ); + } +for (i =0 ; i <4 ; i++) { +pci_set_byte (d->config +ICH9_LPC_PIRQE_ROUT + i, +ICH9_LPC_PIRQ_ROUT_DEFAULT ); + } +pci_set_byte (d->config +ICH9_LPC_ACPI_CTRL ,ICH9_LPC_ACPI_CTRL_DEFAULT ); + +pci_set_long (d->config +ICH9_LPC_PMBASE ,ICH9_LPC_PMBASE_DEFAULT ); +pci_set_long (d->config +ICH9_LPC_RCBA ,ICH9_LPC_RCBA_DEFAULT ); + +ich9_cc_reset (lpc); + +ich9_lpc_pmbase_update (lpc); +ich9_lpc_rcba_update (lpc, rbca_old); + + lpc->sci_level =0 ; +} + +static const MemoryRegionOps rbca_mmio_ops = { + .read = ich9_cc_read, + .write = ich9_cc_write, + .endianness =DEVICE_LITTLE_ENDIAN , +}; + +static int ich9_lpc_initfn (PCIDevice *d) +{ +ICH9LPCState *lpc =ICH9_LPC_DEVICE (d); +ISABus *isa_bus; + + isa_bus =isa_bus_new (&d->qdev,get_system_io ()); + +pci_set_long (d->wmask +ICH9_LPC_PMBASE , +ICH9_LPC_PMBASE_BASE_ADDRESS_MASK ); + +memory_region_init_io (&lpc->rbca_mem, &rbca_mmio_ops, lpc, +"lpc-rbca-mmio" ,ICH9_CC_SIZE ); + + lpc->isa_bus = isa_bus; + +ich9_cc_init (lpc); +apm_init (&lpc->apm, ich9_apm_ctrl_changed, lpc); +return 0 ; +} + +static const VMStateDescription vmstate_ich9_lpc = { + .name ="ICH9LPC" , + .version_id =1 , + .minimum_version_id =1 , + .minimum_version_id_old =1 , + .post_load = ich9_lpc_post_load, + .fields = (VMStateField []) { +VMSTATE_PCI_DEVICE (d, ICH9LPCState), +VMSTATE_STRUCT (apm, ICH9LPCState,0 , vmstate_apm, APMState), +VMSTATE_STRUCT (pm, ICH9LPCState,0 , vmstate_ich9_pm, ICH9LPCPMRegs), +VMSTATE_UINT8_ARRAY (chip_config, ICH9LPCState,ICH9_CC_SIZE ), +VMSTATE_UINT32 (sci_level, ICH9LPCState), +VMSTATE_END_OF_LIST () + } +}; + +static void ich9_lpc_class_init (ObjectClass *klass,void *data) +{ +DeviceClass *dc =DEVICE_CLASS (klass); +PCIDeviceClass *k =PCI_DEVICE_CLASS (klass); + + dc->reset = ich9_lpc_reset; + k->init = ich9_lpc_initfn; + dc->vmsd = &vmstate_ich9_lpc; + dc->no_user =1 ; + k->config_write = ich9_lpc_config_write; + dc->desc ="ICH9 LPC bridge" ; + k->vendor_id =PCI_VENDOR_ID_INTEL ; + k->device_id =PCI_DEVICE_ID_INTEL_ICH9_8 ; + k->revision =ICH9_A2_LPC_REVISION ; + k->class_id =PCI_CLASS_BRIDGE_ISA ; + +} + +static const TypeInfo ich9_lpc_info = { + .name =TYPE_ICH9_LPC_DEVICE , + .parent =TYPE_PCI_DEVICE , + .instance_size =sizeof (struct ICH9LPCState ), + .class_init = ich9_lpc_class_init, +}; + +static void ich9_lpc_register (void ) +{ +type_register_static (&ich9_lpc_info); +} + +type_init (ich9_lpc_register);Signature · 1 line
1.7.1
Re: [Qemu-devel] [PATCH v3 13/26] ich9: Add the lpc chip
Quoted 31 lines · Michael S. Tsirkin
Quoted 17 lines
hw/lpc_ich9.c new file +11
-0@@ -0,0 +1,523 @@ +/* +* Copyright (c) 2006 Fabrice Bellard +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in hw/lpc_ich9.c line 21
Quoted 10 lines
hw/lpc_ich9.c new file +10
-0+* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +* THE SOFTWARE. +*/ Above is confusing until one notices the below "this is based on
piix_pci.c" and looks at that file.
Quoted 3 lines
I think it's best to just use copyright Fabrice selected for all of this file. Jason, Isaku, could you please both respond whether it's OK with you both?
I'm fine with it. This applies to other files.
Signature · 1 line
yamahata
Re: [Qemu-devel] [PATCH v3 13/26] ich9: Add the lpc chip
In reply to Jason BaronQuoted 81 lines · Jason Baron
From: Jason Baron <[email protected]>
Add support for the ich9 LPC chip.
Signed-off-by Isaku Yamahata <[email protected]>Signed-off-by Jason Baron <[email protected]>--- hw/i386/Makefile.objs | 2 +- hw/lpc_ich9.c | 523 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 524 insertions(+), 1 deletions(-) create mode 100644 hw/lpc_ich9.chw/i386/Makefile.objs +1
-1@@ -7,7 +7,7 @@ obj-y += debugcon.o multiboot.o obj-y += pc_piix.o obj-y += pc_sysfw.o obj-y += pam.o -obj-y += acpi_ich9.o +obj-y += acpi_ich9.o lpc_ich9.o obj-$(CONFIG_XEN) += xen_platform.o xen_apic.o obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen-host-pci-device.o obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pt.o xen_pt_config_init.o xen_pt_msi.ohw/lpc_ich9.c new file +50
-0@@ -0,0 +1,523 @@ +/* +* Copyright (c) 2006 Fabrice Bellard +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +* THE SOFTWARE. +*/ +/* +* QEMU ICH9 Emulation +* +* Copyright (c) 2009, 2010, 2011 +* Isaku Yamahata <yamahata at valinux co jp> +* VA Linux Systems Japan K.K. +* Copyright (C) 2012 Jason Baron <[email protected]> +* +* This is based on piix_pci.c, but heavily modified. +* +* This library is free software; you can redistribute it and/or +* modify it under the terms of the GNU Lesser General Public +* License as published by the Free Software Foundation; either +* version 2 of the License, or (at your option) any later version. +* +* This library is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +* Lesser General Public License for more details. +* +* You should have received a copy of the GNU Lesser General Public +* License along with this library; if not, see <http://www.gnu.org/licenses/> +*/ + +#include "qemu-common.h" +#include "hw.h" +#include "range.h" +#include "isa.h" +#include "sysbus.h"
hw/lpc_ich9.c line 60
Quoted 10 lines
hw/lpc_ich9.c new file +10
-0+#include "pc.h" +#include "apm.h" +#include "ioapic.h" +#include "pci.h" +#include "pcie_host.h" +#include "pci_bridge.h" +#include "ich9.h" +#include "acpi.h" +#include "acpi_ich9.h" +#include "pam.h"
pam.h seems unused. I dropped it.
Quoted 465 lines
hw/lpc_ich9.c new file +463
-0+#include "pci_internals.h" +#include "exec-memory.h" + +static int ich9_lpc_sci_irq (ICH9LPCState *lpc); + +/*****************************************************************************/ +/* ICH9 LPC PCI to ISA bridge */ + +static void ich9_lpc_reset (DeviceState *qdev); + +/* chipset configuration register +* to access chipset configuration registers, pci_[sg]et_{byte, word, long} +* are used. +* Although it's not pci configuration space, it's little endian as Intel. +*/ + +static void ich9_cc_update_ir (uint8_t irr[PCI_NUM_PINS ],uint16_t ir) +{ +int intx; +for (intx =0 ; intx <PCI_NUM_PINS ; intx++) { + irr[intx] = (ir >> (intx *ICH9_CC_DIR_SHIFT )) &ICH9_CC_DIR_MASK ; + } +} + +static void ich9_cc_update (ICH9LPCState *lpc) +{ +int slot; +int pci_intx; + +const int reg_offsets[] = { +ICH9_CC_D25IR , +ICH9_CC_D26IR , +ICH9_CC_D27IR , +ICH9_CC_D28IR , +ICH9_CC_D29IR , +ICH9_CC_D30IR , +ICH9_CC_D31IR , + }; +const int *offset; + +/* D{25 - 31}IR, but D30IR is read only to 0. */ +for (slot =25 , offset = reg_offsets; slot <32 ; slot++, offset++) { +if (slot ==30 ) { +continue ; + } +ich9_cc_update_ir (lpc->irr[slot], +pci_get_word (lpc->chip_config + *offset)); + } + +/* +* D30: DMI2PCI bridge +* It is arbitrarily decided how INTx lines of PCI devicesbehind the bridge +* are connected to pirq lines. Our choice is PIRQ[E-H]. +* INT[A-D] are connected to PIRQ[E-H] +*/ +for (pci_intx =0 ; pci_intx <PCI_NUM_PINS ; pci_intx++) { + lpc->irr[30 ][pci_intx] = pci_intx +4 ; + } +} + +static void ich9_cc_init (ICH9LPCState *lpc) +{ +int slot; +int intx; + +/* the default irq routing is arbitrary as long as it matches with +* acpi irq routing table. +* The one that is incompatible with piix_pci(= bochs) one is +* intentionally chosen to let the users know that the different +* board is used. +* +* int[A-D] -> pirq[E-F] +* avoid pirq A-D because they are used for pci express port +*/ +for (slot =0 ; slot <PCI_SLOT_MAX ; slot++) { +for (intx =0 ; intx <PCI_NUM_PINS ; intx++) { + lpc->irr[slot][intx] = (slot + intx) %4 +4 ; + } + } +ich9_cc_update (lpc); +} + +static void ich9_cc_reset (ICH9LPCState *lpc) +{ +uint8_t *c = lpc->chip_config; + +memset (lpc->chip_config,0 ,sizeof (lpc->chip_config)); + +pci_set_long (c +ICH9_CC_D31IR ,ICH9_CC_DIR_DEFAULT ); +pci_set_long (c +ICH9_CC_D30IR ,ICH9_CC_D30IR_DEFAULT ); +pci_set_long (c +ICH9_CC_D29IR ,ICH9_CC_DIR_DEFAULT ); +pci_set_long (c +ICH9_CC_D28IR ,ICH9_CC_DIR_DEFAULT ); +pci_set_long (c +ICH9_CC_D27IR ,ICH9_CC_DIR_DEFAULT ); +pci_set_long (c +ICH9_CC_D26IR ,ICH9_CC_DIR_DEFAULT ); +pci_set_long (c +ICH9_CC_D25IR ,ICH9_CC_DIR_DEFAULT ); + +ich9_cc_update (lpc); +} + +static void ich9_cc_addr_len (uint64_t *addr,unsigned *len) +{ + *addr &=ICH9_CC_ADDR_MASK ; +if (*addr + *len >=ICH9_CC_SIZE ) { + *len =ICH9_CC_SIZE - *addr; + } +} + +/* val: little endian */ +static void ich9_cc_write (void *opaque,target_phys_addr_t addr, +uint64_t val,unsigned len) +{ +ICH9LPCState *lpc = (ICH9LPCState *)opaque; + +ich9_cc_addr_len (&addr, &len); +memcpy (lpc->chip_config + addr, &val, len); +ich9_cc_update (lpc); +} + +/* return value: little endian */ +static uint64_t ich9_cc_read (void *opaque,target_phys_addr_t addr, +unsigned len) +{ +ICH9LPCState *lpc = (ICH9LPCState *)opaque; + +uint32_t val =0 ; +ich9_cc_addr_len (&addr, &len); +memcpy (&val, lpc->chip_config + addr, len); +return val; +} + +/* IRQ routing */ +/* */ +static void ich9_lpc_rout (uint8_t pirq_rout,int *pic_irq,int *pic_dis) +{ + *pic_irq = pirq_rout &ICH9_LPC_PIRQ_ROUT_MASK ; + *pic_dis = pirq_rout &ICH9_LPC_PIRQ_ROUT_IRQEN ; +} + +static void ich9_lpc_pic_irq (ICH9LPCState *lpc,int pirq_num, +int *pic_irq,int *pic_dis) +{ +switch (pirq_num) { + case 0 ... 3: /* A-D */ +ich9_lpc_rout (lpc->d.config[ICH9_LPC_PIRQA_ROUT + pirq_num], + pic_irq, pic_dis); +return ; + case 4 ... 7: /* E-H */ +ich9_lpc_rout (lpc->d.config[ICH9_LPC_PIRQE_ROUT + (pirq_num -4 )], + pic_irq, pic_dis); +return ; +default : +break ; + } +abort (); +} + +/* pic_irq: i8254 irq 0-15 */ +static void ich9_lpc_update_pic (ICH9LPCState *lpc,int pic_irq) +{ +int i, pic_level; + +/* The pic level is the logical OR of all the PCI irqs mapped to it */ + pic_level =0 ; +for (i =0 ; i <ICH9_LPC_NB_PIRQS ; i++) { +int tmp_irq; +int tmp_dis; +ich9_lpc_pic_irq (lpc, i, &tmp_irq, &tmp_dis); +if (!tmp_dis && pic_irq == tmp_irq) { + pic_level |=pci_bus_get_irq_level (lpc->d.bus, i); + } + } +if (pic_irq ==ich9_lpc_sci_irq (lpc)) { + pic_level |= lpc->sci_level; + } + +qemu_set_irq (lpc->pic[pic_irq], pic_level); +} + +/* pirq: pirq[A-H] 0-7*/ +static void ich9_lpc_update_by_pirq (ICH9LPCState *lpc,int pirq) +{ +int pic_irq; +int pic_dis; + +ich9_lpc_pic_irq (lpc, pirq, &pic_irq, &pic_dis); +assert (pic_irq <ICH9_LPC_PIC_NUM_PINS ); +if (pic_dis) { +return ; + } + +ich9_lpc_update_pic (lpc, pic_irq); +} + +/* APIC mode: GSIx: PIRQ[A-H] -> GSI 16, ... no pirq shares same APIC pins. */ +static int ich9_pirq_to_gsi (int pirq) +{ +return pirq +ICH9_LPC_PIC_NUM_PINS ; +} + +static int ich9_gsi_to_pirq (int gsi) +{ +return gsi -ICH9_LPC_PIC_NUM_PINS ; +} + +static void ich9_lpc_update_apic (ICH9LPCState *lpc,int gsi) +{ +int level; + + level =pci_bus_get_irq_level (lpc->d.bus,ich9_gsi_to_pirq (gsi)); +if (gsi ==ich9_lpc_sci_irq (lpc)) { + level |= lpc->sci_level; + } + +qemu_set_irq (lpc->ioapic[gsi], level); +} + +void ich9_lpc_set_irq (void *opaque,int pirq,int level) +{ +ICH9LPCState *lpc = opaque; + +assert (0 <= pirq); +assert (pirq <ICH9_LPC_NB_PIRQS ); + +ich9_lpc_update_apic (lpc,ich9_pirq_to_gsi (pirq)); +ich9_lpc_update_by_pirq (lpc, pirq); +} + +/* return the pirq number (PIRQ[A-H]:0-7) corresponding to +* a given device irq pin. +*/ +int ich9_lpc_map_irq (PCIDevice *pci_dev,int intx) +{ +BusState *bus =qdev_get_parent_bus (&pci_dev->qdev); +PCIBus *pci_bus =PCI_BUS (bus); +PCIDevice *lpc_pdev = + pci_bus->devices[PCI_DEVFN (ICH9_LPC_DEV ,ICH9_LPC_FUNC )]; +ICH9LPCState *lpc =ICH9_LPC_DEVICE (lpc_pdev); + +return lpc->irr[PCI_SLOT (pci_dev->devfn)][intx]; +} + +static int ich9_lpc_sci_irq (ICH9LPCState *lpc) +{ +switch (lpc->d.config[ICH9_LPC_ACPI_CTRL ] & +ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK ) { +case ICH9_LPC_ACPI_CTRL_9 : +return 9 ; +case ICH9_LPC_ACPI_CTRL_10 : +return 10 ; +case ICH9_LPC_ACPI_CTRL_11 : +return 11 ; +case ICH9_LPC_ACPI_CTRL_20 : +return 20 ; +case ICH9_LPC_ACPI_CTRL_21 : +return 21 ; +default : +/* reserved */ +break ; + } +return -1 ; +} + +static void ich9_set_sci (void *opaque,int irq_num,int level) +{ +ICH9LPCState *lpc = opaque; +int irq; + +assert (irq_num ==0 ); + level = !!level; +if (level == lpc->sci_level) { +return ; + } + lpc->sci_level = level; + + irq =ich9_lpc_sci_irq (lpc); +if (irq <0 ) { +return ; + } + +ich9_lpc_update_apic (lpc, irq); +if (irq <ICH9_LPC_PIC_NUM_PINS ) { +ich9_lpc_update_pic (lpc, irq); + } +} + +void ich9_lpc_pm_init (PCIDevice *lpc_pci,qemu_irq cmos_s3) +{ +ICH9LPCState *lpc =ICH9_LPC_DEVICE (lpc_pci); +qemu_irq *sci_irq; + + sci_irq =qemu_allocate_irqs (ich9_set_sci, lpc,1 ); +ich9_pm_init (&lpc->pm, sci_irq[0 ], cmos_s3); + +ich9_lpc_reset (&lpc->d.qdev); +} + +/* APM */ + +static void ich9_apm_ctrl_changed (uint32_t val,void *arg) +{ +ICH9LPCState *lpc = arg; + +/* ACPI specs 3.0, 4.7.2.5 */ +acpi_pm1_cnt_update (&lpc->pm.acpi_regs, + val ==ICH9_APM_ACPI_ENABLE , + val ==ICH9_APM_ACPI_DISABLE ); + +/* SMI_EN = PMBASE + 30. SMI control and enable register */ +if (lpc->pm.smi_en &ICH9_PMIO_SMI_EN_APMC_EN ) { +cpu_interrupt (first_cpu,CPU_INTERRUPT_SMI ); + } +} + +/* config:PMBASE */ +static void +ich9_lpc_pmbase_update (ICH9LPCState *lpc) +{ +uint32_t pm_io_base =pci_get_long (lpc->d.config +ICH9_LPC_PMBASE ); + pm_io_base &=ICH9_LPC_PMBASE_BASE_ADDRESS_MASK ; + +ich9_pm_iospace_update (&lpc->pm, pm_io_base); +} + +/* config:RBCA */ +static void ich9_lpc_rcba_update (ICH9LPCState *lpc,uint32_t rbca_old) +{ +uint32_t rbca =pci_get_long (lpc->d.config +ICH9_LPC_RCBA ); + +if (rbca_old &ICH9_LPC_RCBA_EN ) { +memory_region_del_subregion (get_system_memory (), &lpc->rbca_mem); + } +if (rbca &ICH9_LPC_RCBA_EN ) { +memory_region_add_subregion_overlap (get_system_memory (), + rbca &ICH9_LPC_RCBA_BA_MASK , + &lpc->rbca_mem,1 ); + } +} + +static int ich9_lpc_post_load (void *opaque,int version_id) +{ +ICH9LPCState *lpc = opaque; + +ich9_lpc_pmbase_update (lpc); +ich9_lpc_rcba_update (lpc,0 /* disabled ICH9_LPC_RBCA_EN */ ); +return 0 ; +} + +static void ich9_lpc_config_write (PCIDevice *d, +uint32_t addr,uint32_t val,int len) +{ +ICH9LPCState *lpc =ICH9_LPC_DEVICE (d); +uint32_t rbca_old =pci_get_long (d->config +ICH9_LPC_RCBA ); + +pci_default_write_config (d, addr, val, len); +if (ranges_overlap (addr, len,ICH9_LPC_PMBASE ,4 )) { +ich9_lpc_pmbase_update (lpc); + } +if (ranges_overlap (addr, len,ICH9_LPC_RCBA ,4 )) { +ich9_lpc_rcba_update (lpc, rbca_old); + } +} + +static void ich9_lpc_reset (DeviceState *qdev) +{ +PCIDevice *d =PCI_DEVICE (qdev); +ICH9LPCState *lpc =ICH9_LPC_DEVICE (d); +uint32_t rbca_old =pci_get_long (d->config +ICH9_LPC_RCBA ); +int i; + +for (i =0 ; i <4 ; i++) { +pci_set_byte (d->config +ICH9_LPC_PIRQA_ROUT + i, +ICH9_LPC_PIRQ_ROUT_DEFAULT ); + } +for (i =0 ; i <4 ; i++) { +pci_set_byte (d->config +ICH9_LPC_PIRQE_ROUT + i, +ICH9_LPC_PIRQ_ROUT_DEFAULT ); + } +pci_set_byte (d->config +ICH9_LPC_ACPI_CTRL ,ICH9_LPC_ACPI_CTRL_DEFAULT ); + +pci_set_long (d->config +ICH9_LPC_PMBASE ,ICH9_LPC_PMBASE_DEFAULT ); +pci_set_long (d->config +ICH9_LPC_RCBA ,ICH9_LPC_RCBA_DEFAULT ); + +ich9_cc_reset (lpc); + +ich9_lpc_pmbase_update (lpc); +ich9_lpc_rcba_update (lpc, rbca_old); + + lpc->sci_level =0 ; +} + +static const MemoryRegionOps rbca_mmio_ops = { + .read = ich9_cc_read, + .write = ich9_cc_write, + .endianness =DEVICE_LITTLE_ENDIAN , +}; + +static int ich9_lpc_initfn (PCIDevice *d) +{ +ICH9LPCState *lpc =ICH9_LPC_DEVICE (d); +ISABus *isa_bus; + + isa_bus =isa_bus_new (&d->qdev,get_system_io ()); + +pci_set_long (d->wmask +ICH9_LPC_PMBASE , +ICH9_LPC_PMBASE_BASE_ADDRESS_MASK ); + +memory_region_init_io (&lpc->rbca_mem, &rbca_mmio_ops, lpc, +"lpc-rbca-mmio" ,ICH9_CC_SIZE ); + + lpc->isa_bus = isa_bus; + +ich9_cc_init (lpc); +apm_init (&lpc->apm, ich9_apm_ctrl_changed, lpc); +return 0 ; +} + +static const VMStateDescription vmstate_ich9_lpc = { + .name ="ICH9LPC" , + .version_id =1 , + .minimum_version_id =1 , + .minimum_version_id_old =1 , + .post_load = ich9_lpc_post_load, + .fields = (VMStateField []) { +VMSTATE_PCI_DEVICE (d, ICH9LPCState), +VMSTATE_STRUCT (apm, ICH9LPCState,0 , vmstate_apm, APMState), +VMSTATE_STRUCT (pm, ICH9LPCState,0 , vmstate_ich9_pm, ICH9LPCPMRegs), +VMSTATE_UINT8_ARRAY (chip_config, ICH9LPCState,ICH9_CC_SIZE ), +VMSTATE_UINT32 (sci_level, ICH9LPCState), +VMSTATE_END_OF_LIST () + } +}; + +static void ich9_lpc_class_init (ObjectClass *klass,void *data) +{ +DeviceClass *dc =DEVICE_CLASS (klass); +PCIDeviceClass *k =PCI_DEVICE_CLASS (klass); + + dc->reset = ich9_lpc_reset; + k->init = ich9_lpc_initfn; + dc->vmsd = &vmstate_ich9_lpc; + dc->no_user =1 ; + k->config_write = ich9_lpc_config_write; + dc->desc ="ICH9 LPC bridge" ; + k->vendor_id =PCI_VENDOR_ID_INTEL ; + k->device_id =PCI_DEVICE_ID_INTEL_ICH9_8 ; + k->revision =ICH9_A2_LPC_REVISION ; + k->class_id =PCI_CLASS_BRIDGE_ISA ; + +} + +static const TypeInfo ich9_lpc_info = { + .name =TYPE_ICH9_LPC_DEVICE , + .parent =TYPE_PCI_DEVICE , + .instance_size =sizeof (struct ICH9LPCState ), + .class_init = ich9_lpc_class_init, +}; + +static void ich9_lpc_register (void ) +{ +type_register_static (&ich9_lpc_info); +} + +type_init (ich9_lpc_register);Signature · 1 line
1.7.1
PATCH v3 14/26 ich9: Add smbus
In reply to Jason BaronFrom: Jason Baron <[email protected]>
Add support for the ich9 smbus chip.
--- hw/i386/Makefile.objs | 2 +- hw/smbus_ich9.c | 159 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 160 insertions(+), 1 deletions(-) create mode 100644 hw/smbus_ich9.c
hw/i386/Makefile.objs +1 -1
@@ -7,7 +7,7 @@ obj-y += debugcon.o multiboot.o obj-y += pc_piix.o obj-y += pc_sysfw.o obj-y += pam.o -obj-y += acpi_ich9.o lpc_ich9.o +obj-y += acpi_ich9.o lpc_ich9.o smbus_ich9.o obj-$(CONFIG_XEN) += xen_platform.o xen_apic.o obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen-host-pci-device.o obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pt.o xen_pt_config_init.o xen_pt_msi.o
hw/smbus_ich9.c new file +159 -0
159 lines not on this page · raw message
Signature · 1 line
1.7.1
Michael S. Tsirkin
AppliedRe: [Qemu-devel] [PATCH v3 14/26] ich9: Add smbus
Quoted 6 lines · Jason Baron
From: Jason Baron <[email protected]>
Add support for the ich9 smbus chip.
Signed-off-by Isaku Yamahata <[email protected]>Signed-off-by Jason Baron <[email protected]>
Applied, thanks.
Quoted 186 lines
--- hw/i386/Makefile.objs | 2 +- hw/smbus_ich9.c | 159 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 160 insertions(+), 1 deletions(-) create mode 100644 hw/smbus_ich9.chw/i386/Makefile.objs +1
-1@@ -7,7 +7,7 @@ obj-y += debugcon.o multiboot.o obj-y += pc_piix.o obj-y += pc_sysfw.o obj-y += pam.o -obj-y += acpi_ich9.o lpc_ich9.o +obj-y += acpi_ich9.o lpc_ich9.o smbus_ich9.o obj-$(CONFIG_XEN) += xen_platform.o xen_apic.o obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen-host-pci-device.o obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pt.o xen_pt_config_init.o xen_pt_msi.ohw/smbus_ich9.c new file +159
-0@@ -0,0 +1,159 @@ +/* +* ACPI implementation +* +* Copyright (c) 2006 Fabrice Bellard +* +* This library is free software; you can redistribute it and/or +* modify it under the terms of the GNU Lesser General Public +* License version 2 as published by the Free Software Foundation. +* +* This library is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +* Lesser General Public License for more details. +* +* You should have received a copy of the GNU Lesser General Public +* License along with this library; if not, see <http://www.gnu.org/licenses/> +*/ +/* +* Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp> +* VA Linux Systems Japan K.K. +* Copyright (C) 2012 Jason Baron <[email protected]> +* +* This is based on acpi.c, but heavily rewritten. +*/ +#include "hw.h" +#include "pc.h" +#include "pm_smbus.h" +#include "pci.h" +#include "sysemu.h" +#include "i2c.h" +#include "smbus.h" + +#include "ich9.h" + +#define TYPE_ICH9_SMB_DEVICE "ICH9 SMB" +#define ICH9_SMB_DEVICE (obj) \ + OBJECT_CHECK(ICH9SMBState, (obj), TYPE_ICH9_SMB_DEVICE) + +typedef struct ICH9SMBState { +PCIDevice dev; + +PMSMBus smb; +MemoryRegion mem_bar; +}ICH9SMBState ; + +static const VMStateDescription vmstate_ich9_smbus = { + .name ="ich9_smb" , + .version_id =1 , + .minimum_version_id =1 , + .minimum_version_id_old =1 , + .fields = (VMStateField []) { + VMSTATE_PCI_DEVICE(dev, struct ICH9SMBState), +VMSTATE_END_OF_LIST () + } +}; + +static void ich9_smb_ioport_writeb (void *opaque,target_phys_addr_t addr, +uint64_t val,unsigned size) +{ +ICH9SMBState *s = opaque; +uint8_t hostc = s->dev.config[ICH9_SMB_HOSTC ]; + +if ((hostc &ICH9_SMB_HOSTC_HST_EN ) && !(hostc &ICH9_SMB_HOSTC_I2C_EN )) { +uint64_t offset = addr - s->dev.io_regions[ICH9_SMB_SMB_BASE_BAR ].addr; +smb_ioport_writeb (&s->smb, offset, val); + } +} + +static uint64_t ich9_smb_ioport_readb (void *opaque,target_phys_addr_t addr, +unsigned size) +{ +ICH9SMBState *s = opaque; +uint8_t hostc = s->dev.config[ICH9_SMB_HOSTC ]; + +if ((hostc &ICH9_SMB_HOSTC_HST_EN ) && !(hostc &ICH9_SMB_HOSTC_I2C_EN )) { +uint64_t offset = addr - s->dev.io_regions[ICH9_SMB_SMB_BASE_BAR ].addr; +return smb_ioport_readb (&s->smb, offset); + } + +return 0xff ; +} + +static const MemoryRegionOps lpc_smb_mmio_ops = { + .read = ich9_smb_ioport_readb, + .write = ich9_smb_ioport_writeb, + .endianness =DEVICE_LITTLE_ENDIAN , + .impl = { + .min_access_size =1 , + .max_access_size =1 , + }, +}; + +static int ich9_smbus_initfn (PCIDevice *d) +{ +ICH9SMBState *s =ICH9_SMB_DEVICE (d); + +/* TODO? D31IP.SMIP in chipset configuration space */ +pci_config_set_interrupt_pin (d->config,0x01 );/* interrupt pin 1 */ + +pci_set_byte (d->config +ICH9_SMB_HOSTC ,0 ); + +/* +* update parameters based on +* paralell_hds[0] +* serial_hds[0] +* serial_hds[0] +* fdc +* +* Is there any OS that depends on them? +*/ + +/* TODO smb_io_base */ +pci_set_byte (d->config +ICH9_SMB_HOSTC ,0 ); +/* TODO bar0, bar1: 64bit BAR support*/ + +memory_region_init_io (&s->mem_bar, &lpc_smb_mmio_ops, s,"ich9-smbus-bar" , +ICH9_SMB_SMB_BASE_SIZE ); +pci_register_bar (d,ICH9_SMB_SMB_BASE_BAR ,PCI_BASE_ADDRESS_SPACE_IO , + &s->mem_bar); +pm_smbus_init (&d->qdev, &s->smb); +return 0 ; +} + +static void ich9_smb_class_init (ObjectClass *klass,void *data) +{ +DeviceClass *dc =DEVICE_CLASS (klass); +PCIDeviceClass *k =PCI_DEVICE_CLASS (klass); + + k->vendor_id =PCI_VENDOR_ID_INTEL ; + k->device_id =PCI_DEVICE_ID_INTEL_ICH9_6 ; + k->revision =ICH9_A2_SMB_REVISION ; + k->class_id =PCI_CLASS_SERIAL_SMBUS ; + dc->no_user =1 ; + dc->vmsd = &vmstate_ich9_smbus; + dc->desc ="ICH9 SMBUS Bridge" ; + k->init = ich9_smbus_initfn; +} + +i2c_bus *ich9_smb_init (PCIBus *bus,int devfn,uint32_t smb_io_base) +{ +PCIDevice *d = +pci_create_simple_multifunction (bus, devfn, true,TYPE_ICH9_SMB_DEVICE ); +ICH9SMBState *s =ICH9_SMB_DEVICE (d); +return s->smb.smbus; +} + +static const TypeInfo ich9_smb_info = { + .name =TYPE_ICH9_SMB_DEVICE , + .parent =TYPE_PCI_DEVICE , + .instance_size =sizeof (ICH9SMBState), + .class_init = ich9_smb_class_init, +}; + +static void ich9_smb_register (void ) +{ +type_register_static (&ich9_smb_info); +} + +type_init (ich9_smb_register);Signature · 1 line
1.7.1
PATCH v3 15/26 q35: Introduce q35 pc based chipset emulator
In reply to Jason BaronFrom: Isaku Yamahata <[email protected]>
pc q35 based chipset emulator to support pci express natively.
--- hw/i386/Makefile.objs | 2 +- hw/pc.h | 2 + hw/pc_piix.c | 4 +- hw/pc_q35.c | 316 ++++++++++++++++++++++++++++++++++++++++++++++ hw/pci_ids.h | 2 + hw/q35.c | 332 +++++++++++++++++++++++++++++++++++++++++++++++++ hw/q35.h | 161 ++++++++++++++++++++++++ 7 files changed, 816 insertions(+), 3 deletions(-) create mode 100644 hw/pc_q35.c create mode 100644 hw/q35.c create mode 100644 hw/q35.h
hw/i386/Makefile.objs +1 -1
@@ -7,7 +7,7 @@ obj-y += debugcon.o multiboot.o obj-y += pc_piix.o obj-y += pc_sysfw.o obj-y += pam.o -obj-y += acpi_ich9.o lpc_ich9.o smbus_ich9.o +obj-y += acpi_ich9.o lpc_ich9.o smbus_ich9.o q35.o pc_q35.o obj-$(CONFIG_XEN) += xen_platform.o xen_apic.o obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen-host-pci-device.o obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pt.o xen_pt_config_init.o xen_pt_msi.o
hw/pc.h +2 -0
@@ -69,6 +69,8 @@ int pic_read_irq(DeviceState *d);int pic_get_output (DeviceState *d);void pic_info (Monitor *mon);void irq_info (Monitor *mon); +void kvm_piix3_gsi_handler (void *opaque,int n,int level); +void kvm_piix3_setup_irq_routing (bool pci_enabled);/* Global System Interrupts */
hw/pc_piix.c +2 -2
@@ -53,7 +53,7 @@ static const int ide_iobase[MAX_IDE_BUS] = { 0x1f0, 0x170 };static const int ide_iobase2[MAX_IDE_BUS ] = {0x3f6 ,0x376 };static const int ide_irq[MAX_IDE_BUS ] = {14 ,15 }; -static void kvm_piix3_setup_irq_routing (bool pci_enabled) +void kvm_piix3_setup_irq_routing (bool pci_enabled) {#ifdef CONFIG_KVM KVMState *s = kvm_state;
@@ -82,7 +82,7 @@ static void kvm_piix3_setup_irq_routing(bool pci_enabled)#endif /* CONFIG_KVM */ } -static void kvm_piix3_gsi_handler (void *opaque,int n,int level) +void kvm_piix3_gsi_handler (void *opaque,int n,int level) {GSIState *s = opaque;
hw/pc_q35.c new file +316 -0
316 lines not on this page · raw message
hw/pci_ids.h +2 -0
@@ -137,6 +137,8 @@#define PCI_DEVICE_ID_INTEL_82801I_EHCI2 0x293c#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed +#define PCI_DEVICE_ID_INTEL_Q35_MCH 0x29c0 +#define PCI_VENDOR_ID_XEN 0x5853#define PCI_DEVICE_ID_XEN_PLATFORM 0x0001
hw/q35.c new file +332 -0
332 lines not on this page · raw message
hw/q35.h new file +161 -0
161 lines not on this page · raw message
Signature · 1 line
1.7.1
PATCH v3 16/26 ich9: Add i82801b11 dmi-to-pci bridge
In reply to Jason BaronFrom: Jason Baron <[email protected]>
Add the dmi-to-pci i82801b11 bridge chip. This is the pci bridge chip that q35 uses on its host bus for PCI bus arbitration.
--- hw/Makefile.objs | 1 + hw/i82801b11.c | 125 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 126 insertions(+), 0 deletions(-) create mode 100644 hw/i82801b11.c
hw/Makefile.objs +1 -0
@@ -9,6 +9,7 @@ common-obj-$(CONFIG_PCI) += shpc.o common-obj-$(CONFIG_PCI) += slotid_cap.o common-obj-$(CONFIG_PCI) += pci_host.o pcie_host.o common-obj-$(CONFIG_PCI) += ioh3420.o xio3130_upstream.o xio3130_downstream.o +common-obj-$(CONFIG_PCI) += i82801b11.o common-obj-y += watchdog.o common-obj-$(CONFIG_ISA_MMIO) += isa_mmio.o common-obj-$(CONFIG_ECC) += ecc.o
hw/i82801b11.c new file +125 -0
125 lines not on this page · raw message
Signature · 1 line
1.7.1
Michael S. Tsirkin
AppliedRe: [Qemu-devel] [PATCH v3 16/26] ich9: Add i82801b11 dmi-to-pci bridge
Quoted 7 lines · Jason Baron
From: Jason Baron <[email protected]>
Add the dmi-to-pci i82801b11 bridge chip. This is the pci bridge chip that q35 uses on its host bus for PCI bus arbitration.
Signed-off-by Isaku Yamahata <[email protected]>Signed-off-by Jason Baron <[email protected]>
Applied, after removing the use of the PCI_CLASS_BRDIGE_PCI_INF_SUB. I also note that subtractive decoding isn't really supported. Added a comment to this end.
Quoted 151 lines
--- hw/Makefile.objs | 1 + hw/i82801b11.c | 125 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 126 insertions(+), 0 deletions(-) create mode 100644 hw/i82801b11.chw/Makefile.objs +1
-0@@ -9,6 +9,7 @@ common-obj-$(CONFIG_PCI) += shpc.o common-obj-$(CONFIG_PCI) += slotid_cap.o common-obj-$(CONFIG_PCI) += pci_host.o pcie_host.o common-obj-$(CONFIG_PCI) += ioh3420.o xio3130_upstream.o xio3130_downstream.o +common-obj-$(CONFIG_PCI) += i82801b11.o common-obj-y += watchdog.o common-obj-$(CONFIG_ISA_MMIO) += isa_mmio.o common-obj-$(CONFIG_ECC) += ecc.ohw/i82801b11.c new file +125
-0@@ -0,0 +1,125 @@ +/* +* Copyright (c) 2006 Fabrice Bellard +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +* THE SOFTWARE. +*/ +/* +* QEMU i82801b11 dmi-to-pci Bridge Emulation +* +* Copyright (c) 2009, 2010, 2011 +* Isaku Yamahata <yamahata at valinux co jp> +* VA Linux Systems Japan K.K. +* Copyright (C) 2012 Jason Baron <[email protected]> +* +* This library is free software; you can redistribute it and/or +* modify it under the terms of the GNU Lesser General Public +* License as published by the Free Software Foundation; either +* version 2 of the License, or (at your option) any later version. +* +* This library is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +* Lesser General Public License for more details. +* +* You should have received a copy of the GNU Lesser General Public +* License along with this library; if not, see <http://www.gnu.org/licenses/> +*/ + +#include "pci.h" +#include "ich9.h" + + +/*****************************************************************************/ +/* ICH9 DMI-to-PCI bridge */ +#define I82801ba_SSVID_OFFSET 0x50 +#define I82801ba_SSVID_SVID 0 +#define I82801ba_SSVID_SSID 0 + +typedef struct I82801b11Bridge { +PCIBridge br; +}I82801b11Bridge ; + +static int i82801b11_bridge_initfn (PCIDevice *d) +{ +int rc; + + rc =pci_bridge_initfn (d); +if (rc <0 ) { +return rc; + } + + rc =pci_bridge_ssvid_init (d, I82801ba_SSVID_OFFSET, + I82801ba_SSVID_SVID, I82801ba_SSVID_SSID); +if (rc <0 ) { + goto err_bridge; + } +pci_config_set_prog_interface (d->config,PCI_CLASS_BRDIGE_PCI_INF_SUB ); +return 0 ; + +err_bridge: +pci_bridge_exitfn (d); + +return rc; +} + +static void i82801b11_bridge_class_init (ObjectClass *klass,void *data) +{ +PCIDeviceClass *k =PCI_DEVICE_CLASS (klass); + + k->is_bridge =1 ; + k->vendor_id =PCI_VENDOR_ID_INTEL ; + k->device_id =PCI_DEVICE_ID_INTEL_82801BA_11 ; + k->revision =ICH9_D2P_A2_REVISION ; + k->init = i82801b11_bridge_initfn; +} + +static const TypeInfo i82801b11_bridge_info = { + .name ="i82801b11-bridge" , + .parent =TYPE_PCI_DEVICE , + .instance_size =sizeof (I82801b11Bridge), + .class_init = i82801b11_bridge_class_init, +}; + +PCIBus *ich9_d2pbr_init (PCIBus *bus,int devfn,int sec_bus) +{ +PCIDevice *d; +PCIBridge *br; +char buf[16 ]; +DeviceState *qdev; + + d =pci_create_multifunction (bus, devfn, true,"i82801b11-bridge" ); +if (!d) { +return NULL ; + } + br =DO_UPCAST (PCIBridge, dev, d); + qdev = &br->dev.qdev; + +snprintf (buf,sizeof (buf),"pci.%d" , sec_bus); +pci_bridge_map_irq (br, buf, pci_swizzle_map_irq_fn); +qdev_init_nofail (qdev); + +return pci_bridge_get_sec_bus (br); +} + +static void d2pbr_register (void ) +{ +type_register_static (&i82801b11_bridge_info); +} + +type_init (d2pbr_register);Signature · 1 line
1.7.1
PATCH v3 17/26 Add i21154 bridge chip.
In reply to Jason BaronFrom: Jason Baron <[email protected]>
This adds support for the DECchip 21154 PCI bridge.
--- hw/Makefile.objs | 2 +- hw/i21154.c | 113 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ hw/i21154.h | 9 ++++ 3 files changed, 123 insertions(+), 1 deletions(-) create mode 100644 hw/i21154.c create mode 100644 hw/i21154.h
hw/Makefile.objs +1 -1
@@ -9,7 +9,7 @@ common-obj-$(CONFIG_PCI) += shpc.o common-obj-$(CONFIG_PCI) += slotid_cap.o common-obj-$(CONFIG_PCI) += pci_host.o pcie_host.o common-obj-$(CONFIG_PCI) += ioh3420.o xio3130_upstream.o xio3130_downstream.o -common-obj-$(CONFIG_PCI) += i82801b11.o +common-obj-$(CONFIG_PCI) += i82801b11.o i21154.o common-obj-y += watchdog.o common-obj-$(CONFIG_ISA_MMIO) += isa_mmio.o common-obj-$(CONFIG_ECC) += ecc.o
hw/i21154.c new file +113 -0
113 lines not on this page · raw message
hw/i21154.h new file +9 -0
@@ -0,0 +1,9 @@ +#ifndef QEMU_I21154_H +#define QEMU_I21154_H + +#include "pci.h" + +PCIBridge *i21154_init (PCIBus *bus,int devfn,const char *bus_name, +bool multifunction); + +#endif /* QEMU_I21154_H */
Signature · 1 line
1.7.1
Re: [Qemu-devel] [PATCH v3 17/26] Add i21154 bridge chip.
Quoted 92 lines · Jason Baron
From: Jason Baron <[email protected]>
This adds support for the DECchip 21154 PCI bridge.
Signed-off-by Isaku Yamahata <[email protected]>Signed-off-by Jason Baron <[email protected]>--- hw/Makefile.objs | 2 +- hw/i21154.c | 113 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ hw/i21154.h | 9 ++++ 3 files changed, 123 insertions(+), 1 deletions(-) create mode 100644 hw/i21154.c create mode 100644 hw/i21154.hhw/Makefile.objs +1
-1@@ -9,7 +9,7 @@ common-obj-$(CONFIG_PCI) += shpc.o common-obj-$(CONFIG_PCI) += slotid_cap.o common-obj-$(CONFIG_PCI) += pci_host.o pcie_host.o common-obj-$(CONFIG_PCI) += ioh3420.o xio3130_upstream.o xio3130_downstream.o -common-obj-$(CONFIG_PCI) += i82801b11.o +common-obj-$(CONFIG_PCI) += i82801b11.o i21154.o common-obj-y += watchdog.o common-obj-$(CONFIG_ISA_MMIO) += isa_mmio.o common-obj-$(CONFIG_ECC) += ecc.ohw/i21154.c new file +59
-0@@ -0,0 +1,113 @@ +/* +* Copyright (c) 2006 Fabrice Bellard +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +* THE SOFTWARE. +*/ +/* +* QEMU i21154 PCI Bridge Emulation +* +* Copyright (c) 2009, 2010, 2011 +* Isaku Yamahata <yamahata at valinux co jp> +* VA Linux Systems Japan K.K. +* Copyright (C) 2012 Jason Baron <[email protected]> +* +* This library is free software; you can redistribute it and/or +* modify it under the terms of the GNU Lesser General Public +* License as published by the Free Software Foundation; either +* version 2 of the License, or (at your option) any later version. +* +* This library is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +* Lesser General Public License for more details. +* +* You should have received a copy of the GNU Lesser General Public +* License along with this library; if not, see <http://www.gnu.org/licenses/> +*/ + +#include "i21154.h" +#include "pci_ids.h" +#include "pci.h" +#include "pci_bridge.h" +#include "pci_internals.h" + +/* i21154 pci bridge*/ + +typedef struct I21154Bridge { +PCIBridge br; +}I21154Bridge ; + +static int i21154_bridge_initfn (PCIDevice *d) +{ +int rc; +
hw/i21154.c line 69
Quoted 10 lines
hw/i21154.c new file +10
-0+ rc =pci_bridge_initfn (d); +if (rc <0 ) { +return rc; + } + +return 0 ; +} + +#define I21154_REV 0x05 +#define I21154_PI 0x00
_PI seems unused
Quoted 50 lines
hw/i21154.c new file +44
-0+ +static void i21154_bridge_class_init (ObjectClass *klass,void *data) +{ +PCIDeviceClass *k =PCI_DEVICE_CLASS (klass); + + k->is_bridge =1 ; + k->vendor_id =PCI_VENDOR_ID_DEC ; + k->device_id =PCI_DEVICE_ID_DEC_21154 ; + k->revision =I21154_REV ; + k->init = i21154_bridge_initfn; +} + +static const TypeInfo i21154_bridge_info = { + .name ="i21154-bridge" , + .parent =TYPE_PCI_DEVICE , + .instance_size =sizeof (I21154Bridge), + .class_init = i21154_bridge_class_init, +}; + +PCIBridge *i21154_init (PCIBus *bus,int devfn,const char *bus_name, +bool multifunction) +{ +PCIDevice *d; +PCIBridge *br; +DeviceState *qdev; + + d =pci_create_multifunction (bus, devfn, multifunction,"i21154-bridge" ); +if (!d) { +return NULL ; + } + br =DO_UPCAST (PCIBridge, dev, d); + qdev = &br->dev.qdev; + +pci_bridge_map_irq (br, bus_name, pci_swizzle_map_irq_fn); +qdev_init_nofail (qdev); + +return br; +} + +static void i21154_register (void ) +{ +type_register_static (&i21154_bridge_info); +} +type_init (i21154_register);hw/i21154.h new file +0
-0
hw/i21154.h line 9
Quoted 9 lines
hw/i21154.h new file +9
-0@@ -0,0 +1,9 @@ +#ifndef QEMU_I21154_H +#define QEMU_I21154_H + +#include "pci.h" + +PCIBridge *i21154_init (PCIBus *bus,int devfn,const char *bus_name, +bool multifunction); + +#endif /* QEMU_I21154_H */
Looks like one can create this device through -device but if one does i21154_init is not called.
Do we need i21154_init? Can we initialize the device through the type system in the regular way?
Same applies to other system devices.
Quoted 2 lines
Signature · 1 line
1.7.1
Re: [Qemu-devel] [PATCH v3 17/26] Add i21154 bridge chip.
Quoted 97 lines · Michael S. Tsirkin
Quoted 96 lines · Jason Baron
From: Jason Baron <[email protected]>
This adds support for the DECchip 21154 PCI bridge.
Signed-off-by Isaku Yamahata <[email protected]>Signed-off-by Jason Baron <[email protected]>--- hw/Makefile.objs | 2 +- hw/i21154.c | 113 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ hw/i21154.h | 9 ++++ 3 files changed, 123 insertions(+), 1 deletions(-) create mode 100644 hw/i21154.c create mode 100644 hw/i21154.hhw/Makefile.objs +1
-1@@ -9,7 +9,7 @@ common-obj-$(CONFIG_PCI) += shpc.o common-obj-$(CONFIG_PCI) += slotid_cap.o common-obj-$(CONFIG_PCI) += pci_host.o pcie_host.o common-obj-$(CONFIG_PCI) += ioh3420.o xio3130_upstream.o xio3130_downstream.o -common-obj-$(CONFIG_PCI) += i82801b11.o +common-obj-$(CONFIG_PCI) += i82801b11.o i21154.o common-obj-y += watchdog.o common-obj-$(CONFIG_ISA_MMIO) += isa_mmio.o common-obj-$(CONFIG_ECC) += ecc.ohw/i21154.c new file +63
-0@@ -0,0 +1,113 @@ +/* +* Copyright (c) 2006 Fabrice Bellard +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +* THE SOFTWARE. +*/ +/* +* QEMU i21154 PCI Bridge Emulation +* +* Copyright (c) 2009, 2010, 2011 +* Isaku Yamahata <yamahata at valinux co jp> +* VA Linux Systems Japan K.K. +* Copyright (C) 2012 Jason Baron <[email protected]> +* +* This library is free software; you can redistribute it and/or +* modify it under the terms of the GNU Lesser General Public +* License as published by the Free Software Foundation; either +* version 2 of the License, or (at your option) any later version. +* +* This library is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +* Lesser General Public License for more details. +* +* You should have received a copy of the GNU Lesser General Public +* License along with this library; if not, see <http://www.gnu.org/licenses/> +*/ + +#include "i21154.h" +#include "pci_ids.h" +#include "pci.h" +#include "pci_bridge.h" +#include "pci_internals.h" + +/* i21154 pci bridge*/ + +typedef struct I21154Bridge { +PCIBridge br; +}I21154Bridge ; + +static int i21154_bridge_initfn (PCIDevice *d) +{ +int rc; + + rc =pci_bridge_initfn (d); +if (rc <0 ) { +return rc; + }
Quoted 9 lines
hw/i21154.c line 69
Quoted 6 lines
hw/i21154.c new file +6
-0+ +return 0 ; +} + +#define I21154_REV 0x05 +#define I21154_PI 0x00
_PIseems unused
I21154_PI was used in Yamahata's original patch, for the 'prog_interface' field. I didn't find it in my conversion to QOM.
However, I should have used:
pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
Anyways, we can drop this patch for the 'hw/dec_pci.c', and we can set it there.
Quoted 65 lines
Quoted 50 lines
hw/i21154.c new file +44
-0+ +static void i21154_bridge_class_init (ObjectClass *klass,void *data) +{ +PCIDeviceClass *k =PCI_DEVICE_CLASS (klass); + + k->is_bridge =1 ; + k->vendor_id =PCI_VENDOR_ID_DEC ; + k->device_id =PCI_DEVICE_ID_DEC_21154 ; + k->revision =I21154_REV ; + k->init = i21154_bridge_initfn; +} + +static const TypeInfo i21154_bridge_info = { + .name ="i21154-bridge" , + .parent =TYPE_PCI_DEVICE , + .instance_size =sizeof (I21154Bridge), + .class_init = i21154_bridge_class_init, +}; + +PCIBridge *i21154_init (PCIBus *bus,int devfn,const char *bus_name, +bool multifunction) +{ +PCIDevice *d; +PCIBridge *br; +DeviceState *qdev; + + d =pci_create_multifunction (bus, devfn, multifunction,"i21154-bridge" ); +if (!d) { +return NULL ; + } + br =DO_UPCAST (PCIBridge, dev, d); + qdev = &br->dev.qdev; + +pci_bridge_map_irq (br, bus_name, pci_swizzle_map_irq_fn); +qdev_init_nofail (qdev); + +return br; +} + +static void i21154_register (void ) +{ +type_register_static (&i21154_bridge_info); +} +type_init (i21154_register);hw/i21154.h new file +0
-0hw/i21154.h line 9
Quoted 9 lines
hw/i21154.h new file +9
-0@@ -0,0 +1,9 @@ +#ifndef QEMU_I21154_H +#define QEMU_I21154_H + +#include "pci.h" + +PCIBridge *i21154_init (PCIBus *bus,int devfn,const char *bus_name, +bool multifunction); + +#endif /* QEMU_I21154_H */ Looks like one can create this device through -device but if one does
i21154_initis not called.
Do we needi21154_init? Can we initialize the device through the type system in the regular way?
Quoted 2 lines
Same applies to other system devices.
The common pattern in these '_init' functions is:
dev = pci_create_multifunction(parent_bus, devfn, false,
"bridge name foo");
br = DO_UPCAST(PCIBridge, dev, dev);
pci_bridge_map_irq(br, "foo bridge", map_irq);
qdev_init_nofail(&dev->qdev);However, when we initialize bridges through the type system, we typically end up without a 'map_irq' function, since we haven't set one via 'pci_bridge_map_irq'.
A quick hack fix is below (which might be ok for the short term).
hw/pci_bridge.c +3 -0
@@ -321,6 +321,9 @@ int pci_bridge_initfn(PCIDevice *dev)qbus_create_inplace (&sec_bus->qbus,TYPE_PCI_BUS , &dev->qdev, br->bus_name); sec_bus->parent_dev = dev; +if (!br->map_irq) { + br->map_irq = pci_swizzle_map_irq_fn; + } sec_bus->map_irq = br->map_irq; sec_bus->address_space_mem = &br->address_space_mem;memory_region_init (&br->address_space_mem,"pci_bridge_pci" ,INT64_MAX );
A more proper solution might be to introduce an abstract PCIBridgeClass, and have all of the bridges inherit from there instead of PCIDevice and then initialize the map_irq function there. And then have these '_init' functions overwrite things if they want to.
Thanks,
-Jason
Re: [Qemu-devel] [PATCH v3 17/26] Add i21154 bridge chip.
In reply to Jason BaronAm 19.10.2012 22:43, schrieb Jason Baron:
Quoted 6 lines
From: Jason Baron <[email protected]>
This adds support for the DECchip 21154 PCI bridge.
Signed-off-by Isaku Yamahata <[email protected]>Signed-off-by Jason Baron <[email protected]>
Quoted 7 lines
--- hw/Makefile.objs | 2 +- hw/i21154.c | 113 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ hw/i21154.h | 9 ++++ 3 files changed, 123 insertions(+), 1 deletions(-) create mode 100644 hw/i21154.c create mode 100644 hw/i21154.h
Why is this creating a new file and not reusing dec_pci.c? We shouldn't have two parallel implementations of the same chip.
Andreas
Signature · 2 lines
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH v3 17/26] Add i21154 bridge chip.
Quoted 15 lines · Andreas Färber
Am 19.10.2012 22:43, schrieb Jason Baron:
Quoted 6 lines
From: Jason Baron <[email protected]>
This adds support for the DECchip 21154 PCI bridge.
Signed-off-by Isaku Yamahata <[email protected]>Signed-off-by Jason Baron <[email protected]>Quoted 7 lines
--- hw/Makefile.objs | 2 +- hw/i21154.c | 113 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ hw/i21154.h | 9 ++++ 3 files changed, 123 insertions(+), 1 deletions(-) create mode 100644 hw/i21154.c create mode 100644 hw/i21154.h
Quoted 4 lines
Why is this creating a new file and not reusing
dec_pci.c? We shouldn't have two parallel implementations of the same chip.Andreas
Good point I missed this. There's a minor difference wrt dec-21154-p2p-bridge in a couple of fields, these could be set by properties.
Also dec_map_irq differs from the spec compliant map function. I am guessing this is a bug. Would appreciate testing of the patch below.
Are you familiar with dec_pci.c? Looking at it, it seems to implement a pci host bridge "dec-21154-sysbus" ,
a pci to pci bridge "dec-21154-p2p-bridge",
and something called "dec-21154" which sports a comment "PCI2PCI bridge same values as PearPC - check this" - and implements an empty init function;
what this last is and why it's useful I am not sure.
Anyone? Blue Swirl? Anyone can test this doesn't break things and report?
--->
dec_pci: irq swizzle PCI spec compliance
Make IRQ mapping for dec PCI PCI 2 PCI Bridge compliant with the PCI spec.
---
hw/dec_pci.c +1 -1
@@ -82,7 +82,7 @@ PCIBus *pci_dec_21154_init(PCIBus *parent_bus, int devfn) dev =pci_create_multifunction (parent_bus, devfn, false,"dec-21154-p2p-bridge" ); br =DO_UPCAST (PCIBridge, dev, dev); -pci_bridge_map_irq (br,"DEC 21154 PCI-PCI bridge" , dec_map_irq); +pci_bridge_map_irq (br,"DEC 21154 PCI-PCI bridge" , pci_swizzle_map_irq_fn);qdev_init_nofail (&dev->qdev);return pci_bridge_get_sec_bus (br); }
Re: [Qemu-devel] [PATCH v3 17/26] Add i21154 bridge chip.
Quoted 16 lines · Michael S. Tsirkin
Quoted 15 lines · Andreas Färber
Am 19.10.2012 22:43, schrieb Jason Baron:
Quoted 13 lines
From: Jason Baron <[email protected]>
This adds support for the DECchip 21154 PCI bridge.
Signed-off-by Isaku Yamahata <[email protected]>Signed-off-by Jason Baron <[email protected]>--- hw/Makefile.objs | 2 +- hw/i21154.c | 113 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ hw/i21154.h | 9 ++++ 3 files changed, 123 insertions(+), 1 deletions(-) create mode 100644 hw/i21154.c create mode 100644 hw/i21154.h
Quoted 6 lines
Quoted 4 lines
Why is this creating a new file and not reusing
dec_pci.c? We shouldn't have two parallel implementations of the same chip.Andreas
Good point I missed this. There's a minor difference
Yes, I missed this too. No reason to carry this patch, I will drop it.
Thanks,
-Jason
Quoted 42 lines
wrt dec-21154-p2p-bridge in a couple of fields, these could be set by properties.
Alsodec_map_irqdiffers from the spec compliant map function. I am guessing this is a bug. Would appreciate testing of the patch below.Are you familiar with
dec_pci.c? Looking at it, it seems to implement a pci host bridge "dec-21154-sysbus" ,
a pci to pci bridge "dec-21154-p2p-bridge",
and something called "dec-21154" which sports a comment "PCI2PCI bridge same values as PearPC - check this" - and implements an empty init function;
what this last is and why it's useful I am not sure.Anyone? Blue Swirl? Anyone can test this doesn't break things and report?
--->
dec_pci: irq swizzle PCI spec complianceMake IRQ mapping for dec PCI PCI 2 PCI Bridge compliant with the PCI spec.
Signed-off-by Michael S. Tsirkin <[email protected]>---
hw/dec_pci.c +1
-1@@ -82,7 +82,7 @@ PCIBus *pci_dec_21154_init(PCIBus *parent_bus, int devfn) dev =pci_create_multifunction (parent_bus, devfn, false,"dec-21154-p2p-bridge" ); br =DO_UPCAST (PCIBridge, dev, dev); -pci_bridge_map_irq (br,"DEC 21154 PCI-PCI bridge" , dec_map_irq); +pci_bridge_map_irq (br,"DEC 21154 PCI-PCI bridge" , pci_swizzle_map_irq_fn);qdev_init_nofail (&dev->qdev);return pci_bridge_get_sec_bus (br); }
Re: [Qemu-devel] [PATCH v3 17/26] Add i21154 bridge chip.
In reply to Michael S. TsirkinAm 22.10.2012 18:17, schrieb Michael S. Tsirkin:
Quoted 16 lines · Andreas Färber
Quoted 6 lines
Am 19.10.2012 22:43, schrieb Jason Baron:
Quoted 2 lines
create mode 100644 hw/i21154.c create mode 100644 hw/i21154.hWhy is this creating a new file and not reusing
dec_pci.c? We shouldn't have two parallel implementations of the same chip.Good point I missed this. There's a minor difference wrt dec-21154-p2p-bridge in a couple of fields, these could be set by properties.
Alsodec_map_irqdiffers from the spec compliant map function. I am guessing this is a bug. Would appreciate testing of the patch below.
Quoted 7 lines
Are you familiar with
dec_pci.c? Looking at it, it seems to implement a pci host bridge "dec-21154-sysbus" ,
a pci to pci bridge "dec-21154-p2p-bridge",
and something called "dec-21154" which sports a comment "PCI2PCI bridge same values as PearPC - check this" - and implements an empty init function;
what this last is and why it's useful I am not sure.
Apart from my PHB rework touching it, I had a branch starting to QOM'ify it. From what I remember it was a PCIDevice that interfaces with a "regular" SysBus PHB device and like most PHBs has a PCIDevice on its PCIBus. That would match the number of devices you mention, although the exact names are pretty confusing for all PHBs IMO. ;)
Quoted 2 lines
Anyone? Blue Swirl? Anyone can test this doesn't break things and report?
I'll look more closely and test when I'm back from oSC mid of the week. I think it was ppc_newworld that was using this, possibly subject to #if 0 (which I was trying to clean up, too).
Thanks,
Andreas
Signature · 2 lines
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH v3 17/26] Add i21154 bridge chip.
In reply to Michael S. TsirkinQuoted 37 lines · Michael S. Tsirkin
Quoted 15 lines · Andreas Färber
Am 19.10.2012 22:43, schrieb Jason Baron:
Quoted 6 lines
From: Jason Baron <[email protected]>
This adds support for the DECchip 21154 PCI bridge.
Signed-off-by Isaku Yamahata <[email protected]>Signed-off-by Jason Baron <[email protected]>Quoted 7 lines
--- hw/Makefile.objs | 2 +- hw/i21154.c | 113 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ hw/i21154.h | 9 ++++ 3 files changed, 123 insertions(+), 1 deletions(-) create mode 100644 hw/i21154.c create mode 100644 hw/i21154.hQuoted 4 lines
Why is this creating a new file and not reusing
dec_pci.c? We shouldn't have two parallel implementations of the same chip.Andreas
Good point I missed this. There's a minor difference wrt dec-21154-p2p-bridge in a couple of fields, these could be set by properties.
Alsodec_map_irqdiffers from the spec compliant map function. I am guessing this is a bug. Would appreciate testing of the patch below.Are you familiar with
dec_pci.c? Looking at it, it seems to implement a pci host bridge "dec-21154-sysbus" ,
a pci to pci bridge "dec-21154-p2p-bridge",
and something called "dec-21154" which sports a comment "PCI2PCI bridge same values as PearPC - check this" - and implements an empty init function;
what this last is and why it's useful I am not sure.
Quoted 2 lines
Anyone? Blue Swirl? Anyone can test this doesn't break things and report?
The device is only linked by PPC but the init function is not invoked. It should be also used by Sparc64 (it's present on real Ultra-5 machine and several devices should be behind the bridge) but it isn't.
Quoted 17 lines
--->
dec_pci: irq swizzle PCI spec complianceMake IRQ mapping for dec PCI PCI 2 PCI Bridge compliant with the PCI spec.
Signed-off-by Michael S. Tsirkin <[email protected]>---
hw/dec_pci.c +0
-0
hw/dec_pci.c PCIBus *pci_dec_21154_init(PCIBus *parent_bus, int devfn) · line 85
Quoted 4 lines
hw/dec_pci.c +0
-1@@ -82,7 +82,7 @@ PCIBus *pci_dec_21154_init(PCIBus *parent_bus, int devfn) dev =pci_create_multifunction (parent_bus, devfn, false,"dec-21154-p2p-bridge" ); br =DO_UPCAST (PCIBridge, dev, dev); -pci_bridge_map_irq (br,"DEC 21154 PCI-PCI bridge" , dec_map_irq);
dec_map_irq is now unused and should be removed to avoid build breakage.
hw/dec_pci.c PCIBus *pci_dec_21154_init(PCIBus *parent_bus, int devfn) · line 88
Quoted 4 lines
hw/dec_pci.c +1
-0+pci_bridge_map_irq (br,"DEC 21154 PCI-PCI bridge" , pci_swizzle_map_irq_fn);qdev_init_nofail (&dev->qdev);return pci_bridge_get_sec_bus (br); }
Otherwise I think the patch is fine.
PATCH v3 18/26 q35: Suppress SMM BIOS initialization under KVM
In reply to Jason BaronFrom: Jan Kiszka <[email protected]>
Same as for i44fx: KVM does not support SMM yet. Signal it initialized to Seabios to avoid failures.
--- hw/acpi_ich9.c | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-)
hw/acpi_ich9.c +7 -0
@@ -28,6 +28,7 @@#include "qemu-timer.h" #include "sysemu.h" #include "acpi.h" +#include "kvm.h" #include "ich9.h"
@@ -292,6 +293,12 @@ static void pm_reset(void *opaque)acpi_pm_tmr_reset (&pm->acpi_regs);acpi_gpe_reset (&pm->acpi_regs); +if (kvm_enabled ()) { +/* Mark SMM as already inited to prevent SMM from running. KVM does not +* support SMM mode. */ + pm->smi_en |=ICH9_PMIO_SMI_EN_APMC_EN ; + } +pm_update_sci (pm); }
Signature · 1 line
1.7.1
PATCH v3 19/26 q35: Fix non-PCI IRQ processing in ich9_lpc_update_apic
In reply to Jason BaronFrom: Jan Kiszka <[email protected]>
Avoid passing a non-PCI IRQ to ich9_gsi_to_pirq. It's wrong and triggers an assertion.
--- hw/lpc_ich9.c | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-)
hw/lpc_ich9.c +4 -2
@@ -264,9 +264,11 @@ static int ich9_gsi_to_pirq(int gsi)static void ich9_lpc_update_apic (ICH9LPCState *lpc,int gsi) { -int level; +int level =0 ; - level =pci_bus_get_irq_level (lpc->d.bus,ich9_gsi_to_pirq (gsi)); +if (gsi >=ICH9_LPC_PIC_NUM_PINS ) { + level |=pci_bus_get_irq_level (lpc->d.bus,ich9_gsi_to_pirq (gsi)); + }if (gsi ==ich9_lpc_sci_irq (lpc)) { level |= lpc->sci_level; }
Signature · 1 line
1.7.1
Michael S. Tsirkin
AppliedRe: [Qemu-devel] [PATCH v3 19/26] q35: Fix non-PCI IRQ processing in ich9_lpc_update_apic
Quoted 8 lines · Jason Baron
From: Jan Kiszka <[email protected]>
Avoid passing a non-PCI IRQ to
ich9_gsi_to_pirq. It's wrong and triggers an assertion.Reviewed-by Paolo Bonzini <[email protected]>Signed-off-by Jan Kiszka <[email protected]>Signed-off-by Jason Baron <[email protected]>
Thanks, applied.
Quoted 24 lines
--- hw/lpc_ich9.c | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-)hw/lpc_ich9.c +4
-2@@ -264,9 +264,11 @@ static int ich9_gsi_to_pirq(int gsi)static void ich9_lpc_update_apic (ICH9LPCState *lpc,int gsi) { -int level; +int level =0 ; - level =pci_bus_get_irq_level (lpc->d.bus,ich9_gsi_to_pirq (gsi)); +if (gsi >=ICH9_LPC_PIC_NUM_PINS ) { + level |=pci_bus_get_irq_level (lpc->d.bus,ich9_gsi_to_pirq (gsi)); + }if (gsi ==ich9_lpc_sci_irq (lpc)) { level |= lpc->sci_level; }Signature · 1 line
1.7.1
PATCH v3 20/26 q35: smbus: Remove PCI_STATUS_SIG_SYSTEM_ERROR and PCI_STATUS_DETECTED_PARITY from w1cmask
In reply to Jason BaronFrom: Jan Kiszka <[email protected]>
Both bits are added to the write-1-to-clear mask by default. As the smbus device does not allow writes at all, we have to remove it from that mask, also to avoid triggering a runtime assertion.
--- hw/smbus_ich9.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-)
hw/smbus_ich9.c +4 -0
@@ -94,6 +94,10 @@ static int ich9_smbus_initfn(PCIDevice *d) {ICH9SMBState *s =ICH9_SMB_DEVICE (d); +pci_set_word (d->w1cmask +PCI_STATUS , +pci_get_word (d->w1cmask +PCI_STATUS ) & + ~(PCI_STATUS_SIG_SYSTEM_ERROR |PCI_STATUS_DETECTED_PARITY )); +/* TODO? D31IP.SMIP in chipset configuration space */ pci_config_set_interrupt_pin (d->config,0x01 );/* interrupt pin 1 */
Signature · 1 line
1.7.1
Re: [Qemu-devel] [PATCH v3 20/26] q35: smbus: Remove PCI_STATUS_SIG_SYSTEM_ERROR and PCI_STATUS_DETECTED_PARITY from w1cmask
Quoted 9 lines · Jason Baron
From: Jan Kiszka <[email protected]>
Both bits are added to the write-1-to-clear mask by default. As the smbus device does not allow writes at all, we have to remove it from that mask, also to avoid triggering a runtime assertion.
Reviewed-by Paolo Bonzini <[email protected]>Signed-off-by Jan Kiszka <[email protected]>Signed-off-by Jason Baron <[email protected]>
Is this patch still needed?
What does it mean that smbus does not allow writes at all? What's the assertion triggered here?
Quoted 21 lines
--- hw/smbus_ich9.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-)hw/smbus_ich9.c +4
-0@@ -94,6 +94,10 @@ static int ich9_smbus_initfn(PCIDevice *d) {ICH9SMBState *s =ICH9_SMB_DEVICE (d); +pci_set_word (d->w1cmask +PCI_STATUS , +pci_get_word (d->w1cmask +PCI_STATUS ) & + ~(PCI_STATUS_SIG_SYSTEM_ERROR |PCI_STATUS_DETECTED_PARITY )); +/* TODO? D31IP.SMIP in chipset configuration space */ pci_config_set_interrupt_pin (d->config,0x01 );/* interrupt pin 1 */ Signature · 1 line
1.7.1
PATCH v3 21/26 q35: Add kvmclock support
In reply to Jason BaronFrom: Jan Kiszka <[email protected]>
--- hw/pc_q35.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-)
hw/pc_q35.c +3 -0
@@ -69,6 +69,7 @@#include "mc146818rtc.h" #include "xen.h" #include "kvm.h" +#include "kvm/clock.h" #include "q35.h" #include "exec-memory.h"
@@ -224,6 +225,8 @@ static void pc_q35_init(ram_addr_t ram_size,pc_cpus_init (cpu_model); +kvmclock_create (); +if (ram_size >=0xb0000000 ) { above_4g_mem_size = ram_size -0xb0000000 ; below_4g_mem_size =0xb0000000 ;
Signature · 1 line
1.7.1
PATCH v3 22/26 Add a fallback bios file search, if -L fails.
In reply to Jason BaronFrom: Jason Baron <[email protected]>
If -L <dir> is specified, and qemu does not find the bios file in <dir>, then the search fails. Add infrastructure such that the search will continue in the default paths, if not found in the -L path.
--- vl.c | 36 +++++++++++++++++++++++++----------- 1 files changed, 25 insertions(+), 11 deletions(-)
vl.c +25 -11
@@ -177,6 +177,7 @@ int main(int argc, char **argv)#define MAX_VIRTIO_CONSOLES 1static const char *data_dir; +static const char *data_dir_fallback;const char *bios_name =NULL ;enum vga_retrace_method vga_retrace_method =VGA_RETRACE_DUMB ;DisplayType display_type =DT_DEFAULT ;
@@ -1892,16 +1893,16 @@ static int balloon_parse(const char *arg)return -1 ; } -char *qemu_find_file (int type,const char *name) +static char *qemu_find_file_in_dir (int type,const char *name,const char *dir) {int len;const char *subdir;char *buf; -/* Try the name as a straight path first */ -if (access (name,R_OK ) ==0 ) { -return g_strdup (name); +if (!dir) { +return NULL ; } +switch (type) {case QEMU_FILE_TYPE_BIOS : subdir ="" ;
@@ -1912,9 +1913,9 @@ char *qemu_find_file(int type, const char *name)default :abort (); } - len =strlen (data_dir) +strlen (name) +strlen (subdir) +2 ; + len =strlen (dir) +strlen (name) +strlen (subdir) +2 ; buf =g_malloc0 (len); -snprintf (buf, len,"%s/%s%s" , data_dir, subdir, name); +snprintf (buf, len,"%s/%s%s" , dir, subdir, name);if (access (buf,R_OK )) {g_free (buf);return NULL ;
@@ -1922,6 +1923,21 @@ char *qemu_find_file(int type, const char *name)return buf; } +char *qemu_find_file (int type,const char *name) +{ +char *filename; + +/* Try the name as a straight path first */ +if (access (name,R_OK ) ==0 ) { +return g_strdup (name); + } + filename =qemu_find_file_in_dir (type, name, data_dir); +if (!filename) { + filename =qemu_find_file_in_dir (type, name, data_dir_fallback); + } +return filename; +} +static int device_help_func (QemuOpts *opts,void *opaque) {return qdev_device_help (opts);
@@ -3359,12 +3375,10 @@ int main(int argc, char **argv, char **envp)/* If no data_dir is specified then try to find it relative to the executable path. */ -if (!data_dir) { - data_dir =os_find_datadir (argv[0 ]); - } + data_dir_fallback =os_find_datadir (argv[0 ]);/* If all else fails use the install path specified when building. */ -if (!data_dir) { - data_dir =CONFIG_QEMU_DATADIR ; +if (!data_dir_fallback) { + data_dir_fallback =CONFIG_QEMU_DATADIR ; }/*
Signature · 1 line
1.7.1
Re: [Qemu-devel] [PATCH v3 22/26] Add a fallback bios file search, if -L fails.
Quoted 59 lines · Jason Baron
From: Jason Baron <[email protected]>
If -L <dir> is specified, and qemu does not find the bios file in <dir>, then the search fails. Add infrastructure such that the search will continue in the default paths, if not found in the -L path.
Reviewed-by Paolo Bonzini <[email protected]>Signed-off-by Jason Baron <[email protected]>--- vl.c | 36 +++++++++++++++++++++++++----------- 1 files changed, 25 insertions(+), 11 deletions(-)vl.c +7
-6@@ -177,6 +177,7 @@ int main(int argc, char **argv)#define MAX_VIRTIO_CONSOLES 1static const char *data_dir; +static const char *data_dir_fallback;const char *bios_name =NULL ;enum vga_retrace_method vga_retrace_method =VGA_RETRACE_DUMB ;DisplayType display_type =DT_DEFAULT ;@@ -1892,16 +1893,16 @@ static int balloon_parse(const char *arg)return -1 ; } -char *qemu_find_file (int type,const char *name) +static char *qemu_find_file_in_dir (int type,const char *name,const char *dir) {int len;const char *subdir;char *buf; -/* Try the name as a straight path first */ -if (access (name,R_OK ) ==0 ) { -return g_strdup (name); +if (!dir) { +return NULL ; } +switch (type) {case QEMU_FILE_TYPE_BIOS : subdir ="" ;@@ -1912,9 +1913,9 @@ char *qemu_find_file(int type, const char *name)default :abort (); } - len =strlen (data_dir) +strlen (name) +strlen (subdir) +2 ; + len =strlen (dir) +strlen (name) +strlen (subdir) +2 ; buf =g_malloc0 (len); -snprintf (buf, len,"%s/%s%s" , data_dir, subdir, name); +snprintf (buf, len,"%s/%s%s" , dir, subdir, name);if (access (buf,R_OK )) {g_free (buf);return NULL ;@@ -1922,6 +1923,21 @@ char *qemu_find_file(int type, const char *name)return buf;
vl.c char *qemu_find_file(int type, const char *name) · line 1933
Quoted 10 lines
vl.c +8
-0} +char *qemu_find_file (int type,const char *name) +{ +char *filename; + +/* Try the name as a straight path first */ +if (access (name,R_OK ) ==0 ) { +return g_strdup (name); + }
FWIW, this can be a security issue, when a more privileged user tries to run qemu from trusted path (/usr/bin) in a directory owned by non-privileged user, to utilize -runas or somesuch. I understand it's been this way since the beginning.
Maybe we can do a bit better here, like (windows systems aside) this:
if (strchr(name, '/') && access(name, R_OK) == 0) {...}Note that -L can be set to "." in order to check in current directory too.
And going forward, maybe we can treat -L argument as a PATH (separated by whatever delimiter is okay) instead of just a single directory? This way, for example, we can put various kinds of data (pxe roms, vgabios roms etc) into different places and qemu will be able to find them all.
I understand this whole thing is not really related to q35 changes, so can be pushed/applied separately.
Thanks,
/mjt
Re: [Qemu-devel] [PATCH v3 22/26] Add a fallback bios file search, if -L fails.
Quoted 16 lines · Michael Tokarev
vl.c char *qemu_find_file(int type, const char *name) · line 1933
Quoted 8 lines · Jason Baron
vl.c +8
-0+char *qemu_find_file (int type,const char *name) +{ +char *filename; + +/* Try the name as a straight path first */ +if (access (name,R_OK ) ==0 ) { +return g_strdup (name); + }FWIW, this can be a security issue, when a more privileged user tries to run qemu from trusted path (
/usr/bin) in a directory owned by non-privileged user, to utilize -runas or somesuch. I understand it's been this way since the beginning.
Quoted 4 lines
Maybe we can do a bit better here, like (windows systems aside) this:
if (strchr(name, '/') && access(name, R_OK) == 0) {...}
We used to do that, but it was removed in commit 3178320 because it's inconsistent with how we handle other file access (like -kernel). The documentation says -bios takes a filename, so it should just take a filename, with no weird undocumented restrictions.
If you want qemu not to read files from the current working directory by default the right fix for that is probably to make those defaults be "foo.bin in the bios path", not unqualified "foo.bin".
-- PMM
PATCH v3 23/26 q35: automatically load the q35 dsdt table
In reply to Jason BaronFrom: Jason Baron <[email protected]>
Automatically, locate the required q35 dsdt table on load. Otherwise we error out. This could be done in the bios, but its harder to produce a good error message.
--- hw/pc.c | 19 +++++++++++++++++++ hw/pc.h | 2 ++ hw/pc_q35.c | 7 +++++++ 3 files changed, 28 insertions(+), 0 deletions(-)
hw/pc.c +19 -0
@@ -1149,3 +1149,22 @@ void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name) gsi_state->ioapic_irq[i] =qdev_get_gpio_in (dev, i); } } + +int find_and_load_dsdt (const char *dsdt_name) +{ +char *filename; +char buf[1024 ]; + + filename =qemu_find_file (QEMU_FILE_TYPE_BIOS , dsdt_name); +if (!filename) { +return -1 ; + } +snprintf (buf,sizeof (buf),"file=%s" , filename); +g_free (filename); +if (acpi_table_add (buf) <0 ) { +fprintf (stderr,"Wrong acpi table provided\n" ); +return -1 ; + } + +return 0 ; +}
hw/pc.h +2 -0
@@ -214,5 +214,7 @@ void pc_system_firmware_init(MemoryRegion *rom_memory);#define E820_UNUSABLE 5int e820_add_entry (uint64_t ,uint64_t ,uint32_t ); +int find_and_load_dsdt (const char *dsdt_name); +#endif
hw/pc_q35.c +7 -0
@@ -223,6 +223,13 @@ static void pc_q35_init(ram_addr_t ram_size,qemu_irq *i8259;int i; +/* let's first see if we can find the proper dsdt */ +if (find_and_load_dsdt ("q35-acpi-dsdt.aml" )) { +fprintf (stderr,"Couldn't find q35 dsdt table!\n" +"Try updating your bios.\n" ); +exit (1 ); + } +pc_cpus_init (cpu_model);kvmclock_create ();
Signature · 1 line
1.7.1
PATCH v3 24/26 q35: add acpi-based pci hotplug.
In reply to Jason BaronFrom: Jason Baron <[email protected]>
Add piix style acpi hotplug to q35.
--- hw/acpi_ich9.c | 172 +++++++++++++++++++++++++++++++++++++++++++++++++++++++- hw/acpi_ich9.h | 10 +++ 2 files changed, 181 insertions(+), 1 deletions(-)
hw/acpi_ich9.c +171 -1
@@ -41,6 +41,13 @@ do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0)#define ICH9_DEBUG (fmt, ...) do { } while (0)#endif +#define PCI_UP_BASE 0xae00 +#define PCI_DOWN_BASE 0xae04 +#define PCI_EJ_BASE 0xae08 +#define PCI_RMV_BASE 0xae0c +#define ICH9_PCI_HOTPLUG_STATUS 2 + +static void pm_ioport_write_fallback (void *opaque,uint32_t addr,int len,uint32_t val);static uint32_t pm_ioport_read_fallback (void *opaque,uint32_t addr,int len);
@@ -55,7 +62,10 @@ static void pm_update_sci(ICH9LPCPMRegs *pm) (ACPI_BITMASK_RT_CLOCK_ENABLE |ACPI_BITMASK_POWER_BUTTON_ENABLE |ACPI_BITMASK_GLOBAL_LOCK_ENABLE | - ACPI_BITMASK_TIMER_ENABLE)) != 0); + ACPI_BITMASK_TIMER_ENABLE)) != 0) || + (((pm->acpi_regs.gpe.sts[0 ] & pm->acpi_regs.gpe.en[0 ]) + &ICH9_PCI_HOTPLUG_STATUS ) !=0 ); +qemu_set_irq (pm->irq, sci_level);/* schedule a timer interruption if needed */
@@ -77,6 +87,7 @@ static void pm_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)switch (addr &ICH9_PMIO_MASK ) { case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + ICH9_PMIO_GPE0_LEN - 1):acpi_gpe_ioport_writeb (&pm->acpi_regs, addr, val); +pm_update_sci (pm);break ;default :break ;
@@ -283,6 +294,65 @@ const VMStateDescription vmstate_ich9_pm = { } }; +static void acpi_ich9_eject_slot (ICH9LPCPMRegs *opaque,unsigned slots) +{ +BusChild *kid, *next; +ICH9LPCPMRegs *pm = opaque; +ICH9LPCState *lpc =container_of (pm, ICH9LPCState, pm); +PCIDevice *s =PCI_DEVICE (lpc); +BusState *bus =qdev_get_parent_bus (&s->qdev); +int slot =ffs (slots) -1 ; +bool slot_free = true; + +/* Mark request as complete */ + pm->pci0_status.down &= ~(1U << slot); + + QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) { +DeviceState *qdev = kid->child; +PCIDevice *dev =PCI_DEVICE (qdev); +PCIDeviceClass *pc =PCI_DEVICE_GET_CLASS (dev); +if (PCI_SLOT (dev->devfn) == slot) { +if (pc->no_hotplug) { + slot_free = false; + }else { +qdev_free (qdev); + } + } + } +if (slot_free) { + pm->pci0_slot_device_present &= ~(1U << slot); + } +} + +static void acpi_ich9_update_hotplug (ICH9LPCPMRegs *pm) +{ +ICH9LPCState *lpc =container_of (pm, ICH9LPCState, pm); +PCIDevice *dev =PCI_DEVICE (lpc); +BusState *bus =qdev_get_parent_bus (&dev->qdev); +BusChild *kid, *next; + +/* Execute any pending removes during reset */ +while (pm->pci0_status.down) { +acpi_ich9_eject_slot (pm, pm->pci0_status.down); + } + + pm->pci0_hotplug_enable = ~0 ; + pm->pci0_slot_device_present =0 ; + + QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) { +DeviceState *qdev = kid->child; +PCIDevice *pdev =PCI_DEVICE (qdev); +PCIDeviceClass *pc =PCI_DEVICE_GET_CLASS (pdev); +int slot =PCI_SLOT (pdev->devfn); + +if (pc->no_hotplug) { + pm->pci0_hotplug_enable &= ~(1U << slot); + } + + pm->pci0_slot_device_present |= (1U << slot); + } +} +static void pm_reset (void *opaque) {ICH9LPCPMRegs *pm = opaque;
@@ -300,6 +370,7 @@ static void pm_reset(void *opaque) }pm_update_sci (pm); +acpi_ich9_update_hotplug (pm); }static void pm_powerdown_req (Notifier *n,void *opaque)
@@ -309,6 +380,104 @@ static void pm_powerdown_req(Notifier *n, void *opaque)acpi_pm1_evt_power_down (&pm->acpi_regs); } +static uint32_t pci_up_read (void *opaque,uint32_t addr) +{ +ICH9LPCPMRegs *pm = opaque; +uint32_t val; + +/* Manufacture an "up" value to cause a device check on any hotplug +* slot with a device. Extra device checks are harmless. */ + val = pm->pci0_slot_device_present & pm->pci0_hotplug_enable; + +ICH9_DEBUG ("pci_up_read %x\n" , val); +return val; +} + +static uint32_t pci_down_read (void *opaque,uint32_t addr) +{ +ICH9LPCPMRegs *pm = opaque; +uint32_t val = pm->pci0_status.down; + +ICH9_DEBUG ("pci_down_read %x\n" , val); +return val; +} + +static uint32_t pci_features_read (void *opaque,uint32_t addr) +{ +/* No feature defined yet */ +ICH9_DEBUG ("pci_features_read %x\n" ,0 ); +return 0 ; +} + +static void pciej_write (void *opaque,uint32_t addr,uint32_t val) +{ +acpi_ich9_eject_slot (opaque, val); + +ICH9_DEBUG ("pciej write %x <== %d\n" , addr, val); +} + +static uint32_t pcirmv_read (void *opaque,uint32_t addr) +{ +ICH9LPCPMRegs *pm = opaque; + +return pm->pci0_hotplug_enable; +} + +static void enable_device (ICH9LPCPMRegs *pm,int slot) +{ + pm->acpi_regs.gpe.sts[0 ] |=ICH9_PCI_HOTPLUG_STATUS ; + pm->pci0_slot_device_present |= (1U << slot); +} + +static void disable_device (ICH9LPCPMRegs *pm,int slot) +{ + pm->acpi_regs.gpe.sts[0 ] |=ICH9_PCI_HOTPLUG_STATUS ; + pm->pci0_status.down |= (1U << slot); +} + +static int ich9_device_hotplug (DeviceState *qdev,PCIDevice *dev, +PCIHotplugState state) +{ +int slot =PCI_SLOT (dev->devfn); +ICH9LPCState *lpc =DO_UPCAST (ICH9LPCState, d, +PCI_DEVICE (qdev)); +ICH9LPCPMRegs *pm = &lpc->pm; + +/* Don't send event when device is enabled during qemu machine creation: +* it is present on boot, no hotplug event is necessary. We do send an +* event when the device is disabled later. */ +if (state ==PCI_COLDPLUG_ENABLED ) { + pm->pci0_slot_device_present |= (1U << slot); +return 0 ; + } + +if (state ==PCI_HOTPLUG_ENABLED ) { +enable_device (pm, slot); + }else { +disable_device (pm, slot); + } + +pm_update_sci (pm); + +return 0 ; +} + +static void ich9_acpi_system_hot_add_init (ICH9LPCPMRegs *s) +{ +ICH9LPCState *lpc =container_of (s, ICH9LPCState, pm); +PCIDevice *pdev =PCI_DEVICE (lpc); + +register_ioport_read (PCI_UP_BASE ,4 ,4 , pci_up_read, s); +register_ioport_read (PCI_DOWN_BASE ,4 ,4 , pci_down_read, s); + +register_ioport_write (PCI_EJ_BASE ,4 ,4 , pciej_write, s); +register_ioport_read (PCI_EJ_BASE ,4 ,4 , pci_features_read, s); + +register_ioport_read (PCI_RMV_BASE ,4 ,4 , pcirmv_read, s); + +pci_bus_hotplug (pdev->bus, ich9_device_hotplug, &pdev->qdev); +} +void ich9_pm_init (ICH9LPCPMRegs *pm,qemu_irq sci_irq,qemu_irq cmos_s3) {acpi_pm_tmr_init (&pm->acpi_regs, ich9_pm_update_sci_fn);
@@ -319,4 +488,5 @@ void ich9_pm_init(ICH9LPCPMRegs *pm, qemu_irq sci_irq, qemu_irq cmos_s3)qemu_register_reset (pm_reset, pm); pm->powerdown_notifier.notify = pm_powerdown_req;qemu_register_powerdown_notifier (&pm->powerdown_notifier); +ich9_acpi_system_hot_add_init (pm); }
hw/acpi_ich9.h +10 -0
@@ -23,6 +23,11 @@#include "acpi.h" +struct pci_status { +uint32_t up;/* deprecated, maintained for migration compatibility */ +uint32_t down; +}; + typedef struct ICH9LPCPMRegs { /* * In ich9 spec says that pm1_cnt register is 32bit width and
@@ -37,6 +42,11 @@ typedef struct ICH9LPCPMRegs {uint32_t pm_io_base;Notifier powerdown_notifier; + +/* for pci hotplug */ +struct pci_status pci0_status; +uint32_t pci0_hotplug_enable; +uint32_t pci0_slot_device_present; } ICH9LPCPMRegs; void ich9_pm_init(ICH9LPCPMRegs *pm,
Signature · 1 line
1.7.1
Re: [Qemu-devel] [PATCH v3 24/26] q35: add acpi-based pci hotplug.
Quoted 3 lines · Jason Baron
From: Jason Baron <[email protected]>
Add piix style acpi hotplug to q35.
piix style is an understatement. This is exactly the same interface probably to enable the same bios code to run on both piix and q35.
If true let's not duplicate code: please factor relevant functionality out of piix and reuse.
You might be able to reuse migration support as well:
it seems broken currently so this needs a TODO.
Quoted 259 lines
Signed-off-by Jason Baron <[email protected]>--- hw/acpi_ich9.c | 172 +++++++++++++++++++++++++++++++++++++++++++++++++++++++- hw/acpi_ich9.h | 10 +++ 2 files changed, 181 insertions(+), 1 deletions(-)hw/acpi_ich9.c +171
-1@@ -41,6 +41,13 @@ do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0)#define ICH9_DEBUG (fmt, ...) do { } while (0)#endif +#define PCI_UP_BASE 0xae00 +#define PCI_DOWN_BASE 0xae04 +#define PCI_EJ_BASE 0xae08 +#define PCI_RMV_BASE 0xae0c +#define ICH9_PCI_HOTPLUG_STATUS 2 + +static void pm_ioport_write_fallback (void *opaque,uint32_t addr,int len,uint32_t val);static uint32_t pm_ioport_read_fallback (void *opaque,uint32_t addr,int len);@@ -55,7 +62,10 @@ static void pm_update_sci(ICH9LPCPMRegs *pm) (ACPI_BITMASK_RT_CLOCK_ENABLE |ACPI_BITMASK_POWER_BUTTON_ENABLE |ACPI_BITMASK_GLOBAL_LOCK_ENABLE | - ACPI_BITMASK_TIMER_ENABLE)) != 0); + ACPI_BITMASK_TIMER_ENABLE)) != 0) || + (((pm->acpi_regs.gpe.sts[0 ] & pm->acpi_regs.gpe.en[0 ]) + &ICH9_PCI_HOTPLUG_STATUS ) !=0 ); +qemu_set_irq (pm->irq, sci_level);/* schedule a timer interruption if needed */ @@ -77,6 +87,7 @@ static void pm_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)switch (addr &ICH9_PMIO_MASK ) { case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + ICH9_PMIO_GPE0_LEN - 1):acpi_gpe_ioport_writeb (&pm->acpi_regs, addr, val); +pm_update_sci (pm);break ;default :break ;@@ -283,6 +294,65 @@ const VMStateDescription vmstate_ich9_pm = { } }; +static void acpi_ich9_eject_slot (ICH9LPCPMRegs *opaque,unsigned slots) +{ +BusChild *kid, *next; +ICH9LPCPMRegs *pm = opaque; +ICH9LPCState *lpc =container_of (pm, ICH9LPCState, pm); +PCIDevice *s =PCI_DEVICE (lpc); +BusState *bus =qdev_get_parent_bus (&s->qdev); +int slot =ffs (slots) -1 ; +bool slot_free = true; + +/* Mark request as complete */ + pm->pci0_status.down &= ~(1U << slot); + + QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) { +DeviceState *qdev = kid->child; +PCIDevice *dev =PCI_DEVICE (qdev); +PCIDeviceClass *pc =PCI_DEVICE_GET_CLASS (dev); +if (PCI_SLOT (dev->devfn) == slot) { +if (pc->no_hotplug) { + slot_free = false; + }else { +qdev_free (qdev); + } + } + } +if (slot_free) { + pm->pci0_slot_device_present &= ~(1U << slot); + } +} + +static void acpi_ich9_update_hotplug (ICH9LPCPMRegs *pm) +{ +ICH9LPCState *lpc =container_of (pm, ICH9LPCState, pm); +PCIDevice *dev =PCI_DEVICE (lpc); +BusState *bus =qdev_get_parent_bus (&dev->qdev); +BusChild *kid, *next; + +/* Execute any pending removes during reset */ +while (pm->pci0_status.down) { +acpi_ich9_eject_slot (pm, pm->pci0_status.down); + } + + pm->pci0_hotplug_enable = ~0 ; + pm->pci0_slot_device_present =0 ; + + QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) { +DeviceState *qdev = kid->child; +PCIDevice *pdev =PCI_DEVICE (qdev); +PCIDeviceClass *pc =PCI_DEVICE_GET_CLASS (pdev); +int slot =PCI_SLOT (pdev->devfn); + +if (pc->no_hotplug) { + pm->pci0_hotplug_enable &= ~(1U << slot); + } + + pm->pci0_slot_device_present |= (1U << slot); + } +} +static void pm_reset (void *opaque) {ICH9LPCPMRegs *pm = opaque;@@ -300,6 +370,7 @@ static void pm_reset(void *opaque) }pm_update_sci (pm); +acpi_ich9_update_hotplug (pm); }static void pm_powerdown_req (Notifier *n,void *opaque)@@ -309,6 +380,104 @@ static void pm_powerdown_req(Notifier *n, void *opaque)acpi_pm1_evt_power_down (&pm->acpi_regs); } +static uint32_t pci_up_read (void *opaque,uint32_t addr) +{ +ICH9LPCPMRegs *pm = opaque; +uint32_t val; + +/* Manufacture an "up" value to cause a device check on any hotplug +* slot with a device. Extra device checks are harmless. */ + val = pm->pci0_slot_device_present & pm->pci0_hotplug_enable; + +ICH9_DEBUG ("pci_up_read %x\n" , val); +return val; +} + +static uint32_t pci_down_read (void *opaque,uint32_t addr) +{ +ICH9LPCPMRegs *pm = opaque; +uint32_t val = pm->pci0_status.down; + +ICH9_DEBUG ("pci_down_read %x\n" , val); +return val; +} + +static uint32_t pci_features_read (void *opaque,uint32_t addr) +{ +/* No feature defined yet */ +ICH9_DEBUG ("pci_features_read %x\n" ,0 ); +return 0 ; +} + +static void pciej_write (void *opaque,uint32_t addr,uint32_t val) +{ +acpi_ich9_eject_slot (opaque, val); + +ICH9_DEBUG ("pciej write %x <== %d\n" , addr, val); +} + +static uint32_t pcirmv_read (void *opaque,uint32_t addr) +{ +ICH9LPCPMRegs *pm = opaque; + +return pm->pci0_hotplug_enable; +} + +static void enable_device (ICH9LPCPMRegs *pm,int slot) +{ + pm->acpi_regs.gpe.sts[0 ] |=ICH9_PCI_HOTPLUG_STATUS ; + pm->pci0_slot_device_present |= (1U << slot); +} + +static void disable_device (ICH9LPCPMRegs *pm,int slot) +{ + pm->acpi_regs.gpe.sts[0 ] |=ICH9_PCI_HOTPLUG_STATUS ; + pm->pci0_status.down |= (1U << slot); +} + +static int ich9_device_hotplug (DeviceState *qdev,PCIDevice *dev, +PCIHotplugState state) +{ +int slot =PCI_SLOT (dev->devfn); +ICH9LPCState *lpc =DO_UPCAST (ICH9LPCState, d, +PCI_DEVICE (qdev)); +ICH9LPCPMRegs *pm = &lpc->pm; + +/* Don't send event when device is enabled during qemu machine creation: +* it is present on boot, no hotplug event is necessary. We do send an +* event when the device is disabled later. */ +if (state ==PCI_COLDPLUG_ENABLED ) { + pm->pci0_slot_device_present |= (1U << slot); +return 0 ; + } + +if (state ==PCI_HOTPLUG_ENABLED ) { +enable_device (pm, slot); + }else { +disable_device (pm, slot); + } + +pm_update_sci (pm); + +return 0 ; +} + +static void ich9_acpi_system_hot_add_init (ICH9LPCPMRegs *s) +{ +ICH9LPCState *lpc =container_of (s, ICH9LPCState, pm); +PCIDevice *pdev =PCI_DEVICE (lpc); + +register_ioport_read (PCI_UP_BASE ,4 ,4 , pci_up_read, s); +register_ioport_read (PCI_DOWN_BASE ,4 ,4 , pci_down_read, s); + +register_ioport_write (PCI_EJ_BASE ,4 ,4 , pciej_write, s); +register_ioport_read (PCI_EJ_BASE ,4 ,4 , pci_features_read, s); + +register_ioport_read (PCI_RMV_BASE ,4 ,4 , pcirmv_read, s); + +pci_bus_hotplug (pdev->bus, ich9_device_hotplug, &pdev->qdev); +} +void ich9_pm_init (ICH9LPCPMRegs *pm,qemu_irq sci_irq,qemu_irq cmos_s3) {acpi_pm_tmr_init (&pm->acpi_regs, ich9_pm_update_sci_fn);@@ -319,4 +488,5 @@ void ich9_pm_init(ICH9LPCPMRegs *pm, qemu_irq sci_irq, qemu_irq cmos_s3)qemu_register_reset (pm_reset, pm); pm->powerdown_notifier.notify = pm_powerdown_req;qemu_register_powerdown_notifier (&pm->powerdown_notifier); +ich9_acpi_system_hot_add_init (pm); }hw/acpi_ich9.h +10
-0@@ -23,6 +23,11 @@#include "acpi.h" +struct pci_status { +uint32_t up;/* deprecated, maintained for migration compatibility */ +uint32_t down; +}; + typedef struct ICH9LPCPMRegs { /* * In ich9 spec says that pm1_cnt register is 32bit width and@@ -37,6 +42,11 @@ typedef struct ICH9LPCPMRegs {uint32_t pm_io_base;Notifier powerdown_notifier; + +/* for pci hotplug */ +struct pci_status pci0_status; +uint32_t pci0_hotplug_enable; +uint32_t pci0_slot_device_present; } ICH9LPCPMRegs; void ich9_pm_init(ICH9LPCPMRegs *pm,Signature · 1 line
1.7.1
PATCH v3 25/26 q35: fill in usb pci slots with -usb
In reply to Jason BaronFrom: Jason Baron <[email protected]>
This fills out the usb slots on q35, when -usb is passed. We now have (lspci output):
00:1d.0 USB Controller: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #1 (rev 03) 00:1d.1 USB Controller: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #2 (rev 03) 00:1d.2 USB Controller: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #3 (rev 03) 00:1d.7 USB Controller: Intel Corporation 82801I (ICH9 Family) USB2 EHCI Controller #1 (rev 03)
--- hw/ich9.h | 5 ++++- hw/pc_q35.c | 11 ++++++++++- 2 files changed, 14 insertions(+), 2 deletions(-)
hw/ich9.h +4 -1
@@ -87,8 +87,11 @@ typedef struct ICH9LPCState {/* D29:F0 USB UHCI Controller #1 */ -#define ICH9_USB_UHCI1_DEV 29 +#define ICH9_USB_DEV 29#define ICH9_USB_UHCI1_FUNC 0 +#define ICH9_USB_UHCI2_FUNC 1 +#define ICH9_USB_UHCI3_FUNC 2 +#define ICH9_USB_EHCI1_FUNC 7/* D30:F0 DMI-to-PCI brdige */ #define ICH9_D2P_BRIDGE "ICH9 D2P BRIDGE"
hw/pc_q35.c +10 -1
@@ -185,8 +185,17 @@ static void pc_q35_init_late(BusState **idebus, ISADevice *rtc_state,if (usb_enabled) {/* Should we create 6 UHCI according to ich9 spec? */ pci_create_simple_multifunction ( - host_bus,PCI_DEVFN (ICH9_USB_UHCI1_DEV ,ICH9_USB_UHCI1_FUNC ), + host_bus,PCI_DEVFN (ICH9_USB_DEV ,ICH9_USB_UHCI1_FUNC ), true,"ich9-usb-uhci1" ); +pci_create_simple_multifunction ( + host_bus,PCI_DEVFN (ICH9_USB_DEV ,ICH9_USB_UHCI2_FUNC ), + true,"ich9-usb-uhci2" ); +pci_create_simple_multifunction ( + host_bus,PCI_DEVFN (ICH9_USB_DEV ,ICH9_USB_UHCI3_FUNC ), + true,"ich9-usb-uhci3" ); +pci_create_simple_multifunction ( + host_bus,PCI_DEVFN (ICH9_USB_DEV ,ICH9_USB_EHCI1_FUNC ), + true,"ich9-usb-ehci1" );/* XXX: EHCI */ }
Signature · 1 line
1.7.1
Re: [Qemu-devel] [PATCH v3 25/26] q35: fill in usb pci slots with -usb
Hi,
hw/pc_q35.c static void pc_q35_init_late(BusState **idebus, ISADevice *rtc_state, · line 199
Quoted 4 lines
hw/pc_q35.c +3
-0+pci_create_simple_multifunction ( + host_bus,PCI_DEVFN (ICH9_USB_DEV ,ICH9_USB_EHCI1_FUNC ), + true,"ich9-usb-ehci1" );/* XXX: EHCI */
You can remove that comment now ;)
cheers,
Gerd
Re: [Qemu-devel] [PATCH v3 25/26] q35: fill in usb pci slots with -usb
In reply to Jason BaronIl 19/10/2012 22:43, Jason Baron ha scritto:
Quoted 45 lines
From: Jason Baron <[email protected]>
This fills out the usb slots on q35, when -usb is passed. We now have (lspci output):
00:1d.0 USB Controller: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #1 (rev 03) 00:1d.1 USB Controller: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #2 (rev 03) 00:1d.2 USB Controller: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #3 (rev 03) 00:1d.7 USB Controller: Intel Corporation 82801I (ICH9 Family) USB2 EHCI Controller #1 (rev 03)
Signed-off-by Jason Baron <[email protected]>--- hw/ich9.h | 5 ++++- hw/pc_q35.c | 11 ++++++++++- 2 files changed, 14 insertions(+), 2 deletions(-)hw/ich9.h +4
-1@@ -87,8 +87,11 @@ typedef struct ICH9LPCState {/* D29:F0 USB UHCI Controller #1 */ -#define ICH9_USB_UHCI1_DEV 29 +#define ICH9_USB_DEV 29#define ICH9_USB_UHCI1_FUNC 0 +#define ICH9_USB_UHCI2_FUNC 1 +#define ICH9_USB_UHCI3_FUNC 2 +#define ICH9_USB_EHCI1_FUNC 7/* D30:F0 DMI-to-PCI brdige */ #define ICH9_D2P_BRIDGE "ICH9 D2P BRIDGE"hw/pc_q35.c +2
-1@@ -185,8 +185,17 @@ static void pc_q35_init_late(BusState **idebus, ISADevice *rtc_state,if (usb_enabled) {/* Should we create 6 UHCI according to ich9 spec? */ pci_create_simple_multifunction ( - host_bus,PCI_DEVFN (ICH9_USB_UHCI1_DEV ,ICH9_USB_UHCI1_FUNC ), + host_bus,PCI_DEVFN (ICH9_USB_DEV ,ICH9_USB_UHCI1_FUNC ), true,"ich9-usb-uhci1" ); + pci_create_simple_multifunction(
hw/pc_q35.c static void pc_q35_init_late(BusState **idebus, ISADevice *rtc_state, · line 200
Quoted 10 lines
hw/pc_q35.c +8
-0+ host_bus,PCI_DEVFN (ICH9_USB_DEV ,ICH9_USB_UHCI2_FUNC ), + true, "ich9-usb-uhci2"); +pci_create_simple_multifunction ( + host_bus,PCI_DEVFN (ICH9_USB_DEV ,ICH9_USB_UHCI3_FUNC ), + true,"ich9-usb-uhci3" ); +pci_create_simple_multifunction ( + host_bus,PCI_DEVFN (ICH9_USB_DEV ,ICH9_USB_EHCI1_FUNC ), + true,"ich9-usb-ehci1" );/* XXX: EHCI */ }
Compared to docs/ich9-ehci-uhci.cfg, this is missing:
[device "uhci-1"]
masterbus = "ehci.0"
firstport = "0"
[device "uhci-2"]
masterbus = "ehci.0"
firstport = "2"
[device "uhci-3"]
masterbus = "ehci.0"
firstport = "4"
Paolo
PATCH v3 26/26 ich9: add support pci assignment
In reply to Jason BaronFrom: Jason Baron <[email protected]>
Fills out support for the pci assignment API. Added:
PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin)
Add calls to pci_bus_fire_intx_routing_notifier() when routing changes are made.
--- hw/ich9.h | 1 + hw/lpc_ich9.c | 33 +++++++++++++++++++++++++++++++++ hw/pc_q35.c | 1 + 3 files changed, 35 insertions(+), 0 deletions(-)
hw/ich9.h +1 -0
@@ -18,6 +18,7 @@void ich9_lpc_set_irq (void *opaque,int irq_num,int level);int ich9_lpc_map_irq (PCIDevice *pci_dev,int intx); +PCIINTxRoute ich9_route_intx_pin_to_irq (void *opaque,int pirq_pin);void ich9_lpc_pm_init (PCIDevice *pci_lpc,qemu_irq cmos_s3);PCIBus *ich9_d2pbr_init (PCIBus *bus,int devfn,int sec_bus);i2c_bus *ich9_smb_init (PCIBus *bus,int devfn,uint32_t smb_io_base);
hw/lpc_ich9.c +33 -0
@@ -173,6 +173,7 @@ static void ich9_cc_write(void *opaque, target_phys_addr_t addr,ich9_cc_addr_len (&addr, &len);memcpy (lpc->chip_config + addr, &val, len); +pci_bus_fire_intx_routing_notifier (lpc->d.bus);ich9_cc_update (lpc); }
@@ -301,6 +302,32 @@ int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx)return lpc->irr[PCI_SLOT (pci_dev->devfn)][intx]; } +PCIINTxRoute ich9_route_intx_pin_to_irq (void *opaque,int pirq_pin) +{ +ICH9LPCState *lpc = opaque; +PCIINTxRoute route; +int pic_irq; +int pic_dis; + +assert (0 <= pirq_pin); +assert (pirq_pin <ICH9_LPC_NB_PIRQS ); + + route.mode =PCI_INTX_ENABLED ; +ich9_lpc_pic_irq (lpc, pirq_pin, &pic_irq, &pic_dis); +if (!pic_dis) { +if (pic_irq <ICH9_LPC_PIC_NUM_PINS ) { + route.irq = pic_irq; + }else { + route.mode =PCI_INTX_DISABLED ; + route.irq =-1 ; + } + }else { + route.irq =ich9_pirq_to_gsi (pirq_pin); + } + +return route; +} +static int ich9_lpc_sci_irq (ICH9LPCState *lpc) { switch (lpc->d.config[ICH9_LPC_ACPI_CTRL] &
@@ -420,6 +447,12 @@ static void ich9_lpc_config_write(PCIDevice *d,if (ranges_overlap (addr, len,ICH9_LPC_RCBA ,4 )) {ich9_lpc_rcba_update (lpc, rbca_old); } +if (ranges_overlap (addr, len,ICH9_LPC_PIRQA_ROUT ,4 )) { +pci_bus_fire_intx_routing_notifier (lpc->d.bus); + } +if (ranges_overlap (addr, len,ICH9_LPC_PIRQE_ROUT ,4 )) { +pci_bus_fire_intx_routing_notifier (lpc->d.bus); + } }static void ich9_lpc_reset (DeviceState *qdev)
hw/pc_q35.c +1 -0
@@ -112,6 +112,7 @@ static void pc_q35_init_early(qemu_irq *gsi, GSIState *gsi_state, ich9_lpc->ioapic = gsi_state->ioapic_irq;pci_bus_irqs (host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,ICH9_LPC_NB_PIRQS ); +pci_bus_set_route_irq_fn (host_bus, ich9_route_intx_pin_to_irq); gmps->ram_memory = ram_memory; gmps->pci_address_space = pci_address_space;
Signature · 1 line
1.7.1
Quoted 4 lines · Jason Baron
Hi,
Qemu bits for q35 support, I'm posting the seabios changes separately. The patches require '-M
pc_q35' and -L 'seabios dir with q35 changes' on the
Just a small maybe-nitpick: can we ue pc-q35 here instead of pc_q35 (ie, minus instead of underscore)? We've converted several underscores to minuses in a few places recently, in order to make it all consistent, maybe it is time to stop introducing new occurences? Note that other values for -machine already uses minus signs instead of underscores: pc-1.2, pc-0.15 etc...
Thanks,
/mjt
Quoted 48 lines · Jason Baron
Hi,
Qemu bits for q35 support, I'm posting the seabios changes separately. The patches require '-M
pc_q35' and -L 'seabios dir with q35 changes' on the qemu command line. Hopefully, we can make it the default for x86 at some future point when we feel comfortable with it.The current patches have been tested with basic install testing and memory testing on f16, f17, windows 7 and windows 8. They can be run on the various BSD flavors by adding a 'piix4-ide' device to the pci bus. ie: -device piix4-ide. Patches have also been reported to work with a small dsdt change on OSX 10.6 as well.
I've dropped the ahci migration bits, which means q35 is not migratable at the moment. I simply haven't had time to make them more complete yet.
I'm hoping that we'll come to some agreement on the minimal functionality required for q35 to be merged.
Git trees:
git://github.com/jibaron/q35-qemu.gitgit://github.com/jibaron/q35-seabios.gitNotes:
I've dropped automatic load of the dsdt table on the piix for now. We can't pull this in until we have snapshot of the dsdt aml, and I wanted it to be done at a clean seabios freeze point (Although I guess that could be the current snapshot). I don't see the harm in pulling this in later though.
I've also gone to a model of the pci host being sparse:
00:00.0 Host bridge: Intel Corporation 82G33/G31/P35/P31 Express DRAM Controller
00:01.0 VGA compatible controller: Cirrus Logic GD 5446
00:02.0 Ethernet controller: Intel Corporation 82540EM Gigabit Ethernet Controller (rev 03) 00:1f.0 ISA bridge: Intel Corporation 82801IB (ICH9) LPC Interface Controller (rev 02) 00:1f.2 SATA controller: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller (rev 02) 00:1f.3 SMBus: Intel Corporation 82801I (ICH9 Family) SMBus Controller (rev 02)The idea is only to populate the essential stuff at 1f, and have the rest filled out via command line options. In this way we have minimal bus configuration with 1 slot occupied as in piix. Should make things easier for libvirt. And this way user has complete control over things. For example, I have added support that when '-usb' is passed the usb controllers for ich9 are filled out.
Todo:
Review
Quoted 3 lines
(quoted diff) +0
-3-add ahci migration back (need to cover more fields, but basically works) -add base addr for hpet in LPC device (for osx per agraf) -convert hotplug to use MemoryRegionPortio for hotplug (need an IsaDevice?)
- add acpi hotplug for devices behind bridge
(this is needed so we can add e.g. PCI devices behind a bridge
in a compliant way)
Quoted 117 lines
Thanks,
-Jason
Changes from v2:
-Patch restructure (broke out ich9 chips + data structures separately) -added passthrough support
-add support for -usb to fill out host pci bus
-Dropped automatic load of dsdt table for piix
-cleanups
-dropped wmask on smbus (mst)
-sparse host busChanges from v1:
-Updated end of low mem from0xe0000000->0xb0000000(Gerd Hoffmann)-so 0xb000000-0xc000000 is memconfig -0xc000000-0xfec00000 is 32-bit pci window-style/various cleanups
-introducedIF_AHCI
-introducedmach_if
-split dsdt out of bios, now passed for piix4 as well (Paolo, Gerd) -Removed add opaque argument topci_map_irq_fn(Michael S. Tsirkin) -removed patches that were merged in v1Isaku Yamahata (6):
pci: pci capability must be in PCI space
pci: introducepci_swizzle_map_irq_fn()for standardized interrupt
pin swizzle
pc,pc_piix: split out pc nic initialization pc/piix_pci: factor out smram/pam logic
pci_ids: add intel 82801BA pci-to-pci bridge id
q35: Introduce q35 pc based chipset emulatorJan Kiszka (5):
pci: Add class0xc05as 'SMBus'
q35: Suppress SMM BIOS initialization under KVM
q35: Fix non-PCI IRQ processing inich9_lpc_update_apic
q35: smbus: RemovePCI_STATUS_SIG_SYSTEM_ERRORand
PCI_STATUS_DETECTED_PARITYfrom w1cmask
q35: Add kvmclock supportJason Baron (15):
blockdev: Introduce a default machine blockdev interface field,QEMUMachine->mach_ifblockdev: Introduce
IF_AHCI
pc: Moveioapic_init()frompc_piix.ctopc.c
pcie: pass pcie window size topcie_host_mmcfg_update()
pcie: Convert PCIExpressHost to use the QOM.
ich9: Add acpi support and definitions
ich9: Add the lpc chip
ich9: Add smbus
ich9: Add i82801b11 dmi-to-pci bridge
Add i21154 bridge chip.
Add a fallback bios file search, if -L fails.
q35: automatically load the q35 dsdt table
q35: add acpi-based pci hotplug.
q35: fill in usb pci slots with -usb
ich9: add support pci assignmentblockdev.c | 17 ++- blockdev.h | 21 ++ hw/Makefile.objs | 1 + hw/acpi_ich9.c | 492 +++++++++++++++++++++++++++++++++++++++++++ hw/acpi_ich9.h | 57 +++++ hw/boards.h | 2 +- hw/device-hotplug.c | 2 +- hw/highbank.c | 2 +- hw/i21154.c | 113 ++++++++++ hw/i21154.h | 9 + hw/i386/Makefile.objs | 2 + hw/i82801b11.c | 125 +++++++++++ hw/ich9.h | 211 +++++++++++++++++++ hw/ide.h | 6 + hw/ide/ahci.c | 18 ++ hw/ide/core.c | 23 ++- hw/leon3.c | 2 +- hw/lpc_ich9.c | 558 +++++++++++++++++++++++++++++++++++++++++++++++++ hw/mips_jazz.c | 4 +- hw/pam.c | 120 +++++++++++ hw/pam.h | 98 +++++++++ hw/pc.c | 58 +++++ hw/pc.h | 7 + hw/pc_piix.c | 38 +--- hw/pc_q35.c | 336 +++++++++++++++++++++++++++++ hw/pc_sysfw.c | 2 +- hw/pci.c | 25 ++- hw/pci.h | 2 + hw/pci_ids.h | 16 ++ hw/pcie_host.c | 35 +++- hw/pcie_host.h | 12 +- hw/piix_pci.c | 65 +----- hw/puv3.c | 2 +- hw/q35.c | 332 +++++++++++++++++++++++++++++ hw/q35.h | 161 ++++++++++++++ hw/realview.c | 6 +- hw/smbus_ich9.c | 163 ++++++++++++++ hw/spapr.c | 2 +- hw/sun4m.c | 24 +- hw/versatilepb.c | 4 +- hw/vexpress.c | 4 +- hw/xilinx_zynq.c | 2 +- vl.c | 56 ++++-- 43 files changed, 3074 insertions(+), 161 deletions(-) create mode 100644 hw/acpi_ich9.c create mode 100644 hw/acpi_ich9.h create mode 100644 hw/i21154.c create mode 100644 hw/i21154.h create mode 100644 hw/i82801b11.c create mode 100644 hw/ich9.h create mode 100644 hw/lpc_ich9.c create mode 100644 hw/pam.c create mode 100644 hw/pam.h create mode 100644 hw/pc_q35.c create mode 100644 hw/q35.c create mode 100644 hw/q35.h create mode 100644 hw/smbus_ich9.c
Quoted 52 lines · Jason Baron
Hi,
Qemu bits for q35 support, I'm posting the seabios changes separately. The patches require '-M
pc_q35' and -L 'seabios dir with q35 changes' on the qemu command line. Hopefully, we can make it the default for x86 at some future point when we feel comfortable with it.The current patches have been tested with basic install testing and memory testing on f16, f17, windows 7 and windows 8. They can be run on the various BSD flavors by adding a 'piix4-ide' device to the pci bus. ie: -device piix4-ide. Patches have also been reported to work with a small dsdt change on OSX 10.6 as well.
I've dropped the ahci migration bits, which means q35 is not migratable at the moment. I simply haven't had time to make them more complete yet.
I'm hoping that we'll come to some agreement on the minimal functionality required for q35 to be merged.
Git trees:
git://github.com/jibaron/q35-qemu.gitgit://github.com/jibaron/q35-seabios.gitNotes:
I've dropped automatic load of the dsdt table on the piix for now. We can't pull this in until we have snapshot of the dsdt aml, and I wanted it to be done at a clean seabios freeze point (Although I guess that could be the current snapshot). I don't see the harm in pulling this in later though.
I've also gone to a model of the pci host being sparse:
00:00.0 Host bridge: Intel Corporation 82G33/G31/P35/P31 Express DRAM Controller
00:01.0 VGA compatible controller: Cirrus Logic GD 5446
00:02.0 Ethernet controller: Intel Corporation 82540EM Gigabit Ethernet Controller (rev 03) 00:1f.0 ISA bridge: Intel Corporation 82801IB (ICH9) LPC Interface Controller (rev 02) 00:1f.2 SATA controller: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller (rev 02) 00:1f.3 SMBus: Intel Corporation 82801I (ICH9 Family) SMBus Controller (rev 02)The idea is only to populate the essential stuff at 1f, and have the rest filled out via command line options. In this way we have minimal bus configuration with 1 slot occupied as in piix. Should make things easier for libvirt. And this way user has complete control over things. For example, I have added support that when '-usb' is passed the usb controllers for ich9 are filled out.
Todo:
(quoted diff) +0
-3-add ahci migration back (need to cover more fields, but basically works) -add base addr for hpet in LPC device (for osx per agraf) -convert hotplug to use MemoryRegionPortio for hotplug (need an IsaDevice?)
Quoted 3 lines
Thanks,
-Jason
To me it looks like it's best to merge these bits so the patchset stops growing. However I'd like to make sure we don't create user confusion with all the missing bits.
Would it make sense to temporarily rename the machine type e.g. pc-q35-experimental to stress it's not fully supported?
Signature · 1 line
MST
Hi,
Quoted 2 lines
Would it make sense to temporarily rename the machine type e.g. pc-q35-experimental to stress it's not fully supported?
I don't think this is needed as piix will continue to be the default. It will also cause trouble with libvirt when pc-q35-experimental goes away some day.
cheers,
Gerd
Quoted 6 lines · Gerd Hoffmann
Hi,
Quoted 2 lines
Would it make sense to temporarily rename the machine type e.g. pc-q35-experimental to stress it's not fully supported?
I don't think this is needed as piix will continue to be the default.
Well q35 is not yet 100% ready.
I'm looking for some way in which we can signal libvirt and other users when it's ready, while merging some bits to reduce the maintainance load of maintaining a q35 fork.
Quoted 5 lines
It will also cause trouble with libvirt when pc-q35-experimental goes away some day.
cheers,
Gerd
The point was to hide it from libvirt.
libvirt should support pc-q35 not pc-q35-experimental, then it will not cause trouble.
Signature · 1 line
MST
Quoted 9 lines · Michael S. Tsirkin
Quoted 6 lines · Gerd Hoffmann
Hi,
Quoted 2 lines
Would it make sense to temporarily rename the machine type e.g. pc-q35-experimental to stress it's not fully supported?
I don't think this is needed as piix will continue to be the default.
Well q35 is not yet 100% ready.
I know.
Quoted 3 lines
The point was to hide it from libvirt.
libvirt should support pc-q35 not pc-q35-experimental, then it will not cause trouble.
You'll not going to hide it that way. Libvirt will just 'qemu -M ?' where q35 will show up even if you rename it to be postfixed -experimental.
But as long as 'pc' continues to be the default the causal user will never ever notice q35 is there, at least not with virt-manager (dunno about boxes) as there is simply no gui way to pick the machine type. You'll have to explicitly "virsh edit $guest" to switch it to q35.
So I'm not sure what you are worryed about. But in any case this needs discussion with the libvirt folks to make sure it will actually work as intended. /me tends to think a experimental bit in machine_info (which is then printed by 'qemu -M ?' and the QOM-version of that) is more useful than playing tricks with the name.
cheers,
Gerd
Quoted 20 lines · Gerd Hoffmann
Quoted 9 lines · Michael S. Tsirkin
Quoted 6 lines · Gerd Hoffmann
Hi,
Quoted 2 lines
Would it make sense to temporarily rename the machine type e.g. pc-q35-experimental to stress it's not fully supported?
I don't think this is needed as piix will continue to be the default.
Well q35 is not yet 100% ready.
I know.
Quoted 3 lines
The point was to hide it from libvirt.
libvirt should support pc-q35 not pc-q35-experimental, then it will not cause trouble.You'll not going to hide it that way. Libvirt will just 'qemu -M ?' where q35 will show up even if you rename it to be postfixed -experimental.
Quoted 6 lines
But as long as 'pc' continues to be the default the causal user will never ever notice q35 is there, at least not with virt-manager (dunno about boxes) as there is simply no gui way to pick the machine type. You'll have to explicitly "virsh edit $guest" to switch it to q35.
So I'm not sure what you are worryed about.
I worry about need to maintain bug for bug compatibility on the unlikely chance that the work to complete it gets delayed and we release it in an unready state.
Quoted 8 lines
But in any case this needs
discussion with the libvirt folks to make sure it will actually work as intended. /me tends to think a experimental bit inmachine_info(which is then printed by 'qemu -M ?' and the QOM-version of that) is more useful than playing tricks with the name.cheers,
Gerd
I agree it's best to ask libvirt folks what's the right way to hide a machine type from it. Add a flag so it's not listed in -M ? ? Jason, do you know?
Signature · 1 line
MST
Quoted 10 lines · Michael S. Tsirkin
I worry about need to maintain bug for bug compatibility on the unlikely chance that the work to complete it gets delayed and we release it in an unready state.
Quoted 6 lines
But in any case this needs
discussion with the libvirt folks to make sure it will actually work as intended. /me tends to think a experimental bit inmachine_info(which is then printed by 'qemu -M ?' and the QOM-version of that) is more useful than playing tricks with the name.
Quoted 5 lines
Quoted 2 lines
cheers,
GerdI agree it's best to ask libvirt folks what's the right way to hide a machine type from it. Add a flag so it's not listed in -M ? ?
For qemu 1.3, libvirt will NOT be reading '-M ?', but instead calling the 'query-machines' QMP command. If you want a machine to be avoided by libvirt, then perhaps it is best to augment the MachineInfo QMP datatype to add an optional field that says whether a particular machine type is stable enough for libvirt's use.
Signature · 2 lines
Eric Blake [email protected] +1-919-301-3266 Libvirt virtualization library http://libvirt.org
Quoted 15 lines · Eric Blake
Quoted 13 lines · Michael S. Tsirkin
I worry about need to maintain bug for bug compatibility on the unlikely chance that the work to complete it gets delayed and we release it in an unready state.
Quoted 8 lines
But in any case this needs
discussion with the libvirt folks to make sure it will actually work as intended. /me tends to think a experimental bit inmachine_info(which is then printed by 'qemu -M ?' and the QOM-version of that) is more useful than playing tricks with the name.cheers,
Gerd
Quoted 8 lines
Quoted 2 lines
I agree it's best to ask libvirt folks what's the right way to hide a machine type from it. Add a flag so it's not listed in -M ? ?
For qemu 1.3, libvirt will NOT be reading '-M ?', but instead calling the 'query-machines' QMP command. If you want a machine to be avoided by libvirt, then perhaps it is best to augment the MachineInfo QMP datatype to add an optional field that says whether a particular machine type is stable enough for libvirt's use.
Or just hide this machine type from the query-machines command?
Quoted 4 lines
Signature · 2 lines
Eric Blake [email protected] +1-919-301-3266 Libvirt virtualization library http://libvirt.org
Quoted 19 lines · Michael S. Tsirkin
Quoted 18 lines · Eric Blake
Quoted 15 lines · Michael S. Tsirkin
I worry about need to maintain bug for bug compatibility on the unlikely chance that the work to complete it gets delayed and we release it in an unready state.
Quoted 8 lines
But in any case this needs
discussion with the libvirt folks to make sure it will actually work as intended. /me tends to think a experimental bit inmachine_info(which is then printed by 'qemu -M ?' and the QOM-version of that) is more useful than playing tricks with the name.cheers,
GerdI agree it's best to ask libvirt folks what's the right way to hide a machine type from it. Add a flag so it's not listed in -M ? ?
Quoted 7 lines
Quoted 5 lines
For qemu 1.3, libvirt will NOT be reading '-M ?', but instead calling the 'query-machines' QMP command. If you want a machine to be avoided by libvirt, then perhaps it is best to augment the MachineInfo QMP datatype to add an optional field that says whether a particular machine type is stable enough for libvirt's use.
Or just hide this machine type from the query-machines command?
That would probably work, as well.
Signature · 2 lines
Eric Blake [email protected] +1-919-301-3266 Libvirt virtualization library http://libvirt.org
Quoted 26 lines · Eric Blake
Quoted 25 lines · Michael S. Tsirkin
Quoted 23 lines · Eric Blake
Quoted 10 lines · Michael S. Tsirkin
I worry about need to maintain bug for bug compatibility on the unlikely chance that the work to complete it gets delayed and we release it in an unready state.
Quoted 6 lines
But in any case this needs
discussion with the libvirt folks to make sure it will actually work as intended. /me tends to think a experimental bit inmachine_info(which is then printed by 'qemu -M ?' and the QOM-version of that) is more useful than playing tricks with the name.Quoted 5 lines
Quoted 2 lines
cheers,
GerdI agree it's best to ask libvirt folks what's the right way to hide a machine type from it. Add a flag so it's not listed in -M ? ?
For qemu 1.3, libvirt will NOT be reading '-M ?', but instead calling the 'query-machines' QMP command. If you want a machine to be avoided by libvirt, then perhaps it is best to augment the MachineInfo QMP datatype to add an optional field that says whether a particular machine type is stable enough for libvirt's use.
Quoted 3 lines
Quoted 1 line
Or just hide this machine type from the query-machines command?
That would probably work, as well.
You would still want the testing from users behind libvirt, so hiding is not good. Hiding by default with an experimental tag would probably be the best.
Alex
Quoted 38 lines · Michael S. Tsirkin
Quoted 20 lines · Gerd Hoffmann
Quoted 9 lines · Michael S. Tsirkin
Quoted 6 lines · Gerd Hoffmann
Hi,
Quoted 2 lines
Would it make sense to temporarily rename the machine type e.g. pc-q35-experimental to stress it's not fully supported?
I don't think this is needed as piix will continue to be the default.
Well q35 is not yet 100% ready.
I know.
Quoted 3 lines
The point was to hide it from libvirt.
libvirt should support pc-q35 not pc-q35-experimental, then it will not cause trouble.You'll not going to hide it that way. Libvirt will just 'qemu -M ?' where q35 will show up even if you rename it to be postfixed -experimental.
Quoted 6 lines
But as long as 'pc' continues to be the default the causal user will never ever notice q35 is there, at least not with virt-manager (dunno about boxes) as there is simply no gui way to pick the machine type. You'll have to explicitly "virsh edit $guest" to switch it to q35.
So I'm not sure what you are worryed about.
I worry about need to maintain bug for bug compatibility on the unlikely chance that the work to complete it gets delayed and we release it in an unready state.
Quoted 6 lines
But in any case this needs
discussion with the libvirt folks to make sure it will actually work as intended. /me tends to think a experimental bit inmachine_info(which is then printed by 'qemu -M ?' and the QOM-version of that) is more useful than playing tricks with the name.
Quoted 6 lines
Quoted 2 lines
cheers,
GerdI agree it's best to ask libvirt folks what's the right way to hide a machine type from it. Add a flag so it's not listed in -M ? ? Jason, do you know?
We don't need to hide it from libvirt.
What I'd suggest is that for q35, we don't introduce QEMU versioned machine types but instead provide a machine-level version.
IOW:
q35-next <- bleeding edge version of code. No compatibility guarantee q35-0.1 <- if we decide we want to have a "tech preview" of q35 that's
incomplete but will be supported for compat
q35-1.0 <- the first "complete" release of q35 with full compat support
I think we should also alias 'q35' to 'q35-next'.
Regards,
Anthony Liguori
Quoted 3 lines
Signature · 2 lines
-- MST
On 22.10.2012 19:37, Anthony Liguori wrote:
[]
Quoted 6 lines
IOW:
q35-next <- bleeding edge version of code. No compatibility guarantee q35-0.1 <- if we decide we want to have a "tech preview" of q35 that's
incomplete but will be supported for compat
q35-1.0 <- the first "complete" release of q35 with full compat support
Make it q35-1.3 instead - to match the version of qemu where it appeared (if it will go into 1.3 ofcourse; if not, it will be 1.4 or something). And maybe q35-0.1.3 if it will go into 1.3 in a "tech preview form". Just to avoid confusion.
/mjt
Quoted 6 lines · Jason Baron
Hi,
Qemu bits for q35 support, I'm posting the seabios changes separately. The patches require '-M
pc_q35' and -L 'seabios dir with q35 changes' on the qemu command line. Hopefully, we can make it the default for x86 at some future point when we feel comfortable with it.
Some patches have multiple copyright sections. I realize this is because you copied code from other files but think it would be better to simply keep the original
license in this case, just extending list of copyright holders.
Signature · 1 line
MST