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CLK: SPEAr: Fixes & updates

PATCH New Viresh Kumar 2 participants 11 messages Nov 10, 2012 – Nov 21, 2012

Subsystems (2)
Common clk Spear platform/clock/pinctrl support
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Viresh Kumar

author
#0 lore raw

cover CLK: SPEAr: Fixes & updates

Hi Mike,

These are fixes for SPEAr clock stuff. Most of them are fixes, but we don't mind getting them in 3.8.

Deepak Sikri (2):
CLK: SPEAr1340: Update clock rate table
CLK: SPEAr: Correct index scanning done for clock synths

Rajeev Kumar (1):
CLK: SPEAr: Fix dev_id & con_id for multiple clocks

Shiraz Hashim (2):
CLK: SPEAr13xx: Fix mux clock names
CLK: SPEAr13xx: fix parent names of multiple clocks

Vipul Kumar Samar (3):
CLK: SPEAr: Set CLK_SET_RATE_PARENT for few clocks
CLK: SPEAr: Add missing clocks
CLK: SPEAr: Remove unused dummy apb_pclk

 drivers/clk/spear/clk-aux-synth.c   |   3 +-
 drivers/clk/spear/clk.c             |   3 +
 drivers/clk/spear/spear1310_clock.c | 106 +++++++++-------
 drivers/clk/spear/spear1340_clock.c | 237 ++++++++++++++++++++++--------------
 drivers/clk/spear/spear3xx_clock.c  | 148 +++++++++++++---------
 drivers/clk/spear/spear6xx_clock.c  |  13 +-
 6 files changed, 306 insertions(+), 204 deletions(-)
Signature · 1 line
1.7.12.rc2.18.g61b472e
author
#1 lore raw

PATCH 1/8 CLK: SPEAr: Fix dev_id & con_id for multiple clocks

From: Rajeev Kumar <[email protected]>

dev_id & con_id names of multiple clocks are incorrect. This patch fixes these names with the names that come via DT.

Signed-off-by Rajeev Kumar <[email protected]>
Signed-off-by Shiraz Hashim <[email protected]>
Signed-off-by Bhavna Yadav <[email protected]>
Signed-off-by Vipul Kumar Samar <[email protected]>
Signed-off-by Deepak Sikri <[email protected]>
Signed-off-by Viresh Kumar <[email protected]>
---
 drivers/clk/spear/spear1310_clock.c | 30 +++++++++++++-------------
 drivers/clk/spear/spear1340_clock.c | 42 +++++++++++++++++++------------------
 drivers/clk/spear/spear3xx_clock.c  | 12 ++++++-----
 drivers/clk/spear/spear6xx_clock.c  |  6 ++++--
 4 files changed, 49 insertions(+), 41 deletions(-)
drivers/clk/spear/spear1310_clock.c +16 -14
index 0fcec2a..f13b1d2 100644
@@ -401,7 +401,7 @@ void __init spear1310_clk_init(void)
 	clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_RTC_CLK_ENB, 0,
 			&_lock);
-	clk_register_clkdev(clk, NULL, "fc900000.rtc");
+	clk_register_clkdev(clk, NULL, "e0580000.rtc");
 
 	/* clock derived from 24 or 25 MHz osc clk */
 	/* vco-pll */

@@ -615,7 +615,7 @@ void __init spear1310_clk_init(void)
 			ARRAY_SIZE(gmac_phy_parents), 0,
 			SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GMAC_PHY_CLK_SHIFT,
 			SPEAR1310_GMAC_PHY_CLK_MASK, 0, &_lock);
-	clk_register_clkdev(clk, NULL, "stmmacphy.0");
+	clk_register_clkdev(clk, "stmmacphy.0", NULL);
 
 	/* clcd */
 	clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents,

@@ -638,7 +638,7 @@ void __init spear1310_clk_init(void)
 	clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0,
 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CLCD_CLK_ENB, 0,
 			&_lock);
-	clk_register_clkdev(clk, "clcd_clk", NULL);
+	clk_register_clkdev(clk, NULL, "e1000000.clcd");
 
 	/* i2s */
 	clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents,

@@ -705,35 +705,37 @@ void __init spear1310_clk_init(void)
 	clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0,
 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC0_CLK_ENB, 0,
 			&_lock);
-	clk_register_clkdev(clk, "usbh.0_clk", NULL);
+	clk_register_clkdev(clk, NULL, "e4000000.ohci");
+	clk_register_clkdev(clk, NULL, "e4800000.ehci");
 
 	clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0,
 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC1_CLK_ENB, 0,
 			&_lock);
-	clk_register_clkdev(clk, "usbh.1_clk", NULL);
+	clk_register_clkdev(clk, NULL, "e5000000.ohci");
+	clk_register_clkdev(clk, NULL, "e5800000.ehci");
 
 	clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0,
 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UOC_CLK_ENB, 0,
 			&_lock);
-	clk_register_clkdev(clk, NULL, "uoc");
+	clk_register_clkdev(clk, NULL, "e3800000.otg");
 
 	clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0,
 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_0_CLK_ENB,
 			0, &_lock);
 	clk_register_clkdev(clk, NULL, "dw_pcie.0");
-	clk_register_clkdev(clk, NULL, "ahci.0");
+	clk_register_clkdev(clk, NULL, "b1000000.ahci");
 
 	clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0,
 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_1_CLK_ENB,
 			0, &_lock);
 	clk_register_clkdev(clk, NULL, "dw_pcie.1");
-	clk_register_clkdev(clk, NULL, "ahci.1");
+	clk_register_clkdev(clk, NULL, "b1800000.ahci");
 
 	clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0,
 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_2_CLK_ENB,
 			0, &_lock);
 	clk_register_clkdev(clk, NULL, "dw_pcie.2");
-	clk_register_clkdev(clk, NULL, "ahci.2");
+	clk_register_clkdev(clk, NULL, "b4000000.ahci");
 
 	clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM0_CLK_ENB, 0,

@@ -754,7 +756,7 @@ void __init spear1310_clk_init(void)
 	clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk", 0,
 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_ADC_CLK_ENB, 0,
 			&_lock);
-	clk_register_clkdev(clk, NULL, "adc_clk");
+	clk_register_clkdev(clk, NULL, "e0080000.adc");
 
 	/* clock derived from apb clk */
 	clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0,

@@ -916,15 +918,15 @@ void __init spear1310_clk_init(void)
 			SPEAR1310_RAS_CTRL_REG1,
 			SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT,
 			SPEAR1310_PHY_CLK_MASK, 0, &_lock);
-	clk_register_clkdev(clk, NULL, "stmmacphy.1");
-	clk_register_clkdev(clk, NULL, "stmmacphy.2");
-	clk_register_clkdev(clk, NULL, "stmmacphy.4");
+	clk_register_clkdev(clk, "stmmacphy.1", NULL);
+	clk_register_clkdev(clk, "stmmacphy.2", NULL);
+	clk_register_clkdev(clk, "stmmacphy.4", NULL);
 
 	clk = clk_register_mux(NULL, "rmii_phy_mclk", rmii_phy_parents,
 			ARRAY_SIZE(rmii_phy_parents), 0,
 			SPEAR1310_RAS_CTRL_REG1, SPEAR1310_RMII_PHY_CLK_SHIFT,
 			SPEAR1310_PHY_CLK_MASK, 0, &_lock);
-	clk_register_clkdev(clk, NULL, "stmmacphy.3");
+	clk_register_clkdev(clk, "stmmacphy.3", NULL);
 
 	clk = clk_register_mux(NULL, "uart1_mclk", uart_parents,
 			ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
drivers/clk/spear/spear1340_clock.c +22 -20

145 lines not on this page · raw message

drivers/clk/spear/spear3xx_clock.c +7 -5
index c315745..e6461f7 100644
@@ -251,7 +251,7 @@ static void __init spear320_clk_init(void)
 
 	clk = clk_register_fixed_factor(NULL, "pwm_clk", "ras_ahb_clk", 0, 1,
 			1);
-	clk_register_clkdev(clk, "pwm", NULL);
+	clk_register_clkdev(clk, NULL, "a8000000.pwm");
 
 	clk = clk_register_fixed_factor(NULL, "ssp1_clk", "ras_ahb_clk", 0, 1,
 			1);

@@ -271,7 +271,7 @@ static void __init spear320_clk_init(void)
 
 	clk = clk_register_fixed_factor(NULL, "i2s_clk", "ras_apb_clk", 0, 1,
 			1);
-	clk_register_clkdev(clk, NULL, "i2s");
+	clk_register_clkdev(clk, NULL, "a9400000.i2s");
 
 	clk = clk_register_mux(NULL, "i2s_ref_clk", i2s_ref_parents,
 			ARRAY_SIZE(i2s_ref_parents), 0, SPEAR320_CONTROL_REG,

@@ -480,7 +480,9 @@ void __init spear3xx_clk_init(void)
 	/* clock derived from pll3 clk */
 	clk = clk_register_gate(NULL, "usbh_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
 			USBH_CLK_ENB, 0, &_lock);
-	clk_register_clkdev(clk, "usbh_clk", NULL);
+	clk_register_clkdev(clk, NULL, "e1800000.ehci");
+	clk_register_clkdev(clk, NULL, "e1900000.ohci");
+	clk_register_clkdev(clk, NULL, "e2100000.ohci");
 
 	clk = clk_register_fixed_factor(NULL, "usbh.0_clk", "usbh_clk", 0, 1,
 			1);

@@ -492,7 +494,7 @@ void __init spear3xx_clk_init(void)
 
 	clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
 			USBD_CLK_ENB, 0, &_lock);
-	clk_register_clkdev(clk, NULL, "designware_udc");
+	clk_register_clkdev(clk, NULL, "e1100000.usbd");
 
 	/* clock derived from ahb clk */
 	clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2,

@@ -540,7 +542,7 @@ void __init spear3xx_clk_init(void)
 	/* clock derived from apb clk */
 	clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB,
 			ADC_CLK_ENB, 0, &_lock);
-	clk_register_clkdev(clk, NULL, "adc");
+	clk_register_clkdev(clk, NULL, "d0080000.adc");
 
 	clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
 			GPIO_CLK_ENB, 0, &_lock);
drivers/clk/spear/spear6xx_clock.c +4 -2
index a98d086..c7fa67c 100644
@@ -261,11 +261,13 @@ void __init spear6xx_clk_init(void)
 	/* clock derived from pll3 clk */
 	clk = clk_register_gate(NULL, "usbh0_clk", "pll3_clk", 0,
 			PERIP1_CLK_ENB, USBH0_CLK_ENB, 0, &_lock);
-	clk_register_clkdev(clk, NULL, "usbh.0_clk");
+	clk_register_clkdev(clk, NULL, "e1800000.ehci");
+	clk_register_clkdev(clk, NULL, "e1900000.ohci");
 
 	clk = clk_register_gate(NULL, "usbh1_clk", "pll3_clk", 0,
 			PERIP1_CLK_ENB, USBH1_CLK_ENB, 0, &_lock);
-	clk_register_clkdev(clk, NULL, "usbh.1_clk");
+	clk_register_clkdev(clk, NULL, "e2000000.ehci");
+	clk_register_clkdev(clk, NULL, "e2100000.ohci");
 
 	clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
 			USBD_CLK_ENB, 0, &_lock);
Signature · 1 line
1.7.12.rc2.18.g61b472e
author
#2 lore raw

PATCH 2/8 CLK: SPEAr13xx: Fix mux clock names

In reply to Viresh Kumar

From: Shiraz Hashim <[email protected]>

This patch updates mux clock names of multiple clocks. It updates _clk with _mclk to make it more readable.

Signed-off-by Shiraz Hashim <[email protected]>
Signed-off-by Rajeev Kumar <[email protected]>
Signed-off-by Viresh Kumar <[email protected]>
---
 drivers/clk/spear/spear1310_clock.c |  4 ++--
 drivers/clk/spear/spear1340_clock.c | 20 ++++++++++----------
 2 files changed, 12 insertions(+), 12 deletions(-)
drivers/clk/spear/spear1310_clock.c +2 -2
index f13b1d2..2f1cb71 100644
@@ -633,7 +633,7 @@ void __init spear1310_clk_init(void)
 			ARRAY_SIZE(clcd_pixel_parents), 0,
 			SPEAR1310_PERIP_CLK_CFG, SPEAR1310_CLCD_CLK_SHIFT,
 			SPEAR1310_CLCD_CLK_MASK, 0, &_lock);
-	clk_register_clkdev(clk, "clcd_pixel_clk", NULL);
+	clk_register_clkdev(clk, "clcd_pixel_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0,
 			SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CLCD_CLK_ENB, 0,

@@ -645,7 +645,7 @@ void __init spear1310_clk_init(void)
 			ARRAY_SIZE(i2s_src_parents), 0, SPEAR1310_I2S_CLK_CFG,
 			SPEAR1310_I2S_SRC_CLK_SHIFT, SPEAR1310_I2S_SRC_CLK_MASK,
 			0, &_lock);
-	clk_register_clkdev(clk, "i2s_src_clk", NULL);
+	clk_register_clkdev(clk, "i2s_src_mclk", NULL);
 
 	clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", 0,
 			SPEAR1310_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl,
drivers/clk/spear/spear1340_clock.c +10 -10
index dae2ba6..4733d99 100644
@@ -521,7 +521,7 @@ void __init spear1340_clk_init(void)
 			ARRAY_SIZE(sys_parents), 0, SPEAR1340_SYS_CLK_CTRL,
 			SPEAR1340_SCLK_SRC_SEL_SHIFT,
 			SPEAR1340_SCLK_SRC_SEL_MASK, 0, &_lock);
-	clk_register_clkdev(clk, "sys_clk", NULL);
+	clk_register_clkdev(clk, "sys_mclk", NULL);
 
 	clk = clk_register_fixed_factor(NULL, "cpu_clk", "sys_mclk", 0, 1,
 			2);

@@ -697,7 +697,7 @@ void __init spear1340_clk_init(void)
 			ARRAY_SIZE(clcd_pixel_parents), 0,
 			SPEAR1340_PERIP_CLK_CFG, SPEAR1340_CLCD_CLK_SHIFT,
 			SPEAR1340_CLCD_CLK_MASK, 0, &_lock);
-	clk_register_clkdev(clk, "clcd_pixel_clk", NULL);
+	clk_register_clkdev(clk, "clcd_pixel_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0,
 			SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_CLCD_CLK_ENB, 0,

@@ -709,7 +709,7 @@ void __init spear1340_clk_init(void)
 			ARRAY_SIZE(i2s_src_parents), 0, SPEAR1340_I2S_CLK_CFG,
 			SPEAR1340_I2S_SRC_CLK_SHIFT, SPEAR1340_I2S_SRC_CLK_MASK,
 			0, &_lock);
-	clk_register_clkdev(clk, "i2s_src_clk", NULL);
+	clk_register_clkdev(clk, "i2s_src_mclk", NULL);
 
 	clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", 0,
 			SPEAR1340_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl,

@@ -720,7 +720,7 @@ void __init spear1340_clk_init(void)
 			ARRAY_SIZE(i2s_ref_parents), 0, SPEAR1340_I2S_CLK_CFG,
 			SPEAR1340_I2S_REF_SHIFT, SPEAR1340_I2S_REF_SEL_MASK, 0,
 			&_lock);
-	clk_register_clkdev(clk, "i2s_ref_clk", NULL);
+	clk_register_clkdev(clk, "i2s_ref_mclk", NULL);
 
 	clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0,
 			SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_I2S_REF_PAD_CLK_ENB,

@@ -846,30 +846,30 @@ void __init spear1340_clk_init(void)
 			ARRAY_SIZE(gen_synth0_1_parents), 0, SPEAR1340_PLL_CFG,
 			SPEAR1340_GEN_SYNT0_1_CLK_SHIFT,
 			SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock);
-	clk_register_clkdev(clk, "gen_syn0_1_clk", NULL);
+	clk_register_clkdev(clk, "gen_syn0_1_mclk", NULL);
 
 	clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents,
 			ARRAY_SIZE(gen_synth2_3_parents), 0, SPEAR1340_PLL_CFG,
 			SPEAR1340_GEN_SYNT2_3_CLK_SHIFT,
 			SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock);
-	clk_register_clkdev(clk, "gen_syn2_3_clk", NULL);
+	clk_register_clkdev(clk, "gen_syn2_3_mclk", NULL);
 
-	clk = clk_register_frac("gen_syn0_clk", "gen_syn0_1_clk", 0,
+	clk = clk_register_frac("gen_syn0_clk", "gen_syn0_1_mclk", 0,
 			SPEAR1340_GEN_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl),
 			&_lock);
 	clk_register_clkdev(clk, "gen_syn0_clk", NULL);
 
-	clk = clk_register_frac("gen_syn1_clk", "gen_syn0_1_clk", 0,
+	clk = clk_register_frac("gen_syn1_clk", "gen_syn0_1_mclk", 0,
 			SPEAR1340_GEN_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl),
 			&_lock);
 	clk_register_clkdev(clk, "gen_syn1_clk", NULL);
 
-	clk = clk_register_frac("gen_syn2_clk", "gen_syn2_3_clk", 0,
+	clk = clk_register_frac("gen_syn2_clk", "gen_syn2_3_mclk", 0,
 			SPEAR1340_GEN_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl),
 			&_lock);
 	clk_register_clkdev(clk, "gen_syn2_clk", NULL);
 
-	clk = clk_register_frac("gen_syn3_clk", "gen_syn2_3_clk", 0,
+	clk = clk_register_frac("gen_syn3_clk", "gen_syn2_3_mclk", 0,
 			SPEAR1340_GEN_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl),
 			&_lock);
 	clk_register_clkdev(clk, "gen_syn3_clk", NULL);
Signature · 1 line
1.7.12.rc2.18.g61b472e
author
#3 lore raw

PATCH 3/8 CLK: SPEAr13xx: fix parent names of multiple clocks

In reply to Viresh Kumar

From: Shiraz Hashim <[email protected]>

This patch fixes parent names of multiple clocks.

Signed-off-by Shiraz Hashim <[email protected]>
Signed-off-by Vipul Kumar Samar <[email protected]>
Signed-off-by Rajeev Kumar <[email protected]>
Signed-off-by Viresh Kumar <[email protected]>
---
 drivers/clk/spear/spear1310_clock.c | 2 +-
 drivers/clk/spear/spear1340_clock.c | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)
drivers/clk/spear/spear1310_clock.c +1 -1
index 2f1cb71..e84b1fb 100644
@@ -664,7 +664,7 @@ void __init spear1310_clk_init(void)
 	clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL);
 
 	clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gclk",
-			"i2s_ref_pad_clk", 0, SPEAR1310_I2S_CLK_CFG,
+			"i2s_ref_mclk", 0, SPEAR1310_I2S_CLK_CFG,
 			&i2s_sclk_masks, i2s_sclk_rtbl,
 			ARRAY_SIZE(i2s_sclk_rtbl), &_lock, &clk1);
 	clk_register_clkdev(clk, "i2s_sclk_clk", NULL);
drivers/clk/spear/spear1340_clock.c +3 -3
index 4733d99..020431a 100644
@@ -370,7 +370,7 @@ static struct frac_rate_tbl gen_rtbl[] = {
 /* clock parents */
 static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", };
 static const char *sys_parents[] = { "pll1_clk", "pll1_clk", "pll1_clk",
-	"pll1_clk", "sys_synth_clk", "sys_synth_clk", "pll2_clk", "pll3_clk", };
+	"pll1_clk", "sys_syn_clk", "sys_syn_clk", "pll2_clk", "pll3_clk", };
 static const char *ahb_parents[] = { "cpu_div3_clk", "amba_syn_clk", };
 static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", };
 static const char *uart0_parents[] = { "pll5_clk", "osc_24m_clk",

@@ -391,7 +391,7 @@ static const char *spdif_in_parents[] = { "pll2_clk", "gen_syn3_clk", };
 
 static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk",
 	"pll3_clk", };
-static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco3div2_clk",
+static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco2div2_clk",
 	"pll2_clk", };
 
 void __init spear1340_clk_init(void)

@@ -956,7 +956,7 @@ void __init spear1340_clk_init(void)
 			&_lock);
 	clk_register_clkdev(clk, NULL, "d0500000.cam3");
 
-	clk = clk_register_gate(NULL, "pwm_clk", "pwm_mclk", 0,
+	clk = clk_register_gate(NULL, "pwm_clk", "ahb_clk", 0,
 			SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PWM_CLK_ENB, 0,
 			&_lock);
 	clk_register_clkdev(clk, NULL, "e0180000.pwm");
Signature · 1 line
1.7.12.rc2.18.g61b472e
author
#4 lore raw

PATCH 4/8 CLK: SPEAr: Set CLK_SET_RATE_PARENT for few clocks

In reply to Viresh Kumar

From: Vipul Kumar Samar <[email protected]>

Flag CLK_SET_RATE_PARENT is required for a clock, where we want to propagate clk_set_rate to its parent. This patch adds this to multiple clocks.

Signed-off-by Vipul Kumar Samar <[email protected]>
Signed-off-by Shiraz Hashim <[email protected]>
Signed-off-by Rajeev Kumar <[email protected]>
Signed-off-by Vijay Kumar Mishra <[email protected]>
Signed-off-by Vijay Kumar Mishra <[email protected]>
Signed-off-by Viresh Kumar <[email protected]>
---
 drivers/clk/spear/clk-aux-synth.c   |   3 +-
 drivers/clk/spear/spear1310_clock.c |  49 +++++++--------
 drivers/clk/spear/spear1340_clock.c |  73 +++++++++++-----------
 drivers/clk/spear/spear3xx_clock.c  | 119 ++++++++++++++++++++----------------
 drivers/clk/spear/spear6xx_clock.c  |   3 +-
 5 files changed, 133 insertions(+), 114 deletions(-)
drivers/clk/spear/clk-aux-synth.c +2 -1
index 6756e7c..bdfb442 100644
@@ -179,7 +179,8 @@ struct clk *clk_register_aux(const char *aux_name, const char *gate_name,
 	if (gate_name) {
 		struct clk *tgate_clk;
 
-		tgate_clk = clk_register_gate(NULL, gate_name, aux_name, 0, reg,
+		tgate_clk = clk_register_gate(NULL, gate_name, aux_name,
+				CLK_SET_RATE_PARENT, reg,
 				aux->masks->enable_bit, 0, lock);
 		if (IS_ERR_OR_NULL(tgate_clk))
 			goto free_aux;
drivers/clk/spear/spear1310_clock.c +25 -24

99 lines not on this page · raw message

drivers/clk/spear/spear1340_clock.c +37 -36

146 lines not on this page · raw message

drivers/clk/spear/spear3xx_clock.c +67 -52

207 lines not on this page · raw message

drivers/clk/spear/spear6xx_clock.c +2 -1
index c7fa67c..e8d2b31 100644
@@ -156,7 +156,8 @@ void __init spear6xx_clk_init(void)
 	clk_register_clkdev(clk, NULL, "wdt");
 
 	/* clock derived from pll1 clk */
-	clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 0, 1, 1);
+	clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
+			CLK_SET_RATE_PARENT, 1, 1);
 	clk_register_clkdev(clk, "cpu_clk", NULL);
 
 	clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
Signature · 1 line
1.7.12.rc2.18.g61b472e
author
#5 lore raw

PATCH 5/8 CLK: SPEAr: Add missing clocks

In reply to Viresh Kumar

From: Vipul Kumar Samar <[email protected]>

This patch adds missing clocks: twd and macb.

Signed-off-by Vipul Kumar Samar <[email protected]>
Signed-off-by Deepak Sikri <[email protected]>
Signed-off-by Viresh Kumar <[email protected]>
---
 drivers/clk/spear/spear1310_clock.c | 4 ++++
 drivers/clk/spear/spear1340_clock.c | 4 ++++
 drivers/clk/spear/spear3xx_clock.c  | 8 ++++++++
 3 files changed, 16 insertions(+)
drivers/clk/spear/spear1310_clock.c +4 -0
index 2809b67..b64d511 100644
@@ -491,6 +491,10 @@ void __init spear1310_clk_init(void)
 			2);
 	clk_register_clkdev(clk, NULL, "ec800620.wdt");
 
+	clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1,
+			2);
+	clk_register_clkdev(clk, NULL, "smp_twd");
+
 	clk = clk_register_fixed_factor(NULL, "ahb_clk", "pll1_clk", 0, 1,
 			6);
 	clk_register_clkdev(clk, "ahb_clk", NULL);
drivers/clk/spear/spear1340_clock.c +4 -0
index aa5ed43..8f00533 100644
@@ -535,6 +535,10 @@ void __init spear1340_clk_init(void)
 			2);
 	clk_register_clkdev(clk, NULL, "ec800620.wdt");
 
+	clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1,
+			2);
+	clk_register_clkdev(clk, NULL, "smp_twd");
+
 	clk = clk_register_mux(NULL, "ahb_clk", ahb_parents,
 			ARRAY_SIZE(ahb_parents), 0, SPEAR1340_SYS_CLK_CTRL,
 			SPEAR1340_HCLK_SRC_SEL_SHIFT,
drivers/clk/spear/spear3xx_clock.c +8 -0
index de28152..1cc034b 100644
@@ -284,6 +284,14 @@ static void __init spear320_clk_init(void)
 			4);
 	clk_register_clkdev(clk, "i2s_sclk", NULL);
 
+	clk = clk_register_fixed_factor(NULL, "macb1_clk", "ras_apb_clk", 0, 1,
+			1);
+	clk_register_clkdev(clk, "hclk", "aa000000.eth");
+
+	clk = clk_register_fixed_factor(NULL, "macb2_clk", "ras_apb_clk", 0, 1,
+			1);
+	clk_register_clkdev(clk, "hclk", "ab000000.eth");
+
 	clk = clk_register_mux(NULL, "rs485_clk", uartx_parents,
 			ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
 			SPEAR320_EXT_CTRL_REG, SPEAR320_RS485_PCLK_SHIFT,
Signature · 1 line
1.7.12.rc2.18.g61b472e
author
#6 lore raw

PATCH 6/8 CLK: SPEAr: Update clock rate table

In reply to Viresh Kumar

From: Deepak Sikri <[email protected]>

This patch updates the existing rate tables with new frequencies.

Signed-off-by Deepak Sikri <[email protected]>
Signed-off-by Vipul Kumar Samar <[email protected]>
Signed-off-by Rajeev Kumar <[email protected]>
Signed-off-by Viresh Kumar <[email protected]>
---
 drivers/clk/spear/spear1310_clock.c | 14 ++++++
 drivers/clk/spear/spear1340_clock.c | 89 ++++++++++++++++++++++++++++---------
 drivers/clk/spear/spear3xx_clock.c  |  6 +++
 drivers/clk/spear/spear6xx_clock.c  |  1 +
 4 files changed, 89 insertions(+), 21 deletions(-)
drivers/clk/spear/spear1310_clock.c +14 -0
index b64d511..bc7f37e 100644
@@ -313,6 +313,20 @@ static struct aux_clk_masks i2s_sclk_masks = {
 /* i2s prs1 aux rate configuration table, in ascending order of rates */
 static struct aux_rate_tbl i2s_prs1_rtbl[] = {
 	/* For parent clk = 49.152 MHz */
+	{.xscale = 1, .yscale = 12, .eq = 0}, /* 2.048 MHz, smp freq = 8Khz */
+	{.xscale = 11, .yscale = 96, .eq = 0}, /* 2.816 MHz, smp freq = 11Khz */
+	{.xscale = 1, .yscale = 6, .eq = 0}, /* 4.096 MHz, smp freq = 16Khz */
+	{.xscale = 11, .yscale = 48, .eq = 0}, /* 5.632 MHz, smp freq = 22Khz */
+
+	/*
+	 * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz
+	 * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz
+	 */
+	{.xscale = 1, .yscale = 3, .eq = 0},
+
+	/* For parent clk = 49.152 MHz */
+	{.xscale = 17, .yscale = 37, .eq = 0}, /* 11.289 MHz, smp freq = 44Khz*/
+
 	{.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz */
 };
drivers/clk/spear/spear1340_clock.c +68 -21

144 lines not on this page · raw message

drivers/clk/spear/spear3xx_clock.c +6 -0
index 1cc034b..ea6543e 100644
@@ -107,6 +107,12 @@ static struct pll_rate_tbl pll_rtbl[] = {
 /* aux rate configuration table, in ascending order of rates */
 static struct aux_rate_tbl aux_rtbl[] = {
 	/* For PLL1 = 332 MHz */
+	{.xscale = 1, .yscale = 81, .eq = 0}, /* 2.049 MHz */
+	{.xscale = 1, .yscale = 59, .eq = 0}, /* 2.822 MHz */
+	{.xscale = 2, .yscale = 81, .eq = 0}, /* 4.098 MHz */
+	{.xscale = 3, .yscale = 89, .eq = 0}, /* 5.644 MHz */
+	{.xscale = 4, .yscale = 81, .eq = 0}, /* 8.197 MHz */
+	{.xscale = 4, .yscale = 59, .eq = 0}, /* 11.254 MHz */
 	{.xscale = 2, .yscale = 27, .eq = 0}, /* 12.296 MHz */
 	{.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */
 	{.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */
drivers/clk/spear/spear6xx_clock.c +1 -0
index e8d2b31..8a81770 100644
@@ -92,6 +92,7 @@ static struct pll_rate_tbl pll_rtbl[] = {
 /* aux rate configuration table, in ascending order of rates */
 static struct aux_rate_tbl aux_rtbl[] = {
 	/* For PLL1 = 332 MHz */
+	{.xscale = 2, .yscale = 27, .eq = 0}, /* 12.296 MHz */
 	{.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */
 	{.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */
 	{.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
Signature · 1 line
1.7.12.rc2.18.g61b472e
author
#7 lore raw

PATCH 7/8 CLK: SPEAr: Correct index scanning done for clock synths

In reply to Viresh Kumar

From: Deepak Sikri <[email protected]>

The patch corrects the case when the rate table is being scanned for a given frequency, and the search frequency is beyond the maximum frequency indexed in the table.

By default, the system should be set at max frequency present in the rate table. This patch correctly returns the corresponding index value.

Signed-off-by Deepak Sikri <[email protected]>
Signed-off-by Viresh Kumar <[email protected]>
---
 drivers/clk/spear/clk.c | 3 +++
 1 file changed, 3 insertions(+)
drivers/clk/spear/clk.c +3 -0
index 7cd6378..628b6d5 100644
@@ -32,5 +32,8 @@ long clk_round_rate_index(struct clk_hw *hw, unsigned long drate,
 		}
 	}
 
+	if ((*index) == rtbl_cnt)
+		(*index)--;
+
 	return rate;
 }
Signature · 1 line
1.7.12.rc2.18.g61b472e
author
#8 lore raw

PATCH 8/8 CLK: SPEAr: Remove unused dummy apb_pclk

In reply to Viresh Kumar

From: Vipul Kumar Samar <[email protected]>

Dummy clocks were added for ARM platforms, so that clk_get() for interface clk doesn't fail for amba devices from amba_probe(). Because there is no amba device for SPEAr that doesn't have a valid clock with dev_id for SPEAr, we don't need these dummy clocks. Hence, remove them.

Signed-off-by Vipul Kumar Samar <[email protected]>
Signed-off-by Viresh Kumar <[email protected]>
---
 drivers/clk/spear/spear1310_clock.c | 3 ---
 drivers/clk/spear/spear1340_clock.c | 3 ---
 drivers/clk/spear/spear3xx_clock.c  | 3 ---
 drivers/clk/spear/spear6xx_clock.c  | 3 ---
 4 files changed, 12 deletions(-)
drivers/clk/spear/spear1310_clock.c +0 -3
index bc7f37e..147e25f 100644
@@ -388,9 +388,6 @@ void __init spear1310_clk_init(void)
 {
 	struct clk *clk, *clk1;
 
-	clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
-	clk_register_clkdev(clk, "apb_pclk", NULL);
-
 	clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
 			32000);
 	clk_register_clkdev(clk, "osc_32k_clk", NULL);
drivers/clk/spear/spear1340_clock.c +0 -3
index d4de680..82abea3 100644
@@ -445,9 +445,6 @@ void __init spear1340_clk_init(void)
 {
 	struct clk *clk, *clk1;
 
-	clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
-	clk_register_clkdev(clk, "apb_pclk", NULL);
-
 	clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
 			32000);
 	clk_register_clkdev(clk, "osc_32k_clk", NULL);
drivers/clk/spear/spear3xx_clock.c +0 -3
index ea6543e..f39b023 100644
@@ -360,9 +360,6 @@ void __init spear3xx_clk_init(void)
 {
 	struct clk *clk, *clk1;
 
-	clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
-	clk_register_clkdev(clk, "apb_pclk", NULL);
-
 	clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
 			32000);
 	clk_register_clkdev(clk, "osc_32k_clk", NULL);
drivers/clk/spear/spear6xx_clock.c +0 -3
index 8a81770..e862a33 100644
@@ -119,9 +119,6 @@ void __init spear6xx_clk_init(void)
 {
 	struct clk *clk, *clk1;
 
-	clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
-	clk_register_clkdev(clk, "apb_pclk", NULL);
-
 	clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
 			32000);
 	clk_register_clkdev(clk, "osc_32k_clk", NULL);
Signature · 1 line
1.7.12.rc2.18.g61b472e
author
#9 lore raw

cover CLK: SPEAr: Fixes & updates

In reply to Viresh Kumar
Quoted 12 lines · Viresh Kumar

Hi Mike,

These are fixes for SPEAr clock stuff. Most of them are fixes, but we don't mind getting them in 3.8.

Deepak Sikri (2):
CLK: SPEAr1340: Update clock rate table
CLK: SPEAr: Correct index scanning done for clock synths

Rajeev Kumar (1):
CLK: SPEAr: Fix dev_id & con_id for multiple clocks

Quoted 8 lines

Shiraz Hashim (2):
CLK: SPEAr13xx: Fix mux clock names
CLK: SPEAr13xx: fix parent names of multiple clocks

Vipul Kumar Samar (3):
CLK: SPEAr: Set CLK_SET_RATE_PARENT for few clocks
CLK: SPEAr: Add missing clocks
CLK: SPEAr: Remove unused dummy apb_pclk

Ping!!

#10 lore raw

cover CLK: SPEAr: Fixes & updates

Quoting Viresh Kumar (2012-11-19 23:34:30)

Quoted 17 lines · Viresh Kumar
Quoted 16 lines

Hi Mike,

These are fixes for SPEAr clock stuff. Most of them are fixes, but we don't mind getting them in 3.8.

Deepak Sikri (2):
CLK: SPEAr1340: Update clock rate table
CLK: SPEAr: Correct index scanning done for clock synths

Rajeev Kumar (1):
CLK: SPEAr: Fix dev_id & con_id for multiple clocks

Shiraz Hashim (2):
CLK: SPEAr13xx: Fix mux clock names
CLK: SPEAr13xx: fix parent names of multiple clocks

Quoted 6 lines
Quoted 4 lines

Vipul Kumar Samar (3):
CLK: SPEAr: Set CLK_SET_RATE_PARENT for few clocks
CLK: SPEAr: Add missing clocks
CLK: SPEAr: Remove unused dummy apb_pclk

Ping!!

Thanks for the re-ping. I've taken this series into clk-next.

Regards,
Mike