New driver: i2c_imc (Intel LGA2011 iMC SMBUS)

Intel's LGA2011 chips (Core i7 Extreme and Xeon E5) have two SMBUS controllers per package, addressing up to 16 DIMM slots per package. This is a driver for those SMBUS channels.

The first patch is a minor change to the i2c core to make it work better with extremely limited hardware like this. The second patch is the driver.

Changes from the RFC / v1: Work around an erratum that gave random incorrect reads on multi-socket systems.

Andy Lutomirski (2):
i2c: Allow SPD probing with READ_BYTE_DATA and improve logging
i2c_imc: New driver for Intel's iMC, found on LGA2011 chips

 drivers/i2c/busses/Kconfig   |  14 ++
 drivers/i2c/busses/Makefile  |   1 +
 drivers/i2c/busses/i2c-imc.c | 546 +++++++++++++++++++++++++++++++++++++++++++
 drivers/i2c/i2c-core.c       |   7 +-
 4 files changed, 567 insertions(+), 1 deletion(-)
 create mode 100644 drivers/i2c/busses/i2c-imc.c

1.8.1.4

The Intel iMC SMBUS controller can't READ_BYTE. (This seems odd to me -- it supports WRITE_BYTE.) SPD EEPROMs are safe to probe with READ_BYTE_DATA, so fall back to that.

While I'm in here, also show the address that had no probing method for easier debugging.

---
 drivers/i2c/i2c-core.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

index 991d38d..ea88fc0 100644
@@ -1501,8 +1501,13 @@ static int i2c_default_probe(struct i2c_adapter *adap, unsigned short addr)
 	else if (i2c_check_functionality(adap, I2C_FUNC_SMBUS_READ_BYTE))
 		err = i2c_smbus_xfer(adap, addr, 0, I2C_SMBUS_READ, 0,
 				     I2C_SMBUS_BYTE, &dummy);
+	else if ((addr & ~0x0f) == 0x50
+	 && i2c_check_functionality(adap, I2C_FUNC_SMBUS_READ_BYTE_DATA))
+		err = i2c_smbus_xfer(adap, addr, 0, I2C_SMBUS_READ, 0,
+				     I2C_SMBUS_BYTE_DATA, &dummy);
 	else {
-		dev_warn(&adap->dev, "No suitable probing method supported\n");
+		dev_warn(&adap->dev, "No suitable probing method supported for address 0x%02X\n",
+			 addr);
 		err = -EOPNOTSUPP;
 	}
 

1.8.1.4

Sandy Bridge Xeon and Extreme chips have integrated memory controllers with (rather limited) onboard SMBUS masters. This driver gives access to the bus.

---
 drivers/i2c/busses/Kconfig   |  14 ++
 drivers/i2c/busses/Makefile  |   1 +
 drivers/i2c/busses/i2c-imc.c | 546 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 561 insertions(+)
 create mode 100644 drivers/i2c/busses/i2c-imc.c

index adfee98..91fd632 100644
@@ -133,6 +133,20 @@ config I2C_ISMT
 	  This driver can also be built as a module.  If so, the module will be
 	  called i2c-ismt.
 
+config I2C_IMC
+	tristate "Intel iMC (LGA 2011) SMBus Controller"
+	depends on PCI && X86
+	help
+	  If you say yes to this option, support will be included for the Intel
+	  Integrated Memory Controller SMBus host controller interface.  This
+	  controller is found on LGA 2011 Xeons and Core i7 Extremes.
+
+	  It is possibly, although unlikely, that the use of this driver will
+	  interfere with your platform's RAM thermal management.
+
+	  This driver can also be built as a module.  If so, the module will be
+	  called i2c-imc.
+
 config I2C_PIIX4
 	tristate "Intel PIIX4 and compatible (ATI/AMD/Serverworks/Broadcom/SMSC)"
 	depends on PCI

index 8f4fc23..de46683 100644
@@ -15,6 +15,7 @@ obj-$(CONFIG_I2C_AMD8111)	+= i2c-amd8111.o
 obj-$(CONFIG_I2C_I801)		+= i2c-i801.o
 obj-$(CONFIG_I2C_ISCH)		+= i2c-isch.o
 obj-$(CONFIG_I2C_ISMT)		+= i2c-ismt.o
+obj-$(CONFIG_I2C_IMC)		+= i2c-imc.o
 obj-$(CONFIG_I2C_NFORCE2)	+= i2c-nforce2.o
 obj-$(CONFIG_I2C_NFORCE2_S4985)	+= i2c-nforce2-s4985.o
 obj-$(CONFIG_I2C_PIIX4)		+= i2c-piix4.o

1.8.1.4

Please ignore this series. I have a replacement that's far better.

Andy Lutomirski
AMA Capital Management, LLC