PCI:Add SPEAr13xx PCie support
Subsystems (9)
v5 cover PCI:Add SPEAr13xx PCie support
From: Pratyush Anand <[email protected]>
First three patches are improvement and fixes for SPEAr13xx support. Patches 4-6 add miphy40lp skelten driver and support for spear1310/40 miphy wrapper. Patch 7 add support for SPEAr13xx PCIe.
These pathes are tested with linux-3.14-rc1 with following patch on the top of it:
Author: Balaji T K <[email protected]> Date: Mon Jan 20 16:41:27 2014 +0200
ata: ahci_platform: Manage SATA PHY
Tested with SPEAr1310 evaluation board:
- INTEL PRO 100/100 EP card
- USB xhci gen2 card
- Above cards connected through LeCROY PTC switch
Modifications for SATA are tested with SPEAr1340-evb board
Changes since v4:
- Uses per device function pointers passed from .data field to the of_device_id instead of of_device_is_compatible.
- Incorporated other minor comments from v4
Changes since v3:
- Phy driver renamed to phy-miphy40lp
- ahci phy hook patch used as suggested by Arnd
- Incorporated other minor comments from v3
Changes since v2:
- Incorporated comments to move SPEAr13xx PCIe and SATA phy specific routines to the phy framework
- Modify ahci driver to include phy hooks
- phy-core driver modifications for subsys_initcall()
Changes since v1:
- Few patches of the series are already accepted and applied to mainline e.g. pcie designware driver improvements,fixes for IO translation bug, PCIe dw driver maintainer. So dropped these from v2.
- Incorporated comment to move the common/reset PCIe code to the seperate driver
- PCIe and SATA share common PHY configuration registers, so move SATA platform code to the system config driver
Fourth patch is improves pcie designware driver and fixes the IO translation bug. IO translation bug fix leads to the working of PCIe EP devices connected to RC through switch.
PCIe driver support for SPEAr1310/40 platform board is added.
These patches are tested with SPEAr1310 evaluation board:
- INTEL PRO 100/100 EP card
- USB xhci gen2 card
- Above cards connected through LeCROY PTC switch
Mohit Kumar (2):
SPEAr13xx: defconfig: Update
MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer
Pratyush Anand (6):
clk: SPEAr13xx: Fix pcie clock name
SPEAr13xx: Fix static mapping table
phy: st-miphy-40lp: Add skeleton driver
SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
phy: st-miphy-40lp: Add SPEAr1310 and SPEAr1340 PCIe phy support
pcie: SPEAr13xx: Add designware pcie support
.../devicetree/bindings/arm/spear-misc.txt | 4 + .../devicetree/bindings/pci/spear13xx-pcie.txt | 7 + .../devicetree/bindings/phy/st-miphy40lp.txt | 12 + MAINTAINERS | 6 + arch/arm/boot/dts/spear1310-evb.dts | 4 + arch/arm/boot/dts/spear1310.dtsi | 96 +++- arch/arm/boot/dts/spear1340-evb.dts | 4 + arch/arm/boot/dts/spear1340.dtsi | 32 +- arch/arm/boot/dts/spear13xx.dtsi | 10 +- arch/arm/configs/spear13xx_defconfig | 15 + arch/arm/mach-spear/Kconfig | 3 + arch/arm/mach-spear/include/mach/spear.h | 4 +- arch/arm/mach-spear/spear1340.c | 127 +---- arch/arm/mach-spear/spear13xx.c | 2 +- drivers/clk/spear/spear1310_clock.c | 6 +- drivers/clk/spear/spear1340_clock.c | 2 +- drivers/pci/host/Kconfig | 5 + drivers/pci/host/Makefile | 1 + drivers/pci/host/pcie-spear13xx.c | 414 ++++++++++++++++ drivers/phy/Kconfig | 6 + drivers/phy/Makefile | 1 + drivers/phy/phy-miphy40lp.c | 538 +++++++++++++++++++++ 22 files changed, 1160 insertions(+), 139 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt create mode 100644 Documentation/devicetree/bindings/pci/spear13xx-pcie.txt create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt create mode 100644 drivers/pci/host/pcie-spear13xx.c create mode 100644 drivers/phy/phy-miphy40lp.c
Signature · 1 line
1.8.1.2
PATCH v5 1/8 clk: SPEAr13xx: Fix pcie clock name
From: Pratyush Anand <[email protected]>
Follow dt clock naming convention for PCIe clocks.
--- drivers/clk/spear/spear1310_clock.c | 6 +++--- drivers/clk/spear/spear1340_clock.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-)
drivers/clk/spear/spear1310_clock.c +3 -3
@@ -742,19 +742,19 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base) clk =clk_register_gate (NULL ,"pcie_sata_0_clk" ,"ahb_clk" ,0 ,SPEAR1310_PERIP1_CLK_ENB ,SPEAR1310_PCIE_SATA_0_CLK_ENB ,0 , &_lock); -clk_register_clkdev (clk,NULL ,"dw_pcie.0" ); +clk_register_clkdev (clk,NULL ,"b1000000.pcie" );clk_register_clkdev (clk,NULL ,"b1000000.ahci" ); clk =clk_register_gate (NULL ,"pcie_sata_1_clk" ,"ahb_clk" ,0 ,SPEAR1310_PERIP1_CLK_ENB ,SPEAR1310_PCIE_SATA_1_CLK_ENB ,0 , &_lock); -clk_register_clkdev (clk,NULL ,"dw_pcie.1" ); +clk_register_clkdev (clk,NULL ,"b1800000.pcie" );clk_register_clkdev (clk,NULL ,"b1800000.ahci" ); clk =clk_register_gate (NULL ,"pcie_sata_2_clk" ,"ahb_clk" ,0 ,SPEAR1310_PERIP1_CLK_ENB ,SPEAR1310_PCIE_SATA_2_CLK_ENB ,0 , &_lock); -clk_register_clkdev (clk,NULL ,"dw_pcie.2" ); +clk_register_clkdev (clk,NULL ,"b4000000.pcie" );clk_register_clkdev (clk,NULL ,"b4000000.ahci" ); clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
drivers/clk/spear/spear1340_clock.c +1 -1
@@ -839,7 +839,7 @@ void __init spear1340_clk_init(void __iomem *misc_base) clk =clk_register_gate (NULL ,"pcie_sata_clk" ,"ahb_clk" ,0 ,SPEAR1340_PERIP1_CLK_ENB ,SPEAR1340_PCIE_SATA_CLK_ENB ,0 , &_lock); -clk_register_clkdev (clk,NULL ,"dw_pcie" ); +clk_register_clkdev (clk,NULL ,"b1000000.pcie" );clk_register_clkdev (clk,NULL ,"b1000000.ahci" ); clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
Signature · 1 line
1.8.1.2
PATCH v5 2/8 SPEAr13xx: Fix static mapping table
In reply to Mohit KumarFrom: Pratyush Anand <[email protected]>
SPEAr13xx was using virtual address space 0xFE000000 to map physical address space 0xB3000000. pci_remap_io uses 0xFEE00000 as virtual address. So change 0xFE000000 to 0xF9000000.
--- arch/arm/mach-spear/include/mach/spear.h | 4 ++-- arch/arm/mach-spear/spear13xx.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-)
arch/arm/mach-spear/include/mach/spear.h +2 -2
@@ -52,10 +52,10 @@#ifdef CONFIG_ARCH_SPEAR13XX #define PERIP_GRP2_BASE UL(0xB3000000) -#define VA_PERIP_GRP2_BASE IOMEM(0xFE000000) +#define VA_PERIP_GRP2_BASE IOMEM(0xF9000000)#define MCIF_SDHCI_BASE UL(0xB3000000)#define SYSRAM0_BASE UL(0xB3800000) -#define VA_SYSRAM0_BASE IOMEM(0xFE800000) +#define VA_SYSRAM0_BASE IOMEM(0xF9800000)#define SYS_LOCATION (VA_SYSRAM0_BASE + 0x600)#define PERIP_GRP1_BASE UL(0xE0000000)
arch/arm/mach-spear/spear13xx.c +1 -1
@@ -52,7 +52,7 @@ void __init spear13xx_l2x0_init(void)/* * Following will create 16MB static virtual/physical mappings * PHYSICAL VIRTUAL -* 0xB3000000 0xFE000000 +* 0xB3000000 0xF9000000 * 0xE0000000 0xFD000000 * 0xEC000000 0xFC000000 * 0xED000000 0xFB000000
Signature · 1 line
1.8.1.2
PATCH v5 3/8 SPEAr13xx: defconfig: Update
In reply to Mohit KumarEnable EABI, VFP and NFS configs in default configuration file for SPEAr13xx.
--- arch/arm/configs/spear13xx_defconfig | 13 +++++++++++++ 1 file changed, 13 insertions(+)
arch/arm/configs/spear13xx_defconfig +13 -0
@@ -14,10 +14,18 @@ CONFIG_MACH_SPEAR1340=y CONFIG_SMP=y # CONFIG_SMP_ON_UP is not set # CONFIG_ARM_CPU_TOPOLOGY is not set +CONFIG_AEABI=y CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_ATAG_DTB_COMPAT=y +CONFIG_VFP=y CONFIG_BINFMT_MISC=y CONFIG_NET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_NET_IPIP=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_MTD=y CONFIG_MTD_OF_PARTS=y
@@ -27,6 +35,7 @@ CONFIG_MTD_NAND=y CONFIG_MTD_NAND_FSMC=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=16384 +CONFIG_BLK_DEV_SD=y CONFIG_ATA=y # CONFIG_SATA_PMP is not set CONFIG_SATA_AHCI_PLATFORM=y
@@ -66,6 +75,7 @@ CONFIG_USB=y # CONFIG_USB_DEVICE_CLASS is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y +CONFIG_USB_STORAGE=y CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SPEAR=y
@@ -79,11 +89,14 @@ CONFIG_EXT2_FS_SECURITY=y CONFIG_EXT3_FS=y CONFIG_EXT3_FS_SECURITY=y CONFIG_AUTOFS4_FS=m +CONFIG_FUSE_FS=y CONFIG_MSDOS_FS=m CONFIG_VFAT_FS=m CONFIG_FAT_DEFAULT_IOCHARSET="ascii" CONFIG_TMPFS=y CONFIG_JFFS2_FS=y +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y CONFIG_NLS_DEFAULT="utf8" CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=m
Signature · 1 line
1.8.1.2
PATCH v5 4/8 phy: st-miphy-40lp: Add skeleton driver
In reply to Mohit KumarFrom: Pratyush Anand <[email protected]>
ST miphy-40lp supports PCIe, SATA and Super Speed USB. This driver adds skeleton support for the same.
This skeleton defines function corresponding to phy ops as well as sleep pm ops. Any platform using this phy can add its own platform specific ops(if needed) corresponding to each phy ops.
Phy specific modifications will require phy register space, which is passed from DT as a resource. Currently only SPEAr1310 and SPEAr1340 are known user of this phy, which do not need to modify phy registers normally. Therefore we have not retrieved phy base address from DT and hence not io-remapped it. However, same can be added in future if required.
SoC specific modifications should be done in plat specific ops and phy specific modifications should be done in phy ops itself. As a general rule, follow the convention of modifying misc reg space in plat ops and phy reg space in phy ops.
--- .../devicetree/bindings/phy/st-miphy40lp.txt | 12 ++ drivers/phy/Kconfig | 6 + drivers/phy/Makefile | 1 + drivers/phy/phy-miphy40lp.c | 229 +++++++++++++++++++++ 4 files changed, 248 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/st-miphy40lp.txt create mode 100644 drivers/phy/phy-miphy40lp.c
Documentation/devicetree/bindings/phy/st-miphy40lp.txt new file +12 -0
@@ -0,0 +1,12 @@ +Required properties: +- compatible : should be "st,miphy40lp-phy" + Other supported soc specific compatible: + "st,spear1310-miphy" + "st,spear1340-miphy" +- reg : offset and length of the PHY register set. +- misc: phandle for the syscon node to access misc registers +- phy-id: Instance id of the phy. +- #phy-cells : from the generic PHY bindings, must be 1. + - 1st cell: phandle to the phy node. + - 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe + and 2 for Super Speed USB.
drivers/phy/Kconfig +6 -0
@@ -64,4 +64,10 @@ config BCM_KONA_USB2_PHY help Enable this to support the Broadcom Kona USB 2.0 PHY. +config PHY_ST_MIPHY40LP + tristate "ST MIPHY 40LP driver" + help + Support for ST MIPHY 40LP which can be used for PCIe, SATA and Super Speed USB. + select GENERIC_PHY + endmenu
drivers/phy/Makefile +1 -0
@@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o +obj-$(CONFIG_PHY_ST_MIPHY40LP) += phy-miphy40lp.o
drivers/phy/phy-miphy40lp.c new file +229 -0
229 lines not on this page · raw message
Signature · 1 line
1.8.1.2
Re: [PATCH V5 4/8] phy: st-miphy-40lp: Add skeleton driver
Quoted 8 lines · Mohit Kumar
Documentation/devicetree/bindings/phy/st-miphy40lp.txt new file +2
-0@@ -0,0 +1,12 @@ +Required properties: +- compatible : should be "st,miphy40lp-phy"
Documentation/devicetree/bindings/phy/st-miphy40lp.txt line 12
Quoted 10 lines
Documentation/devicetree/bindings/phy/st-miphy40lp.txt new file +10
-0+ Other supported soc specific compatible: + "st,spear1310-miphy" + "st,spear1340-miphy" +- reg : offset and length of the PHY register set. +- misc: phandle for the syscon node to access misc registers +- phy-id: Instance id of the phy. +- #phy-cells : from the generic PHY bindings, must be 1. + - 1st cell: phandle to the phy node. + - 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe + and 2 for Super Speed USB.
It's common to start this file with a small header explaining what this hardware is.
Quoted 5 lines
drivers/phy/Kconfig +0
-0
drivers/phy/Kconfig config BCM_KONA_USB2_PHY · line 73
Quoted 10 lines
drivers/phy/Kconfig +6
-0@@ -64,4 +64,10 @@ config BCM_KONA_USB2_PHY help Enable this to support the Broadcom Kona USB 2.0 PHY. +config PHY_ST_MIPHY40LP + tristate "ST MIPHY 40LP driver" + help + Support for ST MIPHY 40LP which can be used for PCIe, SATA and Super Speed USB. + select GENERIC_PHY + endmenu
The 'select' statement should come before 'help', for consistency with the rest of the kernel. Maybe mention that this phy is used inside the spear13xx SoC here rather than a standalone phy.
drivers/phy/Kconfig
Quoted 7 lines
drivers/phy/Kconfig +7
-0+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) { + dev_err(dev, "can't alloc miphy40lp private date memory\n"); + return -ENOMEM; + } + + priv->plat_ops = (struct miphy40lp_plat_ops *)of_id->data;
The cast would incorrectly remove the 'const' attribute of the pointer. Better remove the cast and make priv->plat_ops const.
drivers/phy/Kconfig
Quoted 7 lines
drivers/phy/Kconfig +7
-0+static int __init miphy40lp_phy_init(void) +{ + + return platform_driver_probe(&miphy40lp_driver, + miphy40lp_probe); +} +module_init(miphy40lp_phy_init);
There should certainly be a module_exit() function here so you can unload the driver.
Arnd
RE: [PATCH V5 4/8] phy: st-miphy-40lp: Add skeleton driver
Hello Arnd,
Quoted 24 lines
-----Original Message-----
From: Arnd Bergmann [mailto:arnd at arndb.de]
Sent: Monday, February 10, 2014 9:24 PM
To: Mohit KUMAR DCG
Cc: Pratyush ANAND; Kishon Vijay Abraham I; spear-devel; linux-arm- kernel at lists.infradead.org; devicetree at vger.kernel.org; linux- kernel at vger.kernel.org
Subject: Re: [PATCH V5 4/8] phy: st-miphy-40lp: Add skeleton driverQuoted 14 lines · Mohit Kumar
Documentation/devicetree/bindings/phy/st-miphy40lp.txt new file +7
-0@@ -0,0 +1,12 @@ +Required properties: +- compatible : should be "st,miphy40lp-phy" + Other supported soc specific compatible: + "st,spear1310-miphy" + "st,spear1340-miphy" +- reg : offset and length of the PHY register set. +- misc: phandle for the syscon node to access misc registers
Quoted 8 lines
Documentation/devicetree/bindings/phy/st-miphy40lp.txt line 12
Quoted 5 lines
Documentation/devicetree/bindings/phy/st-miphy40lp.txt new file +5
-0+- phy-id: Instance id of the phy. +- #phy-cells : from the generic PHY bindings, must be 1. + - 1st cell: phandle to the phy node. + - 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe + and 2 for Super Speed USB.It's common to start this file with a small header explaining what this hardware is.
- OK
Quoted 14 lines
drivers/phy/Kconfig config BCM_KONA_USB2_PHY · line 70
Quoted 13 lines
drivers/phy/Kconfig index renamed from drivers/phy/Kconfig +0
-0afa2354..2f58993 100644
drivers/phy/Kconfig +4
-0@@ -64,4 +64,10 @@ config BCM_KONA_USB2_PHY help Enable this to support the Broadcom Kona USB 2.0 PHY. +config PHY_ST_MIPHY40LP + tristate "ST MIPHY 40LP driver" + help + Support for ST MIPHY 40LP which can be used for PCIe, SATA andSuper Speed USB.
Quoted 6 lines
drivers/phy/Kconfig config BCM_KONA_USB2_PHY · line 73
Quoted 3 lines
drivers/phy/Kconfig +2
-0+ select GENERIC_PHY + endmenuThe 'select' statement should come before 'help', for consistency with the rest of the kernel.
- OK
Quoted 2 lines
Maybe mention that this phy is used inside the spear13xx SoC here rather than a standalone phy.
- Yes, for spear13xx its used internally. Do you think that it requires to be mentioned here? We have few prototype boards that uses this as external phy.
Quoted 11 lines
drivers/phy/Kconfig
Quoted 3 lines
drivers/phy/Kconfig +3
-0+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) { + dev_err(dev, "can't alloc miphy40lp private datememory\n");
drivers/phy/Kconfig
Quoted 4 lines
drivers/phy/Kconfig +4
-0+ return -ENOMEM; + } + + priv->plat_ops = (struct miphy40lp_plat_ops *)of_id->data;The cast would incorrectly remove the 'const' attribute of the pointer. Better remove the cast and make
priv->plat_opsconst.
- OK
Quoted 10 lines
drivers/phy/Kconfig
Quoted 7 lines
drivers/phy/Kconfig +6
-0+static int __init miphy40lp_phy_init(void) { + + return platform_driver_probe(&miphy40lp_driver, + miphy40lp_probe); +} +module_init(miphy40lp_phy_init);There should certainly be a
module_exit()function here so you can unload the driver.
- yes, will add it in v6.
Thanks
Mohit
Quoted 2 lines
Arnd
Re: [PATCH V5 4/8] phy: st-miphy-40lp: Add skeleton driver
Quoted 7 lines · On Tuesday 11 February 2014 11:57:46 Mohit KUMAR DCG wrote:
Quoted 3 lines
Maybe mention that this phy is used inside the spear13xx SoC here rather than a standalone phy.
- Yes, for spear13xx its used internally. Do you think that it requires to be mentioned here?
We have few prototype boards that uses this as external phy.
[adding Lee since he mentioned working on a similar part]
I'm a bit confused. Is it actually the same IP block that can be used internally as part of a SoC and as a standalone chip?
Since some of the settings of the PHY are controlled through the misc register in case of spear13xx, I assume that part is different on the standalone version. How do you actually select the mode in that case?
It would certainly be helpful to explain this somewhere, and the binding might not be the worst place for this.
On a related note, the driver in its current shape looks a bit silly since it doesn't contain any of the miphy specific code but only the SoC specific parts (as I suggested you do, so I'm not blaming you :-)) and a multiplexer that switches between the two possible implementations.
What is your plan for the future, do you intend to add the actual miphy code soon, or is that something you just want to leave as an option for the future but have no specific plans to do right now? If not, the driver would probably look nicer if it were split into two separate implementations, one for each spear13xx SoC and with a separate set of phy_ops but no multiplexer. The connection to the miphy code (if you want to keep your options open) could be done by implementing some kind of nested phy model where the st,spear1340-phy contains another "phys" property pointing to the st,miphy40 node and the driver just calls the slave phy_ops recursively, or the sata and pcie nodes actually link to two phy nodes that are separate from one another.
Arnd
RE: [PATCH V5 4/8] phy: st-miphy-40lp: Add skeleton driver
Hello Arnd,
Quoted 27 lines
-----Original Message-----
From: Arnd Bergmann [mailto:arnd at arndb.de]
Sent: Tuesday, February 11, 2014 8:09 PM
To: Mohit KUMAR DCG
Cc: Pratyush ANAND; Kishon Vijay Abraham I; spear-devel; linux-arm- kernel at lists.infradead.org; devicetree at vger.kernel.org; linux- kernel at vger.kernel.org; Lee Jones
Subject: Re: [PATCH V5 4/8] phy: st-miphy-40lp: Add skeleton driverQuoted 7 lines · On Tuesday 11 February 2014 11:57:46 Mohit KUMAR DCG wrote:
Quoted 3 lines
Maybe mention that this phy is used inside the spear13xx SoC here rather than a standalone phy.
- Yes, for spear13xx its used internally. Do you think that it requires to be mentioned here?
We have few prototype boards that uses this as external phy.[adding Lee since he mentioned working on a similar part]
I'm a bit confused. Is it actually the same IP block that can be used internally as part of a SoC and as a standalone chip?
Since some of the settings of the PHY are controlled through the misc register in case of spear13xx, I assume that part is different on the standalone version. How do you actually select the mode in that case?
Quoted 7 lines
It would certainly be helpful to explain this somewhere, and the binding might not be the worst place for this.
On a related note, the driver in its current shape looks a bit silly since it doesn't contain any of the miphy specific code but only the SoC specific parts (as I suggested you do, so I'm not blaming you :-)) and a multiplexer that switches between the two possible implementations.
- yes, thats what we were explaining earlier. If it is integrated into some SoC Then there are some soc specific configurations. Actual phy reg settings could also vary for the different SoCs for the best tuning.
However we agreed to your idea as miphy40lp register definitions would remain same across the SoCs.
Quoted 6 lines
What is your plan for the future, do you intend to add the actual miphy code soon, or is that something you just want to leave as an option for the future but have no specific plans to do right now? If not, the driver would probably look nicer if it were split into two separate implementations, one for each spear13xx SoC and with a separate set of
phy_opsbut no multiplexer.
Do you want it to split the code into two different files like phy-miphyspear1310.c and phy-miphyspear1340.c ?
Regards
Mohit
RE: [PATCH V5 4/8] phy: st-miphy-40lp: Add skeleton driver
Hello Arnd,
Quoted 60 lines
-----Original Message-----
From: Mohit KUMAR [mailto:mohit.kumar at st.com]
Sent: Wednesday, February 12, 2014 10:22 AM
To: Arnd Bergmann
Cc: Pratyush ANAND; Kishon Vijay Abraham I; spear-devel; linux-arm- kernel at lists.infradead.org; devicetree at vger.kernel.org; linux- kernel at vger.kernel.org; Lee Jones
Subject: RE: [PATCH V5 4/8] phy: st-miphy-40lp: Add skeleton driverHello Arnd,
Quoted 27 lines
-----Original Message-----
From: Arnd Bergmann [mailto:arnd at arndb.de]
Sent: Tuesday, February 11, 2014 8:09 PM
To: Mohit KUMAR DCG
Cc: Pratyush ANAND; Kishon Vijay Abraham I; spear-devel; linux-arm- kernel at lists.infradead.org; devicetree at vger.kernel.org; linux- kernel at vger.kernel.org; Lee Jones
Subject: Re: [PATCH V5 4/8] phy: st-miphy-40lp: Add skeleton driverQuoted 7 lines · On Tuesday 11 February 2014 11:57:46 Mohit KUMAR DCG wrote:
Quoted 3 lines
Maybe mention that this phy is used inside the spear13xx SoC here rather than a standalone phy.
- Yes, for spear13xx its used internally. Do you think that it requires to be mentioned here?
We have few prototype boards that uses this as external phy.[adding Lee since he mentioned working on a similar part]
I'm a bit confused. Is it actually the same IP block that can be used internally as part of a SoC and as a standalone chip?
Since some of the settings of the PHY are controlled through the misc register in case of spear13xx, I assume that part is different on the standalone version. How do you actually select the mode in that case?
Quoted 7 lines
It would certainly be helpful to explain this somewhere, and the binding might not be the worst place for this.
On a related note, the driver in its current shape looks a bit silly since it doesn't contain any of the miphy specific code but only the SoC specific parts (as I suggested you do, so I'm not blaming you :-)) and a multiplexer that switches between the two possible
implementations.
- yes, thats what we were explaining earlier. If it is integrated into some SoC Then there are some soc specific configurations. Actual phy reg settings could also vary for the different SoCs for the best tuning.
However we agreed to your idea as miphy40lp register definitions would remain same across the SoCs.
Quoted 6 lines
What is your plan for the future, do you intend to add the actual miphy code soon, or is that something you just want to leave as an option for the future but have no specific plans to do right now? If not, the driver would probably look nicer if it were split into two separate implementations, one for each spear13xx SoC and with a separate
Quoted 4 lines
set of
phy_opsbut no multiplexer.Do you want it to split the code into two different files like phy-
miphyspear1310.candphy-miphyspear1340.c?
- Waiting for your final say about splitting into two different files or any other comment for the patch series?
Thanks
Mohit
PATCH v5 5/8 SPEAr13xx: Fixup: Move SPEAr1340 SATA platform code to phy driver
In reply to Mohit KumarFrom: Pratyush Anand <[email protected]>
ahci driver needs some platform specific functions which are called at init, exit, suspend and resume conditions. Till now these functions were present in a platform driver with a fixme notes.
Similar functions modifying same set of registers will also be needed in case of PCIe phy init/exit.
So move all these SATA platform code to phy-miphy40lp driver.
--- .../devicetree/bindings/arm/spear-misc.txt | 4 + arch/arm/boot/dts/spear1310-evb.dts | 4 + arch/arm/boot/dts/spear1310.dtsi | 39 +++++- arch/arm/boot/dts/spear1340-evb.dts | 4 + arch/arm/boot/dts/spear1340.dtsi | 13 +- arch/arm/boot/dts/spear13xx.dtsi | 5 + arch/arm/mach-spear/Kconfig | 2 + arch/arm/mach-spear/spear1340.c | 127 +----------------- drivers/phy/phy-miphy40lp.c | 144 +++++++++++++++++++++ 9 files changed, 212 insertions(+), 130 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/spear-misc.txt
Documentation/devicetree/bindings/arm/spear-misc.txt new file +4 -0
@@ -0,0 +1,4 @@ +* SPEAr Misc configuration +** misc node required properties: +- compatible Should be "st,spear1340-misc", "syscon". +- reg: Address range of misc space
arch/arm/boot/dts/spear1310-evb.dts +4 -0
@@ -106,6 +106,10 @@ status = "okay"; }; + miphy at eb800000 { + status = "okay"; + }; + cf at b2800000 { status = "okay"; };
arch/arm/boot/dts/spear1310.dtsi +36 -3
@@ -29,24 +29,57 @@ #gpio-cells = <2>; }; - ahci at b1000000 { + miphy0: miphy at eb800000 { + compatible = "st,miphy", "st,spear1310-miphy"; + reg = <0xeb800000 0x4000>; + misc = <&misc>; + phy-id = <0>; + #phy-cells = <1>; + status = "disabled"; + }; + + miphy1: miphy at eb804000 { + compatible = "st,miphy", "st,spear1310-miphy"; + reg = <0xeb804000 0x4000>; + misc = <&misc>; + phy-id = <1>; + #phy-cells = <1>; + status = "disabled"; + }; + + miphy2: miphy at eb808000 { + compatible = "st,miphy", "st,spear1310-miphy"; + reg = <0xeb808000 0x4000>; + misc = <&misc>; + phy-id = <2>; + #phy-cells = <1>; + status = "disabled"; + }; + + ahci0: ahci at b1000000 { compatible = "snps,spear-ahci"; reg = <0xb1000000 0x10000>; interrupts = <0 68 0x4>; + phys = <&miphy0 0>; + phy-names = "sata-phy"; status = "disabled"; }; - ahci at b1800000 { + ahci1: ahci at b1800000 { compatible = "snps,spear-ahci"; reg = <0xb1800000 0x10000>; interrupts = <0 69 0x4>; + phys = <&miphy1 0>; + phy-names = "sata-phy"; status = "disabled"; }; - ahci at b4000000 { + ahci2: ahci at b4000000 { compatible = "snps,spear-ahci"; reg = <0xb4000000 0x10000>; interrupts = <0 70 0x4>; + phys = <&miphy2 0>; + phy-names = "sata-phy"; status = "disabled"; };
arch/arm/boot/dts/spear1340-evb.dts +4 -0
@@ -122,6 +122,10 @@ status = "okay"; }; + miphy at eb800000 { + status = "okay"; + }; + dma at ea800000 { status = "okay"; };
arch/arm/boot/dts/spear1340.dtsi +12 -1
@@ -31,10 +31,21 @@ status = "disabled"; }; - ahci at b1000000 { + miphy0: miphy at eb800000 { + compatible = "st,miphy", "st,spear1340-miphy"; + reg = <0xeb800000 0x4000>; + misc = <&misc>; + phy-id = <0>; + #phy-cells = <1>; + status = "disabled"; + }; + + ahci0: ahci at b1000000 { compatible = "snps,spear-ahci"; reg = <0xb1000000 0x10000>; interrupts = <0 72 0x4>; + phys = <&miphy0 0>; + phy-names = "sata-phy"; status = "disabled"; };
arch/arm/boot/dts/spear13xx.dtsi +5 -0
@@ -220,6 +220,11 @@ 0xd8000000 0xd8000000 0x01000000 0xe0000000 0xe0000000 0x10000000>; + misc: syscon at e0700000 { + compatible = "st,spear1340-misc", "syscon"; + reg = <0xe0700000 0x1000>; + }; + gpio0: gpio at e0600000 { compatible = "arm,pl061", "arm,primecell"; reg = <0xe0600000 0x1000>;
arch/arm/mach-spear/Kconfig +2 -0
@@ -26,6 +26,8 @@ config ARCH_SPEAR13XX select MIGHT_HAVE_CACHE_L2X0 select PINCTRL select USE_OF + select MFD_SYSCON + select PHY_ST_MIPHY40LP help Supports for ARM's SPEAR13XX family
arch/arm/mach-spear/spear1340.c +1 -126
139 lines not on this page · raw message
drivers/phy/phy-miphy40lp.c +144 -0
170 lines not on this page · raw message
Signature · 1 line
1.8.1.2
PATCH v5 6/8 phy: st-miphy-40lp: Add SPEAr1310 and SPEAr1340 PCIe phy support
In reply to Mohit KumarFrom: Pratyush Anand <[email protected]>
SPEAr1310 and SPEAr1340 uses miphy40lp phy for PCIe. This driver adds support for the same.
--- drivers/phy/phy-miphy40lp.c | 165 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 165 insertions(+)
drivers/phy/phy-miphy40lp.c +165 -0
@@ -9,6 +9,7 @@* published by the Free Software Foundation. * * 04/02/2014: Adding support of SATA mode for SPEAr1340. +* 04/02/2014: Adding support of PCIe mode for SPEAr1340 and SPEAr1310 */ #include <linux/bitops.h>
@@ -74,6 +75,80 @@#define SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE \ (SPEAR1340_MIPHY_OSC_BYPASS_EXT | \ SPEAR1340_MIPHY_PLL_RATIO_TOP(25)) +/* SPEAr1310 Registers */ +#define SPEAR1310_PCIE_SATA_CFG 0x3A4 +#define SPEAR1310_PCIE_SATA2_SEL_PCIE (0 << 31) +#define SPEAR1310_PCIE_SATA1_SEL_PCIE (0 << 30) +#define SPEAR1310_PCIE_SATA0_SEL_PCIE (0 << 29) +#define SPEAR1310_PCIE_SATA2_SEL_SATA BIT(31) +#define SPEAR1310_PCIE_SATA1_SEL_SATA BIT(30) +#define SPEAR1310_PCIE_SATA0_SEL_SATA BIT(29) +#define SPEAR1310_SATA2_CFG_TX_CLK_EN BIT(27) +#define SPEAR1310_SATA2_CFG_RX_CLK_EN BIT(26) +#define SPEAR1310_SATA2_CFG_POWERUP_RESET BIT(25) +#define SPEAR1310_SATA2_CFG_PM_CLK_EN BIT(24) +#define SPEAR1310_SATA1_CFG_TX_CLK_EN BIT(23) +#define SPEAR1310_SATA1_CFG_RX_CLK_EN BIT(22) +#define SPEAR1310_SATA1_CFG_POWERUP_RESET BIT(21) +#define SPEAR1310_SATA1_CFG_PM_CLK_EN BIT(20) +#define SPEAR1310_SATA0_CFG_TX_CLK_EN BIT(19) +#define SPEAR1310_SATA0_CFG_RX_CLK_EN BIT(18) +#define SPEAR1310_SATA0_CFG_POWERUP_RESET BIT(17) +#define SPEAR1310_SATA0_CFG_PM_CLK_EN BIT(16) +#define SPEAR1310_PCIE2_CFG_DEVICE_PRESENT BIT(11) +#define SPEAR1310_PCIE2_CFG_POWERUP_RESET BIT(10) +#define SPEAR1310_PCIE2_CFG_CORE_CLK_EN BIT(9) +#define SPEAR1310_PCIE2_CFG_AUX_CLK_EN BIT(8) +#define SPEAR1310_PCIE1_CFG_DEVICE_PRESENT BIT(7) +#define SPEAR1310_PCIE1_CFG_POWERUP_RESET BIT(6) +#define SPEAR1310_PCIE1_CFG_CORE_CLK_EN BIT(5) +#define SPEAR1310_PCIE1_CFG_AUX_CLK_EN BIT(4) +#define SPEAR1310_PCIE0_CFG_DEVICE_PRESENT BIT(3) +#define SPEAR1310_PCIE0_CFG_POWERUP_RESET BIT(2) +#define SPEAR1310_PCIE0_CFG_CORE_CLK_EN BIT(1) +#define SPEAR1310_PCIE0_CFG_AUX_CLK_EN BIT(0) + +#define SPEAR1310_PCIE_CFG_MASK (x) ((0xF << (x * 4)) | BIT((x + 29))) +#define SPEAR1310_SATA_CFG_MASK (x) ((0xF << (x * 4 + 16)) | \ + BIT((x + 29))) +#define SPEAR1310_PCIE_CFG_VAL (x) \ + (SPEAR1310_PCIE_SATA##x##_SEL_PCIE | \ + SPEAR1310_PCIE##x##_CFG_AUX_CLK_EN | \ + SPEAR1310_PCIE##x##_CFG_CORE_CLK_EN | \ + SPEAR1310_PCIE##x##_CFG_POWERUP_RESET | \ + SPEAR1310_PCIE##x##_CFG_DEVICE_PRESENT) +#define SPEAR1310_SATA_CFG_VAL (x) \ + (SPEAR1310_PCIE_SATA##x##_SEL_SATA | \ + SPEAR1310_SATA##x##_CFG_PM_CLK_EN | \ + SPEAR1310_SATA##x##_CFG_POWERUP_RESET | \ + SPEAR1310_SATA##x##_CFG_RX_CLK_EN | \ + SPEAR1310_SATA##x##_CFG_TX_CLK_EN) + +#define SPEAR1310_PCIE_MIPHY_CFG_1 0x3A8 +#define SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT BIT(31) +#define SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2 BIT(28) +#define SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP (x) (x << 16) +#define SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT BIT(15) +#define SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 BIT(12) +#define SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP (x) (x << 0) +#define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_MASK (0xFFFF) +#define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK (0xFFFF << 16) +#define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA \ + (SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \ + SPEAR1310_MIPHY_DUAL_CLK_REF_DIV2 | \ + SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(60) | \ + SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \ + SPEAR1310_MIPHY_SINGLE_CLK_REF_DIV2 | \ + SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(60)) +#define SPEAR1310_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK \ + (SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(120)) +#define SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE \ + (SPEAR1310_MIPHY_DUAL_OSC_BYPASS_EXT | \ + SPEAR1310_MIPHY_DUAL_PLL_RATIO_TOP(25) | \ + SPEAR1310_MIPHY_SINGLE_OSC_BYPASS_EXT | \ + SPEAR1310_MIPHY_SINGLE_PLL_RATIO_TOP(25)) + +#define SPEAR1310_PCIE_MIPHY_CFG_2 0x3ACenum phy_mode {SATA ,
@@ -146,12 +221,35 @@ static int miphy40lp_spear1340_sata_exit(struct miphy40lp_priv *priv)return 0 ; } +static int miphy40lp_spear1340_pcie_init (struct miphy40lp_priv *priv) +{ +regmap_update_bits (priv->misc,SPEAR1340_PCIE_MIPHY_CFG , +SPEAR1340_PCIE_MIPHY_CFG_MASK , +SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE ); +regmap_update_bits (priv->misc,SPEAR1340_PCIE_SATA_CFG , +SPEAR1340_PCIE_SATA_CFG_MASK ,SPEAR1340_PCIE_CFG_VAL ); + +return 0 ; +} + +static int miphy40lp_spear1340_pcie_exit (struct miphy40lp_priv *priv) +{ +regmap_update_bits (priv->misc,SPEAR1340_PCIE_MIPHY_CFG , +SPEAR1340_PCIE_MIPHY_CFG_MASK ,0 ); +regmap_update_bits (priv->misc,SPEAR1340_PCIE_SATA_CFG , +SPEAR1340_PCIE_SATA_CFG_MASK ,0 ); + +return 0 ; +} +static int miphy40lp_spear1340_init (struct miphy40lp_priv *priv) {int ret =0 ;if (priv->mode ==SATA ) ret =miphy40lp_spear1340_sata_init (priv); +else if (priv->mode ==PCIE ) + ret =miphy40lp_spear1340_pcie_init (priv);return ret; }
@@ -162,6 +260,8 @@ static int miphy40lp_spear1340_exit(struct miphy40lp_priv *priv)if (priv->mode ==SATA ) ret =miphy40lp_spear1340_sata_exit (priv); +else if (priv->mode ==PCIE ) + ret =miphy40lp_spear1340_pcie_exit (priv);return ret; }
@@ -193,6 +293,70 @@ static struct miphy40lp_plat_ops spear1340_phy_ops = { .plat_resume = miphy40lp_spear1340_resume, }; +static int miphy40lp_spear1310_pcie_init (struct miphy40lp_priv *priv) +{ +u32 val; + +regmap_update_bits (priv->misc,SPEAR1310_PCIE_MIPHY_CFG_1 , +SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK , +SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE ); + +switch (priv->id) { +case 0 : + val =SPEAR1310_PCIE_CFG_VAL (0 ); +break ; +case 1 : + val =SPEAR1310_PCIE_CFG_VAL (1 ); +break ; +case 2 : + val =SPEAR1310_PCIE_CFG_VAL (2 ); +break ; +default : +return -EINVAL ; + } + +regmap_update_bits (priv->misc,SPEAR1310_PCIE_SATA_CFG , +SPEAR1310_PCIE_CFG_MASK (priv->id), val); + +return 0 ; +} + +static int miphy40lp_spear1310_pcie_exit (struct miphy40lp_priv *priv) +{ +regmap_update_bits (priv->misc,SPEAR1310_PCIE_SATA_CFG , +SPEAR1310_PCIE_CFG_MASK (priv->id),0 ); + +regmap_update_bits (priv->misc,SPEAR1310_PCIE_MIPHY_CFG_1 , +SPEAR1310_PCIE_SATA_MIPHY_CFG_PCIE_MASK ,0 ); + +return 0 ; +} + +static int miphy40lp_spear1310_init (struct miphy40lp_priv *priv) +{ +int ret =0 ; + +if (priv->mode ==PCIE ) + ret =miphy40lp_spear1310_pcie_init (priv); + +return ret; +} + +static int miphy40lp_spear1310_exit (struct miphy40lp_priv *priv) +{ +int ret =0 ; + +if (priv->mode ==PCIE ) + ret =miphy40lp_spear1310_pcie_exit (priv); + +return ret; +} + +static struct miphy40lp_plat_ops spear1310_phy_ops = { + .plat_init = miphy40lp_spear1310_init, + .plat_exit = miphy40lp_spear1310_exit, +}; +static int miphy40lp_init (struct phy *phy) {struct miphy40lp_priv *priv =phy_get_drvdata (phy);
@@ -244,6 +408,7 @@ static int miphy40lp_power_on(struct phy *phy)static const struct of_device_id miphy40lp_of_match[] = { { .compatible ="st,miphy40lp-phy" , .data =NULL }, { .compatible ="st,spear1340-miphy" , .data = &spear1340_phy_ops }, + { .compatible ="st,spear1310-miphy" , .data = &spear1310_phy_ops }, { }, };MODULE_DEVICE_TABLE (of, miphy40lp_of_match);
Signature · 1 line
1.8.1.2
PATCH v5 7/8 pcie: SPEAr13xx: Add designware pcie support
In reply to Mohit KumarFrom: Pratyush Anand <[email protected]>
SPEAr1310 and SPEAr1340 SOC uses designware PCIe controller. Add SPEAr13xx PCIe driver based on designware controller driver.
SPEAr1310 has 3 PCIe ports and SPEAr1340 has 1, which are multiplexed with ahci/sata pins. By default evaluation board of both controller works for ahci mode.
To use these patches on SPEAr1340/1310 evaluation board, do the necessary modifications on board and enable (okay) pcie and miphy from respective evb dtsi file.
--- .../devicetree/bindings/pci/spear13xx-pcie.txt | 7 + arch/arm/boot/dts/spear1310.dtsi | 57 +++ arch/arm/boot/dts/spear1340.dtsi | 19 + arch/arm/boot/dts/spear13xx.dtsi | 5 +- arch/arm/configs/spear13xx_defconfig | 2 + arch/arm/mach-spear/Kconfig | 1 + drivers/pci/host/Kconfig | 5 + drivers/pci/host/Makefile | 1 + drivers/pci/host/pcie-spear13xx.c | 414 +++++++++++++++++++++ 9 files changed, 509 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/spear13xx-pcie.txt create mode 100644 drivers/pci/host/pcie-spear13xx.c
Documentation/devicetree/bindings/pci/spear13xx-pcie.txt new file +7 -0
@@ -0,0 +1,7 @@ +Required properties: +- compatible : should be "st,spear1340-pcie", "snps,dw-pcie". +- pcie_is_gen1: pass <1> if forced gen1 initialization is needed to work with + some buggy cards else pass <0>. +- phys : phandle to phy node associated with pcie controller +- phy-names : must be "pcie-phy" +- All other definitions as per generic PCI bindings
arch/arm/boot/dts/spear1310.dtsi +57 -0
63 lines not on this page · raw message
arch/arm/boot/dts/spear1340.dtsi +19 -0
@@ -49,6 +49,25 @@ status = "disabled"; }; + pcie0: pcie@b1000000 { + compatible = "st,spear1340-pcie", "snps,dw-pcie"; + reg = <0xb1000000 0x4000>; + interrupts = <0 68 0x4>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0x0 0 &gic 68>; + pcie_is_gen1 = <0>; + num-lanes = <1>; + phys = <&miphy0 1>; + phy-names = "pcie-phy"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */ + 0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ + status = "disabled"; + }; + i2s-play@b2400000 { compatible = "snps,designware-i2s"; reg = <0xb2400000 0x10000>;
arch/arm/boot/dts/spear13xx.dtsi +3 -2
@@ -83,8 +83,8 @@ #size-cells = <1>; compatible = "simple-bus"; ranges = <0x50000000 0x50000000 0x10000000 - 0xb0000000 0xb0000000 0x10000000 - 0xd0000000 0xd0000000 0x02000000 + 0x80000000 0x80000000 0x20000000 + 0xb0000000 0xb0000000 0x22000000 0xd8000000 0xd8000000 0x01000000 0xe0000000 0xe0000000 0x10000000>;
@@ -338,6 +338,7 @@ reg = <0xe07008c4 0x4>; thermal_flags = <0x7000>; }; + }; }; };
arch/arm/configs/spear13xx_defconfig +2 -0
@@ -11,6 +11,8 @@ CONFIG_ARCH_SPEAR13XX=y CONFIG_MACH_SPEAR1310=y CONFIG_MACH_SPEAR1340=y # CONFIG_SWP_EMULATE is not set +CONFIG_PCI_MSI=y +CONFIG_PCIE_SPEAR13XX=y CONFIG_SMP=y # CONFIG_SMP_ON_UP is not set # CONFIG_ARM_CPU_TOPOLOGY is not set
arch/arm/mach-spear/Kconfig +1 -0
@@ -28,6 +28,7 @@ config ARCH_SPEAR13XX select USE_OF select MFD_SYSCON select PHY_ST_MIPHY40LP + select PCI help Supports for ARM's SPEAR13XX family
drivers/pci/host/Kconfig +5 -0
@@ -33,4 +33,9 @@ config PCI_RCAR_GEN2 There are 3 internal PCI controllers available with a single built-in EHCI/OHCI host controller present on each one. +config PCIE_SPEAR13XX + bool "STMicroelectronics SPEAr PCIe controller" + depends on ARCH_SPEAR13XX + select PCIEPORTBUS + select PCIE_DW endmenu
drivers/pci/host/Makefile +1 -0
@@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o +obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
drivers/pci/host/pcie-spear13xx.c new file +414 -0
414 lines not on this page · raw message
Signature · 1 line
1.8.1.2
Re: [PATCH V5 7/8] pcie: SPEAr13xx: Add designware pcie support
Documentation/devicetree/bindings/pci/spear13xx-pcie.txt line 4
Quoted 10 lines · Mohit Kumar
Documentation/devicetree/bindings/pci/spear13xx-pcie.txt new file +4
-0@@ -0,0 +1,7 @@ +Required properties: +- compatible : should be "st,spear1340-pcie", "snps,dw-pcie". +- pcie_is_gen1: pass <1> if forced gen1 initialization is needed to work with + some buggy cards else pass <0>.
Better make this an optional property that is only present if gen1 is forced, and then use of_property_read_bool to check it.
Also, use the common naming convention: "-" instead of "_", and you may want to prefix it with 'st,'.
Documentation/devicetree/bindings/pci/spear13xx-pcie.txt line 7
Quoted 3 lines
Documentation/devicetree/bindings/pci/spear13xx-pcie.txt new file +3
-0+- phys : phandle to phy node associated with pcie controller +- phy-names : must be "pcie-phy" +- All other definitions as per generic PCI bindings
Please send the binding to the devicetree mailing list, ideally as a separate patch.
arch/arm/boot/dts/spear1310.dtsi
Quoted 4 lines
arch/arm/boot/dts/spear1310.dtsi +0
-0
Best split out the DT changes as well, since we may want to apply them through the arm-soc tree.
Quoted 12 lines
arch/arm/boot/dts/spear1310.dtsi +8
-0@@ -83,6 +83,63 @@ status = "disabled"; }; + pcie0: pcie@b1000000 { + compatible = "st,spear1340-pcie", "snps,dw-pcie"; + reg = <0xb1000000 0x4000>; + interrupts = <0 68 0x4>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0x0 0 &gic 68>; + pcie_is_gen1 = <0>; + num-lanes = <1>;
arch/arm/boot/dts/spear1310.dtsi line 103
Quoted 10 lines
arch/arm/boot/dts/spear1310.dtsi +10
-0+ phys = <&miphy0 1>; + phy-names = "pcie-phy"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */ + 0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ + status = "disabled"; + };
But keep the changes for the phy together with the pci changes.
arch/arm/boot/dts/spear1310.dtsi line 344
Quoted 8 lines
arch/arm/boot/dts/spear1310.dtsi +1
-0@@ -338,6 +338,7 @@ reg = <0xe07008c4 0x4>; thermal_flags = <0x7000>; }; + }; }; };
I assume this change was not intentional.
arch/arm/configs/spear13xx_defconfig CONFIG_ARCH_SPEAR13XX=y · line 18
Quoted 13 lines
arch/arm/configs/spear13xx_defconfig +2
-0@@ -11,6 +11,8 @@ CONFIG_ARCH_SPEAR13XX=y CONFIG_MACH_SPEAR1310=y CONFIG_MACH_SPEAR1340=y # CONFIG_SWP_EMULATE is not set +CONFIG_PCI_MSI=y +CONFIG_PCIE_SPEAR13XX=y CONFIG_SMP=y # CONFIG_SMP_ON_UP is not set # CONFIG_ARM_CPU_TOPOLOGY is not set
This change can also get folded into patch 3.
arch/arm/mach-spear/Kconfig config ARCH_SPEAR13XX · line 34
Quoted 12 lines
arch/arm/mach-spear/Kconfig +1
-0@@ -28,6 +28,7 @@ config ARCH_SPEAR13XX select USE_OF select MFD_SYSCON select PHY_ST_MIPHY40LP + select PCI help Supports for ARM's SPEAR13XX family
This doesn't seem right: You are making it impossible to turn off PCI here. Better use MIGHT_HAVE_PCI instead to make CONFIG_PCI a user-selectable option.
Quoted 5 lines
drivers/pci/host/Kconfig +0
-0
drivers/pci/host/Kconfig config PCI_RCAR_GEN2 · line 41
Quoted 9 lines
drivers/pci/host/Kconfig +5
-0@@ -33,4 +33,9 @@ config PCI_RCAR_GEN2 There are 3 internal PCI controllers available with a single built-in EHCI/OHCI host controller present on each one. +config PCIE_SPEAR13XX + bool "STMicroelectronics SPEAr PCIe controller" + depends on ARCH_SPEAR13XX + select PCIEPORTBUS + select PCIE_DW endmenu
This can probably be "tristate" instead of "bool. You need to add a help text.
drivers/pci/host/Makefile obj-$(CONFIG_PCI_IMX6) += pci-imx6.o · line 7
Quoted 9 lines
drivers/pci/host/Makefile +1
-0@@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o +obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
I'd use the "pci" naming instead of "pcie" here for consistency.
drivers/pci/host/Makefile
Quoted 9 lines
drivers/pci/host/Makefile +9
-0+ +/* SPEAr13xx PCIe driver does not allow module unload */ + +static int __init pcie_init(void) +{ + + return platform_driver_probe(&spear13xx_pcie_driver, + spear13xx_pcie_probe); +}
This should be platform_driver_register() so you can support deferred probing, e.g. if the phy driver gets loaded after the PCI driver.
Arnd
RE: [PATCH V5 7/8] pcie: SPEAr13xx: Add designware pcie support
Hello Arnd,
Quoted 9 lines
-----Original Message-----
From: Arnd Bergmann [mailto:[email protected]]
Sent: Monday, February 10, 2014 9:13 PM
To: Mohit KUMAR DCG
Cc: Pratyush ANAND; Jingoo Han; Viresh Kumar; spear-devel; linux- [email protected]
Subject: Re: [PATCH V5 7/8] pcie: SPEAr13xx: Add designware pcie supportOn Monday 10 February 2014, Mohit Kumar wrote:
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Documentation/devicetree/bindings/pci/spear13xx-pcie.txt line 5
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Documentation/devicetree/bindings/pci/spear13xx-pcie.txt new file +5
-0@@ -0,0 +1,7 @@ +Required properties: +- compatible : should be "st,spear1340-pcie", "snps,dw-pcie". +- pcie_is_gen1: pass <1> if forced gen1 initialization is needed to +work with + some buggy cards else pass <0>.Better make this an optional property that is only present if gen1 is forced, and then use
of_property_read_boolto check it.
- OK
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Also, use the common naming convention: "-" instead of "_", and you may want to prefix it with 'st,'.
- OK
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Documentation/devicetree/bindings/pci/spear13xx-pcie.txt line 6
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Documentation/devicetree/bindings/pci/spear13xx-pcie.txt new file +1
-0+- phys : phandle to phy node associated with pciecontroller
Documentation/devicetree/bindings/pci/spear13xx-pcie.txt line 7
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Documentation/devicetree/bindings/pci/spear13xx-pcie.txt new file +2
-0+- phy-names : must be "pcie-phy" +- All other definitions as per generic PCI bindingsPlease send the binding to the devicetree mailing list, ideally as a separate patch.
- OK, prepare separate patch for this.
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arch/arm/boot/dts/spear1310.dtsi
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arch/arm/boot/dts/spear1310.dtsi +0
-0Best split out the DT changes as well, since we may want to apply them through the arm-soc tree.
- split in v6.
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arch/arm/boot/dts/spear1310.dtsi +4
-0@@ -83,6 +83,63 @@ status = "disabled"; }; + pcie0: pcie@b1000000 { + compatible = "st,spear1340-pcie", "snps,dw-pcie"; + reg = <0xb1000000 0x4000>; + interrupts = <0 68 0x4>;arch/arm/boot/dts/spear1310.dtsi line 99
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arch/arm/boot/dts/spear1310.dtsi +10
-0+ interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0x0 0 &gic 68>; + pcie_is_gen1 = <0>; + num-lanes = <1>; + phys = <&miphy0 1>; + phy-names = "pcie-phy"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x00000800 0 0x80000000 0x80000000 0
0x00020000/* configuration space */
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arch/arm/boot/dts/spear1310.dtsi line 100
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arch/arm/boot/dts/spear1310.dtsi +1
-0+ 0x81000000 0 0 0x80020000 0 0x00010000 /*downstream I/O */
arch/arm/boot/dts/spear1310.dtsi line 101
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arch/arm/boot/dts/spear1310.dtsi +1
-0+ 0x82000000 0 0x80030000 0xc0030000 0
0x0ffd0000>; /* non-prefetchable memory */arch/arm/boot/dts/spear1310.dtsi line 103
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arch/arm/boot/dts/spear1310.dtsi +2
-0+ status = "disabled"; + };But keep the changes for the phy together with the pci changes.
- ok
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arch/arm/boot/dts/spear1310.dtsi line 344
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arch/arm/boot/dts/spear1310.dtsi +1
-0@@ -338,6 +338,7 @@ reg = <0xe07008c4 0x4>; thermal_flags = <0x7000>; }; + }; }; };I assume this change was not intentional.
- :-).
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arch/arm/configs/spear13xx_defconfig CONFIG_ARCH_SPEAR13XX=y
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arch/arm/configs/spear13xx_defconfig +0
-0@@ -11,6 +11,8 @@ CONFIG_ARCH_SPEAR13XX=y
CONFIG_MACH_SPEAR1310=y
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arch/arm/configs/spear13xx_defconfig CONFIG_ARCH_SPEAR13XX=y · line 18
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CONFIG_MACH_SPEAR1340=y#CONFIG_SWP_EMULATEis not setarch/arm/configs/spear13xx_defconfig +2
-0+CONFIG_PCI_MSI=y +CONFIG_PCIE_SPEAR13XX=y CONFIG_SMP=y # CONFIG_SMP_ON_UP is not set # CONFIG_ARM_CPU_TOPOLOGY is not setThis change can also get folded into patch 3.
- ok
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arch/arm/mach-spear/Kconfig +0
-0@@ -28,6 +28,7 @@ config ARCH_SPEAR13XX select USE_OF select MFD_SYSCON select PHY_ST_MIPHY40LP
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arch/arm/mach-spear/Kconfig config ARCH_SPEAR13XX · line 34
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arch/arm/mach-spear/Kconfig +1
-0+ select PCI help Supports for ARM's SPEAR13XX familyThis doesn't seem right: You are making it impossible to turn off PCI here. Better use
MIGHT_HAVE_PCIinstead to makeCONFIG_PCIa user-selectable option.
- will replace with MIGHT_HAVE_PCI.
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drivers/pci/host/Kconfig index renamed from drivers/pci/host/Kconfig +0
-047d46c6..df52fad 100644
drivers/pci/host/Kconfig +0
-0@@ -33,4 +33,9 @@ config PCI_RCAR_GEN2 There are 3 internal PCI controllers available with a single built-in EHCI/OHCI host controller present on each one.
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drivers/pci/host/Kconfig config PCI_RCAR_GEN2 · line 41
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drivers/pci/host/Kconfig +5
-0+config PCIE_SPEAR13XX + bool "STMicroelectronics SPEAr PCIe controller" + depends on ARCH_SPEAR13XX + select PCIEPORTBUS + select PCIE_DW endmenuThis can probably be "tristate" instead of "bool. You need to add a help text.
- ok
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drivers/pci/host/Makefile obj-$(CONFIG_PCI_IMX6) += pci-imx6.o · line 7
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drivers/pci/host/Makefile +1
-0@@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o +obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.oI'd use the "pci" naming instead of "pcie" here for consistency.
- No, let it be pcie as SPEAr13xx soc has pci controller as well , though PCI is not used on current eval boards.
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drivers/pci/host/Makefile +4
-0+ +/* SPEAr13xx PCIe driver does not allow module unload */ + +static int __init pcie_init(void)
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drivers/pci/host/Makefile
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drivers/pci/host/Makefile +5
-0+{ + + return platform_driver_probe(&spear13xx_pcie_driver, + spear13xx_pcie_probe); +}This should be
platform_driver_register()so you can support deferred probing, e.g. if the phy driver gets loaded after the PCI driver.
- ok
Thanks
Mohit
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Arnd
Re: [PATCH V5 7/8] pcie: SPEAr13xx: Add designware pcie support
Quoted 13 lines · On Tuesday 11 February 2014 12:23:58 Mohit KUMAR DCG wrote:
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drivers/pci/host/Makefile obj-$(CONFIG_PCI_IMX6) += pci-imx6.o · line 7
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drivers/pci/host/Makefile +1
-0@@ -4,3 +4,4 @@ obj-$(CONFIG_PCI_IMX6) += pci-imx6.o obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o +obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.oI'd use the "pci" naming instead of "pcie" here for consistency.
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- No, let it be pcie as SPEAr13xx soc has pci controller as well , though PCI is not used on current eval boards.
Hmm, it's still inconsistent, but I can see your argument. Let's see if someone has a better idea, otherwise keep the pcie name.
I'd prefer to avoid having to rename drivers in the long run, but if we start naming some pcie drivers pci and others pcie, it gets rather confusing.
Arnd
PATCH v5 8/8 MAINTAINERS: Add ST SPEAr13xx PCIe driver maintainer
In reply to Mohit KumarAdd Mohit Kumar as maintainer for ST SPEAr13xx PCIe driver.
--- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+)
MAINTAINERS +6 -0
@@ -6596,6 +6596,12 @@ L: [email protected] S: Maintained F: drivers/pci/host/*designware* +PCIE DRIVER FOR ST SPEAR13XX +M: Mohit Kumar <[email protected]> +L: [email protected] +S: Maintained +F: drivers/pci/host/pcie-spear13xx.c + PCMCIA SUBSYSTEM P: Linux PCMCIA Team L: [email protected]
Signature · 1 line
1.8.1.2