samsung: xgmac:

index 4932824..4c46504 100644
@@ -544,24 +544,24 @@ struct xgmac_priv_data {
 };
 
 /* Function prototypes */
-extern struct xgmac_priv_data *xgmac_dvr_probe(struct device *device,
+struct xgmac_priv_data *xgmac_dvr_probe(struct device *device,
 					struct xgmac_plat_data *plat_dat,
 					void __iomem *addr);
-extern int xgmac_dvr_remove(struct net_device *ndev);
-extern void xgmac_set_ethtool_ops(struct net_device *netdev);
-extern int xgmac_mdio_unregister(struct net_device *ndev);
-extern int xgmac_mdio_register(struct net_device *ndev);
-extern int xgmac_register_platform(void);
-extern void xgmac_unregister_platform(void);
+int xgmac_dvr_remove(struct net_device *ndev);
+void xgmac_set_ethtool_ops(struct net_device *netdev);
+int xgmac_mdio_unregister(struct net_device *ndev);
+int xgmac_mdio_register(struct net_device *ndev);
+int xgmac_register_platform(void);
+void xgmac_unregister_platform(void);
 
 #ifdef CONFIG_PM
-extern int xgmac_suspend(struct net_device *ndev);
-extern int xgmac_resume(struct net_device *ndev);
-extern int xgmac_freeze(struct net_device *ndev);
-extern int xgmac_restore(struct net_device *ndev);
+int xgmac_suspend(struct net_device *ndev);
+int xgmac_resume(struct net_device *ndev);
+int xgmac_freeze(struct net_device *ndev);
+int xgmac_restore(struct net_device *ndev);
 #endif /* CONFIG_PM */
 
-extern const struct xgmac_mtl_ops *xgmac_get_mtl_ops(void);
+const struct xgmac_mtl_ops *xgmac_get_mtl_ops(void);
 
 void xgmac_disable_eee_mode(struct xgmac_priv_data * const priv);
 bool xgmac_eee_init(struct xgmac_priv_data * const priv);

index c5417de..ddf3e94 100644
@@ -196,7 +196,6 @@ static void xgmac_tx_ctxt_desc_set_tstamp(struct xgmac_tx_ctxt_desc *p,
 		p->tstamp_lo = (u32) tstamp;
 		p->tstamp_hi = (u32) (tstamp>>32);
 	}
-
 }
 /* Close TX context descriptor */
 static void xgmac_tx_ctxt_desc_close(struct xgmac_tx_ctxt_desc *p)

@@ -217,7 +216,6 @@ static void xgmac_init_rx_desc(struct xgmac_rx_norm_desc *p, int disable_rx_ic,
 	p->rdes23.rx_rd_des23.own_bit = 1;
 	if (disable_rx_ic)
 		p->rdes23.rx_rd_des23.int_on_com = disable_rx_ic;
-
 }
 
 /* Get RX own bit */

@@ -337,7 +335,6 @@ static int xgmac_rx_wbstatus(struct xgmac_rx_norm_desc *p,
 			pr_err("\tInvalid L2 Packet type\n");
 			break;
 		}
-
 	}
 
 	/* L3/L4 Pkt type */

@@ -443,7 +440,6 @@ static void xgmac_rx_ctxt_wbstatus(struct xgmac_rx_ctxt_desc *p,
 		x->rx_ptp_signal++;
 	else if (p->ptp_msgtype == RX_PTP_RESV_MSG)
 		x->rx_ptp_resv_msg_type++;
-
 }
 
 /* get rx timestamp status */

index 47945a3..384866c 100644
@@ -85,14 +85,14 @@ static void xgmac_dma_channel_init(void __iomem *ioaddr, int cha_num,
 
 	/* program desc registers */
 	writel((dma_tx >> 32),
-			ioaddr + XGMAC_DMA_CHA_TXDESC_HADD_REG(cha_num));
+	       ioaddr + XGMAC_DMA_CHA_TXDESC_HADD_REG(cha_num));
 	writel((dma_tx & 0xFFFFFFFF),
-			ioaddr + XGMAC_DMA_CHA_TXDESC_LADD_REG(cha_num));
+	       ioaddr + XGMAC_DMA_CHA_TXDESC_LADD_REG(cha_num));
 
 	writel((dma_rx >> 32),
-			ioaddr + XGMAC_DMA_CHA_RXDESC_HADD_REG(cha_num));
+	       ioaddr + XGMAC_DMA_CHA_RXDESC_HADD_REG(cha_num));
 	writel((dma_rx & 0xFFFFFFFF),
-			ioaddr + XGMAC_DMA_CHA_RXDESC_LADD_REG(cha_num));
+	       ioaddr + XGMAC_DMA_CHA_RXDESC_LADD_REG(cha_num));
 
 	/* program tail pointers */
 	/* assumption: upper 32 bits are constant and

@@ -100,18 +100,18 @@ static void xgmac_dma_channel_init(void __iomem *ioaddr, int cha_num,
 	 */
 	dma_addr = dma_tx + ((t_rsize-1) * XGMAC_DESC_SIZE_BYTES);
 	writel((dma_addr & 0xFFFFFFFF),
-			ioaddr + XGMAC_DMA_CHA_TXDESC_TAILPTR_REG(cha_num));
+	       ioaddr + XGMAC_DMA_CHA_TXDESC_TAILPTR_REG(cha_num));
 
 	dma_addr = dma_rx + ((r_rsize-1) * XGMAC_DESC_SIZE_BYTES);
 	writel((dma_addr & 0xFFFFFFFF),
-			ioaddr + XGMAC_DMA_CHA_RXDESC_LADD_REG(cha_num));
+	       ioaddr + XGMAC_DMA_CHA_RXDESC_LADD_REG(cha_num));
 	/* program the ring sizes */
 	writel(t_rsize-1, ioaddr + XGMAC_DMA_CHA_TXDESC_RINGLEN_REG(cha_num));
 	writel(r_rsize-1, ioaddr + XGMAC_DMA_CHA_RXDESC_RINGLEN_REG(cha_num));
 
 	/* Enable TX/RX interrupts */
 	writel(XGMAC_DMA_ENA_INT,
-			ioaddr + XGMAC_DMA_CHA_INT_ENABLE_REG(cha_num));
+	       ioaddr + XGMAC_DMA_CHA_INT_ENABLE_REG(cha_num));
 }
 
 static void xgmac_enable_dma_transmission(void __iomem *ioaddr, int cha_num)

@@ -126,7 +126,7 @@ static void xgmac_enable_dma_irq(void __iomem *ioaddr, int dma_cnum)
 {
 	/* Enable TX/RX interrupts */
 	writel(XGMAC_DMA_ENA_INT,
-			ioaddr + XGMAC_DMA_CHA_INT_ENABLE_REG(dma_cnum));
+	       ioaddr + XGMAC_DMA_CHA_INT_ENABLE_REG(dma_cnum));
 }
 
 static void xgmac_disable_dma_irq(void __iomem *ioaddr, int dma_cnum)

@@ -144,7 +144,7 @@ static void xgmac_dma_start_tx(void __iomem *ioaddr, int tchannels)
 		tx_ctl_reg = readl(ioaddr + XGMAC_DMA_CHA_TXCTL_REG(cnum));
 		tx_ctl_reg |= XGMAC_TX_ENABLE;
 		writel(tx_ctl_reg,
-			ioaddr + XGMAC_DMA_CHA_TXCTL_REG(cnum));
+		       ioaddr + XGMAC_DMA_CHA_TXCTL_REG(cnum));
 	}
 }
 

@@ -187,7 +187,7 @@ static void xgmac_dma_start_rx(void __iomem *ioaddr, int rchannels)
 		rx_ctl_reg = readl(ioaddr + XGMAC_DMA_CHA_RXCTL_REG(cnum));
 		rx_ctl_reg |= XGMAC_RX_ENABLE;
 		writel(rx_ctl_reg,
-			ioaddr + XGMAC_DMA_CHA_RXCTL_REG(cnum));
+		       ioaddr + XGMAC_DMA_CHA_RXCTL_REG(cnum));
 	}
 }
 

@@ -245,14 +245,16 @@ static int xgmac_tx_dma_int_status(void __iomem *ioaddr, int channel_no,
 			if (int_status & XGMAC_DMA_INT_STATUS_TEB0) {
 				x->tx_read_transfer_err++;
 				clear_val |= XGMAC_DMA_INT_STATUS_TEB0;
-			} else
+			} else {
 				x->tx_write_transfer_err++;
+			}
 
 			if (int_status & XGMAC_DMA_INT_STATUS_TEB1) {
 				x->tx_desc_access_err++;
 				clear_val |= XGMAC_DMA_INT_STATUS_TEB1;
-			} else
+			} else {
 				 x->tx_buffer_access_err++;
+			}
 
 			if (int_status & XGMAC_DMA_INT_STATUS_TEB2) {
 				x->tx_data_transfer_err++;

@@ -315,14 +317,16 @@ static int xgmac_rx_dma_int_status(void __iomem *ioaddr, int channel_no,
 			if (int_status & XGMAC_DMA_INT_STATUS_REB0) {
 				x->rx_read_transfer_err++;
 				clear_val |= XGMAC_DMA_INT_STATUS_REB0;
-			} else
+			} else {
 				x->rx_write_transfer_err++;
+			}
 
 			if (int_status & XGMAC_DMA_INT_STATUS_REB1) {
 				x->rx_desc_access_err++;
 				clear_val |= XGMAC_DMA_INT_STATUS_REB1;
-			} else
+			} else {
 				 x->rx_buffer_access_err++;
+			}
 
 			if (int_status & XGMAC_DMA_INT_STATUS_REB2) {
 				x->rx_data_transfer_err++;

87 lines not on this page · raw message

265 lines not on this page · raw message

index 647a7bd..568c2fb 100644
@@ -78,7 +78,7 @@ static int xgmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
 		 */
 		if (phyaddr < 4)
 			writel((1 << phyaddr),
-				priv->ioaddr + XGMAC_MDIO_CLAUSE22_PORT_REG);
+			       priv->ioaddr + XGMAC_MDIO_CLAUSE22_PORT_REG);
 		else
 			return -ENODEV;
 		/* set mdio address register */

@@ -137,12 +137,12 @@ static int xgmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
 		/* configure the port for C22
 		 * ports 0-3 only supports C22
 		 */
-		if (phyaddr < 4)
-			writel((1 << phyaddr),
-				priv->ioaddr + XGMAC_MDIO_CLAUSE22_PORT_REG);
-		else
+		if (phyaddr >= 4)
 			return -ENODEV;
 
+		writel((1 << phyaddr),
+		       priv->ioaddr + XGMAC_MDIO_CLAUSE22_PORT_REG);
+
 		/* set mdio address register */
 		reg_val = (phyaddr << 16) | (phyreg & 0x1F);
 		writel(reg_val, priv->ioaddr + mii_addr);

@@ -173,8 +173,7 @@ int xgmac_mdio_register(struct net_device *ndev)
 	/* allocate the new mdio bus */
 	mdio_bus = mdiobus_alloc();
 	if (!mdio_bus) {
-		pr_err("%s : mii bus allocation failed\n",
-			__func__);
+		pr_err("%s : mii bus allocation failed\n", __func__);
 		return -ENOMEM;
 	}
 

index 85e0132..82d275b 100644
@@ -208,9 +208,9 @@ static void xgmac_set_tx_mtl_mode(void __iomem *ioaddr, int queue_num,
 
 	reg_val = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE_REG(queue_num));
 	/* TX specific MTL mode settings */
-	if (tx_mode == XGMAC_MTL_SFMODE)
+	if (tx_mode == XGMAC_MTL_SFMODE) {
 		reg_val |= XGMAC_MTL_SFMODE;
-	else {
+	} else {
 		/* set the TTC values */
 		if (tx_mode <= 64)
 			reg_val |= MTL_CONTROL_TTC_64;

index 8fa2241..c5afba4 100644
@@ -11,6 +11,8 @@
  * published by the Free Software Foundation.
  */
 
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include <linux/export.h>
 #include <linux/io.h>
 #include <linux/netdevice.h>

@@ -92,15 +94,15 @@ static void xgmac_core_pmt(void __iomem *ioaddr, unsigned long mode)
 	unsigned int pmt = 0;
 
 	if (mode & WAKE_MAGIC) {
-		pr_debug("GMAC: WOL Magic frame\n");
+		pr_debug("WOL Magic frame\n");
 		pmt |= PMT_MGPKT_EN;
 	}
 	if (mode & WAKE_UCAST) {
-		pr_debug("GMAC: WOL on global unicast\n");
+		pr_debug("WOL on global unicast\n");
 		pmt |= PMT_GUCAST_EN;
 	}
 	if (mode & (WAKE_MCAST | WAKE_BCAST)) {
-		pr_debug("GMAC: WOL on any other packet\n");
+		pr_debug("WOL on any other packet\n");
 		pmt |= PMT_RWKPKT_EN;
 	}
 

index ddf3e94..ef25efd 100644
@@ -9,6 +9,9 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include <linux/bitops.h>
 #include <linux/export.h>
 #include <linux/io.h>

@@ -287,7 +290,7 @@ static int xgmac_rx_wbstatus(struct xgmac_rx_norm_desc *p,
 			x->overflow_error++;
 			break;
 		default:
-			pr_err("\tInvalid Error type\n");
+			pr_err("Invalid Error type\n");
 			break;
 		}
 	} else {

@@ -332,7 +335,7 @@ static int xgmac_rx_wbstatus(struct xgmac_rx_norm_desc *p,
 			x->dvlan_ocvlan_icvlan_pkt++;
 			break;
 		default:
-			pr_err("\tInvalid L2 Packet type\n");
+			pr_err("Invalid L2 Packet type\n");
 			break;
 		}
 	}

@@ -367,7 +370,7 @@ static int xgmac_rx_wbstatus(struct xgmac_rx_norm_desc *p,
 		x->ip6_unknown_pkt++;
 		break;
 	default:
-		pr_err("\tInvalid L3/L4 Packet type\n");
+		pr_err("Invalid L3/L4 Packet type\n");
 		break;
 	}
 

@@ -446,7 +449,7 @@ static void xgmac_rx_ctxt_wbstatus(struct xgmac_rx_ctxt_desc *p,
 static int xgmac_get_rx_ctxt_tstamp_status(struct xgmac_rx_ctxt_desc *p)
 {
 	if ((p->tstamp_hi == 0xffffffff) && (p->tstamp_lo == 0xffffffff)) {
-		pr_err("\tTime stamp corrupted\n");
+		pr_err("Time stamp corrupted\n");
 		return 0;
 	}
 

index 3f0698a..576b23e 100644
@@ -9,6 +9,9 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include <linux/clk.h>
 #include <linux/interrupt.h>
 #include <linux/kernel.h>

@@ -200,7 +203,7 @@ static int xgmac_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 		return -EOPNOTSUPP;
 
 	if (wol->wolopts) {
-		pr_info("xgmac: wakeup enable\n");
+		pr_info("wakeup enable\n");
 		device_set_wakeup_enable(priv->device, true);
 		enable_irq_wake(priv->wol_irq);
 	} else {

203 lines not on this page · raw message

index 568c2fb..98cd311 100644
@@ -9,6 +9,9 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include <linux/io.h>
 #include <linux/mii.h>
 #include <linux/netdevice.h>

@@ -173,7 +176,7 @@ int xgmac_mdio_register(struct net_device *ndev)
 	/* allocate the new mdio bus */
 	mdio_bus = mdiobus_alloc();
 	if (!mdio_bus) {
-		pr_err("%s : mii bus allocation failed\n", __func__);
+		pr_err("%s: mii bus allocation failed\n", __func__);
 		return -ENOMEM;
 	}
 

index 82d275b..2edad0f 100644
@@ -9,6 +9,9 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include <linux/io.h>
 #include <linux/errno.h>
 #include <linux/export.h>

@@ -172,7 +175,7 @@ static int xgmac_mtl_flush_txqueue(void __iomem *ioaddr, int queue_num)
 	while ((reg_val &
 		(XGMAC_MTL_TXQ_EMPTY_STAT | XGMAC_MTL_TXQ_WRITE_STAT))) {
 		if (time_after(jiffies, timeout)) {
-			pr_err("cannot flush tx queue - timeout");
+			pr_err("cannot flush tx queue - timeout\n");
 			return -ETIMEDOUT;
 		}
 		reg_val = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE_REG(queue_num));

@@ -192,7 +195,7 @@ static int xgmac_mtl_readout_rxqueue(void __iomem *ioaddr, int queue_num)
 	while ((reg_val &
 		(XGMAC_MTL_TXQ_EMPTY_STAT | XGMAC_MTL_TXQ_WRITE_STAT))) {
 		if (time_after(jiffies, timeout)) {
-			pr_err("cannot flush tx queue - timeout");
+			pr_err("cannot flush tx queue - timeout\n");
 			return -ETIMEDOUT;
 		}
 		reg_val = readl(ioaddr + XGMAC_MTL_TXQ_OPMODE_REG(queue_num));

index d0cf6cf..f6b3d20 100644
@@ -9,6 +9,9 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
 #include <linux/etherdevice.h>
 #include <linux/io.h>
 #include <linux/module.h>

@@ -69,7 +72,7 @@ static int xgmac_probe_config_dt(struct platform_device *pdev,
 					"samsung,force_thresh_dma_mode");
 	if (plat->force_thresh_dma_mode) {
 		plat->force_sf_dma_mode = 0;
-		pr_warn("force_sf_dma_mode is ignored as force_thresh_dma_mode is set.");
+		pr_warn("force_sf_dma_mode is ignored as force_thresh_dma_mode is set\n");
 	}
 
 	return 0;

@@ -119,20 +122,20 @@ static int xgmac_platform_probe(struct platform_device *pdev)
 					sizeof(struct xgmac_plat_data),
 					GFP_KERNEL);
 		if (!plat_dat) {
-			pr_err("%s: ERROR: no memory", __func__);
+			pr_err("%s: ERROR: no memory\n", __func__);
 			return  -ENOMEM;
 		}
 
 		ret = xgmac_probe_config_dt(pdev, plat_dat, &mac);
 		if (ret) {
-			pr_err("%s: main dt probe failed", __func__);
+			pr_err("%s: main dt probe failed\n", __func__);
 			return ret;
 		}
 	}
 
 	priv = xgmac_dvr_probe(&(pdev->dev), plat_dat, addr);
 	if (!priv) {
-		pr_err("%s: main driver probe failed", __func__);
+		pr_err("%s: main driver probe failed\n", __func__);
 		return -ENODEV;
 	}
 

@@ -176,7 +179,7 @@ static int xgmac_platform_probe(struct platform_device *pdev)
 
 	platform_set_drvdata(pdev, priv->dev);
 
-	pr_debug("XGMAC platform driver registration completed");
+	pr_debug("platform driver registration completed\n");
 
 	return 0;
 }

@@ -261,7 +264,7 @@ int xgmac_register_platform(void)
 
 	err = platform_driver_register(&xgmac_platform_driver);
 	if (err)
-		pr_err("xgmac: failed to register the platform driver\n");
+		pr_err("failed to register the platform driver\n");
 
 	return err;
 }

index 576b23e..378f6f1 100644
@@ -203,7 +203,7 @@ static int xgmac_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 		return -EOPNOTSUPP;
 
 	if (wol->wolopts) {
-		pr_info("wakeup enable\n");
+		netdev_info(dev, "wakeup enable\n");
 		device_set_wakeup_enable(priv->device, true);
 		enable_irq_wake(priv->wol_irq);
 	} else {

380 lines not on this page · raw message

index 98cd311..5e1e40e 100644
@@ -176,7 +176,7 @@ int xgmac_mdio_register(struct net_device *ndev)
 	/* allocate the new mdio bus */
 	mdio_bus = mdiobus_alloc();
 	if (!mdio_bus) {
-		pr_err("%s: mii bus allocation failed\n", __func__);
+		netdev_err(ndev, "%s: mii bus allocation failed\n", __func__);
 		return -ENOMEM;
 	}
 

@@ -198,7 +198,7 @@ int xgmac_mdio_register(struct net_device *ndev)
 	/* register with kernel subsystem */
 	err = mdiobus_register(mdio_bus);
 	if (err != 0) {
-		pr_err("mdiobus register failed\n");
+		netdev_err(ndev, "mdiobus register failed\n");
 		goto mdiobus_err;
 	}
 

@@ -236,16 +236,15 @@ int xgmac_mdio_register(struct net_device *ndev)
 				irq_str = irq_num;
 				break;
 			}
-			pr_info("%s: PHY ID %08x at %d IRQ %s (%s)%s\n",
-				ndev->name, phy->phy_id, phy_addr,
-				irq_str, dev_name(&phy->dev),
-				act ? " active" : "");
+			netdev_info(ndev, "PHY ID %08x at %d IRQ %s (%s)%s\n",
+				    phy->phy_id, phy_addr, irq_str,
+				    dev_name(&phy->dev), act ? " active" : "");
 			phy_found = 1;
 		}
 	}
 
 	if (!phy_found) {
-		pr_err("%s: PHY not found\n", ndev->name);
+		netdev_err(ndev, "PHY not found\n");
 		mdiobus_unregister(mdio_bus);
 		mdiobus_free(mdio_bus);
 		return -ENODEV;

index f6b3d20..fb80c2c 100644
@@ -121,10 +121,8 @@ static int xgmac_platform_probe(struct platform_device *pdev)
 			plat_dat = devm_kzalloc(&pdev->dev,
 					sizeof(struct xgmac_plat_data),
 					GFP_KERNEL);
-		if (!plat_dat) {
-			pr_err("%s: ERROR: no memory\n", __func__);
+		if (!plat_dat)
 			return  -ENOMEM;
-		}
 
 		ret = xgmac_probe_config_dt(pdev, plat_dat, &mac);
 		if (ret) {

index c5afba4..40b1946 100644
@@ -1,4 +1,3 @@
-
 /* 10G controller driver for Samsung SoCs
  *
  * Copyright (C) 2013 Samsung Electronics Co., Ltd.

index ef25efd..2a7fd21 100644
@@ -84,7 +84,7 @@ static void xgmac_release_tx_desc(struct xgmac_tx_norm_desc *p)
 
 /* Clear interrupt on tx frame completion. When this bit is
  * set an interrupt happens as soon as the frame is transmitted
-*/
+ */
 static void xgmac_clear_tx_ic(struct xgmac_tx_norm_desc *p)
 {
 	p->tdes23.tx_rd_des23.int_on_com = 0;

@@ -158,8 +158,8 @@ static void xgmac_tx_ctxt_desc_reset_ostc(struct xgmac_tx_ctxt_desc *p)
 
 /* Set IVLAN information */
 static void xgmac_tx_ctxt_desc_set_ivlantag(struct xgmac_tx_ctxt_desc *p,
-				     int is_ivlanvalid, int ivlan_tag,
-				     int ivlan_ctl)
+					    int is_ivlanvalid, int ivlan_tag,
+					    int ivlan_ctl)
 {
 	if (is_ivlanvalid) {
 		p->ivlan_tag_valid = is_ivlanvalid;

@@ -176,7 +176,7 @@ static int xgmac_tx_ctxt_desc_get_ivlantag(struct xgmac_tx_ctxt_desc *p)
 
 /* Set VLAN Tag */
 static void xgmac_tx_ctxt_desc_set_vlantag(struct xgmac_tx_ctxt_desc *p,
-					int is_vlanvalid, int vlan_tag)
+					   int is_vlanvalid, int vlan_tag)
 {
 	if (is_vlanvalid) {
 		p->vltag_valid = is_vlanvalid;

@@ -214,7 +214,7 @@ static int xgmac_tx_ctxt_desc_get_cde(struct xgmac_tx_ctxt_desc *p)
 
 /* DMA RX descriptor ring initialization */
 static void xgmac_init_rx_desc(struct xgmac_rx_norm_desc *p, int disable_rx_ic,
-			int mode, int end)
+			       int mode, int end)
 {
 	p->rdes23.rx_rd_des23.own_bit = 1;
 	if (disable_rx_ic)

@@ -413,7 +413,7 @@ static void xgmac_set_ctxt_rx_owner(struct xgmac_rx_ctxt_desc *p)
 
 /* Return the reception status looking at Context control information */
 static void xgmac_rx_ctxt_wbstatus(struct xgmac_rx_ctxt_desc *p,
-				struct xgmac_extra_stats *x)
+				   struct xgmac_extra_stats *x)
 {
 	if (p->tstamp_dropped)
 		x->timestamp_dropped++;

@@ -445,7 +445,7 @@ static void xgmac_rx_ctxt_wbstatus(struct xgmac_rx_ctxt_desc *p,
 		x->rx_ptp_resv_msg_type++;
 }
 
-/* get rx timestamp status */
+/* Get rx timestamp status */
 static int xgmac_get_rx_ctxt_tstamp_status(struct xgmac_rx_ctxt_desc *p)
 {
 	if ((p->tstamp_hi == 0xffffffff) && (p->tstamp_lo == 0xffffffff)) {

index 028b505..8433030 100644
@@ -14,7 +14,7 @@
 
 #define XGMAC_DESC_SIZE_BYTES	16
 
-/* forward declatarion */
+/* forward declaration */
 struct xgmac_extra_stats;
 
 /* Transmit checksum insertion control */

index 384866c..9a22990a 100644
@@ -20,9 +20,10 @@
 #include "xgmac_dma.h"
 #include "xgmac_reg.h"
 #include "xgmac_desc.h"
+
 /* DMA core initialization */
 static int xgmac_dma_init(void __iomem *ioaddr, int fix_burst,
-			     int burst_map, int adv_addr_mode)
+			  int burst_map, int adv_addr_mode)
 {
 	int retry_count = 10;
 	u32 reg_val;

index 2e76ae0..022fd2b 100644
@@ -12,7 +12,7 @@
 #ifndef __XGMAC_DMA_H__
 #define __XGMAC_DMA_H__
 
-/* forward declatarion */
+/* forward declaration */
 struct xgmac_extra_stats;
 
 #define XGMAC_DMA_BLENMAP_LSHIFT	1

index f642c99..e0e339e 100644
@@ -1880,7 +1880,8 @@ static void xgmac_set_umac_addr(void __iomem *ioaddr, unsigned char *addr,
 	writel(data, ioaddr + XGMAC_ADDR_LOW(reg_n));
 }
 
-/* xgmac_set_rx_mode - entry point for setting different receive mode of
+/**
+ * xgmac_set_rx_mode - entry point for setting different receive mode of
  * a device. unicast, multicast addressing
  * @dev : pointer to the device structure
  * Description:

@@ -1952,7 +1953,8 @@ static void xgmac_set_rx_mode(struct net_device *dev)
 	readl(ioaddr + XGMAC_HASH_HIGH), readl(ioaddr + XGMAC_HASH_LOW));
 }
 
-/* xgmac_config - entry point for changing configuration mode passed on by
+/**
+ * xgmac_config - entry point for changing configuration mode passed on by
  * ifconfig
  * @dev : pointer to the device structure
  * @map : pointer to the device mapping structure

@@ -1984,7 +1986,8 @@ static int xgmac_config(struct net_device *dev, struct ifmap *map)
 }
 
 #ifdef CONFIG_NET_POLL_CONTROLLER
-/* xgmac_poll_controller - entry point for polling receive by device
+/**
+ * xgmac_poll_controller - entry point for polling receive by device
  * @dev : pointer to the device structure
  * Description:
  * This function is used by NETCONSOLE and other diagnostic tools

@@ -2048,7 +2051,7 @@ static const struct net_device_ops xgmac_netdev_ops = {
 	.ndo_set_mac_address = eth_mac_addr,
 };
 
-/* get the hardware ops */
+/* Get the hardware ops */
 void xgmac_get_ops(struct xgmac_ops * const ops_ptr)
 {
 	ops_ptr->mac = xgmac_get_core_ops();

@@ -2359,8 +2362,7 @@ int xgmac_restore(struct net_device *ndev)
 }
 #endif /* CONFIG_PM */
 
-/* Driver is configured as Platf drivers
- */
+/* Driver is configured as Platform driver */
 static int __init xgmac_init(void)
 {
 	int ret;

index 1218f8d..b26d99b 100644
@@ -195,7 +195,7 @@
 #define XGMAC_CORE_RSS_ADD_REG		0x0C88
 #define XGMAC_CORE_RSS_DATA_REG		0x0C8C
 
-/* RSS conrol register bits */
+/* RSS control register bits */
 #define XGMAC_CORE_RSS_CTL_UDP4TE	BIT(3)
 #define XGMAC_CORE_RSS_CTL_TCP4TE	BIT(2)
 #define XGMAC_CORE_RSS_CTL_IP2TE	BIT(1)

@@ -256,7 +256,7 @@
 #define XGMAC_MTL_TX_PRTYMAP0_REG	(XGMAC_MTL_BASE_REG + 0x0040)
 #define XGMAC_MTL_TX_PRTYMAP1_REG	(XGMAC_MTL_BASE_REG + 0x0044)
 
-/* TC/Queue registers , qnum=0-15 */
+/* TC/Queue registers, qnum=0-15 */
 #define XGMAC_MTL_TC_TXBASE_REG		(XGMAC_MTL_BASE_REG + 0x0100)
 #define XGMAC_MTL_TXQ_OPMODE_REG(qnum) \
 		(XGMAC_MTL_TC_TXBASE_REG + (qnum * 0x80) + 0x00)

@@ -404,10 +404,10 @@ enum vlan_tag_ctl_tx {
 #define XGMAC_RX_UNICAST_DETECT		BIT(1)
 #define XGMAC_RX_PRTYFLOW_CTL_ENABLE	BIT(8)
 
-/* xgmac rx Q control0 register bifields */
+/* xgmac rx Q control0 register bitfields */
 #define XGMAC_RX_Q_ENABLE	0x2
 
-/* XGMAC hardware features bit field specific */
+/* XGMAC hardware features bitfield specific */
 /* Capability Register 0 */
 #define XGMAC_HW_FEAT_GMII(cap)			((cap & 0x00000002) >> 1)
 #define XGMAC_HW_FEAT_VLAN_HASH_FILTER(cap)	((cap & 0x00000010) >> 4)

index 4c46504..47721b6 100644
@@ -8,7 +8,7 @@
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
-*/
+ */
 
 #ifndef __XGMAC_COMMON_H__
 #define __XGMAC_COMMON_H__

@@ -167,21 +167,21 @@ enum dma_irq_status {
 	handle_rx = BIT(5),
 };
 
-#define NETIF_F_HW_VLAN_ALL     (NETIF_F_HW_VLAN_CTAG_RX |\
-				NETIF_F_HW_VLAN_STAG_RX |\
-				NETIF_F_HW_VLAN_CTAG_TX |\
-				NETIF_F_HW_VLAN_STAG_TX |\
-				NETIF_F_HW_VLAN_CTAG_FILTER |\
-				NETIF_F_HW_VLAN_STAG_FILTER)
+#define NETIF_F_HW_VLAN_ALL     (NETIF_F_HW_VLAN_CTAG_RX |	\
+				 NETIF_F_HW_VLAN_STAG_RX |	\
+				 NETIF_F_HW_VLAN_CTAG_TX |	\
+				 NETIF_F_HW_VLAN_STAG_TX |	\
+				 NETIF_F_HW_VLAN_CTAG_FILTER |	\
+				 NETIF_F_HW_VLAN_STAG_FILTER)
 
 /* MMC control defines */
 #define XGMAC_MMC_CTRL_CNT_FRZ  0x00000008
 
 /* XGMAC HW ADDR regs */
 #define XGMAC_ADDR_HIGH(reg)    (((reg > 15) ? 0x00000800 : 0x00000040) + \
-				(reg * 8))
+				 (reg * 8))
 #define XGMAC_ADDR_LOW(reg)     (((reg > 15) ? 0x00000804 : 0x00000044) + \
-				(reg * 8))
+				 (reg * 8))
 #define XGMAC_MAX_PERFECT_ADDRESSES 32 /* Maximum unicast perfect filtering */
 #define XGMAC_FRAME_FILTER       0x00000004      /* Frame Filter */
 

@@ -207,7 +207,7 @@ enum dma_irq_status {
 #define MIN_MTU         68
 #define MAX_MTU         9000
 
-#define XGMAC_FOR_EACH_QUEUE(max_queues, queue_num) \
+#define XGMAC_FOR_EACH_QUEUE(max_queues, queue_num)			\
 	for (queue_num = 0; queue_num < max_queues; queue_num++)
 
 #define DRV_VERSION "1.0.0"

@@ -331,7 +331,7 @@ struct xgmac_hwtimestamp {
 	int (*init_systime)(void __iomem *ioaddr, u32 sec, u32 nsec);
 	int (*config_addend)(void __iomem *ioaddr, u32 addend);
 	int (*adjust_systime)(void __iomem *ioaddr, u32 sec, u32 nsec,
-			       int add_sub);
+			      int add_sub);
 	u64 (*get_systime)(void __iomem *ioaddr);
 };
 

@@ -353,14 +353,14 @@ struct xgmac_core_ops {
 	void (*dump_regs)(void __iomem *ioaddr);
 	/* Handle extra events on specific interrupts hw dependent */
 	int (*host_irq_status)(void __iomem *ioaddr,
-				struct xgmac_extra_stats *x);
+			       struct xgmac_extra_stats *x);
 	/* Set power management mode (e.g. magic frame) */
 	void (*pmt)(void __iomem *ioaddr, unsigned long mode);
 	/* Set/Get Unicast MAC addresses */
 	void (*set_umac_addr)(void __iomem *ioaddr, unsigned char *addr,
-			       unsigned int reg_n);
+			      unsigned int reg_n);
 	void (*get_umac_addr)(void __iomem *ioaddr, unsigned char *addr,
-			       unsigned int reg_n);
+			      unsigned int reg_n);
 	void (*enable_rx)(void __iomem *ioaddr, bool enable);
 	void (*enable_tx)(void __iomem *ioaddr, bool enable);
 

@@ -369,7 +369,7 @@ struct xgmac_core_ops {
 
 	/* If supported then get the optional core features */
 	unsigned int (*get_hw_feature)(void __iomem *ioaddr,
-						unsigned char feature_index);
+				       unsigned char feature_index);
 	/* adjust XGMAC speed */
 	void (*set_speed)(void __iomem *ioaddr, unsigned char speed);
 

@@ -377,7 +377,7 @@ struct xgmac_core_ops {
 	void (*set_eee_mode)(void __iomem *ioaddr);
 	void (*reset_eee_mode)(void __iomem *ioaddr);
 	void (*set_eee_timer)(void __iomem *ioaddr, const int ls,
-			const int tw);
+			      const int tw);
 	void (*set_eee_pls)(void __iomem *ioaddr, const int link);
 
 	/* Enable disable checksum offload operations */

index 40b1946..2a239d1 100644
@@ -69,7 +69,7 @@ static int xgmac_get_lpi_status(void __iomem *ioaddr, const u32 irq_status)
 
 /* Handle extra events on specific interrupts hw dependent */
 static int xgmac_core_host_irq_status(void __iomem *ioaddr,
-				struct xgmac_extra_stats *x)
+				      struct xgmac_extra_stats *x)
 {
 	int irq_status, status = 0;
 

@@ -110,26 +110,26 @@ static void xgmac_core_pmt(void __iomem *ioaddr, unsigned long mode)
 	/* Enable power down bit if any of the requested mode is enabled */
 	if (pmt) {
 		writel(XGMAC_RX_ENABLE, ioaddr + XGMAC_CORE_RX_CONFIG_REG);
-		 pmt |= PMT_PWRDWN;
+		pmt |= PMT_PWRDWN;
 		writel(pmt, ioaddr + XGMAC_CORE_PMT_CTL_STATUS_REG);
 	}
 }
 
 /* Set/Get Unicast MAC addresses */
 static void xgmac_core_set_umac_addr(void __iomem *ioaddr, unsigned char *addr,
-			       unsigned int reg_n)
+				     unsigned int reg_n)
 {
 	u32 high_word, low_word;
 
 	high_word = (addr[5] << 8) || (addr[4]);
-	low_word = (addr[3] << 24) || (addr[2] << 16) ||
-		   (addr[1] << 8) || (addr[0]);
+	low_word = ((addr[3] << 24) || (addr[2] << 16) ||
+		    (addr[1] << 8) || (addr[0]));
 	writel(high_word, ioaddr + XGMAC_CORE_ADD_HIGHOFFSET(reg_n));
 	writel(low_word, ioaddr + XGMAC_CORE_ADD_LOWOFFSET(reg_n));
 }
 
 static void xgmac_core_get_umac_addr(void __iomem *ioaddr, unsigned char *addr,
-			       unsigned int reg_n)
+				     unsigned int reg_n)
 {
 	u32 high_word, low_word;
 

@@ -176,13 +176,12 @@ static int xgmac_get_controller_version(void __iomem *ioaddr)
 
 /* If supported then get the optional core features */
 static unsigned int xgmac_get_hw_feature(void __iomem *ioaddr,
-						unsigned char feature_index)
+					 unsigned char feature_index)
 {
 	return readl(ioaddr + (XGMAC_CORE_HW_FEA_REG(feature_index)));
 }
 
-static void xgmac_core_set_speed(void __iomem *ioaddr,
-					unsigned char speed)
+static void xgmac_core_set_speed(void __iomem *ioaddr, unsigned char speed)
 {
 	u32 tx_cfg = readl(ioaddr + XGMAC_CORE_TX_CONFIG_REG);
 

@@ -233,7 +232,7 @@ static void  xgmac_set_eee_pls(void __iomem *ioaddr, const int link)
 }
 
 static void  xgmac_set_eee_timer(void __iomem *ioaddr,
-					const int ls, const int tw)
+				 const int ls, const int tw)
 {
 	int value = ((tw & 0xffff)) | ((ls & 0x7ff) << 16);
 

index 2a7fd21..45e6676 100644
@@ -29,8 +29,8 @@ static void xgmac_init_tx_desc(struct xgmac_tx_norm_desc *p)
 }
 
 static void xgmac_tx_desc_enable_tse(struct xgmac_tx_norm_desc *p, u8 is_tse,
-			      u32 total_hdr_len, u32 tcp_hdr_len,
-			      u32 tcp_payload_len)
+				     u32 total_hdr_len, u32 tcp_hdr_len,
+				     u32 tcp_payload_len)
 {
 	p->tdes23.tx_rd_des23.tse_bit = is_tse;
 	p->tdes23.tx_rd_des23.buf1_size = total_hdr_len;

@@ -40,7 +40,7 @@ static void xgmac_tx_desc_enable_tse(struct xgmac_tx_norm_desc *p, u8 is_tse,
 
 /* Assign buffer lengths for descriptor */
 static void xgmac_prepare_tx_desc(struct xgmac_tx_norm_desc *p, u8 is_fd,
-			int buf1_len, int pkt_len, int cksum)
+				  int buf1_len, int pkt_len, int cksum)
 {
 	p->tdes23.tx_rd_des23.first_desc = is_fd;
 	p->tdes23.tx_rd_des23.buf1_size = buf1_len;

@@ -49,7 +49,7 @@ static void xgmac_prepare_tx_desc(struct xgmac_tx_norm_desc *p, u8 is_fd,
 
 	if (cksum)
 		p->tdes23.tx_rd_des23.tx_pkt_len.cksum_pktlen.cksum_ctl =
-								cic_full;
+			cic_full;
 }
 
 /* Set VLAN control information */

@@ -192,7 +192,7 @@ static int xgmac_tx_ctxt_desc_get_vlantag(struct xgmac_tx_ctxt_desc *p)
 
 /* Set Time stamp */
 static void xgmac_tx_ctxt_desc_set_tstamp(struct xgmac_tx_ctxt_desc *p,
-					 u8 ostc_enable, u64 tstamp)
+					  u8 ostc_enable, u64 tstamp)
 {
 	if (ostc_enable) {
 		p->ostc = ostc_enable;

index 8433030..adf5a0f 100644
@@ -125,7 +125,7 @@ struct xgmac_rx_norm_desc {
 			u32 recv_context_desc:1;
 			u32 own_bit:1;
 		} rx_wb_des23;
-	 } rdes23;
+	} rdes23;
 };
 
 /* Context descriptor structure */

@@ -173,7 +173,7 @@ struct xgmac_desc_ops {
 
 	/* Assign buffer lengths for descriptor */
 	void (*prepare_tx_desc)(struct xgmac_tx_norm_desc *p, u8 is_fd,
-				 int buf1_len, int pkt_len, int cksum);
+				int buf1_len, int pkt_len, int cksum);
 
 	/* Set VLAN control information */
 	void (*tx_vlanctl_desc)(struct xgmac_tx_norm_desc *p, int vlan_ctl);

@@ -230,22 +230,22 @@ struct xgmac_desc_ops {
 
 	/* Set IVLAN information */
 	void (*tx_ctxt_desc_set_ivlantag)(struct xgmac_tx_ctxt_desc *p,
-					int is_ivlanvalid, int ivlan_tag,
-					int ivlan_ctl);
+					  int is_ivlanvalid, int ivlan_tag,
+					  int ivlan_ctl);
 
 	/* Return IVLAN Tag */
 	int (*tx_ctxt_desc_get_ivlantag)(struct xgmac_tx_ctxt_desc *p);
 
 	/* Set VLAN Tag */
 	void (*tx_ctxt_desc_set_vlantag)(struct xgmac_tx_ctxt_desc *p,
-					int is_vlanvalid, int vlan_tag);
+					 int is_vlanvalid, int vlan_tag);
 
 	/* Return VLAN Tag */
 	int (*tx_ctxt_desc_get_vlantag)(struct xgmac_tx_ctxt_desc *p);
 
 	/* Set Time stamp */
 	void (*tx_ctxt_set_tstamp)(struct xgmac_tx_ctxt_desc *p,
-					u8 ostc_enable, u64 tstamp);
+				   u8 ostc_enable, u64 tstamp);
 
 	/* Close TX context descriptor */
 	void (*close_tx_ctxt_desc)(struct xgmac_tx_ctxt_desc *p);

@@ -255,7 +255,7 @@ struct xgmac_desc_ops {
 
 	/* DMA RX descriptor ring initialization */
 	void (*init_rx_desc)(struct xgmac_rx_norm_desc *p, int disable_rx_ic,
-				int mode, int end);
+			     int mode, int end);
 
 	/* Get own bit */
 	int (*get_rx_owner)(struct xgmac_rx_norm_desc *p);

index 9a22990a..e606ea7 100644
@@ -32,7 +32,7 @@ static int xgmac_dma_init(void __iomem *ioaddr, int fix_burst,
 	writel(XGMAC_DMA_SOFT_RESET, ioaddr + XGMAC_DMA_MODE_REG);
 	while (retry_count--) {
 		if (!(readl(ioaddr + XGMAC_DMA_MODE_REG) &
-			XGMAC_DMA_SOFT_RESET))
+		      XGMAC_DMA_SOFT_RESET))
 			break;
 		mdelay(10);
 	}

@@ -63,8 +63,8 @@ static int xgmac_dma_init(void __iomem *ioaddr, int fix_burst,
 }
 
 static void xgmac_dma_channel_init(void __iomem *ioaddr, int cha_num,
-				int fix_burst, int pbl, dma_addr_t dma_tx,
-				dma_addr_t dma_rx, int t_rsize, int r_rsize)
+				   int fix_burst, int pbl, dma_addr_t dma_tx,
+				   dma_addr_t dma_rx, int t_rsize, int r_rsize)
 {
 	u32 reg_val;
 	dma_addr_t dma_addr;

@@ -205,7 +205,7 @@ static void xgmac_dma_stop_rx(void __iomem *ioaddr, int rchannels)
 }
 
 static int xgmac_tx_dma_int_status(void __iomem *ioaddr, int channel_no,
-			      struct xgmac_extra_stats *x)
+				   struct xgmac_extra_stats *x)
 {
 	u32 int_status = readl(ioaddr + XGMAC_DMA_CHA_STATUS_REG(channel_no));
 	u32 clear_val = 0;

@@ -254,7 +254,7 @@ static int xgmac_tx_dma_int_status(void __iomem *ioaddr, int channel_no,
 				x->tx_desc_access_err++;
 				clear_val |= XGMAC_DMA_INT_STATUS_TEB1;
 			} else {
-				 x->tx_buffer_access_err++;
+				x->tx_buffer_access_err++;
 			}
 
 			if (int_status & XGMAC_DMA_INT_STATUS_TEB2) {

@@ -277,7 +277,7 @@ static int xgmac_tx_dma_int_status(void __iomem *ioaddr, int channel_no,
 }
 
 static int xgmac_rx_dma_int_status(void __iomem *ioaddr, int channel_no,
-			      struct xgmac_extra_stats *x)
+				   struct xgmac_extra_stats *x)
 {
 	u32 int_status = readl(ioaddr + XGMAC_DMA_CHA_STATUS_REG(channel_no));
 	u32 clear_val = 0;

@@ -326,7 +326,7 @@ static int xgmac_rx_dma_int_status(void __iomem *ioaddr, int channel_no,
 				x->rx_desc_access_err++;
 				clear_val |= XGMAC_DMA_INT_STATUS_REB1;
 			} else {
-				 x->rx_buffer_access_err++;
+				x->rx_buffer_access_err++;
 			}
 
 			if (int_status & XGMAC_DMA_INT_STATUS_REB2) {

index 022fd2b..64ccd91 100644
@@ -23,10 +23,10 @@ struct xgmac_extra_stats;
 struct xgmac_dma_ops {
 	/* DMA core initialization */
 	int (*init)(void __iomem *ioaddr, int fix_burst,
-		     int burst_map, int enhance_amode);
+		    int burst_map, int enhance_amode);
 	void (*cha_init)(void __iomem *ioaddr, int cha_num, int fix_burst,
-			int pbl, dma_addr_t dma_tx, dma_addr_t dma_rx,
-			int t_rzie, int r_rsize);
+			 int pbl, dma_addr_t dma_tx, dma_addr_t dma_rx,
+			 int t_rzie, int r_rsize);
 	void (*enable_dma_transmission)(void __iomem *ioaddr, int dma_cnum);
 	void (*enable_dma_irq)(void __iomem *ioaddr, int dma_cnum);
 	void (*disable_dma_irq)(void __iomem *ioaddr, int dma_cnum);

@@ -37,9 +37,9 @@ struct xgmac_dma_ops {
 	void (*start_rx)(void __iomem *ioaddr, int rchannels);
 	void (*stop_rx)(void __iomem *ioaddr, int rchannels);
 	int (*tx_dma_int_status)(void __iomem *ioaddr, int channel_no,
-			      struct xgmac_extra_stats *x);
+				 struct xgmac_extra_stats *x);
 	int (*rx_dma_int_status)(void __iomem *ioaddr, int channel_no,
-			      struct xgmac_extra_stats *x);
+				 struct xgmac_extra_stats *x);
 	/* Program the HW RX Watchdog */
 	void (*rx_watchdog)(void __iomem *ioaddr, u32 riwt);
 	/* Enable TSO for each DMA channel */

index 378f6f1..46198bf 100644
@@ -30,9 +30,12 @@ struct xgmac_stats {
 	int stat_offset;
 };
 
-#define XGMAC_STAT(m)	\
-	{ #m, FIELD_SIZEOF(struct xgmac_extra_stats, m),	\
-	offsetof(struct xgmac_priv_data, xstats.m)}
+#define XGMAC_STAT(m)						\
+{								\
+	#m,							\
+	FIELD_SIZEOF(struct xgmac_extra_stats, m),		\
+	offsetof(struct xgmac_priv_data, xstats.m)		\
+}
 
 static const struct xgmac_stats xgmac_gstrings_stats[] = {
 	/* TX/RX IRQ events */

@@ -134,7 +137,7 @@ static const struct xgmac_stats xgmac_gstrings_stats[] = {
 #define XGMAC_STATS_LEN ARRAY_SIZE(xgmac_gstrings_stats)
 
 static int xgmac_get_eee(struct net_device *dev,
-				     struct ethtool_eee *edata)
+			 struct ethtool_eee *edata)
 {
 	struct xgmac_priv_data *priv = netdev_priv(dev);
 

@@ -149,7 +152,7 @@ static int xgmac_get_eee(struct net_device *dev,
 }
 
 static int xgmac_set_eee(struct net_device *dev,
-				     struct ethtool_eee *edata)
+			 struct ethtool_eee *edata)
 {
 	struct xgmac_priv_data *priv = netdev_priv(dev);
 

@@ -217,14 +220,14 @@ static int xgmac_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 }
 
 static void xgmac_getdrvinfo(struct net_device *dev,
-				     struct ethtool_drvinfo *info)
+			     struct ethtool_drvinfo *info)
 {
 	strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
 	strlcpy(info->version, DRV_VERSION, sizeof(info->version));
 }
 
 static int xgmac_getsettings(struct net_device *dev,
-				     struct ethtool_cmd *cmd)
+			     struct ethtool_cmd *cmd)
 {
 	struct xgmac_priv_data *priv = netdev_priv(dev);
 

@@ -257,7 +260,7 @@ static void xgmac_setmsglevel(struct net_device *dev, u32 level)
 }
 
 static int xgmac_get_ts_info(struct net_device *dev,
-				     struct ethtool_ts_info *info)
+			     struct ethtool_ts_info *info)
 {
 	struct xgmac_priv_data *priv = netdev_priv(dev);
 

@@ -370,12 +373,12 @@ static void xgmac_get_ethtool_stats(struct net_device *dev,
 	for (i = 0; i < XGMAC_STATS_LEN; i++) {
 		p = (char *)priv + xgmac_gstrings_stats[i].stat_offset;
 		data[j++] = (xgmac_gstrings_stats[i].sizeof_stat == sizeof(u64))
-				? (*(u64 *)p) : (*(u32 *)p);
+			? (*(u64 *)p) : (*(u32 *)p);
 	}
 }
 
 static void xgmac_get_channels(struct net_device *dev,
-		struct ethtool_channels *channel)
+			       struct ethtool_channels *channel)
 {
 	channel->max_rx = XGMAC_MAX_RX_CHANNELS;
 	channel->max_tx = XGMAC_MAX_TX_CHANNELS;

291 lines not on this page · raw message

index 5e1e40e..6d85b65 100644
@@ -67,30 +67,28 @@ static int xgmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
 	if (phyreg & MII_ADDR_C45) {
 		devaddr = (phyreg >> 16) & 0x1F;
 		/* set mdio address register */
-		reg_val = (phyaddr << 16) | (devaddr << 21) |
-			  (phyreg & 0xFFFF);
+		reg_val = (phyaddr << 16) | (devaddr << 21) | (phyreg & 0xFFFF);
 		writel(reg_val, priv->ioaddr + mii_addr);
 
 		/* set mdio control/data register */
-		reg_val = (XGMAC_SMA_READ_CMD << 16) | XGMAC_SMA_SKIP_ADDRFRM |
-			  ((priv->clk_csr & 0x7) << 19) | XGMAC_MII_BUSY;
+		reg_val = ((XGMAC_SMA_READ_CMD << 16) | XGMAC_SMA_SKIP_ADDRFRM |
+			   ((priv->clk_csr & 0x7) << 19) | XGMAC_MII_BUSY);
 		writel(reg_val, priv->ioaddr + mii_data);
 	} else {
 		/* configure the port for C22
 		 * ports 0-3 only supports C22
 		 */
-		if (phyaddr < 4)
-			writel((1 << phyaddr),
-			       priv->ioaddr + XGMAC_MDIO_CLAUSE22_PORT_REG);
-		else
+		if (phyaddr >= 4)
 			return -ENODEV;
+		writel((1 << phyaddr),
+		       priv->ioaddr + XGMAC_MDIO_CLAUSE22_PORT_REG);
 		/* set mdio address register */
 		reg_val = (phyaddr << 16) | (phyreg & 0x1F);
 		writel(reg_val, priv->ioaddr + mii_addr);
 
 		/* set mdio control/data register */
-		reg_val = (XGMAC_SMA_READ_CMD << 16) | XGMAC_SMA_SKIP_ADDRFRM |
-			  ((priv->clk_csr & 0x7) << 19) | XGMAC_MII_BUSY;
+		reg_val = ((XGMAC_SMA_READ_CMD << 16) | XGMAC_SMA_SKIP_ADDRFRM |
+			   ((priv->clk_csr & 0x7) << 19) | XGMAC_MII_BUSY);
 		writel(reg_val, priv->ioaddr + mii_data);
 	}
 

@@ -111,7 +109,7 @@ static int xgmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
  * Description: this function is used for C45 and C22 MDIO write
  */
 static int xgmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
-			     u16 phydata)
+			    u16 phydata)
 {
 	struct net_device *ndev = bus->priv;
 	struct xgmac_priv_data *priv = netdev_priv(ndev);

@@ -126,13 +124,13 @@ static int xgmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
 	if (phyreg & MII_ADDR_C45) {
 		devaddr = (phyreg >> 16) & 0x1F;
 		/* set mdio address register */
-		reg_val = (phyaddr << 16) | (devaddr << 21) |
-			  (phyreg & 0xFFFF);
+		reg_val = (phyaddr << 16) | (devaddr << 21) | (phyreg & 0xFFFF);
 		writel(reg_val, priv->ioaddr + mii_addr);
 
 		/* set mdio control/data register */
-		reg_val = (XGMAC_SMA_WRITE_CMD << 16) | XGMAC_SMA_SKIP_ADDRFRM |
-			  ((priv->clk_csr & 0x7) << 19) | XGMAC_MII_BUSY;
+		reg_val = ((XGMAC_SMA_WRITE_CMD << 16) |
+			   XGMAC_SMA_SKIP_ADDRFRM |
+			   ((priv->clk_csr & 0x7) << 19) | XGMAC_MII_BUSY);
 		reg_val |= phydata;
 
 		writel(reg_val, priv->ioaddr + mii_data);

@@ -151,8 +149,9 @@ static int xgmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
 		writel(reg_val, priv->ioaddr + mii_addr);
 
 		/* set mdio control/data register */
-		reg_val = (XGMAC_SMA_WRITE_CMD << 16) | XGMAC_SMA_SKIP_ADDRFRM |
-			  ((priv->clk_csr & 0x7) << 19) | XGMAC_MII_BUSY;
+		reg_val = ((XGMAC_SMA_WRITE_CMD << 16) |
+			   XGMAC_SMA_SKIP_ADDRFRM |
+			   ((priv->clk_csr & 0x7) << 19) | XGMAC_MII_BUSY);
 		reg_val |= phydata;
 		writel(reg_val, priv->ioaddr + mii_data);
 	}

index 2edad0f..0c1e100 100644
@@ -61,7 +61,7 @@ static void xgmac_mtl_dma_dm_rxqueue(void __iomem *ioaddr)
 }
 
 static void xgmac_mtl_set_txfifosize(void __iomem *ioaddr, int queue_num,
-				int queue_fifo)
+				     int queue_fifo)
 {
 	u32 fifo_bits, reg_val;
 	/* 0 means 256 bytes */

@@ -72,7 +72,7 @@ static void xgmac_mtl_set_txfifosize(void __iomem *ioaddr, int queue_num,
 }
 
 static void xgmac_mtl_set_rxfifosize(void __iomem *ioaddr, int queue_num,
-				int queue_fifo)
+				     int queue_fifo)
 {
 	u32 fifo_bits, reg_val;
 	/* 0 means 256 bytes */

index bacd5e3..2c80753 100644
@@ -62,31 +62,31 @@ enum flow_control_th {
 
 struct xgmac_mtl_ops {
 	void (*mtl_init)(void __iomem *ioaddr, unsigned int etsalg,
-			unsigned int raa);
+			 unsigned int raa);
 
 	void (*mtl_set_txfifosize)(void __iomem *ioaddr, int queue_num,
-				    int mtl_fifo);
+				   int mtl_fifo);
 
 	void (*mtl_set_rxfifosize)(void __iomem *ioaddr, int queue_num,
-					  int queue_fifo);
+				   int queue_fifo);
 
 	void (*mtl_enable_txqueue)(void __iomem *ioaddr, int queue_num);
 
 	void (*mtl_disable_txqueue)(void __iomem *ioaddr, int queue_num);
 
 	void (*set_tx_mtl_mode)(void __iomem *ioaddr, int queue_num,
-				 int tx_mode);
+				int tx_mode);
 
 	void (*set_rx_mtl_mode)(void __iomem *ioaddr, int queue_num,
-				 int rx_mode);
+				int rx_mode);
 
 	void (*mtl_dynamic_dma_rxqueue)(void __iomem *ioaddr);
 
 	void (*mtl_fc_active)(void __iomem *ioaddr, int queue_num,
-			       int threshold);
+			      int threshold);
 
 	void (*mtl_fc_deactive)(void __iomem *ioaddr, int queue_num,
-				 int threshold);
+				int threshold);
 
 	void (*mtl_fc_enable)(void __iomem *ioaddr, int queue_num);
 

index fb80c2c..d56602c 100644
@@ -28,8 +28,8 @@
 
 #ifdef CONFIG_OF
 static int xgmac_probe_config_dt(struct platform_device *pdev,
-				  struct xgmac_plat_data *plat,
-				  const char **mac)
+				 struct xgmac_plat_data *plat,
+				 const char **mac)
 {
 	struct device_node *np = pdev->dev.of_node;
 	struct xgmac_dma_cfg *dma_cfg;

@@ -55,7 +55,7 @@ static int xgmac_probe_config_dt(struct platform_device *pdev,
 		plat->pmt = 1;
 
 	plat->force_sf_dma_mode = of_property_read_bool(np,
-					"samsung,force_sf_dma_mode");
+							"samsung,force_sf_dma_mode");
 
 	dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*dma_cfg), GFP_KERNEL);
 	if (!dma_cfg)

@@ -66,10 +66,10 @@ static int xgmac_probe_config_dt(struct platform_device *pdev,
 	of_property_read_u32(np, "samsung,burst-map", &dma_cfg->burst_map);
 	dma_cfg->fixed_burst = of_property_read_bool(np, "samsung,fixed-burst");
 	dma_cfg->adv_addr_mode = of_property_read_bool(np,
-							"samsung,adv-addr-mode");
+						       "samsung,adv-addr-mode");
 
 	plat->force_thresh_dma_mode = of_property_read_bool(np,
-					"samsung,force_thresh_dma_mode");
+							    "samsung,force_thresh_dma_mode");
 	if (plat->force_thresh_dma_mode) {
 		plat->force_sf_dma_mode = 0;
 		pr_warn("force_sf_dma_mode is ignored as force_thresh_dma_mode is set\n");

@@ -79,8 +79,8 @@ static int xgmac_probe_config_dt(struct platform_device *pdev,
 }
 #else
 static int xgmac_probe_config_dt(struct platform_device *pdev,
-				  struct xgmac_plat_data *plat,
-				  const char **mac)
+				 struct xgmac_plat_data *plat,
+				 const char **mac)
 {
 	return -ENOSYS;
 }

@@ -119,8 +119,8 @@ static int xgmac_platform_probe(struct platform_device *pdev)
 	if (pdev->dev.of_node) {
 		if (!plat_dat)
 			plat_dat = devm_kzalloc(&pdev->dev,
-					sizeof(struct xgmac_plat_data),
-					GFP_KERNEL);
+						sizeof(struct xgmac_plat_data),
+						GFP_KERNEL);
 		if (!plat_dat)
 			return  -ENOMEM;
 

@@ -249,11 +249,11 @@ struct platform_driver xgmac_platform_driver = {
 	.probe = xgmac_platform_probe,
 	.remove = xgmac_platform_remove,
 	.driver = {
-		   .name = XGMAC_RESOURCE_NAME,
-		   .owner = THIS_MODULE,
-		   .pm = &xgmac_platform_pm_ops,
-		   .of_match_table = of_match_ptr(xgmac_dt_ids),
-		   },
+		.name = XGMAC_RESOURCE_NAME,
+		.owner = THIS_MODULE,
+		.pm = &xgmac_platform_pm_ops,
+		.of_match_table = of_match_ptr(xgmac_dt_ids),
+	},
 };
 
 int xgmac_register_platform(void)

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