ARM: SPEAr13xx: Add PCIe support

From: Pratyush Anand <[email protected]>

ARM based ST Microelectronics's SPEAr1310 and SPEAr1340 SOCs have onchip designware PCIe controller. To make that usable, this patch adds a wrapper driver based on existing designware driver.

Adds bindings for this new driver and update MAINTAINERS as well.

Cc linux-pci at vger.kernel.org

Acked-by Arnd Bergmann <[email protected]>

Acked-by Bjorn Helgaas <[email protected]>

Acked-by Jingoo Han <[email protected]>

Signed-off-by Pratyush Anand <[email protected]>

Signed-off-by Mohit Kumar <[email protected]>

[viresh: fixed logs/cclist/checkpatch warnings, broken into smaller patches]

Signed-off-by Viresh Kumar <[email protected]>

MAINTAINERS +0 -0

index 702ca10..443dd05 100644

I guess I'm obsessive, but I think it's nice when people run "git log --oneline" on the file or directory they're changing, and then follow the existing style.

In this case, that would lead to a subject line like:

PCI: spear: Add PCIe driver for ST Microelectronics SPEAr13xx

Quoted 6 lines

MAINTAINERS +0 -0

index 702ca10..443dd05 100644

MAINTAINERS S: Maintained · line 6827

Quoted 8 lines

MAINTAINERS +5 -0

@@ -6820,6 +6820,12 @@ S:     Maintained
 F:   Documentation/devicetree/bindings/pci/host-generic-pci.txt
 F:   drivers/pci/host/pci-host-generic.c
 
+PCIE DRIVER FOR ST SPEAR13XX
+M:   Mohit Kumar <[email protected]>
+L:   linux-pci at vger.kernel.org
+S:   Maintained
+F:   drivers/pci/host/pcie-spear13xx.c

Wildcards work here, so you could follow the lead of IMX6, MVEBU, RCAR, and DESIGNWARE and use:

F: drivers/pci/host/*spear*

drivers/pci/host/pcie-spear13xx.c line 142

Quoted 4 lines

drivers/pci/host/pcie-spear13xx.c new file +1 -0

...
+#define PCI_CAP_ID_EXP_OFFSET                        0x70

A nit, but I'd use a name like EXP_CAP_ID_OFFSET to make it more clear that this is specific to SPEAr, not something from the PCI specs.

I guess I'm obsessive, but I think it's nice when people run "git log --oneline" on the file or directory they're changing, and then follow the existing style.

In this case, that would lead to a subject line like:

PCI: spear: Add PCIe driver for ST Microelectronics SPEAr13xx

MAINTAINERS S: Maintained · line 6827

Quoted 13 lines

MAINTAINERS +5 -0

index 702ca10..443dd05 100644
@@ -6820,6 +6820,12 @@ S:     Maintained
 F:   Documentation/devicetree/bindings/pci/host-generic-pci.txt
 F:   drivers/pci/host/pci-host-generic.c
 
+PCIE DRIVER FOR ST SPEAR13XX
+M:   Mohit Kumar <[email protected]>
+L:   linux-pci at vger.kernel.org
+S:   Maintained
+F:   drivers/pci/host/pcie-spear13xx.c

Wildcards work here, so you could follow the lead of IMX6, MVEBU, RCAR, and DESIGNWARE and use:

F: drivers/pci/host/*spear*

drivers/pci/host/pcie-spear13xx.c

Quoted 4 lines

drivers/pci/host/pcie-spear13xx.c new file +1 -0

...
+#define PCI_CAP_ID_EXP_OFFSET                        0x70

A nit, but I'd use a name like EXP_CAP_ID_OFFSET to make it more clear that this is specific to SPEAr, not something from the PCI specs.

From: Pratyush Anand <[email protected]>

ARM based ST Microelectronics's SPEAr1310/40 platforms uses ST's phy (known as 'miphy') for PCIe and SATA. This patch adds drivers for these miphys.

This also adds proper bindings for miphys.

Acked-by Arnd Bergmann <[email protected]>

Signed-off-by Pratyush Anand <[email protected]>

Tested-by Mohit Kumar <[email protected]>

Cc Kishon Vijay Abraham I <[email protected]>

[viresh: fixed logs/cclist/checkpatch warnings, broken into smaller patches]

Signed-off-by Viresh Kumar <[email protected]>

---
 .../devicetree/bindings/phy/st-spear1310-miphy.txt |  12 +
 .../devicetree/bindings/phy/st-spear1340-miphy.txt |  11 +
 drivers/phy/Kconfig                                |  12 +
 drivers/phy/Makefile                               |   2 +
 drivers/phy/phy-spear1310-miphy.c                  | 274 +++++++++++++++++++
 drivers/phy/phy-spear1340-miphy.c                  | 302 +++++++++++++++++++++

Documentation/devicetree/bindings/phy/st-spear1340-miphy.txt new file +11 -0

@@ -0,0 +1,11 @@
+ST SPEAr1340-miphy DT detail
+===================================
+
+SPEAr1340-miphy is a phy controller supporting PCIe and SATA.
+
+Required properties:
+- compatible : should be "st,spear1340-miphy"
+- reg : offset and length of the PHY register set.
+- misc: phandle for the syscon node to access misc registers
+- #phy-cells : from the generic PHY bindings, must be 1.
+	- cell[1]: 0 if phy used for SATA, 1 for PCIe.

drivers/phy/Kconfig +0 -0

index 16a2f06..e8f8a2d 100644

drivers/phy/Kconfig +8 -0

+
+static int spear1340_miphy_sata_init(struct spear1340_miphy_priv *priv)
+{
+	regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
+			   SPEAR1340_PCIE_SATA_CFG_MASK,
+			   SPEAR1340_SATA_CFG_VAL);
+	regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+			   SPEAR1340_PCIE_MIPHY_CFG_MASK,

drivers/phy/Kconfig +10 -0

+
+	return 0;
+}
+
+static int spear1340_miphy_sata_exit(struct spear1340_miphy_priv *priv)
+{
+	regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
+			   SPEAR1340_PCIE_SATA_CFG_MASK, 0);
+	regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+			   SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);

drivers/phy/Kconfig +62 -0

+
+	return 0;
+}
+
+static int spear1340_miphy_pcie_init(struct spear1340_miphy_priv *priv)
+{
+	regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+			   SPEAR1340_PCIE_MIPHY_CFG_MASK,
+			   SPEAR1340_PCIE_SATA_MIPHY_CFG_PCIE);
+	regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
+			   SPEAR1340_PCIE_SATA_CFG_MASK,
+			   SPEAR1340_PCIE_CFG_VAL);
+
+	return 0;
+}
+
+static int spear1340_miphy_pcie_exit(struct spear1340_miphy_priv *priv)
+{
+	regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+			   SPEAR1340_PCIE_MIPHY_CFG_MASK, 0);
+	regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
+			   SPEAR1340_PCIE_SATA_CFG_MASK, 0);
+
+	return 0;
+}
+
+static int spear1340_miphy_init(struct phy *phy)
+{
+	struct spear1340_miphy_priv *priv = phy_get_drvdata(phy);
+	int ret = 0;
+
+	if (priv->mode == SATA)
+		ret = spear1340_miphy_sata_init(priv);
+	else if (priv->mode == PCIE)
+		ret = spear1340_miphy_pcie_init(priv);
+
+	return ret;
+}
+
+static int spear1340_miphy_exit(struct phy *phy)
+{
+	struct spear1340_miphy_priv *priv = phy_get_drvdata(phy);
+	int ret = 0;
+
+	if (priv->mode == SATA)
+		ret = spear1340_miphy_sata_exit(priv);
+	else if (priv->mode == PCIE)
+		ret = spear1340_miphy_pcie_exit(priv);
+
+	return ret;
+}
+
+static const struct of_device_id spear1340_miphy_of_match[] = {
+	{ .compatible = "st,spear1340-miphy" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, spear1340_miphy_of_match);
+
+static struct phy_ops spear1340_miphy_ops = {
+	.init = spear1340_miphy_init,
+	.exit = spear1340_miphy_exit,
+	.owner = THIS_MODULE,

Quoted 13 lines · Viresh Kumar

From: Pratyush Anand <[email protected]>

ARM based ST Microelectronics's SPEAr1310/40 platforms uses ST's phy (known as 'miphy') for PCIe and SATA. This patch adds drivers for these miphys.

This also adds proper bindings for miphys.

Acked-by Arnd Bergmann <[email protected]>

Signed-off-by Pratyush Anand <[email protected]>

Tested-by Mohit Kumar <[email protected]>

Cc Kishon Vijay Abraham I <[email protected]>

[viresh: fixed logs/cclist/checkpatch warnings, broken into smaller patches]

Signed-off-by Viresh Kumar <[email protected]>

Quoted 7 lines

---
 .../devicetree/bindings/phy/st-spear1310-miphy.txt |  12 +
 .../devicetree/bindings/phy/st-spear1340-miphy.txt |  11 +
 drivers/phy/Kconfig                                |  12 +
 drivers/phy/Makefile                               |   2 +
 drivers/phy/phy-spear1310-miphy.c                  | 274 +++++++++++++++++++
 drivers/phy/phy-spear1340-miphy.c                  | 302 +++++++++++++++++++++

Please send separate patche for each driver.

Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt

Quoted 5 lines

Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt new file +0 -0

new file mode 100644
index 0000000..b9b281a

We generally create a single document for a SoC vendor. So just use st-phy.txt.

<snip>

Quoted 12 lines

Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt new file +12 -0

+
+static int spear1340_miphy_sata_init(struct spear1340_miphy_priv *priv)
+{
+     regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
+                        SPEAR1340_PCIE_SATA_CFG_MASK,
+                        SPEAR1340_SATA_CFG_VAL);
+     regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+                        SPEAR1340_PCIE_MIPHY_CFG_MASK,
+                        SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
+     /* Switch on sata power domain */
+     regmap_update_bits(priv->misc, SPEAR1340_PCM_CFG,
+                        SPEAR1340_PCM_CFG_SATA_POWER_EN,

Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt

Quoted 6 lines

Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt new file +6 -0

+                        SPEAR1340_PCM_CFG_SATA_POWER_EN);
+     msleep(20);
+     /* Disable PCIE SATA Controller reset */
+     regmap_update_bits(priv->misc, SPEAR1340_PERIP1_SW_RST,
+                        SPEAR1340_PERIP1_SW_RSATA, 0);
+     msleep(20);

Please add a comment for all delays added.

Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt

Quoted 8 lines

Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt new file +8 -0

+#ifdef CONFIG_PM_SLEEP
+static int spear1340_miphy_suspend(struct device *dev)
+{
+     struct spear1340_miphy_priv *priv = dev_get_drvdata(dev);
+     int ret = 0;
+
+     if (priv->mode == SATA)
+             ret = spear1340_miphy_sata_exit(priv);

Shouldn't this be spear1340_miphy_init()?

Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt

Quoted 11 lines

Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt new file +11 -0

+
+     return ret;
+}
+
+static int spear1340_miphy_resume(struct device *dev)
+{
+     struct spear1340_miphy_priv *priv = dev_get_drvdata(dev);
+     int ret = 0;
+
+     if (priv->mode == SATA)
+             ret = spear1340_miphy_sata_init(priv);

And here spear1340_miphy_exit()? Why only for sata phys?

Quoted 22 lines · Kishon Vijay Abraham I

Quoted 13 lines · Viresh Kumar

From: Pratyush Anand <[email protected]>

ARM based ST Microelectronics's SPEAr1310/40 platforms uses ST's phy (known as 'miphy') for PCIe and SATA. This patch adds drivers for these miphys.

This also adds proper bindings for miphys.

Acked-by Arnd Bergmann <[email protected]>

Signed-off-by Pratyush Anand <[email protected]>

Tested-by Mohit Kumar <[email protected]>

Cc Kishon Vijay Abraham I <[email protected]>

[viresh: fixed logs/cclist/checkpatch warnings, broken into smaller patches]

Signed-off-by Viresh Kumar <[email protected]>

Quoted 7 lines

---
 .../devicetree/bindings/phy/st-spear1310-miphy.txt |  12 +
 .../devicetree/bindings/phy/st-spear1340-miphy.txt |  11 +
 drivers/phy/Kconfig                                |  12 +
 drivers/phy/Makefile                               |   2 +
 drivers/phy/phy-spear1310-miphy.c                  | 274 +++++++++++++++++++
 drivers/phy/phy-spear1340-miphy.c                  | 302 +++++++++++++++++++++

Quoted 1 line

Please send separate patche for each driver.

These were both around SPEAr and were on the same lines.
So sending these in a single patch shouldn't be a big issue I believe.

In case another version is required, I may do it.

Quoted 7 lines

Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt

Quoted 5 lines

Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt new file +0 -0

new file mode 100644
index 0000000..b9b281a

We generally create a single document for a SoC vendor. So just use st-phy.txt.

Probably yes.

Quoted 1 line

<snip>

Please keep line containing file names while removing stuff, makes it easy to locate code.

Quoted 13 lines

Quoted 13 lines

Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt new file +12 -0

+
+static int spear1340_miphy_sata_init(struct spear1340_miphy_priv *priv)
+{
+     regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
+                        SPEAR1340_PCIE_SATA_CFG_MASK,
+                        SPEAR1340_SATA_CFG_VAL);
+     regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+                        SPEAR1340_PCIE_MIPHY_CFG_MASK,
+                        SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
+     /* Switch on sata power domain */
+     regmap_update_bits(priv->misc, SPEAR1340_PCM_CFG,
+                        SPEAR1340_PCM_CFG_SATA_POWER_EN,

Quoted 8 lines

Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt

Quoted 6 lines

Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt new file +6 -0

+                        SPEAR1340_PCM_CFG_SATA_POWER_EN);
+     msleep(20);
+     /* Disable PCIE SATA Controller reset */
+     regmap_update_bits(priv->misc, SPEAR1340_PERIP1_SW_RST,
+                        SPEAR1340_PERIP1_SW_RSATA, 0);
+     msleep(20);

Please add a comment for all delays added.

@Pratyush/Mohit: please let me know what to add here.

Quoted 10 lines

Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt

Quoted 8 lines

Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt new file +8 -0

+#ifdef CONFIG_PM_SLEEP
+static int spear1340_miphy_suspend(struct device *dev)
+{
+     struct spear1340_miphy_priv *priv = dev_get_drvdata(dev);
+     int ret = 0;
+
+     if (priv->mode == SATA)
+             ret = spear1340_miphy_sata_exit(priv);

Shouldn't this be spear1340_miphy_init()?

Quoted 13 lines

Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt

Quoted 11 lines

Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt new file +11 -0

+
+     return ret;
+}
+
+static int spear1340_miphy_resume(struct device *dev)
+{
+     struct spear1340_miphy_priv *priv = dev_get_drvdata(dev);
+     int ret = 0;
+
+     if (priv->mode == SATA)
+             ret = spear1340_miphy_sata_init(priv);

And here spear1340_miphy_exit()? Why only for sata phys?

@Mohit/Pratyush ??

Thanks Kishon for another round of review :)

Quoted 22 lines · Kishon Vijay Abraham I

Quoted 20 lines · Viresh Kumar

From: Pratyush Anand <[email protected]>

ARM based ST Microelectronics's SPEAr1310/40 platforms uses ST's phy (known as 'miphy') for PCIe and SATA. This patch adds drivers for these miphys.

This also adds proper bindings for miphys.

Acked-by Arnd Bergmann <[email protected]>

Signed-off-by Pratyush Anand <[email protected]>

Tested-by Mohit Kumar <[email protected]>

Cc Kishon Vijay Abraham I <[email protected]>

[viresh: fixed logs/cclist/checkpatch warnings, broken into smaller patches]

Signed-off-by Viresh Kumar <[email protected]>

---
 .../devicetree/bindings/phy/st-spear1310-miphy.txt |  12 +
 .../devicetree/bindings/phy/st-spear1340-miphy.txt |  11 +
 drivers/phy/Kconfig                                |  12 +
 drivers/phy/Makefile                               |   2 +
 drivers/phy/phy-spear1310-miphy.c                  | 274 +++++++++++++++++++
 drivers/phy/phy-spear1340-miphy.c                  | 302 +++++++++++++++++++++

Quoted 1 line

Please send separate patche for each driver.

These were both around SPEAr and were on the same lines.
So sending these in a single patch shouldn't be a big issue I believe.

In case another version is required, I may do it.

Quoted 8 lines

Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt

Quoted 6 lines

Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt new file +0 -0

new file mode 100644
index 0000000..b9b281a

We generally create a single document for a SoC vendor. So just use st-phy.txt.

Probably yes.

Quoted 1 line

<snip>

Please keep line containing file names while removing stuff, makes it easy to locate code.

Quoted 12 lines

Quoted 12 lines

Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt new file +12 -0

+
+static int spear1340_miphy_sata_init(struct spear1340_miphy_priv *priv)
+{
+     regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
+                        SPEAR1340_PCIE_SATA_CFG_MASK,
+                        SPEAR1340_SATA_CFG_VAL);
+     regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+                        SPEAR1340_PCIE_MIPHY_CFG_MASK,
+                        SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);
+     /* Switch on sata power domain */
+     regmap_update_bits(priv->misc, SPEAR1340_PCM_CFG,
+                        SPEAR1340_PCM_CFG_SATA_POWER_EN,

Quoted 8 lines

Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt

Quoted 6 lines

Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt new file +6 -0

+                        SPEAR1340_PCM_CFG_SATA_POWER_EN);
+     msleep(20);
+     /* Disable PCIE SATA Controller reset */
+     regmap_update_bits(priv->misc, SPEAR1340_PERIP1_SW_RST,
+                        SPEAR1340_PERIP1_SW_RSATA, 0);
+     msleep(20);

Please add a comment for all delays added.

@Pratyush/Mohit: please let me know what to add here.

Quoted 10 lines

Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt

Quoted 8 lines

Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt new file +8 -0

+#ifdef CONFIG_PM_SLEEP
+static int spear1340_miphy_suspend(struct device *dev)
+{
+     struct spear1340_miphy_priv *priv = dev_get_drvdata(dev);
+     int ret = 0;
+
+     if (priv->mode == SATA)
+             ret = spear1340_miphy_sata_exit(priv);

Shouldn't this be spear1340_miphy_init()?

Quoted 13 lines

Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt

Quoted 11 lines

Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt new file +11 -0

+
+     return ret;
+}
+
+static int spear1340_miphy_resume(struct device *dev)
+{
+     struct spear1340_miphy_priv *priv = dev_get_drvdata(dev);
+     int ret = 0;
+
+     if (priv->mode == SATA)
+             ret = spear1340_miphy_sata_init(priv);

And here spear1340_miphy_exit()? Why only for sata phys?

@Mohit/Pratyush ??

Thanks Kishon for another round of review :)

-----Original Message-----
From: Kishon Vijay Abraham I [mailto:kishon at ti.com]
Sent: Friday, July 11, 2014 2:03 PM
To: Viresh Kumar
Cc: Arnd Bergmann; olof at lixom.net; linux-arm-kernel at lists.infradead.org; spear-devel; Bartlomiej Zolnierkiewicz; Bjorn Helgaas; Mark Nicholson; linux- pci at vger.kernel.org; Pratyush ANAND
Subject: Re: [PATCH V9 2/7] phy: Add drivers for PCIe and SATA phy on SPEAr13xx

Quoted 4 lines · Viresh Kumar

Quoted 3 lines · Kishon Vijay Abraham I

Quoted 2 lines · Viresh Kumar

From: Pratyush Anand <[email protected]>

Quoted 9 lines

Quoted 9 lines

drivers/phy/phy-spear1340-miphy.c line 109

Quoted 9 lines

drivers/phy/phy-spear1340-miphy.c new file +9 -0

+
+static int spear1340_miphy_sata_init(struct spear1340_miphy_priv
+*priv) {
+     regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG,
+                        SPEAR1340_PCIE_SATA_CFG_MASK,
+                        SPEAR1340_SATA_CFG_VAL);
+     regmap_update_bits(priv->misc, SPEAR1340_PCIE_MIPHY_CFG,
+                        SPEAR1340_PCIE_MIPHY_CFG_MASK,
+

SPEAR1340_PCIE_SATA_MIPHY_CFG_SATA_25M_CRYSTAL_CLK);

Quoted 14 lines

Quoted 11 lines

drivers/phy/phy-spear1340-miphy.c line 108

Quoted 9 lines

drivers/phy/phy-spear1340-miphy.c new file +9 -0

+     /* Switch on sata power domain */
+     regmap_update_bits(priv->misc, SPEAR1340_PCM_CFG,
+                        SPEAR1340_PCM_CFG_SATA_POWER_EN,
+                        SPEAR1340_PCM_CFG_SATA_POWER_EN);
+     msleep(20);
+     /* Disable PCIE SATA Controller reset */
+     regmap_update_bits(priv->misc, SPEAR1340_PERIP1_SW_RST,
+                        SPEAR1340_PERIP1_SW_RSATA, 0);
+     msleep(20);

Please add a comment for all delays added.

@Pratyush/Mohit: please let me know what to add here.

- I think we should read regmap_*() and msleep() in continuation and so the comment above it is valid for both the operations.

Otherwise we can add comment line for msleep() like:
/* Wait for SATA power domain on */
/* Wait for SATA reset de-assert completion */

Similarily in *_exit routine:
/* Wait for SATA power domain off */
/* Wait for SATA reset assert completion */

These makes sense. Will add them.

Quoted 10 lines

drivers/phy/phy-spear1340-miphy.c line 200

Quoted 8 lines

drivers/phy/phy-spear1340-miphy.c new file +8 -0

+#ifdef CONFIG_PM_SLEEP
+static int spear1340_miphy_suspend(struct device *dev)
+{
+     struct spear1340_miphy_priv *priv = dev_get_drvdata(dev);
+     int ret = 0;
+
+     if (priv->mode == SATA)
+             ret = spear1340_miphy_sata_exit(priv);

Shouldn't this be spear1340_miphy_init()?

Quoted 5 lines

Quoted 5 lines

drivers/phy/phy-spear1340-miphy.c new file +5 -0

+
+     return ret;
+}
+
+static int spear1340_miphy_resume(struct device *dev)

Quoted 8 lines

drivers/phy/phy-spear1340-miphy.c line 211

Quoted 6 lines

drivers/phy/phy-spear1340-miphy.c new file +6 -0

+{
+     struct spear1340_miphy_priv *priv = dev_get_drvdata(dev);
+     int ret = 0;
+
+     if (priv->mode == SATA)
+             ret = spear1340_miphy_sata_init(priv);

And here spear1340_miphy_exit()? Why only for sata phys?

Quoted 4 lines

Quoted 2 lines

 drivers/phy/phy-spear1310-miphy.c                  | 274 +++++++++++++++++++
 drivers/phy/phy-spear1340-miphy.c                  | 302 +++++++++++++++++++++

Please send separate patche for each driver.

These were both around SPEAr and were on the same lines.
So sending these in a single patch shouldn't be a big issue I believe.

Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt

Quoted 5 lines

Documentation/devicetree/bindings/phy/st-spear1310-miphy.txt new file +0 -0

new file mode 100644
index 0000000..b9b281a

We generally create a single document for a SoC vendor. So just use st-phy.txt.

From: Pratyush Anand <[email protected]>

Follow dt clock naming convention for PCIe clocks.

Signed-off-by Pratyush Anand <[email protected]>

Acked-by Viresh Kumar <[email protected]>

Cc Mike Turquette <[email protected]>

[viresh: fixed logs/cclist]

Signed-off-by Viresh Kumar <[email protected]>

---
 drivers/clk/spear/spear1310_clock.c | 6 +++---
 drivers/clk/spear/spear1340_clock.c | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

drivers/clk/spear/spear1310_clock.c +3 -3

index 65894f7..4daa597 100644
@@ -742,19 +742,19 @@ void __init spear1310_clk_init(void __iomem *misc_base, void __iomem *ras_base)
        clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0,
                        SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_0_CLK_ENB,
                        0, &_lock);
-       clk_register_clkdev(clk, NULL, "dw_pcie.0");
+       clk_register_clkdev(clk, NULL, "b1000000.pcie");
        clk_register_clkdev(clk, NULL, "b1000000.ahci");
 
        clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0,
                        SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_1_CLK_ENB,
                        0, &_lock);
-       clk_register_clkdev(clk, NULL, "dw_pcie.1");
+       clk_register_clkdev(clk, NULL, "b1800000.pcie");
        clk_register_clkdev(clk, NULL, "b1800000.ahci");
 
        clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0,
                        SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_2_CLK_ENB,
                        0, &_lock);
-       clk_register_clkdev(clk, NULL, "dw_pcie.2");
+       clk_register_clkdev(clk, NULL, "b4000000.pcie");
        clk_register_clkdev(clk, NULL, "b4000000.ahci");
 
        clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,

drivers/clk/spear/spear1340_clock.c +1 -1

index fe835c1..5a5c664 100644
@@ -839,7 +839,7 @@ void __init spear1340_clk_init(void __iomem *misc_base)
        clk = clk_register_gate(NULL, "pcie_sata_clk", "ahb_clk", 0,
                        SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_PCIE_SATA_CLK_ENB,
                        0, &_lock);
-       clk_register_clkdev(clk, NULL, "dw_pcie");
+       clk_register_clkdev(clk, NULL, "b1000000.pcie");
        clk_register_clkdev(clk, NULL, "b1000000.ahci");
 
        clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,

Signature · 1 line

2.0.0.rc2

This adds PCIe support for ARM based ST Microelectronics SPEAr13xx SoCs.

V8 was here: https://lkml.org/lkml/2014/4/15/260 and just before being pulled by Olof this happened: https://lkml.org/lkml/2014/7/9/641.

An detailed look at the patches make it clear why Olof was unhappy. Patches weren't in right order, groups, etc..

So, this is an attempt to fix all those issues. Pushed here:
git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/linux.git spear/pcie-support-v9