staging: sm750fb: Coding style cleanups
Subsystems (2)
cover staging: sm750fb: Coding style cleanups
Coding style cleanups for sm750fb staging driver
All of the issues it fixes were caught by checkpatch.pl script
Helen Fornazier (8):
staging: sm750fb: Add space after struct definition
staging: sm750fb: Fix if/else/for/switch braces style
staging: sm750fb: Fix for statement style
staging: sm750fb: Add space before if statement
staging: sm750fb: Add space before switch statement
staging: sm750fb: Add spaces after ','
staging: sm750fb: Move switch case trailing statment
staging: sm750fb: Change "foo * bar" style to "foo *bar"
drivers/staging/sm750fb/ddk750_chip.c | 156 +++++++++++++++------------------- 1 file changed, 69 insertions(+), 87 deletions(-)
Signature · 1 line
1.9.1
PATCH 1/8 staging: sm750fb: Add space after struct definition
This patch fixes checkpatch.pl warning:
WARNING: missing space after struct definition
+typedef struct _pllcalparam{
--- drivers/staging/sm750fb/ddk750_chip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/staging/sm750fb/ddk750_chip.c +1 -1
@@ -2,7 +2,7 @@#include "ddk750_reg.h" #include "ddk750_chip.h" #include "ddk750_power.h" -typedef struct _pllcalparam{ +typedef struct _pllcalparam { unsigned char power;/* d : 0~ 6*/ unsigned char pod; unsigned char od;
Signature · 1 line
1.9.1
PATCH 2/8 staging: sm750fb: Fix if/else/for/switch braces style
In reply to Helen FornazierThis patch fixes the checkpatch.pl errors:
ERROR: that open brace { should be on the previous line
ERROR: else should follow close brace '}'
WARNING: braces {} are not necessary for single statement blocks
ERROR: space required before the open brace '{'
--- drivers/staging/sm750fb/ddk750_chip.c | 75 ++++++++++++----------------------- 1 file changed, 26 insertions(+), 49 deletions(-)
drivers/staging/sm750fb/ddk750_chip.c +26 -49
@@ -21,21 +21,14 @@ logical_chip_type_t getChipType(void) physicalRev = revId750;if (physicalID ==0x718 ) - { chip =SM718 ; - } -else if (physicalID ==0x750 ) - { +else if (physicalID ==0x750 ) { chip =SM750 ;/* SM750 and SM750LE are different in their revision ID only. */ -if (physicalRev ==SM750LE_REVISION_ID ){ +if (physicalRev ==SM750LE_REVISION_ID ) chip =SM750LE ; - } - } -else - { + }else chip =SM_UNKNOWN ; - }return chip; }
@@ -63,8 +56,7 @@ unsigned int getPllValue(clock_type_t clockType, pll_value_t *pPLL) pPLL->inputFreq =DEFAULT_INPUT_CLOCK ; pPLL->clockType = clockType; -switch (clockType) - { +switch (clockType) {case MXCLK_PLL : ulPllReg =PEEK32 (MXCLK_PLL_CTRL );break ;
@@ -118,8 +110,7 @@ void setChipClock(unsigned int frequency)return ;#endif -if (frequency !=0 ) - { +if (frequency !=0 ) {/* * Set up PLL, a structure to hold the value to be set in clocks. */
@@ -148,8 +139,7 @@ void setMemoryClock(unsigned int frequency)if (getChipType () ==SM750LE )return ;#endif -if (frequency !=0 ) - { +if (frequency !=0 ) {/* Set the frequency to the maximum frequency that the DDR Memory can take which is 336MHz. */ if (frequency >MHz (336 ))
@@ -160,8 +150,7 @@ void setMemoryClock(unsigned int frequency)/* Set the corresponding divisor in the register. */ ulReg =PEEK32 (CURRENT_GATE ); -switch (divisor) - { +switch (divisor) {default :case 1 : ulReg =FIELD_SET (ulReg,CURRENT_GATE ,M2XCLK ,DIV_1 );
@@ -198,8 +187,7 @@ void setMasterClock(unsigned int frequency)if (getChipType () ==SM750LE )return ;#endif -if (frequency !=0 ) - { +if (frequency !=0 ) {/* Set the frequency to the maximum frequency that the SM750 engine can run, which is about 190 MHz. */ if (frequency >MHz (190 ))
@@ -210,8 +198,7 @@ void setMasterClock(unsigned int frequency)/* Set the corresponding divisor in the register. */ ulReg =PEEK32 (CURRENT_GATE ); -switch (divisor) - { +switch (divisor) {default :case 3 : ulReg =FIELD_SET (ulReg,CURRENT_GATE ,MCLK ,DIV_3 );
@@ -248,7 +235,7 @@ unsigned int ddk750_getVMSize(void)/* get frame buffer size from GPIO */ reg =FIELD_GET (PEEK32 (MISC_CTRL ),MISC_CTRL ,LOCALMEM_SIZE ); -switch (reg){ +switch (reg) {case MISC_CTRL_LOCALMEM_SIZE_8M : data =MB (8 );break ;/* 8 Mega byte */ case MISC_CTRL_LOCALMEM_SIZE_16M : data =MB (16 );break ;/* 16 Mega byte */ case MISC_CTRL_LOCALMEM_SIZE_32M : data =MB (32 );break ;/* 32 Mega byte */
@@ -265,7 +252,7 @@ int ddk750_initHw(initchip_param_t * pInitParam)unsigned int ulReg;#if 0 //move the code to map regiter function. -if (getChipType () ==SM718 ){ +if (getChipType () ==SM718 ) {/* turn on big endian bit*/ ulReg =PEEK32 (0x74 );/* now consider register definition in a big endian pattern*/
@@ -285,13 +272,13 @@ int ddk750_initHw(initchip_param_t * pInitParam) ulReg =FIELD_SET (ulReg,CURRENT_GATE ,LOCALMEM ,ON );setCurrentGate (ulReg); -if (getChipType () !=SM750LE ){ +if (getChipType () !=SM750LE ) {/* set panel pll and graphic mode via mmio_88 */ ulReg =PEEK32 (VGA_CONFIGURATION ); ulReg =FIELD_SET (ulReg,VGA_CONFIGURATION ,PLL ,PANEL ); ulReg =FIELD_SET (ulReg,VGA_CONFIGURATION ,MODE ,GRAPHIC );POKE32 (VGA_CONFIGURATION ,ulReg); - }else { + }else {#if defined(__i386__) || defined( __x86_64__)/* set graphic mode via IO method */ outb_p (0x88 ,0x3d4 );
@@ -313,8 +300,7 @@ int ddk750_initHw(initchip_param_t * pInitParam)the system might hang when sw accesses the memory. The memory should be resetted after changing the MXCLK. */ -if (pInitParam->resetMemory ==1 ) - { +if (pInitParam->resetMemory ==1 ) { ulReg =PEEK32 (MISC_CTRL ); ulReg =FIELD_SET (ulReg,MISC_CTRL ,LOCALMEM_RESET ,RESET );POKE32 (MISC_CTRL , ulReg);
@@ -323,8 +309,7 @@ int ddk750_initHw(initchip_param_t * pInitParam)POKE32 (MISC_CTRL , ulReg); } -if (pInitParam->setAllEngOff ==1 ) - { +if (pInitParam->setAllEngOff ==1 ) {enable2DEngine (0 );/* Disable Overlay, if a former application left it on */
@@ -445,8 +430,7 @@ unsigned int calcPllValue(unsigned int request_orig,pll_value_t *pll)pllcalparam * xparm;#if 1 -if (getChipType () ==SM750LE ) - { +if (getChipType () ==SM750LE ) {/* SM750LE don't have prgrammable PLL and M/N values to work on. Just return the requested clock. */ return request_orig;
@@ -460,36 +444,33 @@ unsigned int calcPllValue(unsigned int request_orig,pll_value_t *pll)/* for MXCLK register , no POD provided, so need be treated differently */ -if (pll->clockType !=MXCLK_PLL ){ +if (pll->clockType !=MXCLK_PLL ) { xparm = &xparm_PIXEL[0 ]; xcnt =sizeof (xparm_PIXEL)/sizeof (xparm_PIXEL[0 ]); - }else { + }else { xparm = &xparm_MXCLK[0 ]; xcnt =sizeof (xparm_MXCLK)/sizeof (xparm_MXCLK[0 ]); } -for (N =15 ;N >1 ;N --) - { +for (N =15 ;N >1 ;N --) {/* RN will not exceed maximum long if @request <= 285 MHZ (for 32bit cpu) */ RN =N * request; quo =RN / input; rem =RN % input;/* rem always small than 14318181 */ fl_quo = (rem *10000 /input); -for (d = xcnt -1 ;d >=0 ;d--){ +for (d = xcnt -1 ;d >=0 ;d--) {X = xparm[d].value;M = quo*X ;M += fl_quo *X /10000 ;/* round step */ M += (fl_quo*X %10000 )>5000 ?1 :0 ; -if (M <256 &&M >0 ) - { +if (M <256 &&M >0 ) {unsigned int diff; tmpClock = pll->inputFreq *M /N /X ; diff =absDiff (tmpClock,request_orig); -if (diff < miniDiff) - { +if (diff < miniDiff) { pll->M =M ; pll->N =N ; pll->OD = xparm[d].od;
@@ -541,8 +522,7 @@ pll_value_t *pPLL /* Structure to hold the value to be set in PLL */ podPower =twoToPowerOfx (POD );/* OD has only 2 bits [15:14] and its value must between 0 to 3 */ -for (OD =0 ;OD <=3 ;OD ++) - { +for (OD =0 ;OD <=3 ;OD ++) {/* Work out 2 to the power of OD */ odPower =twoToPowerOfx (OD );
@@ -555,8 +535,7 @@ pll_value_t *pPLL /* Structure to hold the value to be set in PLL *//* N has 4 bits [11:8] and its value must between 2 and 15. The N == 1 will behave differently --> Result is not correct. */ -for (N =2 ;N <=15 ;N ++) - { +for (N =2 ;N <=15 ;N ++) {/* The formula for PLL is ulRequestClk = inputFreq * M / N / (2^OD) In the following steps, we try to work out a best M value given the others are known. To avoid decimal calculation, we use 1000 as multiplier for up to 3 decimal places of accuracy.
@@ -565,16 +544,14 @@ pll_value_t *pPLL /* Structure to hold the value to be set in PLL */M =roundedDiv (M ,1000 );/* M field has only 8 bits, reject value bigger than 8 bits */ -if (M <256 ) - { +if (M <256 ) {/* Calculate the actual clock for a given M & N */ pllClk = pPLL->inputFreq *M /N / odPower / podPower;/* How much are we different from the requirement */ diff =absDiff (pllClk, ulRequestClk); -if (diff < bestDiff) - { +if (diff < bestDiff) { bestDiff = diff;/* Store M and N values */
Signature · 1 line
1.9.1
PATCH 3/8 staging: sm750fb: Fix for statement style
In reply to Helen FornazierThis patch fixes the checkpatch.pl warnings:
ERROR: spaces required around that '=' (ctx:VxV)
ERROR: spaces required around that '<=' (ctx:VxV)
ERROR: spaces required around that '>' (ctx:VxV)
ERROR: space required before the open parenthesis '('
ERROR: space required after that ';' (ctx:VxV)
--- drivers/staging/sm750fb/ddk750_chip.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)
drivers/staging/sm750fb/ddk750_chip.c +6 -6
@@ -39,7 +39,7 @@ inline unsigned int twoToPowerOfx(unsigned long x)unsigned long i;unsigned long result =1 ; -for (i=1 ; i<=x; i++) +for (i =1 ; i <= x; i++) result *=2 ;return result; }
@@ -453,14 +453,14 @@ unsigned int calcPllValue(unsigned int request_orig,pll_value_t *pll) } -for (N =15 ;N >1 ;N --) { +for (N =15 ;N >1 ;N --) {/* RN will not exceed maximum long if @request <= 285 MHZ (for 32bit cpu) */ RN =N * request; quo =RN / input; rem =RN % input;/* rem always small than 14318181 */ fl_quo = (rem *10000 /input); -for (d = xcnt -1 ;d >=0 ;d--) { +for (d = xcnt -1 ; d >=0 ; d--) {X = xparm[d].value;M = quo*X ;M += fl_quo *X /10000 ;
@@ -508,7 +508,7 @@ pll_value_t *pPLL /* Structure to hold the value to be set in PLL */#ifndef VALIDATION_CHIP /* The maximum of post divider is 8. */ - for (POD=0; POD<=3; POD++) + for (POD = 0; POD <= 3; POD++)#endif {
@@ -522,7 +522,7 @@ pll_value_t *pPLL /* Structure to hold the value to be set in PLL */ podPower =twoToPowerOfx (POD );/* OD has only 2 bits [15:14] and its value must between 0 to 3 */ -for (OD =0 ;OD <=3 ;OD ++) { +for (OD =0 ;OD <=3 ;OD ++) {/* Work out 2 to the power of OD */ odPower =twoToPowerOfx (OD );
@@ -535,7 +535,7 @@ pll_value_t *pPLL /* Structure to hold the value to be set in PLL *//* N has 4 bits [11:8] and its value must between 2 and 15. The N == 1 will behave differently --> Result is not correct. */ -for (N =2 ;N <=15 ;N ++) { +for (N =2 ;N <=15 ;N ++) {/* The formula for PLL is ulRequestClk = inputFreq * M / N / (2^OD) In the following steps, we try to work out a best M value given the others are known. To avoid decimal calculation, we use 1000 as multiplier for up to 3 decimal places of accuracy.
Signature · 1 line
1.9.1
PATCH 4/8 staging: sm750fb: Add space before if statement
In reply to Helen FornazierThis patch fix the checkpatch.pl warning:
ERROR: space required before the open parenthesis '('
--- drivers/staging/sm750fb/ddk750_chip.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-)
drivers/staging/sm750fb/ddk750_chip.c +7 -7
@@ -87,7 +87,7 @@ unsigned int getChipClock(void) {pll_value_t pll;#if 1 -if (getChipType () ==SM750LE ) +if (getChipType () ==SM750LE )return MHz (130 );#endif
@@ -225,7 +225,7 @@ unsigned int ddk750_getVMSize(void)unsigned int data;/* sm750le only use 64 mb memory*/ -if (getChipType () ==SM750LE ) +if (getChipType () ==SM750LE )return MB (64 );/* for 750,always use power mode0*/
@@ -252,7 +252,7 @@ int ddk750_initHw(initchip_param_t * pInitParam)unsigned int ulReg;#if 0 //move the code to map regiter function. -if (getChipType () ==SM718 ) { +if (getChipType () ==SM718 ) {/* turn on big endian bit*/ ulReg =PEEK32 (0x74 );/* now consider register definition in a big endian pattern*/
@@ -272,7 +272,7 @@ int ddk750_initHw(initchip_param_t * pInitParam) ulReg =FIELD_SET (ulReg,CURRENT_GATE ,LOCALMEM ,ON );setCurrentGate (ulReg); -if (getChipType () !=SM750LE ) { +if (getChipType () !=SM750LE ) {/* set panel pll and graphic mode via mmio_88 */ ulReg =PEEK32 (VGA_CONFIGURATION ); ulReg =FIELD_SET (ulReg,VGA_CONFIGURATION ,PLL ,PANEL );
@@ -444,7 +444,7 @@ unsigned int calcPllValue(unsigned int request_orig,pll_value_t *pll)/* for MXCLK register , no POD provided, so need be treated differently */ -if (pll->clockType !=MXCLK_PLL ) { +if (pll->clockType !=MXCLK_PLL ) { xparm = &xparm_PIXEL[0 ]; xcnt =sizeof (xparm_PIXEL)/sizeof (xparm_PIXEL[0 ]); }else {
@@ -466,11 +466,11 @@ unsigned int calcPllValue(unsigned int request_orig,pll_value_t *pll)M += fl_quo *X /10000 ;/* round step */ M += (fl_quo*X %10000 )>5000 ?1 :0 ; -if (M <256 &&M >0 ) { +if (M <256 &&M >0 ) {unsigned int diff; tmpClock = pll->inputFreq *M /N /X ; diff =absDiff (tmpClock,request_orig); -if (diff < miniDiff) { +if (diff < miniDiff) { pll->M =M ; pll->N =N ; pll->OD = xparm[d].od;
Signature · 1 line
1.9.1
PATCH 5/8 staging: sm750fb: Add space before switch statement
In reply to Helen FornazierThis patch fixes the checkpatch.pl warnings:
ERROR: space required before the open parenthesis '('
+ switch(divisor) {
ERROR: space required before the open parenthesis '('
+ switch(divisor) {
ERROR: space required before the open parenthesis '('
+ switch(reg) {
--- drivers/staging/sm750fb/ddk750_chip.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
drivers/staging/sm750fb/ddk750_chip.c +3 -3
@@ -150,7 +150,7 @@ void setMemoryClock(unsigned int frequency)/* Set the corresponding divisor in the register. */ ulReg =PEEK32 (CURRENT_GATE ); -switch (divisor) { +switch (divisor) {default :case 1 : ulReg =FIELD_SET (ulReg,CURRENT_GATE ,M2XCLK ,DIV_1 );
@@ -198,7 +198,7 @@ void setMasterClock(unsigned int frequency)/* Set the corresponding divisor in the register. */ ulReg =PEEK32 (CURRENT_GATE ); -switch (divisor) { +switch (divisor) {default :case 3 : ulReg =FIELD_SET (ulReg,CURRENT_GATE ,MCLK ,DIV_3 );
@@ -235,7 +235,7 @@ unsigned int ddk750_getVMSize(void)/* get frame buffer size from GPIO */ reg =FIELD_GET (PEEK32 (MISC_CTRL ),MISC_CTRL ,LOCALMEM_SIZE ); -switch (reg) { +switch (reg) {case MISC_CTRL_LOCALMEM_SIZE_8M : data =MB (8 );break ;/* 8 Mega byte */ case MISC_CTRL_LOCALMEM_SIZE_16M : data =MB (16 );break ;/* 16 Mega byte */ case MISC_CTRL_LOCALMEM_SIZE_32M : data =MB (32 );break ;/* 32 Mega byte */
Signature · 1 line
1.9.1
Re: [Outreachy kernel] [PATCH 5/8] staging: sm750fb: Add space before switch statement
Quoted 10 lines · Helen Fornazier
This patch fixes the checkpatch.pl warnings:
ERROR: space required before the open parenthesis '('
+ switch(divisor) {ERROR: space required before the open parenthesis '('
+ switch(divisor) {ERROR: space required before the open parenthesis '('
+ switch(reg) {
No need to resend, but you don't really need to include all three messages. Just the part: ERROR: space required before the open parenthesis '(' would be fine.
julia
Quoted 47 lines
Signed-off-by Helen Fornazier <[email protected]>--- drivers/staging/sm750fb/ddk750_chip.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)drivers/staging/sm750fb/ddk750_chip.c +3
-4@@ -150,7 +150,7 @@ void setMemoryClock(unsigned int frequency)/* Set the corresponding divisor in the register. */ ulReg =PEEK32 (CURRENT_GATE ); -switch (divisor) { +switch (divisor) {default :case 1 : ulReg =FIELD_SET (ulReg,CURRENT_GATE ,M2XCLK ,DIV_1 );@@ -198,7 +198,7 @@ void setMasterClock(unsigned int frequency)/* Set the corresponding divisor in the register. */ ulReg =PEEK32 (CURRENT_GATE ); -switch (divisor) { +switch (divisor) {default :case 3 : ulReg =FIELD_SET (ulReg,CURRENT_GATE ,MCLK ,DIV_3 );@@ -235,7 +235,7 @@ unsigned int ddk750_getVMSize(void)/* get frame buffer size from GPIO */ reg =FIELD_GET (PEEK32 (MISC_CTRL ),MISC_CTRL ,LOCALMEM_SIZE ); -switch (reg) { +switch (reg) {case MISC_CTRL_LOCALMEM_SIZE_8M : data =MB (8 );break ;/* 8 Mega byte */ case MISC_CTRL_LOCALMEM_SIZE_16M : data =MB (16 );break ;/* 16 Mega byte */ case MISC_CTRL_LOCALMEM_SIZE_32M : data =MB (32 );break ;/* 32 Mega byte */ --1.9.1
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PATCH 6/8 staging: sm750fb: Add spaces after ','
In reply to Helen FornazierThis patch fixes the checkpatch.pl error:
ERROR: space required after that ',' (ctx:VxV)
--- drivers/staging/sm750fb/ddk750_chip.c | 54 +++++++++++++++++------------------ 1 file changed, 27 insertions(+), 27 deletions(-)
drivers/staging/sm750fb/ddk750_chip.c +27 -27
@@ -230,11 +230,11 @@ unsigned int ddk750_getVMSize(void)/* for 750,always use power mode0*/ reg =PEEK32 (MODE0_GATE ); - reg =FIELD_SET (reg,MODE0_GATE ,GPIO ,ON ); -POKE32 (MODE0_GATE ,reg); + reg =FIELD_SET (reg,MODE0_GATE ,GPIO ,ON ); +POKE32 (MODE0_GATE , reg);/* get frame buffer size from GPIO */ - reg =FIELD_GET (PEEK32 (MISC_CTRL ),MISC_CTRL ,LOCALMEM_SIZE ); + reg =FIELD_GET (PEEK32 (MISC_CTRL ),MISC_CTRL ,LOCALMEM_SIZE );switch (reg) {case MISC_CTRL_LOCALMEM_SIZE_8M : data =MB (8 );break ;/* 8 Mega byte */ case MISC_CTRL_LOCALMEM_SIZE_16M : data =MB (16 );break ;/* 16 Mega byte */
@@ -256,7 +256,7 @@ int ddk750_initHw(initchip_param_t * pInitParam)/* turn on big endian bit*/ ulReg =PEEK32 (0x74 );/* now consider register definition in a big endian pattern*/ - POKE32(0x74,ulReg|0x80000000); + POKE32(0x74, ulReg|0x80000000); }#endif
@@ -269,20 +269,20 @@ int ddk750_initHw(initchip_param_t * pInitParam)/* Enable display power gate & LOCALMEM power gate*/ ulReg =PEEK32 (CURRENT_GATE ); ulReg =FIELD_SET (ulReg,CURRENT_GATE ,DISPLAY ,ON ); - ulReg =FIELD_SET (ulReg,CURRENT_GATE ,LOCALMEM ,ON ); + ulReg =FIELD_SET (ulReg,CURRENT_GATE ,LOCALMEM ,ON );setCurrentGate (ulReg);if (getChipType () !=SM750LE ) {/* set panel pll and graphic mode via mmio_88 */ ulReg =PEEK32 (VGA_CONFIGURATION ); - ulReg =FIELD_SET (ulReg,VGA_CONFIGURATION ,PLL ,PANEL ); - ulReg =FIELD_SET (ulReg,VGA_CONFIGURATION ,MODE ,GRAPHIC ); -POKE32 (VGA_CONFIGURATION ,ulReg); + ulReg =FIELD_SET (ulReg,VGA_CONFIGURATION ,PLL ,PANEL ); + ulReg =FIELD_SET (ulReg,VGA_CONFIGURATION ,MODE ,GRAPHIC ); +POKE32 (VGA_CONFIGURATION , ulReg); }else {#if defined(__i386__) || defined( __x86_64__)/* set graphic mode via IO method */ -outb_p (0x88 ,0x3d4 ); -outb_p (0x06 ,0x3d5 ); +outb_p (0x88 ,0x3d4 ); +outb_p (0x06 ,0x3d5 );#endif }
@@ -399,34 +399,34 @@ unsigned int absDiff(unsigned int a, unsigned int b)M = {1,...,255} N = {2,...,15} */ -unsigned int calcPllValue (unsigned int request_orig,pll_value_t *pll) +unsigned int calcPllValue (unsigned int request_orig,pll_value_t *pll) {/* used for primary and secondary channel pixel clock pll */ static pllcalparam xparm_PIXEL[] = { -/* 2^0 = 1*/ {0 ,0 ,0 ,1 }, -/* 2^ 1 =2*/ {1 ,0 ,1 ,2 }, -/* 2^ 2 = 4*/ {2 ,0 ,2 ,4 }, - {3 ,0 ,3 ,8 }, - {4 ,1 ,3 ,16 }, - {5 ,2 ,3 ,32 }, -/* 2^6 = 64 */ {6 ,3 ,3 ,64 }, +/* 2^0 = 1*/ {0 ,0 ,0 ,1 }, +/* 2^ 1 =2*/ {1 ,0 ,1 ,2 }, +/* 2^ 2 = 4*/ {2 ,0 ,2 ,4 }, + {3 ,0 ,3 ,8 }, + {4 ,1 ,3 ,16 }, + {5 ,2 ,3 ,32 }, +/* 2^6 = 64 */ {6 ,3 ,3 ,64 }, };/* used for MXCLK (chip clock) */ static pllcalparam xparm_MXCLK[] = { -/* 2^0 = 1*/ {0 ,0 ,0 ,1 }, -/* 2^ 1 =2*/ {1 ,0 ,1 ,2 }, -/* 2^ 2 = 4*/ {2 ,0 ,2 ,4 }, - {3 ,0 ,3 ,8 }, +/* 2^0 = 1*/ {0 ,0 ,0 ,1 }, +/* 2^ 1 =2*/ {1 ,0 ,1 ,2 }, +/* 2^ 2 = 4*/ {2 ,0 ,2 ,4 }, + {3 ,0 ,3 ,8 }, };/* as sm750 register definition, N located in 2,15 and M located in 1,255 */ -int N ,M ,X ,d; +int N ,M ,X , d;int xcnt;int miniDiff; -unsigned int RN ,quo,rem,fl_quo; -unsigned int input,request; -unsigned int tmpClock,ret; +unsigned int RN , quo, rem, fl_quo; +unsigned int input, request; +unsigned int tmpClock, ret;pllcalparam * xparm;#if 1
@@ -469,7 +469,7 @@ unsigned int calcPllValue(unsigned int request_orig,pll_value_t *pll)if (M <256 &&M >0 ) {unsigned int diff; tmpClock = pll->inputFreq *M /N /X ; - diff =absDiff (tmpClock,request_orig); + diff =absDiff (tmpClock, request_orig);if (diff < miniDiff) { pll->M =M ; pll->N =N ;
Signature · 1 line
1.9.1
PATCH 7/8 staging: sm750fb: Move switch case trailing statment
In reply to Helen FornazierThis patch fixes the checkpatch.pl error:
ERROR: trailing statements should be on next line
--- drivers/staging/sm750fb/ddk750_chip.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-)
drivers/staging/sm750fb/ddk750_chip.c +10 -5
@@ -236,11 +236,16 @@ unsigned int ddk750_getVMSize(void)/* get frame buffer size from GPIO */ reg =FIELD_GET (PEEK32 (MISC_CTRL ),MISC_CTRL ,LOCALMEM_SIZE );switch (reg) { -case MISC_CTRL_LOCALMEM_SIZE_8M : data =MB (8 );break ;/* 8 Mega byte */ -case MISC_CTRL_LOCALMEM_SIZE_16M : data =MB (16 );break ;/* 16 Mega byte */ -case MISC_CTRL_LOCALMEM_SIZE_32M : data =MB (32 );break ;/* 32 Mega byte */ -case MISC_CTRL_LOCALMEM_SIZE_64M : data =MB (64 );break ;/* 64 Mega byte */ -default : data =0 ;break ; +case MISC_CTRL_LOCALMEM_SIZE_8M : + data =MB (8 );break ;/* 8 Mega byte */ +case MISC_CTRL_LOCALMEM_SIZE_16M : + data =MB (16 );break ;/* 16 Mega byte */ +case MISC_CTRL_LOCALMEM_SIZE_32M : + data =MB (32 );break ;/* 32 Mega byte */ +case MISC_CTRL_LOCALMEM_SIZE_64M : + data =MB (64 );break ;/* 64 Mega byte */ +default : + data =0 ;break ; }return data;
Signature · 1 line
1.9.1
PATCH 8/8 staging: sm750fb: Change "foo * bar" style to "foo *bar"
In reply to Helen FornazierThis patch fixes the checkpatch.pl error:
ERROR: "foo * bar" should be "foo *bar"
+int ddk750_initHw(initchip_param_t * pInitParam)
--- drivers/staging/sm750fb/ddk750_chip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/staging/sm750fb/ddk750_chip.c +1 -1
@@ -251,7 +251,7 @@ unsigned int ddk750_getVMSize(void) } -int ddk750_initHw (initchip_param_t * pInitParam) +int ddk750_initHw (initchip_param_t *pInitParam) {unsigned int ulReg;
Signature · 1 line
1.9.1