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Extend Microblaze Properties

PATCH Superseded Alistair Francis 2 participants 9 messages Jun 16, 2015 – Jun 18, 2015

v3 of 4 Superseded Latest is v4 →

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Alistair Francis

author
#0 lore raw

v3 cover Extend Microblaze Properties

This patch series extends the MicroBlaze properties that I have been working on. It applies on top of my original work:
'Add Microblaze configuration options'.

This patch series converts various MicroBlaze PVR registers to properties. This then allows the individual Microblaze machine reset functions to be removed as well as some other dead code.

V3:
- Update the pvr register to be a uint8
- Add the 8.50.a version to the version_mask

Alistair Francis (9):
target-microblaze: Rename the usefpu variable
target-microblaze: Convert use-mmu to a CPU property
target-microblaze: Convert dcache-writeback to a CPU property
target-microblaze: Convert endi to a CPU property
target-microblaze: Convert version_mask to a CPU property
target-microblaze: Convert pvr-full to a CPU property
ml605_mmu: Move the hardcoded values to the init function
s3adsp1800: Remove the hardcoded values from the reset
target-microblaze: Remove dead code

 hw/microblaze/petalogix_ml605_mmu.c      |   23 +++-----
 hw/microblaze/petalogix_s3adsp1800_mmu.c |    9 +---
 target-microblaze/cpu-qom.h              |    7 ++-
 target-microblaze/cpu.c                  |   79 +++++++++++++++++++++++++----
 target-microblaze/cpu.h                  |    4 +-
 target-microblaze/helper.c               |    6 +-
 target-microblaze/translate.c            |    6 +-
 7 files changed, 92 insertions(+), 42 deletions(-)
author
#1 lore raw

PATCH v3 1/9 target-microblaze: Rename the usefpu variable

Rename the usefpu variable to use_fpu.

Signed-off-by Alistair Francis <[email protected]>
Reviewed-by Peter Crosthwaite <[email protected]>
---
 target-microblaze/cpu-qom.h   |    2 +-
 target-microblaze/cpu.c       |    8 ++++----
 target-microblaze/translate.c |    6 +++---
 3 files changed, 8 insertions(+), 8 deletions(-)
target-microblaze/cpu-qom.h +1 -1
index a6474f9..aa9c032 100644
@@ -63,7 +63,7 @@ typedef struct MicroBlazeCPU {
     struct {
         bool stackprot;
         uint32_t base_vectors;
-        uint8_t usefpu;
+        uint8_t use_fpu;
     } cfg;
 
     CPUMBState env;
target-microblaze/cpu.c +4 -4
index 13ae49a..a6b6fd7 100644
@@ -114,10 +114,10 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
                         | 0;
 
     env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
-                        (cpu->cfg.usefpu ? PVR0_USE_FPU_MASK : 0);
+                        (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0);
 
-    env->pvr.regs[2] |= (cpu->cfg.usefpu ? PVR2_USE_FPU_MASK : 0) |
-                        (cpu->cfg.usefpu > 1 ? PVR2_USE_FPU2_MASK : 0);
+    env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
+                        (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);
 
     env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family.  */
     env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);

@@ -167,7 +167,7 @@ static Property mb_properties[] = {
      * If use-fpu = 2 - Floating point conversion and square root instructions
      *                  are enabled
      */
-    DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.usefpu, 2),
+    DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
     DEFINE_PROP_END_OF_LIST(),
 };
target-microblaze/translate.c +3 -3
index 8187700..1f5fe9a 100644
@@ -1411,11 +1411,11 @@ static void dec_rts(DisasContext *dc)
 
 static int dec_check_fpuv2(DisasContext *dc)
 {
-    if ((dc->cpu->cfg.usefpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) {
+    if ((dc->cpu->cfg.use_fpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) {
         tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_FPU);
         t_gen_raise_exception(dc, EXCP_HW_EXCP);
     }
-    return (dc->cpu->cfg.usefpu == 2) ? 0 : PVR2_USE_FPU2_MASK;
+    return (dc->cpu->cfg.use_fpu == 2) ? 0 : PVR2_USE_FPU2_MASK;
 }
 
 static void dec_fpu(DisasContext *dc)

@@ -1424,7 +1424,7 @@ static void dec_fpu(DisasContext *dc)
 
     if ((dc->tb_flags & MSR_EE_FLAG)
           && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
-          && (dc->cpu->cfg.usefpu != 1)) {
+          && (dc->cpu->cfg.use_fpu != 1)) {
         tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
         t_gen_raise_exception(dc, EXCP_HW_EXCP);
         return;
Signature · 1 line
1.7.1
author
#2 lore raw

PATCH v3 4/9 target-microblaze: Convert endi to a CPU property

In reply to Alistair Francis

Originally the endi PVR bits were manually set for each machine. This is a hassle and difficult to read, instead set them based on the CPU properties.

Signed-off-by Alistair Francis <[email protected]>
Reviewed-by Edgar E. Iglesias <[email protected]>
Reviewed-by Peter Crosthwaite <[email protected]>
---
 hw/microblaze/petalogix_ml605_mmu.c |    2 +-
 target-microblaze/cpu-qom.h         |    1 +
 target-microblaze/cpu.c             |    4 +++-
 target-microblaze/cpu.h             |    2 +-
 4 files changed, 6 insertions(+), 3 deletions(-)
hw/microblaze/petalogix_ml605_mmu.c +1 -1
index 995a579..e9adc2f 100644
@@ -70,7 +70,6 @@ static void machine_cpu_reset(MicroBlazeCPU *cpu)
 
     env->pvr.regs[10] = 0x0e000000; /* virtex 6 */
     /* setup pvr to match kernel setting */
-    env->pvr.regs[0] |= PVR0_ENDI;
     env->pvr.regs[0] = (env->pvr.regs[0] & ~PVR0_VERSION_MASK) | (0x14 << 8);
     env->pvr.regs[4] = 0xc56b8000;
     env->pvr.regs[5] = 0xc56be000;

@@ -99,6 +98,7 @@ petalogix_ml605_init(MachineState *machine)
     object_property_set_int(OBJECT(cpu), 1, "use-fpu", &error_abort);
     object_property_set_bool(OBJECT(cpu), true, "dcache-writeback",
                              &error_abort);
+    object_property_set_bool(OBJECT(cpu), true, "endianness", &error_abort);
     object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort);
 
     /* Attach emulated BRAM through the LMB.  */
target-microblaze/cpu-qom.h +1 -0
index 3b6165d..d1d814b 100644
@@ -66,6 +66,7 @@ typedef struct MicroBlazeCPU {
         uint8_t use_fpu;
         bool use_mmu;
         bool dcache_writeback;
+        bool endi;
     } cfg;
 
     CPUMBState env;
target-microblaze/cpu.c +3 -1
index 92c51a0..8429275 100644
@@ -114,7 +114,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
 
     env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
                         (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
-                        (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0);
+                        (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
+                        (cpu->cfg.endi ? PVR0_ENDI_MASK : 0);
 
     env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
                         (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);

@@ -174,6 +175,7 @@ static Property mb_properties[] = {
     DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
     DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
                      false),
+    DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
     DEFINE_PROP_END_OF_LIST(),
 };
target-microblaze/cpu.h +1 -1
index 54e41e8..0f82abd 100644
@@ -124,7 +124,7 @@ typedef struct CPUMBState CPUMBState;
 #define PVR0_USE_DCACHE_MASK            0x01000000
 #define PVR0_USE_MMU_MASK               0x00800000
 #define PVR0_USE_BTC			0x00400000
-#define PVR0_ENDI			0x00200000
+#define PVR0_ENDI_MASK                  0x00200000
 #define PVR0_FAULT			0x00100000
 #define PVR0_VERSION_MASK               0x0000FF00
 #define PVR0_USER1_MASK                 0x000000FF
Signature · 1 line
1.7.1
author
#3 lore raw

PATCH v3 6/9 target-microblaze: Convert pvr-full to a CPU property

In reply to Alistair Francis

Originally the pvr-full PVR bits were manually set for each machine. This is a hassle and difficult to read, instead set them based on the CPU properties.

Signed-off-by Alistair Francis <[email protected]>

---
V3:
- Convert PVR to an 8-bit uint instead of a bool
V2:
- Rename DTS mapping

 target-microblaze/cpu-qom.h |    1 +
 target-microblaze/cpu.c     |    7 ++++---
 target-microblaze/helper.c  |    4 ++--
 3 files changed, 7 insertions(+), 5 deletions(-)
target-microblaze/cpu-qom.h +1 -0
index 7da25fa..34f6273 100644
@@ -68,6 +68,7 @@ typedef struct MicroBlazeCPU {
         bool dcache_writeback;
         bool endi;
         char *version;
+        uint8_t pvr;
     } cfg;
 
     CPUMBState env;
target-microblaze/cpu.c +4 -3
index df3dd89..b1ffa8e 100644
@@ -130,8 +130,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
 
     qemu_init_vcpu(cs);
 
-    env->pvr.regs[0] = PVR0_PVR_FULL_MASK \
-                       | PVR0_USE_BARREL_MASK \
+    env->pvr.regs[0] = PVR0_USE_BARREL_MASK \
                        | PVR0_USE_DIV_MASK \
                        | PVR0_USE_HW_MUL_MASK \
                        | PVR0_USE_EXC_MASK \

@@ -166,7 +165,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
                         (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
                         (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
                         (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
-                        (version_code << 16);
+                        (version_code << 16) |
+                        (cpu->cfg.pvr == 2 ? PVR0_PVR_FULL_MASK : 0);
 
     env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
                         (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);

@@ -228,6 +228,7 @@ static Property mb_properties[] = {
                      false),
     DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
     DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
+    DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, 2),
     DEFINE_PROP_END_OF_LIST(),
 };
target-microblaze/helper.c +2 -2
index 5156c12..fa783ff 100644
@@ -58,8 +58,8 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
     mmu_available = 0;
     if (cpu->cfg.use_mmu) {
         mmu_available = 1;
-        if ((env->pvr.regs[0] & PVR0_PVR_FULL_MASK)
-            && (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
+        if ((cpu->cfg.pvr == 2) &&
+            (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
             mmu_available = 0;
         }
     }
Signature · 1 line
1.7.1
Reviewed-by on v3 6/9
#4 lore raw

Re: [Qemu-devel] [PATCH v3 6/9] target-microblaze: Convert pvr-full to a CPU property

Quoted 53 lines · Alistair Francis

Originally the pvr-full PVR bits were manually set for each machine. This is a hassle and difficult to read, instead set them based on the CPU properties.

Signed-off-by Alistair Francis <[email protected]>

---
V3:
- Convert PVR to an 8-bit uint instead of a bool
V2:
- Rename DTS mapping

 target-microblaze/cpu-qom.h |    1 +
 target-microblaze/cpu.c     |    7 ++++---
 target-microblaze/helper.c  |    4 ++--
 3 files changed, 7 insertions(+), 5 deletions(-)
target-microblaze/cpu-qom.h +1 -0
index 7da25fa..34f6273 100644
@@ -68,6 +68,7 @@ typedef struct MicroBlazeCPU {
         bool dcache_writeback;
         bool endi;
         char *version;
+        uint8_t pvr;
     } cfg;
 
     CPUMBState env;
target-microblaze/cpu.c +3 -3
index df3dd89..b1ffa8e 100644
@@ -130,8 +130,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
 
     qemu_init_vcpu(cs);
 
-    env->pvr.regs[0] = PVR0_PVR_FULL_MASK \
-                       | PVR0_USE_BARREL_MASK \
+    env->pvr.regs[0] = PVR0_USE_BARREL_MASK \
                        | PVR0_USE_DIV_MASK \
                        | PVR0_USE_HW_MUL_MASK \
                        | PVR0_USE_EXC_MASK \

@@ -166,7 +165,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
                         (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
                         (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
                         (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
-                        (version_code << 16);
+                        (version_code << 16) |
+                        (cpu->cfg.pvr == 2 ? PVR0_PVR_FULL_MASK : 0);
 
     env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
                         (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);

target-microblaze/cpu.c static Property mb_properties[] = { · line 231

Quoted 4 lines
target-microblaze/cpu.c +1 -0
@@ -228,6 +228,7 @@ static Property mb_properties[] = {
                      false),
     DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
     DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
+    DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, 2),

The encodings should be macroified:

#define C_PVR_NONE = 0;
#define C_PVR_BASIC = 1;
#define C_PVR_FULL = 2;

Otherwise,

Reviewed-by Peter Crosthwaite <[email protected]>
Quoted 22 lines
target-microblaze/cpu.c +0 -0
     DEFINE_PROP_END_OF_LIST(),
 };
target-microblaze/helper.c +2 -3
index 5156c12..fa783ff 100644
@@ -58,8 +58,8 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
     mmu_available = 0;
     if (cpu->cfg.use_mmu) {
         mmu_available = 1;
-        if ((env->pvr.regs[0] & PVR0_PVR_FULL_MASK)
-            && (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
+        if ((cpu->cfg.pvr == 2) &&
+            (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
             mmu_available = 0;
         }
     }
--

1.7.1

author
#5 lore raw

Re: [Qemu-devel] [PATCH v3 6/9] target-microblaze: Convert pvr-full to a CPU property

Quoted 62 lines · Peter Crosthwaite
Quoted 53 lines · Alistair Francis

Originally the pvr-full PVR bits were manually set for each machine. This is a hassle and difficult to read, instead set them based on the CPU properties.

Signed-off-by Alistair Francis <[email protected]>

---
V3:
- Convert PVR to an 8-bit uint instead of a bool
V2:
- Rename DTS mapping

 target-microblaze/cpu-qom.h |    1 +
 target-microblaze/cpu.c     |    7 ++++---
 target-microblaze/helper.c  |    4 ++--
 3 files changed, 7 insertions(+), 5 deletions(-)
target-microblaze/cpu-qom.h +1 -0
index 7da25fa..34f6273 100644
@@ -68,6 +68,7 @@ typedef struct MicroBlazeCPU {
         bool dcache_writeback;
         bool endi;
         char *version;
+        uint8_t pvr;
     } cfg;
 
     CPUMBState env;
target-microblaze/cpu.c +3 -3
index df3dd89..b1ffa8e 100644
@@ -130,8 +130,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
 
     qemu_init_vcpu(cs);
 
-    env->pvr.regs[0] = PVR0_PVR_FULL_MASK \
-                       | PVR0_USE_BARREL_MASK \
+    env->pvr.regs[0] = PVR0_USE_BARREL_MASK \
                        | PVR0_USE_DIV_MASK \
                        | PVR0_USE_HW_MUL_MASK \
                        | PVR0_USE_EXC_MASK \

@@ -166,7 +165,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
                         (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
                         (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
                         (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
-                        (version_code << 16);
+                        (version_code << 16) |
+                        (cpu->cfg.pvr == 2 ? PVR0_PVR_FULL_MASK : 0);
 
     env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
                         (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);

target-microblaze/cpu.c static Property mb_properties[] = { · line 231

Quoted 4 lines
target-microblaze/cpu.c +1 -0
@@ -228,6 +228,7 @@ static Property mb_properties[] = {
                      false),
     DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
     DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
+    DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, 2),

The encodings should be macroified:

Quoted 3 lines

#define C_PVR_NONE = 0;
#define C_PVR_BASIC = 1;
#define C_PVR_FULL = 2;

Yep, will fix.

Quoted 4 lines

Otherwise,

Reviewed-by Peter Crosthwaite <[email protected]>

Thanks Peter

Quoted 24 lines
Quoted 23 lines
target-microblaze/cpu.c +0 -0
     DEFINE_PROP_END_OF_LIST(),
 };
target-microblaze/helper.c +2 -3
index 5156c12..fa783ff 100644
@@ -58,8 +58,8 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
     mmu_available = 0;
     if (cpu->cfg.use_mmu) {
         mmu_available = 1;
-        if ((env->pvr.regs[0] & PVR0_PVR_FULL_MASK)
-            && (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
+        if ((cpu->cfg.pvr == 2) &&
+            (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
             mmu_available = 0;
         }
     }
--

1.7.1

author
#6 lore raw

PATCH v3 7/9 ml605_mmu: Move the hardcoded values to the init function

In reply to Alistair Francis

Move the hard coded register values to the init function. This also allows the entire reset function to be deleted, as PVR registers are now preserved on reset.

The hardcoded PVR0 values can be removed as they are setting the endianness and stack protection, which is already done or invalid.

Signed-off-by Alistair Francis <[email protected]>
Reviewed-by Peter Crosthwaite <[email protected]>

---
V2:
- Don't set PVR0

 hw/microblaze/petalogix_ml605_mmu.c |   18 ++++++------------
 1 files changed, 6 insertions(+), 12 deletions(-)
hw/microblaze/petalogix_ml605_mmu.c +6 -12
index 609c90b..ed84a37 100644
@@ -64,17 +64,6 @@
 #define SPI_IRQ             4
 #define UART16550_IRQ       5
 
-static void machine_cpu_reset(MicroBlazeCPU *cpu)
-{
-    CPUMBState *env = &cpu->env;
-
-    env->pvr.regs[10] = 0x0e000000; /* virtex 6 */
-    /* setup pvr to match kernel setting */
-    env->pvr.regs[0] |= (0x14 << 8);
-    env->pvr.regs[4] = 0xc56b8000;
-    env->pvr.regs[5] = 0xc56be000;
-}
-
 static void
 petalogix_ml605_init(MachineState *machine)
 {

@@ -205,10 +194,15 @@ petalogix_ml605_init(MachineState *machine)
         }
     }
 
+    /* setup PVR to match kernel settings */
+    cpu->env.pvr.regs[4] = 0xc56b8000;
+    cpu->env.pvr.regs[5] = 0xc56be000;
+    cpu->env.pvr.regs[10] = 0x0e000000; /* virtex 6 */
+
     microblaze_load_kernel(cpu, MEMORY_BASEADDR, ram_size,
                            machine->initrd_filename,
                            BINARY_DEVICE_TREE_FILE,
-                           machine_cpu_reset);
+                           NULL);
 
 }
Signature · 1 line
1.7.1
author
#7 lore raw

PATCH v3 8/9 s3adsp1800: Remove the hardcoded values from the reset

In reply to Alistair Francis

Remove the hardcoded values from the machine specific reset function, as the same values are already set in the standard MicroBlaze reset.

This also allows the entire reset function to be deleted, as PVR registers are now preserved on reset.

Signed-off-by Alistair Francis <[email protected]>
Reviewed-by Edgar E. Iglesias <[email protected]>
Reviewed-by Peter Crosthwaite <[email protected]>
---
 hw/microblaze/petalogix_s3adsp1800_mmu.c |    9 +--------
 1 files changed, 1 insertions(+), 8 deletions(-)
hw/microblaze/petalogix_s3adsp1800_mmu.c +1 -8
index 84f6e74..7109e63 100644
@@ -51,13 +51,6 @@
 #define ETHLITE_IRQ         1
 #define UARTLITE_IRQ        3
 
-static void machine_cpu_reset(MicroBlazeCPU *cpu)
-{
-    CPUMBState *env = &cpu->env;
-
-    env->pvr.regs[10] = 0x0c000000; /* spartan 3a dsp family.  */
-}
-
 static void
 petalogix_s3adsp1800_init(MachineState *machine)
 {

@@ -132,7 +125,7 @@ petalogix_s3adsp1800_init(MachineState *machine)
     microblaze_load_kernel(cpu, ddr_base, ram_size,
                            machine->initrd_filename,
                            BINARY_DEVICE_TREE_FILE,
-                           machine_cpu_reset);
+                           NULL);
 }
 
 static QEMUMachine petalogix_s3adsp1800_machine = {
Signature · 1 line
1.7.1
author
#8 lore raw

PATCH v3 9/9 target-microblaze: Remove dead code

In reply to Alistair Francis

This code is already being run in the mb_cpu_realizefn() function. As PVR registers are preserved on reset this code is not required.

Signed-off-by Alistair Francis <[email protected]>
Reviewed-by Edgar E. Iglesias <[email protected]>
Reviewed-by Peter Crosthwaite <[email protected]>
---
 target-microblaze/cpu.c |    4 ----
 1 files changed, 0 insertions(+), 4 deletions(-)
target-microblaze/cpu.c +0 -4
index b1ffa8e..a97a1aa 100644
@@ -179,10 +179,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
 
     env->sregs[SR_PC] = cpu->cfg.base_vectors;
 
-#if defined(CONFIG_USER_ONLY)
-    env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp.  */
-#endif
-
     mcc->parent_realize(dev, errp);
 }
Signature · 1 line
1.7.1