ARM: Enable GICv2m on 32-bit virt machine
v4 cover ARM: Enable GICv2m on 32-bit virt machine
qemu implementation of "virt" includes GICv2m. This series allows to use it also on ARM32 architecture.
v3 => v4:
- Split into two patches as requested by Marc Zyngier
- Use specialized word extraction macros instead of #ifdef
v1 => v2:
Added verbose explanation in commit message
v2 => v3:
Fixed build warning in irq-gic-v2m.c
v1 => v2:
Added verbose explanation in commit message
Pavel Fedin (2):
ARM: Enable GICv2m on 32-bit virt machine
ARM: Fix GICv2m build warning on 32 bits
arch/arm/Kconfig | 1 + arch/arm/include/asm/Kbuild | 1 + drivers/irqchip/irq-gic-v2m.c | 4 ++-- 3 files changed, 4 insertions(+), 2 deletions(-)
Signature · 1 line
2.4.4
PATCH v4 1/2 ARM: Enable GICv2m on 32-bit virt machine
msi.h is added because it is required by linux/msi.h if CONFIG_GENERIC_MSI_IRQ_DOMAIN is defined. It gets enabled by the following KConfig dependency chain:ARM_GIC_V2M => PCI_MSI_IRQ_DOMAIN => GENERIC_MSI_IRQ_DOMAIN
--- arch/arm/Kconfig | 1 + arch/arm/include/asm/Kbuild | 1 + 2 files changed, 2 insertions(+)
arch/arm/Kconfig +1 -0
@@ -815,6 +815,7 @@ config ARCH_VIRT bool "Dummy Virtual Machine" if ARCH_MULTI_V7 select ARM_AMBA select ARM_GIC + select ARM_GIC_V2M if PCI_MSI select ARM_PSCI select HAVE_ARM_ARCH_TIMER
arch/arm/include/asm/Kbuild +1 -0
@@ -14,6 +14,7 @@ generic-y += local.h generic-y += local64.h generic-y += mcs_spinlock.h generic-y += msgbuf.h +generic-y += msi.h generic-y += param.h generic-y += parport.h generic-y += poll.h
Signature · 1 line
2.4.4
PATCH v4 2/2 ARM: Fix GICv2m build warning on 32 bits
In reply to Pavel FedinAfter GICv2m was enabled for 32-bit ARM kernel, a warning popped up:
drivers/irqchip/irq-gic-v2m.c: In function ?gicv2m_compose_msi_msg?:drivers/irqchip/irq-gic-v2m.c:100:2: warning: right shift count >= width of type [enabled by default]
msg->address_hi = (u32) (addr >> 32);
^
This patch fixes it by using proper macros for splitting up the value.
--- drivers/irqchip/irq-gic-v2m.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/irqchip/irq-gic-v2m.c +2 -2
@@ -97,8 +97,8 @@ static void gicv2m_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)struct v2m_data *v2m =irq_data_get_irq_chip_data (data);phys_addr_t addr = v2m->res.start +V2M_MSI_SETSPI_NS ; - msg->address_hi = (u32) (addr >>32 ); - msg->address_lo = (u32) (addr); + msg->address_hi =upper_32_bits (addr); + msg->address_lo =lower_32_bits (addr); msg->data = data->hwirq; }
Signature · 1 line
2.4.4
PATCH v4 2/2 ARM: Fix GICv2m build warning on 32 bits
Quoted 21 lines · Pavel Fedin
After GICv2m was enabled for 32-bit ARM kernel, a warning popped up:
drivers/irqchip/irq-gic-v2m.c: In function ?gicv2m_compose_msi_msg?:drivers/irqchip/irq-gic-v2m.c:100:2: warning: right shift count >= width of type [enabled by default]
msg->address_hi= (u32) (addr >> 32);
^This patch fixes it by using proper macros for splitting up the value.
Signed-off-by Pavel Fedin <[email protected]>--- drivers/irqchip/irq-gic-v2m.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)drivers/irqchip/irq-gic-v2m.c +0
-0
drivers/irqchip/irq-gic-v2m.c static void gicv2m_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) · line 104
Quoted 10 lines
drivers/irqchip/irq-gic-v2m.c +2
-2@@ -97,8 +97,8 @@ static void gicv2m_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)struct v2m_data *v2m =irq_data_get_irq_chip_data (data);phys_addr_t addr = v2m->res.start +V2M_MSI_SETSPI_NS ; - msg->address_hi = (u32) (addr >>32 ); - msg->address_lo = (u32) (addr); + msg->address_hi =upper_32_bits (addr); + msg->address_lo =lower_32_bits (addr); msg->data = data->hwirq; }
I'll add that to my queue of GIC fixes.
Thanks,
M.
Signature · 1 line
Jazz is not dead. It just smells funny...