staging: media: omap4iss: Fixes multiple checkpatch issues

PATCH In review Amarjargal Gundjalam 3 participants 10 messages Oct 26, 2015 – Oct 27, 2015

Subsystems (2)

Media (V4L/DVB) Staging

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Amarjargal Gundjalam

author

2015-10-26 13:09 UTC #0 lore raw

cover staging: media: omap4iss: Fixes multiple checkpatch issues

This patchset fixes multiple checkpatch checks and warnings.

Amarjargal Gundjalam (6):
staging: media: omap4iss: Fixes NULL comparison
staging: media: omap4iss: Fixes misspelling
staging: media: omap4iss: Replaces bit shift on 1 with BIT Macro
staging: media: omap4iss: Removes unnecessary blank lines
staging: media: omap4iss: Matches alignment with open parenthesis
staging: media: omap4iss: Fixes line break

 drivers/staging/media/omap4iss/iss.c         |   40 ++--
 drivers/staging/media/omap4iss/iss_csi2.c    |    6 +-
 drivers/staging/media/omap4iss/iss_csi2.h    |    4 +-
 drivers/staging/media/omap4iss/iss_ipipe.c   |   26 +--
 drivers/staging/media/omap4iss/iss_ipipe.h   |    4 +-
 drivers/staging/media/omap4iss/iss_ipipeif.c |   24 +-
 drivers/staging/media/omap4iss/iss_ipipeif.h |    8 +-
 drivers/staging/media/omap4iss/iss_regs.h    |  316 +++++++++++++-------------
 drivers/staging/media/omap4iss/iss_resizer.c |   28 ++-
 drivers/staging/media/omap4iss/iss_resizer.h |    6 +-
 drivers/staging/media/omap4iss/iss_video.c   |   19 +-
 11 files changed, 239 insertions(+), 242 deletions(-)

Signature · 1 line

1.7.9.5

Amarjargal Gundjalam

author

2015-10-26 13:09 UTC #1 lore raw

PATCH 1/6 staging: media: omap4iss: Fixes NULL comparison

This patch fixes the checkpatch issue:

CHECK: Comparison to NULL could be written

Signed-off-by Amarjargal Gundjalam <[email protected]>

---
 drivers/staging/media/omap4iss/iss.c         |   28 +++++++++++++-------------
 drivers/staging/media/omap4iss/iss_csi2.c    |    6 +++---
 drivers/staging/media/omap4iss/iss_ipipe.c   |    4 ++--
 drivers/staging/media/omap4iss/iss_ipipeif.c |    6 +++---
 drivers/staging/media/omap4iss/iss_resizer.c |    6 +++---
 drivers/staging/media/omap4iss/iss_video.c   |   18 ++++++++---------
 6 files changed, 34 insertions(+), 34 deletions(-)

drivers/staging/media/omap4iss/iss.c +14 ~~-14~~

index 9bfb725..104fc58 100644
@@ -151,7 +151,7 @@ int omap4iss_get_external_info(struct iss_pipeline *pipe,
 
 	ctrl = v4l2_ctrl_find(pipe->external->ctrl_handler,
 			      V4L2_CID_PIXEL_RATE);
-	if (ctrl == NULL) {
+	if (!ctrl) {
 		dev_warn(iss->dev, "no pixel rate control in subdev %s\n",
 			 pipe->external->name);
 		return -EPIPE;

@@ -422,7 +422,7 @@ static int iss_pipeline_pm_power_one(struct media_entity *entity, int change)
 	subdev = media_entity_type(entity) == MEDIA_ENT_T_V4L2_SUBDEV
 	       ? media_entity_to_v4l2_subdev(entity) : NULL;
 
-	if (entity->use_count == 0 && change > 0 && subdev != NULL) {
+	if (entity->use_count == 0 && change > 0 && subdev) {
 		int ret;
 
 		ret = v4l2_subdev_call(subdev, core, s_power, 1);

@@ -433,7 +433,7 @@ static int iss_pipeline_pm_power_one(struct media_entity *entity, int change)
 	entity->use_count += change;
 	WARN_ON(entity->use_count < 0);
 
-	if (entity->use_count == 0 && change < 0 && subdev != NULL)
+	if (entity->use_count == 0 && change < 0 && subdev)
 		v4l2_subdev_call(subdev, core, s_power, 0);
 
 	return 0;

@@ -590,7 +590,7 @@ static int iss_pipeline_disable(struct iss_pipeline *pipe,
 			break;
 
 		pad = media_entity_remote_pad(pad);
-		if (pad == NULL ||
+		if (!pad ||
 		    media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
 			break;

@@ -658,7 +658,7 @@ static int iss_pipeline_enable(struct iss_pipeline *pipe,
 			break;
 
 		pad = media_entity_remote_pad(pad);
-		if (pad == NULL ||
+		if (!pad ||
 		    media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
 			break;

@@ -1050,7 +1050,7 @@ struct iss_device *omap4iss_get(struct iss_device *iss)
 {
 	struct iss_device *__iss = iss;
 
-	if (iss == NULL)
+	if (!iss)
 		return NULL;
 
 	mutex_lock(&iss->iss_mutex);

@@ -1065,7 +1065,7 @@ struct iss_device *omap4iss_get(struct iss_device *iss)
 	iss_enable_interrupts(iss);
 
 out:
-	if (__iss != NULL)
+	if (__iss)
 		iss->ref_count++;
 	mutex_unlock(&iss->iss_mutex);

@@ -1080,7 +1080,7 @@ out:
  */
 void omap4iss_put(struct iss_device *iss)
 {
-	if (iss == NULL)
+	if (!iss)
 		return;
 
 	mutex_lock(&iss->iss_mutex);

@@ -1142,7 +1142,7 @@ iss_register_subdev_group(struct iss_device *iss,
 	struct v4l2_subdev *sensor = NULL;
 	unsigned int first;
 
-	if (board_info->board_info == NULL)
+	if (!board_info->board_info)
 		return NULL;
 
 	for (first = 1; board_info->board_info; ++board_info, first = 0) {

@@ -1150,7 +1150,7 @@ iss_register_subdev_group(struct iss_device *iss,
 		struct i2c_adapter *adapter;
 
 		adapter = i2c_get_adapter(board_info->i2c_adapter_id);
-		if (adapter == NULL) {
+		if (!adapter) {
 			dev_err(iss->dev,
 				"%s: Unable to get I2C adapter %d for device %s\n",
 				__func__, board_info->i2c_adapter_id,

@@ -1160,7 +1160,7 @@ iss_register_subdev_group(struct iss_device *iss,
 
 		subdev = v4l2_i2c_new_subdev_board(&iss->v4l2_dev, adapter,
 				board_info->board_info, NULL);
-		if (subdev == NULL) {
+		if (!subdev) {
 			dev_err(iss->dev, "Unable to register subdev %s\n",
 				board_info->board_info->type);
 			continue;

@@ -1228,7 +1228,7 @@ static int iss_register_entities(struct iss_device *iss)
 		unsigned int pad;
 
 		sensor = iss_register_subdev_group(iss, subdevs->subdevs);
-		if (sensor == NULL)
+		if (!sensor)
 			continue;
 
 		sensor->host_priv = subdevs;

@@ -1369,7 +1369,7 @@ static int iss_probe(struct platform_device *pdev)
 	unsigned int i;
 	int ret;
 
-	if (pdata == NULL)
+	if (!pdata)
 		return -EINVAL;
 
 	iss = devm_kzalloc(&pdev->dev, sizeof(*iss), GFP_KERNEL);

@@ -1406,7 +1406,7 @@ static int iss_probe(struct platform_device *pdev)
 	if (ret < 0)
 		goto error;
 
-	if (omap4iss_get(iss) == NULL)
+	if (!omap4iss_get(iss))
 		goto error;
 
 	ret = iss_reset(iss);

drivers/staging/media/omap4iss/iss_csi2.c +3 -3

index bc83f82..c6e6d47 100644
@@ -658,7 +658,7 @@ static void csi2_isr_buffer(struct iss_csi2_device *csi2)
 	 * Let video queue operation restart engine if there is an underrun
 	 * condition.
 	 */
-	if (buffer == NULL)
+	if (!buffer)
 		return;
 
 	csi2_set_outaddr(csi2, buffer->iss_addr);

@@ -979,7 +979,7 @@ static int csi2_get_format(struct v4l2_subdev *sd,
 	struct v4l2_mbus_framefmt *format;
 
 	format = __csi2_get_format(csi2, cfg, fmt->pad, fmt->which);
-	if (format == NULL)
+	if (!format)
 		return -EINVAL;
 
 	fmt->format = *format;

@@ -1001,7 +1001,7 @@ static int csi2_set_format(struct v4l2_subdev *sd,
 	struct v4l2_mbus_framefmt *format;
 
 	format = __csi2_get_format(csi2, cfg, fmt->pad, fmt->which);
-	if (format == NULL)
+	if (!format)
 		return -EINVAL;
 
 	csi2_try_format(csi2, cfg, fmt->pad, &fmt->format, fmt->which);

drivers/staging/media/omap4iss/iss_ipipe.c +2 -2

index f94a592..fcde8a6 100644
@@ -320,7 +320,7 @@ static int ipipe_get_format(struct v4l2_subdev *sd,
 	struct v4l2_mbus_framefmt *format;
 
 	format = __ipipe_get_format(ipipe, cfg, fmt->pad, fmt->which);
-	if (format == NULL)
+	if (!format)
 		return -EINVAL;
 
 	fmt->format = *format;

@@ -344,7 +344,7 @@ static int ipipe_set_format(struct v4l2_subdev *sd,
 	struct v4l2_mbus_framefmt *format;
 
 	format = __ipipe_get_format(ipipe, cfg, fmt->pad, fmt->which);
-	if (format == NULL)
+	if (!format)
 		return -EINVAL;
 
 	ipipe_try_format(ipipe, cfg, fmt->pad, &fmt->format, fmt->which);

drivers/staging/media/omap4iss/iss_ipipeif.c +3 -3

index c0da13d..fcafdbe 100644
@@ -233,7 +233,7 @@ static void ipipeif_isr_buffer(struct iss_ipipeif_device *ipipeif)
 	ipipeif_write_enable(ipipeif, 0);
 
 	buffer = omap4iss_video_buffer_next(&ipipeif->video_out);
-	if (buffer == NULL)
+	if (!buffer)
 		return;
 
 	ipipeif_set_outaddr(ipipeif, buffer->iss_addr);

@@ -526,7 +526,7 @@ static int ipipeif_get_format(struct v4l2_subdev *sd,
 	struct v4l2_mbus_framefmt *format;
 
 	format = __ipipeif_get_format(ipipeif, cfg, fmt->pad, fmt->which);
-	if (format == NULL)
+	if (!format)
 		return -EINVAL;
 
 	fmt->format = *format;

@@ -550,7 +550,7 @@ static int ipipeif_set_format(struct v4l2_subdev *sd,
 	struct v4l2_mbus_framefmt *format;
 
 	format = __ipipeif_get_format(ipipeif, cfg, fmt->pad, fmt->which);
-	if (format == NULL)
+	if (!format)
 		return -EINVAL;
 
 	ipipeif_try_format(ipipeif, cfg, fmt->pad, &fmt->format, fmt->which);

drivers/staging/media/omap4iss/iss_resizer.c +3 -3

index 5030cf3..8035e01 100644
@@ -274,7 +274,7 @@ static void resizer_isr_buffer(struct iss_resizer_device *resizer)
 	resizer_enable(resizer, 0);
 
 	buffer = omap4iss_video_buffer_next(&resizer->video_out);
-	if (buffer == NULL)
+	if (!buffer)
 		return;
 
 	resizer_set_outaddr(resizer, buffer->iss_addr);

@@ -588,7 +588,7 @@ static int resizer_get_format(struct v4l2_subdev *sd,
 	struct v4l2_mbus_framefmt *format;
 
 	format = __resizer_get_format(resizer, cfg, fmt->pad, fmt->which);
-	if (format == NULL)
+	if (!format)
 		return -EINVAL;
 
 	fmt->format = *format;

@@ -612,7 +612,7 @@ static int resizer_set_format(struct v4l2_subdev *sd,
 	struct v4l2_mbus_framefmt *format;
 
 	format = __resizer_get_format(resizer, cfg, fmt->pad, fmt->which);
-	if (format == NULL)
+	if (!format)
 		return -EINVAL;
 
 	resizer_try_format(resizer, cfg, fmt->pad, &fmt->format, fmt->which);

drivers/staging/media/omap4iss/iss_video.c +9 -9

index 40405d8..a98991a 100644
@@ -191,7 +191,7 @@ iss_video_remote_subdev(struct iss_video *video, u32 *pad)
 
 	remote = media_entity_remote_pad(&video->pad);
 
-	if (remote == NULL ||
+	if (!remote ||
 	    media_entity_type(remote->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
 		return NULL;

@@ -241,7 +241,7 @@ __iss_video_get_format(struct iss_video *video,
 	int ret;
 
 	subdev = iss_video_remote_subdev(video, &pad);
-	if (subdev == NULL)
+	if (!subdev)
 		return -EINVAL;
 
 	memset(&fmt, 0, sizeof(fmt));

@@ -471,7 +471,7 @@ struct iss_buffer *omap4iss_video_buffer_next(struct iss_video *video)
 		return NULL;
 	}
 
-	if (video->type == V4L2_BUF_TYPE_VIDEO_CAPTURE && pipe->input != NULL) {
+	if (video->type == V4L2_BUF_TYPE_VIDEO_CAPTURE && pipe->input) {
 		spin_lock(&pipe->lock);
 		pipe->state &= ~ISS_PIPELINE_STREAM;
 		spin_unlock(&pipe->lock);

@@ -624,7 +624,7 @@ iss_video_try_format(struct file *file, void *fh, struct v4l2_format *format)
 		return -EINVAL;
 
 	subdev = iss_video_remote_subdev(video, &pad);
-	if (subdev == NULL)
+	if (!subdev)
 		return -EINVAL;
 
 	iss_video_pix_to_mbus(&format->fmt.pix, &fmt.format);

@@ -806,7 +806,7 @@ iss_video_streamon(struct file *file, void *fh, enum v4l2_buf_type type)
 		pipe->input = far_end;
 		pipe->output = video;
 	} else {
-		if (far_end == NULL) {
+		if (!far_end) {
 			ret = -EPIPE;
 			goto err_iss_video_check_format;
 		}

@@ -841,7 +841,7 @@ iss_video_streamon(struct file *file, void *fh, enum v4l2_buf_type type)
 	 * to the stream on command. In memory-to-memory mode, it will be
 	 * started when buffers are queued on both the input and output.
 	 */
-	if (pipe->input == NULL) {
+	if (!pipe->input) {
 		unsigned long flags;
 
 		ret = omap4iss_pipeline_set_stream(pipe,

@@ -974,14 +974,14 @@ static int iss_video_open(struct file *file)
 	int ret = 0;
 
 	handle = kzalloc(sizeof(*handle), GFP_KERNEL);
-	if (handle == NULL)
+	if (!handle)
 		return -ENOMEM;
 
 	v4l2_fh_init(&handle->vfh, &video->video);
 	v4l2_fh_add(&handle->vfh);
 
 	/* If this is the first user, initialise the pipeline. */
-	if (omap4iss_get(video->iss) == NULL) {
+	if (!omap4iss_get(video->iss)) {
 		ret = -EBUSY;
 		goto done;
 	}

@@ -1116,7 +1116,7 @@ int omap4iss_video_init(struct iss_video *video, const char *name)
 	mutex_init(&video->stream_lock);
 
 	/* Initialize the video device. */
-	if (video->ops == NULL)
+	if (!video->ops)
 		video->ops = &iss_video_dummy_ops;
 
 	video->video.fops = &iss_video_fops;

Signature · 1 line

1.7.9.5

Amarjargal Gundjalam

author

2015-10-26 13:09 UTC #2 lore raw

PATCH 2/6 staging: media: omap4iss: Fixes misspelling

In reply to Amarjargal Gundjalam

This patch fixes the checkpatch issue:

CHECK: 'splitted' may be misspelled - perhaps 'split'?

Signed-off-by Amarjargal Gundjalam <[email protected]>

---
 drivers/staging/media/omap4iss/iss_ipipeif.c |    2 +-
 drivers/staging/media/omap4iss/iss_resizer.c |    4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

drivers/staging/media/omap4iss/iss_ipipeif.c +1 -1

index fcafdbe..7c78ea1 100644
@@ -115,7 +115,7 @@ static void ipipeif_set_outaddr(struct iss_ipipeif_device *ipipeif, u32 addr)
 {
 	struct iss_device *iss = to_iss_device(ipipeif);
 
-	/* Save address splitted in Base Address H & L */
+	/* Save address split in Base Address H & L */
 	iss_reg_write(iss, OMAP4_ISS_MEM_ISP_ISIF, ISIF_CADU,
 		      (addr >> (16 + 5)) & ISIF_CADU_MASK);
 	iss_reg_write(iss, OMAP4_ISS_MEM_ISP_ISIF, ISIF_CADL,

drivers/staging/media/omap4iss/iss_resizer.c +2 -2

index 8035e01..48bed44 100644
@@ -143,7 +143,7 @@ static void resizer_set_outaddr(struct iss_resizer_device *resizer, u32 addr)
 	informat = &resizer->formats[RESIZER_PAD_SINK];
 	outformat = &resizer->formats[RESIZER_PAD_SOURCE_MEM];
 
-	/* Save address splitted in Base Address H & L */
+	/* Save address split in Base Address H & L */
 	iss_reg_write(iss, OMAP4_ISS_MEM_ISP_RESIZER, RZA_SDR_Y_BAD_H,
 		      (addr >> 16) & 0xffff);
 	iss_reg_write(iss, OMAP4_ISS_MEM_ISP_RESIZER, RZA_SDR_Y_BAD_L,

@@ -168,7 +168,7 @@ static void resizer_set_outaddr(struct iss_resizer_device *resizer, u32 addr)
 			c_addr |= addr & 0x7f;
 		}
 
-		/* Save address splitted in Base Address H & L */
+		/* Save address split in Base Address H & L */
 		iss_reg_write(iss, OMAP4_ISS_MEM_ISP_RESIZER, RZA_SDR_C_BAD_H,
 			      (c_addr >> 16) & 0xffff);
 		iss_reg_write(iss, OMAP4_ISS_MEM_ISP_RESIZER, RZA_SDR_C_BAD_L,

Signature · 1 line

1.7.9.5

Amarjargal Gundjalam

author

2015-10-26 13:09 UTC #3 lore raw

PATCH 3/6 staging: media: omap4iss: Replaces bit shift on 1 with BIT Macro

In reply to Amarjargal Gundjalam

This patch fixes some of the checkpatch issue:

CHECK: Prefer using the BIT macro

Signed-off-by Amarjargal Gundjalam <[email protected]>

---
 drivers/staging/media/omap4iss/iss_csi2.h    |    4 +-
 drivers/staging/media/omap4iss/iss_ipipe.h   |    2 +-
 drivers/staging/media/omap4iss/iss_ipipeif.h |    4 +-
 drivers/staging/media/omap4iss/iss_regs.h    |  316 +++++++++++++-------------
 drivers/staging/media/omap4iss/iss_resizer.h |    2 +-
 5 files changed, 164 insertions(+), 164 deletions(-)

drivers/staging/media/omap4iss/iss_csi2.h +2 -2

index 3b37978..f2f5343 100644
@@ -116,8 +116,8 @@ struct iss_csi2_ctrl_cfg {
 #define CSI2_PAD_SOURCE		1
 #define CSI2_PADS_NUM		2
 
-#define CSI2_OUTPUT_IPIPEIF	(1 << 0)
-#define CSI2_OUTPUT_MEMORY	(1 << 1)
+#define CSI2_OUTPUT_IPIPEIF	BIT(0)
+#define CSI2_OUTPUT_MEMORY	BIT(1)
 
 struct iss_csi2_device {
 	struct v4l2_subdev subdev;

drivers/staging/media/omap4iss/iss_ipipe.h +1 -1

index c22d904..b8c1b8e0 100644
@@ -21,7 +21,7 @@ enum ipipe_input_entity {
 	IPIPE_INPUT_IPIPEIF,
 };
 
-#define IPIPE_OUTPUT_VP		(1 << 0)
+#define IPIPE_OUTPUT_VP				BIT(0)
 
 /* Sink and source IPIPE pads */
 #define IPIPE_PAD_SINK				0

drivers/staging/media/omap4iss/iss_ipipeif.h +2 -2

index cbdccb9..cf8a47a 100644
@@ -22,8 +22,8 @@ enum ipipeif_input_entity {
 	IPIPEIF_INPUT_CSI2B
 };
 
-#define IPIPEIF_OUTPUT_MEMORY		(1 << 0)
-#define IPIPEIF_OUTPUT_VP		(1 << 1)
+#define IPIPEIF_OUTPUT_MEMORY			BIT(0)
+#define IPIPEIF_OUTPUT_VP			BIT(1)
 
 /* Sink and source IPIPEIF pads */
 #define IPIPEIF_PAD_SINK			0

drivers/staging/media/omap4iss/iss_regs.h +158 ~~-158~~

493 lines not on this page · raw message

drivers/staging/media/omap4iss/iss_resizer.h +1 -1

index 3727498..d2a4968 100644
@@ -22,7 +22,7 @@ enum resizer_input_entity {
 	RESIZER_INPUT_IPIPEIF
 };
 
-#define RESIZER_OUTPUT_MEMORY		(1 << 0)
+#define RESIZER_OUTPUT_MEMORY			BIT(0)
 
 /* Sink and source RESIZER pads */
 #define RESIZER_PAD_SINK			0

Signature · 1 line

1.7.9.5

Julia Lawall

2015-10-26 14:46 UTC #4 lore raw

Re: [Outreachy kernel] [PATCH 3/6] staging: media: omap4iss: Replaces bit shift on 1 with BIT Macro

drivers/staging/media/omap4iss/iss_ipipe.h enum ipipe_input_entity { · line 24

Quoted 10 lines

drivers/staging/media/omap4iss/iss_ipipe.h +1 -1

index c22d904..b8c1b8e0 100644
@@ -21,7 +21,7 @@ enum ipipe_input_entity {
 	IPIPE_INPUT_IPIPEIF,
 };
 
-#define IPIPE_OUTPUT_VP		(1 << 0)
+#define IPIPE_OUTPUT_VP				BIT(0)

Why did the amount of space change?

Quoted 8 lines

drivers/staging/media/omap4iss/iss_ipipe.h +0 -0
 /* Sink and source IPIPE pads */
 #define IPIPE_PAD_SINK				0
drivers/staging/media/omap4iss/iss_ipipeif.h +0 -0
index cbdccb9..cf8a47a 100644

drivers/staging/media/omap4iss/iss_ipipeif.h enum ipipeif_input_entity { · line 26

Quoted 7 lines

drivers/staging/media/omap4iss/iss_ipipeif.h +2 -2

@@ -22,8 +22,8 @@ enum ipipeif_input_entity {
 	IPIPEIF_INPUT_CSI2B
 };
 
-#define IPIPEIF_OUTPUT_MEMORY		(1 << 0)
-#define IPIPEIF_OUTPUT_VP		(1 << 1)
+#define IPIPEIF_OUTPUT_MEMORY			BIT(0)
+#define IPIPEIF_OUTPUT_VP			BIT(1)

Here, however, you could take advantage of the opportunity to line them up. Maybe these are just a problem with tabs and the patch?

julia

Quoted 541 lines

drivers/staging/media/omap4iss/iss_ipipeif.h +0 -0

 /* Sink and source IPIPEIF pads */
 #define IPIPEIF_PAD_SINK			0

drivers/staging/media/omap4iss/iss_regs.h +158 ~~-158~~

index d2b6b6a..cb415e8 100644
@@ -22,21 +22,21 @@
 #define ISS_HL_SYSCONFIG_IDLEMODE_FORCEIDLE		0x0
 #define ISS_HL_SYSCONFIG_IDLEMODE_NOIDLE		0x1
 #define ISS_HL_SYSCONFIG_IDLEMODE_SMARTIDLE		0x2
-#define ISS_HL_SYSCONFIG_SOFTRESET			(1 << 0)
+#define ISS_HL_SYSCONFIG_SOFTRESET			BIT(0)
 
 #define ISS_HL_IRQSTATUS_RAW(i)				(0x20 + (0x10 * (i)))
 #define ISS_HL_IRQSTATUS(i)				(0x24 + (0x10 * (i)))
 #define ISS_HL_IRQENABLE_SET(i)				(0x28 + (0x10 * (i)))
 #define ISS_HL_IRQENABLE_CLR(i)				(0x2c + (0x10 * (i)))
 
-#define ISS_HL_IRQ_HS_VS				(1 << 17)
-#define ISS_HL_IRQ_SIMCOP(i)				(1 << (12 + (i)))
-#define ISS_HL_IRQ_BTE					(1 << 11)
-#define ISS_HL_IRQ_CBUFF				(1 << 10)
-#define ISS_HL_IRQ_CCP2(i)				(1 << ((i) > 3 ? 16 : 14 + (i)))
-#define ISS_HL_IRQ_CSIB					(1 << 5)
-#define ISS_HL_IRQ_CSIA					(1 << 4)
-#define ISS_HL_IRQ_ISP(i)				(1 << (i))
+#define ISS_HL_IRQ_HS_VS			BIT(17)
+#define ISS_HL_IRQ_SIMCOP(i)			BIT(12 + (i))
+#define ISS_HL_IRQ_BTE				BIT(11)
+#define ISS_HL_IRQ_CBUFF			BIT(10)
+#define ISS_HL_IRQ_CCP2(i)			BIT((i) > 3 ? 16 : 14 + (i))
+#define ISS_HL_IRQ_CSIB				BIT(5)
+#define ISS_HL_IRQ_CSIA				BIT(4)
+#define ISS_HL_IRQ_ISP(i)			BIT(i)
 
 #define ISS_CTRL					0x80
 #define ISS_CTRL_CLK_DIV_MASK				(3 << 4)

@@ -46,24 +46,24 @@
 #define ISS_CTRL_SYNC_DETECT_VS_RAISING			(3 << 0)
 
 #define ISS_CLKCTRL					0x84
-#define ISS_CLKCTRL_VPORT2_CLK				(1 << 30)
-#define ISS_CLKCTRL_VPORT1_CLK				(1 << 29)
-#define ISS_CLKCTRL_VPORT0_CLK				(1 << 28)
-#define ISS_CLKCTRL_CCP2				(1 << 4)
-#define ISS_CLKCTRL_CSI2_B				(1 << 3)
-#define ISS_CLKCTRL_CSI2_A				(1 << 2)
-#define ISS_CLKCTRL_ISP					(1 << 1)
-#define ISS_CLKCTRL_SIMCOP				(1 << 0)
+#define ISS_CLKCTRL_VPORT2_CLK				BIT(30)
+#define ISS_CLKCTRL_VPORT1_CLK				BIT(29)
+#define ISS_CLKCTRL_VPORT0_CLK				BIT(28)
+#define ISS_CLKCTRL_CCP2				BIT(4)
+#define ISS_CLKCTRL_CSI2_B				BIT(3)
+#define ISS_CLKCTRL_CSI2_A				BIT(2)
+#define ISS_CLKCTRL_ISP					BIT(1)
+#define ISS_CLKCTRL_SIMCOP				BIT(0)
 
 #define ISS_CLKSTAT					0x88
-#define ISS_CLKSTAT_VPORT2_CLK				(1 << 30)
-#define ISS_CLKSTAT_VPORT1_CLK				(1 << 29)
-#define ISS_CLKSTAT_VPORT0_CLK				(1 << 28)
-#define ISS_CLKSTAT_CCP2				(1 << 4)
-#define ISS_CLKSTAT_CSI2_B				(1 << 3)
-#define ISS_CLKSTAT_CSI2_A				(1 << 2)
-#define ISS_CLKSTAT_ISP					(1 << 1)
-#define ISS_CLKSTAT_SIMCOP				(1 << 0)
+#define ISS_CLKSTAT_VPORT2_CLK				BIT(30)
+#define ISS_CLKSTAT_VPORT1_CLK				BIT(29)
+#define ISS_CLKSTAT_VPORT0_CLK				BIT(28)
+#define ISS_CLKSTAT_CCP2				BIT(4)
+#define ISS_CLKSTAT_CSI2_B				BIT(3)
+#define ISS_CLKSTAT_CSI2_A				BIT(2)
+#define ISS_CLKSTAT_ISP					BIT(1)
+#define ISS_CLKSTAT_SIMCOP				BIT(0)
 
 #define ISS_PM_STATUS					0x8c
 #define ISS_PM_STATUS_CBUFF_PM_MASK			(3 << 12)

@@ -75,15 +75,15 @@
 #define ISS_PM_STATUS_CSI2_A_PM_MASK			(3 << 0)
 
 #define REGISTER0					0x0
-#define REGISTER0_HSCLOCKCONFIG				(1 << 24)
+#define REGISTER0_HSCLOCKCONFIG				BIT(24)
 #define REGISTER0_THS_TERM_MASK				(0xff << 8)
 #define REGISTER0_THS_TERM_SHIFT			8
 #define REGISTER0_THS_SETTLE_MASK			(0xff << 0)
 #define REGISTER0_THS_SETTLE_SHIFT			0
 
 #define REGISTER1					0x4
-#define REGISTER1_RESET_DONE_CTRLCLK			(1 << 29)
-#define REGISTER1_CLOCK_MISS_DETECTOR_STATUS		(1 << 25)
+#define REGISTER1_RESET_DONE_CTRLCLK			BIT(29)
+#define REGISTER1_CLOCK_MISS_DETECTOR_STATUS		BIT(25)
 #define REGISTER1_TCLK_TERM_MASK			(0x3f << 18)
 #define REGISTER1_TCLK_TERM_SHIFT			18
 #define REGISTER1_DPHY_HS_SYNC_PATTERN_SHIFT		10

@@ -103,20 +103,20 @@
 #define CSI2_SYSCONFIG_AUTO_IDLE			(1 << 0)
 
 #define CSI2_SYSSTATUS					0x14
-#define CSI2_SYSSTATUS_RESET_DONE			(1 << 0)
+#define CSI2_SYSSTATUS_RESET_DONE			BIT(0)
 
 #define CSI2_IRQSTATUS					0x18
 #define CSI2_IRQENABLE					0x1c
 
 /* Shared bits across CSI2_IRQENABLE and IRQSTATUS */
 
-#define CSI2_IRQ_OCP_ERR				(1 << 14)
-#define CSI2_IRQ_SHORT_PACKET				(1 << 13)
-#define CSI2_IRQ_ECC_CORRECTION				(1 << 12)
-#define CSI2_IRQ_ECC_NO_CORRECTION			(1 << 11)
-#define CSI2_IRQ_COMPLEXIO_ERR				(1 << 9)
-#define CSI2_IRQ_FIFO_OVF				(1 << 8)
-#define CSI2_IRQ_CONTEXT0				(1 << 0)
+#define CSI2_IRQ_OCP_ERR				BIT(14)
+#define CSI2_IRQ_SHORT_PACKET				BIT(13)
+#define CSI2_IRQ_ECC_CORRECTION				BIT(12)
+#define CSI2_IRQ_ECC_NO_CORRECTION			BIT(11)
+#define CSI2_IRQ_COMPLEXIO_ERR				BIT(9)
+#define CSI2_IRQ_FIFO_OVF				BIT(8)
+#define CSI2_IRQ_CONTEXT0				BIT(0)
 
 #define CSI2_CTRL					0x40
 #define CSI2_CTRL_MFLAG_LEVH_MASK			(7 << 20)

@@ -164,55 +164,55 @@
 #define CSI2_COMPLEXIO_IRQENABLE			0x60
 
 /* Shared bits across CSI2_COMPLEXIO_IRQENABLE and IRQSTATUS */
-#define CSI2_COMPLEXIO_IRQ_STATEALLULPMEXIT		(1 << 26)
-#define CSI2_COMPLEXIO_IRQ_STATEALLULPMENTER		(1 << 25)
-#define CSI2_COMPLEXIO_IRQ_STATEULPM5			(1 << 24)
-#define CSI2_COMPLEXIO_IRQ_STATEULPM4			(1 << 23)
-#define CSI2_COMPLEXIO_IRQ_STATEULPM3			(1 << 22)
-#define CSI2_COMPLEXIO_IRQ_STATEULPM2			(1 << 21)
-#define CSI2_COMPLEXIO_IRQ_STATEULPM1			(1 << 20)
-#define CSI2_COMPLEXIO_IRQ_ERRCONTROL5			(1 << 19)
-#define CSI2_COMPLEXIO_IRQ_ERRCONTROL4			(1 << 18)
-#define CSI2_COMPLEXIO_IRQ_ERRCONTROL3			(1 << 17)
-#define CSI2_COMPLEXIO_IRQ_ERRCONTROL2			(1 << 16)
-#define CSI2_COMPLEXIO_IRQ_ERRCONTROL1			(1 << 15)
-#define CSI2_COMPLEXIO_IRQ_ERRESC5			(1 << 14)
-#define CSI2_COMPLEXIO_IRQ_ERRESC4			(1 << 13)
-#define CSI2_COMPLEXIO_IRQ_ERRESC3			(1 << 12)
-#define CSI2_COMPLEXIO_IRQ_ERRESC2			(1 << 11)
-#define CSI2_COMPLEXIO_IRQ_ERRESC1			(1 << 10)
-#define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS5		(1 << 9)
-#define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS4		(1 << 8)
-#define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS3		(1 << 7)
-#define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS2		(1 << 6)
-#define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS1		(1 << 5)
-#define CSI2_COMPLEXIO_IRQ_ERRSOTHS5			(1 << 4)
-#define CSI2_COMPLEXIO_IRQ_ERRSOTHS4			(1 << 3)
-#define CSI2_COMPLEXIO_IRQ_ERRSOTHS3			(1 << 2)
-#define CSI2_COMPLEXIO_IRQ_ERRSOTHS2			(1 << 1)
-#define CSI2_COMPLEXIO_IRQ_ERRSOTHS1			(1 << 0)
+#define CSI2_COMPLEXIO_IRQ_STATEALLULPMEXIT		BIT(26)
+#define CSI2_COMPLEXIO_IRQ_STATEALLULPMENTER		BIT(25)
+#define CSI2_COMPLEXIO_IRQ_STATEULPM5			BIT(24)
+#define CSI2_COMPLEXIO_IRQ_STATEULPM4			BIT(23)
+#define CSI2_COMPLEXIO_IRQ_STATEULPM3			BIT(22)
+#define CSI2_COMPLEXIO_IRQ_STATEULPM2			BIT(21)
+#define CSI2_COMPLEXIO_IRQ_STATEULPM1			BIT(20)
+#define CSI2_COMPLEXIO_IRQ_ERRCONTROL5			BIT(19)
+#define CSI2_COMPLEXIO_IRQ_ERRCONTROL4			BIT(18)
+#define CSI2_COMPLEXIO_IRQ_ERRCONTROL3			BIT(17)
+#define CSI2_COMPLEXIO_IRQ_ERRCONTROL2			BIT(16)
+#define CSI2_COMPLEXIO_IRQ_ERRCONTROL1			BIT(15)
+#define CSI2_COMPLEXIO_IRQ_ERRESC5			BIT(14)
+#define CSI2_COMPLEXIO_IRQ_ERRESC4			BIT(13)
+#define CSI2_COMPLEXIO_IRQ_ERRESC3			BIT(12)
+#define CSI2_COMPLEXIO_IRQ_ERRESC2			BIT(11)
+#define CSI2_COMPLEXIO_IRQ_ERRESC1			BIT(10)
+#define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS5		BIT(9)
+#define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS4		BIT(8)
+#define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS3		BIT(7)
+#define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS2		BIT(6)
+#define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS1		BIT(5)
+#define CSI2_COMPLEXIO_IRQ_ERRSOTHS5			BIT(4)
+#define CSI2_COMPLEXIO_IRQ_ERRSOTHS4			BIT(3)
+#define CSI2_COMPLEXIO_IRQ_ERRSOTHS3			BIT(2)
+#define CSI2_COMPLEXIO_IRQ_ERRSOTHS2			BIT(1)
+#define CSI2_COMPLEXIO_IRQ_ERRSOTHS1			BIT(0)
 
 #define CSI2_DBG_P					0x68
 
 #define CSI2_TIMING					0x6c
-#define CSI2_TIMING_FORCE_RX_MODE_IO1			(1 << 15)
-#define CSI2_TIMING_STOP_STATE_X16_IO1			(1 << 14)
-#define CSI2_TIMING_STOP_STATE_X4_IO1			(1 << 13)
+#define CSI2_TIMING_FORCE_RX_MODE_IO1			BIT(15)
+#define CSI2_TIMING_STOP_STATE_X16_IO1			BIT(14)
+#define CSI2_TIMING_STOP_STATE_X4_IO1			BIT(13)
 #define CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK		(0x1fff << 0)
 #define CSI2_TIMING_STOP_STATE_COUNTER_IO1_SHIFT	0
 
 #define CSI2_CTX_CTRL1(i)				(0x70 + (0x20 * i))
-#define CSI2_CTX_CTRL1_GENERIC				(1 << 30)
+#define CSI2_CTX_CTRL1_GENERIC				BIT(30)
 #define CSI2_CTX_CTRL1_TRANSCODE			(0xf << 24)
 #define CSI2_CTX_CTRL1_FEC_NUMBER_MASK			(0xff << 16)
 #define CSI2_CTX_CTRL1_COUNT_MASK			(0xff << 8)
 #define CSI2_CTX_CTRL1_COUNT_SHIFT			8
-#define CSI2_CTX_CTRL1_EOF_EN				(1 << 7)
-#define CSI2_CTX_CTRL1_EOL_EN				(1 << 6)
-#define CSI2_CTX_CTRL1_CS_EN				(1 << 5)
-#define CSI2_CTX_CTRL1_COUNT_UNLOCK			(1 << 4)
-#define CSI2_CTX_CTRL1_PING_PONG			(1 << 3)
-#define CSI2_CTX_CTRL1_CTX_EN				(1 << 0)
+#define CSI2_CTX_CTRL1_EOF_EN				BIT(7)
+#define CSI2_CTX_CTRL1_EOL_EN				BIT(6)
+#define CSI2_CTX_CTRL1_CS_EN				BIT(5)
+#define CSI2_CTX_CTRL1_COUNT_UNLOCK			BIT(4)
+#define CSI2_CTX_CTRL1_PING_PONG			BIT(3)
+#define CSI2_CTX_CTRL1_CTX_EN				BIT(0)
 
 #define CSI2_CTX_CTRL2(i)				(0x74 + (0x20 * i))
 #define CSI2_CTX_CTRL2_FRAME_MASK			(0xffff << 16)

@@ -244,14 +244,14 @@
 		(0x3fff << CSI2_CTX_CTRL3_ALPHA_SHIFT)
 
 /* Shared bits across CSI2_CTX_IRQENABLE and IRQSTATUS */
-#define CSI2_CTX_IRQ_ECC_CORRECTION			(1 << 8)
-#define CSI2_CTX_IRQ_LINE_NUMBER			(1 << 7)
-#define CSI2_CTX_IRQ_FRAME_NUMBER			(1 << 6)
-#define CSI2_CTX_IRQ_CS					(1 << 5)
-#define CSI2_CTX_IRQ_LE					(1 << 3)
-#define CSI2_CTX_IRQ_LS					(1 << 2)
-#define CSI2_CTX_IRQ_FE					(1 << 1)
-#define CSI2_CTX_IRQ_FS					(1 << 0)
+#define CSI2_CTX_IRQ_ECC_CORRECTION			BIT(8)
+#define CSI2_CTX_IRQ_LINE_NUMBER			BIT(7)
+#define CSI2_CTX_IRQ_FRAME_NUMBER			BIT(6)
+#define CSI2_CTX_IRQ_CS					BIT(5)
+#define CSI2_CTX_IRQ_LE					BIT(3)
+#define CSI2_CTX_IRQ_LS					BIT(2)
+#define CSI2_CTX_IRQ_FE					BIT(1)
+#define CSI2_CTX_IRQ_FS					BIT(0)
 
 /* ISS BTE */
 #define BTE_CTRL					(0x0030)

@@ -272,49 +272,49 @@
 #define ISP5_IRQENABLE_CLR(i)				(0x0030 + (0x10 * (i)))
 
 /* Bits shared for ISP5_IRQ* registers */
-#define ISP5_IRQ_OCP_ERR				(1 << 31)
-#define ISP5_IRQ_IPIPE_INT_DPC_RNEW1			(1 << 29)
-#define ISP5_IRQ_IPIPE_INT_DPC_RNEW0			(1 << 28)
-#define ISP5_IRQ_IPIPE_INT_DPC_INIT			(1 << 27)
-#define ISP5_IRQ_IPIPE_INT_EOF				(1 << 25)
-#define ISP5_IRQ_H3A_INT_EOF				(1 << 24)
-#define ISP5_IRQ_RSZ_INT_EOF1				(1 << 23)
-#define ISP5_IRQ_RSZ_INT_EOF0				(1 << 22)
-#define ISP5_IRQ_RSZ_FIFO_IN_BLK_ERR			(1 << 19)
-#define ISP5_IRQ_RSZ_FIFO_OVF				(1 << 18)
-#define ISP5_IRQ_RSZ_INT_CYC_RSZB			(1 << 17)
-#define ISP5_IRQ_RSZ_INT_CYC_RSZA			(1 << 16)
-#define ISP5_IRQ_RSZ_INT_DMA				(1 << 15)
-#define ISP5_IRQ_RSZ_INT_LAST_PIX			(1 << 14)
-#define ISP5_IRQ_RSZ_INT_REG				(1 << 13)
-#define ISP5_IRQ_H3A_INT				(1 << 12)
-#define ISP5_IRQ_AF_INT					(1 << 11)
-#define ISP5_IRQ_AEW_INT				(1 << 10)
-#define ISP5_IRQ_IPIPEIF_IRQ				(1 << 9)
-#define ISP5_IRQ_IPIPE_INT_HST				(1 << 8)
-#define ISP5_IRQ_IPIPE_INT_BSC				(1 << 7)
-#define ISP5_IRQ_IPIPE_INT_DMA				(1 << 6)
-#define ISP5_IRQ_IPIPE_INT_LAST_PIX			(1 << 5)
-#define ISP5_IRQ_IPIPE_INT_REG				(1 << 4)
-#define ISP5_IRQ_ISIF_INT(i)				(1 << (i))
+#define ISP5_IRQ_OCP_ERR				BIT(31)
+#define ISP5_IRQ_IPIPE_INT_DPC_RNEW1			BIT(29)
+#define ISP5_IRQ_IPIPE_INT_DPC_RNEW0			BIT(28)
+#define ISP5_IRQ_IPIPE_INT_DPC_INIT			BIT(27)
+#define ISP5_IRQ_IPIPE_INT_EOF				BIT(25)
+#define ISP5_IRQ_H3A_INT_EOF				BIT(24)
+#define ISP5_IRQ_RSZ_INT_EOF1				BIT(23)
+#define ISP5_IRQ_RSZ_INT_EOF0				BIT(22)
+#define ISP5_IRQ_RSZ_FIFO_IN_BLK_ERR			BIT(19)
+#define ISP5_IRQ_RSZ_FIFO_OVF				BIT(18)
+#define ISP5_IRQ_RSZ_INT_CYC_RSZB			BIT(17)
+#define ISP5_IRQ_RSZ_INT_CYC_RSZA			BIT(16)
+#define ISP5_IRQ_RSZ_INT_DMA				BIT(15)
+#define ISP5_IRQ_RSZ_INT_LAST_PIX			BIT(14)
+#define ISP5_IRQ_RSZ_INT_REG				BIT(13)
+#define ISP5_IRQ_H3A_INT				BIT(12)
+#define ISP5_IRQ_AF_INT					BIT(11)
+#define ISP5_IRQ_AEW_INT				BIT(10)
+#define ISP5_IRQ_IPIPEIF_IRQ				BIT(9)
+#define ISP5_IRQ_IPIPE_INT_HST				BIT(8)
+#define ISP5_IRQ_IPIPE_INT_BSC				BIT(7)
+#define ISP5_IRQ_IPIPE_INT_DMA				BIT(6)
+#define ISP5_IRQ_IPIPE_INT_LAST_PIX			BIT(5)
+#define ISP5_IRQ_IPIPE_INT_REG				BIT(4)
+#define ISP5_IRQ_ISIF_INT(i)				BIT(i)
 
 #define ISP5_CTRL					(0x006c)
-#define ISP5_CTRL_MSTANDBY				(1 << 24)
-#define ISP5_CTRL_VD_PULSE_EXT				(1 << 23)
-#define ISP5_CTRL_MSTANDBY_WAIT				(1 << 20)
-#define ISP5_CTRL_BL_CLK_ENABLE				(1 << 15)
-#define ISP5_CTRL_ISIF_CLK_ENABLE			(1 << 14)
-#define ISP5_CTRL_H3A_CLK_ENABLE			(1 << 13)
-#define ISP5_CTRL_RSZ_CLK_ENABLE			(1 << 12)
-#define ISP5_CTRL_IPIPE_CLK_ENABLE			(1 << 11)
-#define ISP5_CTRL_IPIPEIF_CLK_ENABLE			(1 << 10)
-#define ISP5_CTRL_SYNC_ENABLE				(1 << 9)
-#define ISP5_CTRL_PSYNC_CLK_SEL				(1 << 8)
+#define ISP5_CTRL_MSTANDBY				BIT(24)
+#define ISP5_CTRL_VD_PULSE_EXT				BIT(23)
+#define ISP5_CTRL_MSTANDBY_WAIT				BIT(20)
+#define ISP5_CTRL_BL_CLK_ENABLE				BIT(15)
+#define ISP5_CTRL_ISIF_CLK_ENABLE			BIT(14)
+#define ISP5_CTRL_H3A_CLK_ENABLE			BIT(13)
+#define ISP5_CTRL_RSZ_CLK_ENABLE			BIT(12)
+#define ISP5_CTRL_IPIPE_CLK_ENABLE			BIT(11)
+#define ISP5_CTRL_IPIPEIF_CLK_ENABLE			BIT(10)
+#define ISP5_CTRL_SYNC_ENABLE				BIT(9)
+#define ISP5_CTRL_PSYNC_CLK_SEL				BIT(8)
 
 /* ISS ISP ISIF register offsets */
 #define ISIF_SYNCEN					(0x0000)
-#define ISIF_SYNCEN_DWEN				(1 << 1)
-#define ISIF_SYNCEN_SYEN				(1 << 0)
+#define ISIF_SYNCEN_DWEN				BIT(1)
+#define ISIF_SYNCEN_SYEN				BIT(0)
 
 #define ISIF_MODESET					(0x0004)
 #define ISIF_MODESET_INPMOD_MASK			(3 << 12)

@@ -338,7 +338,7 @@
 #define ISIF_LNV_MASK					(0x7fff)
 
 #define ISIF_HSIZE					(0x0034)
-#define ISIF_HSIZE_ADCR					(1 << 12)
+#define ISIF_HSIZE_ADCR					BIT(12)
 #define ISIF_HSIZE_HSIZE_MASK				(0xfff)
 
 #define ISIF_CADU					(0x003c)

@@ -373,7 +373,7 @@
 #define ISIF_CGAMMAWD_GWDI(bpp)				((16 - (bpp)) << 1)
 
 #define ISIF_CCDCFG					(0x0088)
-#define ISIF_CCDCFG_Y8POS				(1 << 11)
+#define ISIF_CCDCFG_Y8POS				BIT(11)
 
 /* ISS ISP IPIPEIF register offsets */
 #define IPIPEIF_ENABLE					(0x0000)

@@ -391,22 +391,22 @@
 #define IPIPEIF_CFG1_INPSRC2_SDRAM_YUV			(3 << 2)
 
 #define IPIPEIF_CFG2					(0x0030)
-#define IPIPEIF_CFG2_YUV8P				(1 << 7)
-#define IPIPEIF_CFG2_YUV8				(1 << 6)
-#define IPIPEIF_CFG2_YUV16				(1 << 3)
-#define IPIPEIF_CFG2_VDPOL				(1 << 2)
-#define IPIPEIF_CFG2_HDPOL				(1 << 1)
-#define IPIPEIF_CFG2_INTSW				(1 << 0)
+#define IPIPEIF_CFG2_YUV8P				BIT(7)
+#define IPIPEIF_CFG2_YUV8				BIT(6)
+#define IPIPEIF_CFG2_YUV16				BIT(3)
+#define IPIPEIF_CFG2_VDPOL				BIT(2)
+#define IPIPEIF_CFG2_HDPOL				BIT(1)
+#define IPIPEIF_CFG2_INTSW				BIT(0)
 
 #define IPIPEIF_CLKDIV					(0x0040)
 
 /* ISS ISP IPIPE register offsets */
 #define IPIPE_SRC_EN					(0x0000)
-#define IPIPE_SRC_EN_EN					(1 << 0)
+#define IPIPE_SRC_EN_EN					BIT(0)
 
 #define IPIPE_SRC_MODE					(0x0004)
-#define IPIPE_SRC_MODE_WRT				(1 << 1)
-#define IPIPE_SRC_MODE_OST				(1 << 0)
+#define IPIPE_SRC_MODE_WRT				BIT(1)
+#define IPIPE_SRC_MODE_OST				BIT(0)
 
 #define IPIPE_SRC_FMT					(0x0008)
 #define IPIPE_SRC_FMT_RAW2YUV				(0 << 0)

@@ -449,13 +449,13 @@
 #define IPIPE_SRC_STA					(0x0024)
 
 #define IPIPE_GCK_MMR					(0x0028)
-#define IPIPE_GCK_MMR_REG				(1 << 0)
+#define IPIPE_GCK_MMR_REG				BIT(0)
 
 #define IPIPE_GCK_PIX					(0x002c)
-#define IPIPE_GCK_PIX_G3				(1 << 3)
-#define IPIPE_GCK_PIX_G2				(1 << 2)
-#define IPIPE_GCK_PIX_G1				(1 << 1)
-#define IPIPE_GCK_PIX_G0				(1 << 0)
+#define IPIPE_GCK_PIX_G3				BIT(3)
+#define IPIPE_GCK_PIX_G2				BIT(2)
+#define IPIPE_GCK_PIX_G1				BIT(1)
+#define IPIPE_GCK_PIX_G0				BIT(0)
 
 #define IPIPE_DPC_LUT_EN				(0x0034)
 #define IPIPE_DPC_LUT_SEL				(0x0038)

@@ -633,8 +633,8 @@
 #define IPIPE_YUV_OFT_CR				(0x02c4)
 
 #define IPIPE_YUV_PHS					(0x02c8)
-#define IPIPE_YUV_PHS_LPF				(1 << 1)
-#define IPIPE_YUV_PHS_POS				(1 << 0)
+#define IPIPE_YUV_PHS_LPF				BIT(1)
+#define IPIPE_YUV_PHS_POS				BIT(0)
 
 #define IPIPE_YEE_EN					(0x02d4)
 #define IPIPE_YEE_TYP					(0x02d8)

@@ -739,8 +739,8 @@
 /* ISS ISP Resizer register offsets */
 #define RSZ_REVISION					(0x0000)
 #define RSZ_SYSCONFIG					(0x0004)
-#define RSZ_SYSCONFIG_RSZB_CLK_EN			(1 << 9)
-#define RSZ_SYSCONFIG_RSZA_CLK_EN			(1 << 8)
+#define RSZ_SYSCONFIG_RSZB_CLK_EN			BIT(9)
+#define RSZ_SYSCONFIG_RSZA_CLK_EN			BIT(8)
 
 #define RSZ_IN_FIFO_CTRL				(0x000c)
 #define RSZ_IN_FIFO_CTRL_THRLD_LOW_MASK			(0x1ff << 16)

@@ -752,18 +752,18 @@
 #define RSZ_FRACDIV_MASK				(0xffff)
 
 #define RSZ_SRC_EN					(0x0020)
-#define RSZ_SRC_EN_SRC_EN				(1 << 0)
+#define RSZ_SRC_EN_SRC_EN				BIT(0)
 
 #define RSZ_SRC_MODE					(0x0024)
-#define RSZ_SRC_MODE_OST				(1 << 0)
-#define RSZ_SRC_MODE_WRT				(1 << 1)
+#define RSZ_SRC_MODE_OST				BIT(0)
+#define RSZ_SRC_MODE_WRT				BIT(1)
 
 #define RSZ_SRC_FMT0					(0x0028)
-#define RSZ_SRC_FMT0_BYPASS				(1 << 1)
-#define RSZ_SRC_FMT0_SEL				(1 << 0)
+#define RSZ_SRC_FMT0_BYPASS				BIT(1)
+#define RSZ_SRC_FMT0_SEL				BIT(0)
 
 #define RSZ_SRC_FMT1					(0x002c)
-#define RSZ_SRC_FMT1_IN420				(1 << 1)
+#define RSZ_SRC_FMT1_IN420				BIT(1)
 
 #define RSZ_SRC_VPS					(0x0030)
 #define RSZ_SRC_VSZ					(0x0034)

@@ -773,10 +773,10 @@
 #define RSZ_DMA_RZB					(0x0044)
 #define RSZ_DMA_STA					(0x0048)
 #define RSZ_GCK_MMR					(0x004c)
-#define RSZ_GCK_MMR_MMR					(1 << 0)
+#define RSZ_GCK_MMR_MMR					BIT(0)
 
 #define RSZ_GCK_SDR					(0x0054)
-#define RSZ_GCK_SDR_CORE				(1 << 0)
+#define RSZ_GCK_SDR_CORE				BIT(0)
 
 #define RSZ_IRQ_RZA					(0x0058)
 #define RSZ_IRQ_RZA_MASK				(0x1fff)

@@ -790,12 +790,12 @@
 #define RSZ_YUV_C_MAX					(0x006c)
 
 #define RSZ_SEQ						(0x0074)
-#define RSZ_SEQ_HRVB					(1 << 2)
-#define RSZ_SEQ_HRVA					(1 << 0)
+#define RSZ_SEQ_HRVB					BIT(2)
+#define RSZ_SEQ_HRVA					BIT(0)
 
 #define RZA_EN						(0x0078)
 #define RZA_MODE					(0x007c)
-#define RZA_MODE_ONE_SHOT				(1 << 0)
+#define RZA_MODE_ONE_SHOT				BIT(0)
 
 #define RZA_420						(0x0080)
 #define RZA_I_VPS					(0x0084)

@@ -859,10 +859,10 @@
 #define RZB_SDR_C_PTR_E					(0x0194)
 
 /* Shared Bitmasks between RZA & RZB */
-#define RSZ_EN_EN					(1 << 0)
+#define RSZ_EN_EN					BIT(0)
 
-#define RSZ_420_CEN					(1 << 1)
-#define RSZ_420_YEN					(1 << 0)
+#define RSZ_420_CEN					BIT(1)
+#define RSZ_420_YEN					BIT(0)
 
 #define RSZ_I_VPS_MASK					(0x1fff)

@@ -878,8 +878,8 @@
 
 #define RSZ_V_DIF_MASK					(0x3fff)
 
-#define RSZ_V_TYP_C					(1 << 1)
-#define RSZ_V_TYP_Y					(1 << 0)
+#define RSZ_V_TYP_C					BIT(1)
+#define RSZ_V_TYP_Y					BIT(0)
 
 #define RSZ_V_LPF_C_MASK				(0x3f << 6)
 #define RSZ_V_LPF_C_SHIFT				6

@@ -890,14 +890,14 @@
 
 #define RSZ_H_DIF_MASK					(0x3fff)
 
-#define RSZ_H_TYP_C					(1 << 1)
-#define RSZ_H_TYP_Y					(1 << 0)
+#define RSZ_H_TYP_C					BIT(1)
+#define RSZ_H_TYP_Y					BIT(0)
 
 #define RSZ_H_LPF_C_MASK				(0x3f << 6)
 #define RSZ_H_LPF_C_SHIFT				6
 #define RSZ_H_LPF_Y_MASK				(0x3f << 0)
 #define RSZ_H_LPF_Y_SHIFT				0
 
-#define RSZ_DWN_EN_DWN_EN				(1 << 0)
+#define RSZ_DWN_EN_DWN_EN				BIT(0)
 
 #endif /* _OMAP4_ISS_REGS_H_ */

drivers/staging/media/omap4iss/iss_resizer.h +1 -2

index 3727498..d2a4968 100644
@@ -22,7 +22,7 @@ enum resizer_input_entity {
 	RESIZER_INPUT_IPIPEIF
 };
 
-#define RESIZER_OUTPUT_MEMORY		(1 << 0)
+#define RESIZER_OUTPUT_MEMORY			BIT(0)
 
 /* Sink and source RESIZER pads */
 #define RESIZER_PAD_SINK			0
--

1.7.9.5

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Amarjargal Gundjalam

author

2015-10-26 15:48 UTC #5 lore raw

Re: [Outreachy kernel] [PATCH 3/6] staging: media: omap4iss: Replaces bit shift on 1 with BIT Macro

Quoted 8 lines · On Mon, 26 Oct 2015 15:46:27 +0100 (CET) Julia Lawall <[email protected]>…

Quoted 8 lines
drivers/staging/media/omap4iss/iss_ipipe.h +0 -0
index c22d904..b8c1b8e0 100644
@@ -21,7 +21,7 @@ enum ipipe_input_entity {
 	IPIPE_INPUT_IPIPEIF,
 };
 

Quoted 4 lines

drivers/staging/media/omap4iss/iss_ipipe.h enum ipipe_input_entity { · line 24
Quoted 2 lines
drivers/staging/media/omap4iss/iss_ipipe.h +1 -1
-#define IPIPE_OUTPUT_VP		(1 << 0)
+#define IPIPE_OUTPUT_VP				BIT(0)
Why did the amount of space change?

I tried to align it with the the others below it.

Quoted 12 lines

Quoted 12 lines
drivers/staging/media/omap4iss/iss_ipipe.h +0 -0
 /* Sink and source IPIPE pads */
 #define IPIPE_PAD_SINK				0
drivers/staging/media/omap4iss/iss_ipipeif.h +0 -0
index cbdccb9..cf8a47a 100644
@@ -22,8 +22,8 @@ enum ipipeif_input_entity {
 	IPIPEIF_INPUT_CSI2B
 };
 

Quoted 8 lines

drivers/staging/media/omap4iss/iss_ipipeif.h enum ipipeif_input_entity { · line 26
Quoted 4 lines
drivers/staging/media/omap4iss/iss_ipipeif.h +2 -2
-#define IPIPEIF_OUTPUT_MEMORY		(1 << 0)
-#define IPIPEIF_OUTPUT_VP		(1 << 1)
+#define IPIPEIF_OUTPUT_MEMORY			BIT(0)
+#define IPIPEIF_OUTPUT_VP			BIT(1)
Here, however, you could take advantage of the opportunity to line them up. Maybe these are just a problem with tabs and the patch?

I did aligned them with tabs, maybe it's just a problem with patch formatting?

thanks,
amarjargal

Quoted 543 lines

julia

Quoted 541 lines

drivers/staging/media/omap4iss/iss_ipipeif.h +0 -0

 /* Sink and source IPIPEIF pads */
 #define IPIPEIF_PAD_SINK			0

drivers/staging/media/omap4iss/iss_regs.h +158 ~~-158~~

index d2b6b6a..cb415e8 100644
@@ -22,21 +22,21 @@
 #define ISS_HL_SYSCONFIG_IDLEMODE_FORCEIDLE		0x0
 #define ISS_HL_SYSCONFIG_IDLEMODE_NOIDLE		0x1
 #define ISS_HL_SYSCONFIG_IDLEMODE_SMARTIDLE		0x2
-#define ISS_HL_SYSCONFIG_SOFTRESET			(1 << 0)
+#define ISS_HL_SYSCONFIG_SOFTRESET			BIT(0)
 
 #define ISS_HL_IRQSTATUS_RAW(i)				(0x20 + (0x10 * (i)))
 #define ISS_HL_IRQSTATUS(i)				(0x24 + (0x10 * (i)))
 #define ISS_HL_IRQENABLE_SET(i)				(0x28 + (0x10 * (i)))
 #define ISS_HL_IRQENABLE_CLR(i)				(0x2c + (0x10 * (i)))
 
-#define ISS_HL_IRQ_HS_VS				(1 << 17)
-#define ISS_HL_IRQ_SIMCOP(i)				(1 << (12 + (i)))
-#define ISS_HL_IRQ_BTE					(1 << 11)
-#define ISS_HL_IRQ_CBUFF				(1 << 10)
-#define ISS_HL_IRQ_CCP2(i)				(1 << ((i) > 3 ? 16 : 14 + (i)))
-#define ISS_HL_IRQ_CSIB					(1 << 5)
-#define ISS_HL_IRQ_CSIA					(1 << 4)
-#define ISS_HL_IRQ_ISP(i)				(1 << (i))
+#define ISS_HL_IRQ_HS_VS			BIT(17)
+#define ISS_HL_IRQ_SIMCOP(i)			BIT(12 + (i))
+#define ISS_HL_IRQ_BTE				BIT(11)
+#define ISS_HL_IRQ_CBUFF			BIT(10)
+#define ISS_HL_IRQ_CCP2(i)			BIT((i) > 3 ? 16 : 14 + (i))
+#define ISS_HL_IRQ_CSIB				BIT(5)
+#define ISS_HL_IRQ_CSIA				BIT(4)
+#define ISS_HL_IRQ_ISP(i)			BIT(i)
 
 #define ISS_CTRL					0x80
 #define ISS_CTRL_CLK_DIV_MASK				(3 << 4)

@@ -46,24 +46,24 @@
 #define ISS_CTRL_SYNC_DETECT_VS_RAISING			(3 << 0)
 
 #define ISS_CLKCTRL					0x84
-#define ISS_CLKCTRL_VPORT2_CLK				(1 << 30)
-#define ISS_CLKCTRL_VPORT1_CLK				(1 << 29)
-#define ISS_CLKCTRL_VPORT0_CLK				(1 << 28)
-#define ISS_CLKCTRL_CCP2				(1 << 4)
-#define ISS_CLKCTRL_CSI2_B				(1 << 3)
-#define ISS_CLKCTRL_CSI2_A				(1 << 2)
-#define ISS_CLKCTRL_ISP					(1 << 1)
-#define ISS_CLKCTRL_SIMCOP				(1 << 0)
+#define ISS_CLKCTRL_VPORT2_CLK				BIT(30)
+#define ISS_CLKCTRL_VPORT1_CLK				BIT(29)
+#define ISS_CLKCTRL_VPORT0_CLK				BIT(28)
+#define ISS_CLKCTRL_CCP2				BIT(4)
+#define ISS_CLKCTRL_CSI2_B				BIT(3)
+#define ISS_CLKCTRL_CSI2_A				BIT(2)
+#define ISS_CLKCTRL_ISP					BIT(1)
+#define ISS_CLKCTRL_SIMCOP				BIT(0)
 
 #define ISS_CLKSTAT					0x88
-#define ISS_CLKSTAT_VPORT2_CLK				(1 << 30)
-#define ISS_CLKSTAT_VPORT1_CLK				(1 << 29)
-#define ISS_CLKSTAT_VPORT0_CLK				(1 << 28)
-#define ISS_CLKSTAT_CCP2				(1 << 4)
-#define ISS_CLKSTAT_CSI2_B				(1 << 3)
-#define ISS_CLKSTAT_CSI2_A				(1 << 2)
-#define ISS_CLKSTAT_ISP					(1 << 1)
-#define ISS_CLKSTAT_SIMCOP				(1 << 0)
+#define ISS_CLKSTAT_VPORT2_CLK				BIT(30)
+#define ISS_CLKSTAT_VPORT1_CLK				BIT(29)
+#define ISS_CLKSTAT_VPORT0_CLK				BIT(28)
+#define ISS_CLKSTAT_CCP2				BIT(4)
+#define ISS_CLKSTAT_CSI2_B				BIT(3)
+#define ISS_CLKSTAT_CSI2_A				BIT(2)
+#define ISS_CLKSTAT_ISP					BIT(1)
+#define ISS_CLKSTAT_SIMCOP				BIT(0)
 
 #define ISS_PM_STATUS					0x8c
 #define ISS_PM_STATUS_CBUFF_PM_MASK			(3 << 12)

@@ -75,15 +75,15 @@
 #define ISS_PM_STATUS_CSI2_A_PM_MASK			(3 << 0)
 
 #define REGISTER0					0x0
-#define REGISTER0_HSCLOCKCONFIG				(1 << 24)
+#define REGISTER0_HSCLOCKCONFIG				BIT(24)
 #define REGISTER0_THS_TERM_MASK				(0xff << 8)
 #define REGISTER0_THS_TERM_SHIFT			8
 #define REGISTER0_THS_SETTLE_MASK			(0xff << 0)
 #define REGISTER0_THS_SETTLE_SHIFT			0
 
 #define REGISTER1					0x4
-#define REGISTER1_RESET_DONE_CTRLCLK			(1 << 29)
-#define REGISTER1_CLOCK_MISS_DETECTOR_STATUS		(1 << 25)
+#define REGISTER1_RESET_DONE_CTRLCLK			BIT(29)
+#define REGISTER1_CLOCK_MISS_DETECTOR_STATUS		BIT(25)
 #define REGISTER1_TCLK_TERM_MASK			(0x3f << 18)
 #define REGISTER1_TCLK_TERM_SHIFT			18
 #define REGISTER1_DPHY_HS_SYNC_PATTERN_SHIFT		10

@@ -103,20 +103,20 @@
 #define CSI2_SYSCONFIG_AUTO_IDLE			(1 << 0)
 
 #define CSI2_SYSSTATUS					0x14
-#define CSI2_SYSSTATUS_RESET_DONE			(1 << 0)
+#define CSI2_SYSSTATUS_RESET_DONE			BIT(0)
 
 #define CSI2_IRQSTATUS					0x18
 #define CSI2_IRQENABLE					0x1c
 
 /* Shared bits across CSI2_IRQENABLE and IRQSTATUS */
 
-#define CSI2_IRQ_OCP_ERR				(1 << 14)
-#define CSI2_IRQ_SHORT_PACKET				(1 << 13)
-#define CSI2_IRQ_ECC_CORRECTION				(1 << 12)
-#define CSI2_IRQ_ECC_NO_CORRECTION			(1 << 11)
-#define CSI2_IRQ_COMPLEXIO_ERR				(1 << 9)
-#define CSI2_IRQ_FIFO_OVF				(1 << 8)
-#define CSI2_IRQ_CONTEXT0				(1 << 0)
+#define CSI2_IRQ_OCP_ERR				BIT(14)
+#define CSI2_IRQ_SHORT_PACKET				BIT(13)
+#define CSI2_IRQ_ECC_CORRECTION				BIT(12)
+#define CSI2_IRQ_ECC_NO_CORRECTION			BIT(11)
+#define CSI2_IRQ_COMPLEXIO_ERR				BIT(9)
+#define CSI2_IRQ_FIFO_OVF				BIT(8)
+#define CSI2_IRQ_CONTEXT0				BIT(0)
 
 #define CSI2_CTRL					0x40
 #define CSI2_CTRL_MFLAG_LEVH_MASK			(7 << 20)

@@ -164,55 +164,55 @@
 #define CSI2_COMPLEXIO_IRQENABLE			0x60
 
 /* Shared bits across CSI2_COMPLEXIO_IRQENABLE and IRQSTATUS */
-#define CSI2_COMPLEXIO_IRQ_STATEALLULPMEXIT		(1 << 26)
-#define CSI2_COMPLEXIO_IRQ_STATEALLULPMENTER		(1 << 25)
-#define CSI2_COMPLEXIO_IRQ_STATEULPM5			(1 << 24)
-#define CSI2_COMPLEXIO_IRQ_STATEULPM4			(1 << 23)
-#define CSI2_COMPLEXIO_IRQ_STATEULPM3			(1 << 22)
-#define CSI2_COMPLEXIO_IRQ_STATEULPM2			(1 << 21)
-#define CSI2_COMPLEXIO_IRQ_STATEULPM1			(1 << 20)
-#define CSI2_COMPLEXIO_IRQ_ERRCONTROL5			(1 << 19)
-#define CSI2_COMPLEXIO_IRQ_ERRCONTROL4			(1 << 18)
-#define CSI2_COMPLEXIO_IRQ_ERRCONTROL3			(1 << 17)
-#define CSI2_COMPLEXIO_IRQ_ERRCONTROL2			(1 << 16)
-#define CSI2_COMPLEXIO_IRQ_ERRCONTROL1			(1 << 15)
-#define CSI2_COMPLEXIO_IRQ_ERRESC5			(1 << 14)
-#define CSI2_COMPLEXIO_IRQ_ERRESC4			(1 << 13)
-#define CSI2_COMPLEXIO_IRQ_ERRESC3			(1 << 12)
-#define CSI2_COMPLEXIO_IRQ_ERRESC2			(1 << 11)
-#define CSI2_COMPLEXIO_IRQ_ERRESC1			(1 << 10)
-#define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS5		(1 << 9)
-#define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS4		(1 << 8)
-#define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS3		(1 << 7)
-#define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS2		(1 << 6)
-#define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS1		(1 << 5)
-#define CSI2_COMPLEXIO_IRQ_ERRSOTHS5			(1 << 4)
-#define CSI2_COMPLEXIO_IRQ_ERRSOTHS4			(1 << 3)
-#define CSI2_COMPLEXIO_IRQ_ERRSOTHS3			(1 << 2)
-#define CSI2_COMPLEXIO_IRQ_ERRSOTHS2			(1 << 1)
-#define CSI2_COMPLEXIO_IRQ_ERRSOTHS1			(1 << 0)
+#define CSI2_COMPLEXIO_IRQ_STATEALLULPMEXIT		BIT(26)
+#define CSI2_COMPLEXIO_IRQ_STATEALLULPMENTER		BIT(25)
+#define CSI2_COMPLEXIO_IRQ_STATEULPM5			BIT(24)
+#define CSI2_COMPLEXIO_IRQ_STATEULPM4			BIT(23)
+#define CSI2_COMPLEXIO_IRQ_STATEULPM3			BIT(22)
+#define CSI2_COMPLEXIO_IRQ_STATEULPM2			BIT(21)
+#define CSI2_COMPLEXIO_IRQ_STATEULPM1			BIT(20)
+#define CSI2_COMPLEXIO_IRQ_ERRCONTROL5			BIT(19)
+#define CSI2_COMPLEXIO_IRQ_ERRCONTROL4			BIT(18)
+#define CSI2_COMPLEXIO_IRQ_ERRCONTROL3			BIT(17)
+#define CSI2_COMPLEXIO_IRQ_ERRCONTROL2			BIT(16)
+#define CSI2_COMPLEXIO_IRQ_ERRCONTROL1			BIT(15)
+#define CSI2_COMPLEXIO_IRQ_ERRESC5			BIT(14)
+#define CSI2_COMPLEXIO_IRQ_ERRESC4			BIT(13)
+#define CSI2_COMPLEXIO_IRQ_ERRESC3			BIT(12)
+#define CSI2_COMPLEXIO_IRQ_ERRESC2			BIT(11)
+#define CSI2_COMPLEXIO_IRQ_ERRESC1			BIT(10)
+#define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS5		BIT(9)
+#define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS4		BIT(8)
+#define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS3		BIT(7)
+#define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS2		BIT(6)
+#define CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS1		BIT(5)
+#define CSI2_COMPLEXIO_IRQ_ERRSOTHS5			BIT(4)
+#define CSI2_COMPLEXIO_IRQ_ERRSOTHS4			BIT(3)
+#define CSI2_COMPLEXIO_IRQ_ERRSOTHS3			BIT(2)
+#define CSI2_COMPLEXIO_IRQ_ERRSOTHS2			BIT(1)
+#define CSI2_COMPLEXIO_IRQ_ERRSOTHS1			BIT(0)
 
 #define CSI2_DBG_P					0x68
 
 #define CSI2_TIMING					0x6c
-#define CSI2_TIMING_FORCE_RX_MODE_IO1			(1 << 15)
-#define CSI2_TIMING_STOP_STATE_X16_IO1			(1 << 14)
-#define CSI2_TIMING_STOP_STATE_X4_IO1			(1 << 13)
+#define CSI2_TIMING_FORCE_RX_MODE_IO1			BIT(15)
+#define CSI2_TIMING_STOP_STATE_X16_IO1			BIT(14)
+#define CSI2_TIMING_STOP_STATE_X4_IO1			BIT(13)
 #define CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK		(0x1fff << 0)
 #define CSI2_TIMING_STOP_STATE_COUNTER_IO1_SHIFT	0
 
 #define CSI2_CTX_CTRL1(i)				(0x70 + (0x20 * i))
-#define CSI2_CTX_CTRL1_GENERIC				(1 << 30)
+#define CSI2_CTX_CTRL1_GENERIC				BIT(30)
 #define CSI2_CTX_CTRL1_TRANSCODE			(0xf << 24)
 #define CSI2_CTX_CTRL1_FEC_NUMBER_MASK			(0xff << 16)
 #define CSI2_CTX_CTRL1_COUNT_MASK			(0xff << 8)
 #define CSI2_CTX_CTRL1_COUNT_SHIFT			8
-#define CSI2_CTX_CTRL1_EOF_EN				(1 << 7)
-#define CSI2_CTX_CTRL1_EOL_EN				(1 << 6)
-#define CSI2_CTX_CTRL1_CS_EN				(1 << 5)
-#define CSI2_CTX_CTRL1_COUNT_UNLOCK			(1 << 4)
-#define CSI2_CTX_CTRL1_PING_PONG			(1 << 3)
-#define CSI2_CTX_CTRL1_CTX_EN				(1 << 0)
+#define CSI2_CTX_CTRL1_EOF_EN				BIT(7)
+#define CSI2_CTX_CTRL1_EOL_EN				BIT(6)
+#define CSI2_CTX_CTRL1_CS_EN				BIT(5)
+#define CSI2_CTX_CTRL1_COUNT_UNLOCK			BIT(4)
+#define CSI2_CTX_CTRL1_PING_PONG			BIT(3)
+#define CSI2_CTX_CTRL1_CTX_EN				BIT(0)
 
 #define CSI2_CTX_CTRL2(i)				(0x74 + (0x20 * i))
 #define CSI2_CTX_CTRL2_FRAME_MASK			(0xffff << 16)

@@ -244,14 +244,14 @@
 		(0x3fff << CSI2_CTX_CTRL3_ALPHA_SHIFT)
 
 /* Shared bits across CSI2_CTX_IRQENABLE and IRQSTATUS */
-#define CSI2_CTX_IRQ_ECC_CORRECTION			(1 << 8)
-#define CSI2_CTX_IRQ_LINE_NUMBER			(1 << 7)
-#define CSI2_CTX_IRQ_FRAME_NUMBER			(1 << 6)
-#define CSI2_CTX_IRQ_CS					(1 << 5)
-#define CSI2_CTX_IRQ_LE					(1 << 3)
-#define CSI2_CTX_IRQ_LS					(1 << 2)
-#define CSI2_CTX_IRQ_FE					(1 << 1)
-#define CSI2_CTX_IRQ_FS					(1 << 0)
+#define CSI2_CTX_IRQ_ECC_CORRECTION			BIT(8)
+#define CSI2_CTX_IRQ_LINE_NUMBER			BIT(7)
+#define CSI2_CTX_IRQ_FRAME_NUMBER			BIT(6)
+#define CSI2_CTX_IRQ_CS					BIT(5)
+#define CSI2_CTX_IRQ_LE					BIT(3)
+#define CSI2_CTX_IRQ_LS					BIT(2)
+#define CSI2_CTX_IRQ_FE					BIT(1)
+#define CSI2_CTX_IRQ_FS					BIT(0)
 
 /* ISS BTE */
 #define BTE_CTRL					(0x0030)

@@ -272,49 +272,49 @@
 #define ISP5_IRQENABLE_CLR(i)				(0x0030 + (0x10 * (i)))
 
 /* Bits shared for ISP5_IRQ* registers */
-#define ISP5_IRQ_OCP_ERR				(1 << 31)
-#define ISP5_IRQ_IPIPE_INT_DPC_RNEW1			(1 << 29)
-#define ISP5_IRQ_IPIPE_INT_DPC_RNEW0			(1 << 28)
-#define ISP5_IRQ_IPIPE_INT_DPC_INIT			(1 << 27)
-#define ISP5_IRQ_IPIPE_INT_EOF				(1 << 25)
-#define ISP5_IRQ_H3A_INT_EOF				(1 << 24)
-#define ISP5_IRQ_RSZ_INT_EOF1				(1 << 23)
-#define ISP5_IRQ_RSZ_INT_EOF0				(1 << 22)
-#define ISP5_IRQ_RSZ_FIFO_IN_BLK_ERR			(1 << 19)
-#define ISP5_IRQ_RSZ_FIFO_OVF				(1 << 18)
-#define ISP5_IRQ_RSZ_INT_CYC_RSZB			(1 << 17)
-#define ISP5_IRQ_RSZ_INT_CYC_RSZA			(1 << 16)
-#define ISP5_IRQ_RSZ_INT_DMA				(1 << 15)
-#define ISP5_IRQ_RSZ_INT_LAST_PIX			(1 << 14)
-#define ISP5_IRQ_RSZ_INT_REG				(1 << 13)
-#define ISP5_IRQ_H3A_INT				(1 << 12)
-#define ISP5_IRQ_AF_INT					(1 << 11)
-#define ISP5_IRQ_AEW_INT				(1 << 10)
-#define ISP5_IRQ_IPIPEIF_IRQ				(1 << 9)
-#define ISP5_IRQ_IPIPE_INT_HST				(1 << 8)
-#define ISP5_IRQ_IPIPE_INT_BSC				(1 << 7)
-#define ISP5_IRQ_IPIPE_INT_DMA				(1 << 6)
-#define ISP5_IRQ_IPIPE_INT_LAST_PIX			(1 << 5)
-#define ISP5_IRQ_IPIPE_INT_REG				(1 << 4)
-#define ISP5_IRQ_ISIF_INT(i)				(1 << (i))
+#define ISP5_IRQ_OCP_ERR				BIT(31)
+#define ISP5_IRQ_IPIPE_INT_DPC_RNEW1			BIT(29)
+#define ISP5_IRQ_IPIPE_INT_DPC_RNEW0			BIT(28)
+#define ISP5_IRQ_IPIPE_INT_DPC_INIT			BIT(27)
+#define ISP5_IRQ_IPIPE_INT_EOF				BIT(25)
+#define ISP5_IRQ_H3A_INT_EOF				BIT(24)
+#define ISP5_IRQ_RSZ_INT_EOF1				BIT(23)
+#define ISP5_IRQ_RSZ_INT_EOF0				BIT(22)
+#define ISP5_IRQ_RSZ_FIFO_IN_BLK_ERR			BIT(19)
+#define ISP5_IRQ_RSZ_FIFO_OVF				BIT(18)
+#define ISP5_IRQ_RSZ_INT_CYC_RSZB			BIT(17)
+#define ISP5_IRQ_RSZ_INT_CYC_RSZA			BIT(16)
+#define ISP5_IRQ_RSZ_INT_DMA				BIT(15)
+#define ISP5_IRQ_RSZ_INT_LAST_PIX			BIT(14)
+#define ISP5_IRQ_RSZ_INT_REG				BIT(13)
+#define ISP5_IRQ_H3A_INT				BIT(12)
+#define ISP5_IRQ_AF_INT					BIT(11)
+#define ISP5_IRQ_AEW_INT				BIT(10)
+#define ISP5_IRQ_IPIPEIF_IRQ				BIT(9)
+#define ISP5_IRQ_IPIPE_INT_HST				BIT(8)
+#define ISP5_IRQ_IPIPE_INT_BSC				BIT(7)
+#define ISP5_IRQ_IPIPE_INT_DMA				BIT(6)
+#define ISP5_IRQ_IPIPE_INT_LAST_PIX			BIT(5)
+#define ISP5_IRQ_IPIPE_INT_REG				BIT(4)
+#define ISP5_IRQ_ISIF_INT(i)				BIT(i)
 
 #define ISP5_CTRL					(0x006c)
-#define ISP5_CTRL_MSTANDBY				(1 << 24)
-#define ISP5_CTRL_VD_PULSE_EXT				(1 << 23)
-#define ISP5_CTRL_MSTANDBY_WAIT				(1 << 20)
-#define ISP5_CTRL_BL_CLK_ENABLE				(1 << 15)
-#define ISP5_CTRL_ISIF_CLK_ENABLE			(1 << 14)
-#define ISP5_CTRL_H3A_CLK_ENABLE			(1 << 13)
-#define ISP5_CTRL_RSZ_CLK_ENABLE			(1 << 12)
-#define ISP5_CTRL_IPIPE_CLK_ENABLE			(1 << 11)
-#define ISP5_CTRL_IPIPEIF_CLK_ENABLE			(1 << 10)
-#define ISP5_CTRL_SYNC_ENABLE				(1 << 9)
-#define ISP5_CTRL_PSYNC_CLK_SEL				(1 << 8)
+#define ISP5_CTRL_MSTANDBY				BIT(24)
+#define ISP5_CTRL_VD_PULSE_EXT				BIT(23)
+#define ISP5_CTRL_MSTANDBY_WAIT				BIT(20)
+#define ISP5_CTRL_BL_CLK_ENABLE				BIT(15)
+#define ISP5_CTRL_ISIF_CLK_ENABLE			BIT(14)
+#define ISP5_CTRL_H3A_CLK_ENABLE			BIT(13)
+#define ISP5_CTRL_RSZ_CLK_ENABLE			BIT(12)
+#define ISP5_CTRL_IPIPE_CLK_ENABLE			BIT(11)
+#define ISP5_CTRL_IPIPEIF_CLK_ENABLE			BIT(10)
+#define ISP5_CTRL_SYNC_ENABLE				BIT(9)
+#define ISP5_CTRL_PSYNC_CLK_SEL				BIT(8)
 
 /* ISS ISP ISIF register offsets */
 #define ISIF_SYNCEN					(0x0000)
-#define ISIF_SYNCEN_DWEN				(1 << 1)
-#define ISIF_SYNCEN_SYEN				(1 << 0)
+#define ISIF_SYNCEN_DWEN				BIT(1)
+#define ISIF_SYNCEN_SYEN				BIT(0)
 
 #define ISIF_MODESET					(0x0004)
 #define ISIF_MODESET_INPMOD_MASK			(3 << 12)

@@ -338,7 +338,7 @@
 #define ISIF_LNV_MASK					(0x7fff)
 
 #define ISIF_HSIZE					(0x0034)
-#define ISIF_HSIZE_ADCR					(1 << 12)
+#define ISIF_HSIZE_ADCR					BIT(12)
 #define ISIF_HSIZE_HSIZE_MASK				(0xfff)
 
 #define ISIF_CADU					(0x003c)

@@ -373,7 +373,7 @@
 #define ISIF_CGAMMAWD_GWDI(bpp)				((16 - (bpp)) << 1)
 
 #define ISIF_CCDCFG					(0x0088)
-#define ISIF_CCDCFG_Y8POS				(1 << 11)
+#define ISIF_CCDCFG_Y8POS				BIT(11)
 
 /* ISS ISP IPIPEIF register offsets */
 #define IPIPEIF_ENABLE					(0x0000)

@@ -391,22 +391,22 @@
 #define IPIPEIF_CFG1_INPSRC2_SDRAM_YUV			(3 << 2)
 
 #define IPIPEIF_CFG2					(0x0030)
-#define IPIPEIF_CFG2_YUV8P				(1 << 7)
-#define IPIPEIF_CFG2_YUV8				(1 << 6)
-#define IPIPEIF_CFG2_YUV16				(1 << 3)
-#define IPIPEIF_CFG2_VDPOL				(1 << 2)
-#define IPIPEIF_CFG2_HDPOL				(1 << 1)
-#define IPIPEIF_CFG2_INTSW				(1 << 0)
+#define IPIPEIF_CFG2_YUV8P				BIT(7)
+#define IPIPEIF_CFG2_YUV8				BIT(6)
+#define IPIPEIF_CFG2_YUV16				BIT(3)
+#define IPIPEIF_CFG2_VDPOL				BIT(2)
+#define IPIPEIF_CFG2_HDPOL				BIT(1)
+#define IPIPEIF_CFG2_INTSW				BIT(0)
 
 #define IPIPEIF_CLKDIV					(0x0040)
 
 /* ISS ISP IPIPE register offsets */
 #define IPIPE_SRC_EN					(0x0000)
-#define IPIPE_SRC_EN_EN					(1 << 0)
+#define IPIPE_SRC_EN_EN					BIT(0)
 
 #define IPIPE_SRC_MODE					(0x0004)
-#define IPIPE_SRC_MODE_WRT				(1 << 1)
-#define IPIPE_SRC_MODE_OST				(1 << 0)
+#define IPIPE_SRC_MODE_WRT				BIT(1)
+#define IPIPE_SRC_MODE_OST				BIT(0)
 
 #define IPIPE_SRC_FMT					(0x0008)
 #define IPIPE_SRC_FMT_RAW2YUV				(0 << 0)

@@ -449,13 +449,13 @@
 #define IPIPE_SRC_STA					(0x0024)
 
 #define IPIPE_GCK_MMR					(0x0028)
-#define IPIPE_GCK_MMR_REG				(1 << 0)
+#define IPIPE_GCK_MMR_REG				BIT(0)
 
 #define IPIPE_GCK_PIX					(0x002c)
-#define IPIPE_GCK_PIX_G3				(1 << 3)
-#define IPIPE_GCK_PIX_G2				(1 << 2)
-#define IPIPE_GCK_PIX_G1				(1 << 1)
-#define IPIPE_GCK_PIX_G0				(1 << 0)
+#define IPIPE_GCK_PIX_G3				BIT(3)
+#define IPIPE_GCK_PIX_G2				BIT(2)
+#define IPIPE_GCK_PIX_G1				BIT(1)
+#define IPIPE_GCK_PIX_G0				BIT(0)
 
 #define IPIPE_DPC_LUT_EN				(0x0034)
 #define IPIPE_DPC_LUT_SEL				(0x0038)

@@ -633,8 +633,8 @@
 #define IPIPE_YUV_OFT_CR				(0x02c4)
 
 #define IPIPE_YUV_PHS					(0x02c8)
-#define IPIPE_YUV_PHS_LPF				(1 << 1)
-#define IPIPE_YUV_PHS_POS				(1 << 0)
+#define IPIPE_YUV_PHS_LPF				BIT(1)
+#define IPIPE_YUV_PHS_POS				BIT(0)
 
 #define IPIPE_YEE_EN					(0x02d4)
 #define IPIPE_YEE_TYP					(0x02d8)

@@ -739,8 +739,8 @@
 /* ISS ISP Resizer register offsets */
 #define RSZ_REVISION					(0x0000)
 #define RSZ_SYSCONFIG					(0x0004)
-#define RSZ_SYSCONFIG_RSZB_CLK_EN			(1 << 9)
-#define RSZ_SYSCONFIG_RSZA_CLK_EN			(1 << 8)
+#define RSZ_SYSCONFIG_RSZB_CLK_EN			BIT(9)
+#define RSZ_SYSCONFIG_RSZA_CLK_EN			BIT(8)
 
 #define RSZ_IN_FIFO_CTRL				(0x000c)
 #define RSZ_IN_FIFO_CTRL_THRLD_LOW_MASK			(0x1ff << 16)

@@ -752,18 +752,18 @@
 #define RSZ_FRACDIV_MASK				(0xffff)
 
 #define RSZ_SRC_EN					(0x0020)
-#define RSZ_SRC_EN_SRC_EN				(1 << 0)
+#define RSZ_SRC_EN_SRC_EN				BIT(0)
 
 #define RSZ_SRC_MODE					(0x0024)
-#define RSZ_SRC_MODE_OST				(1 << 0)
-#define RSZ_SRC_MODE_WRT				(1 << 1)
+#define RSZ_SRC_MODE_OST				BIT(0)
+#define RSZ_SRC_MODE_WRT				BIT(1)
 
 #define RSZ_SRC_FMT0					(0x0028)
-#define RSZ_SRC_FMT0_BYPASS				(1 << 1)
-#define RSZ_SRC_FMT0_SEL				(1 << 0)
+#define RSZ_SRC_FMT0_BYPASS				BIT(1)
+#define RSZ_SRC_FMT0_SEL				BIT(0)
 
 #define RSZ_SRC_FMT1					(0x002c)
-#define RSZ_SRC_FMT1_IN420				(1 << 1)
+#define RSZ_SRC_FMT1_IN420				BIT(1)
 
 #define RSZ_SRC_VPS					(0x0030)
 #define RSZ_SRC_VSZ					(0x0034)

@@ -773,10 +773,10 @@
 #define RSZ_DMA_RZB					(0x0044)
 #define RSZ_DMA_STA					(0x0048)
 #define RSZ_GCK_MMR					(0x004c)
-#define RSZ_GCK_MMR_MMR					(1 << 0)
+#define RSZ_GCK_MMR_MMR					BIT(0)
 
 #define RSZ_GCK_SDR					(0x0054)
-#define RSZ_GCK_SDR_CORE				(1 << 0)
+#define RSZ_GCK_SDR_CORE				BIT(0)
 
 #define RSZ_IRQ_RZA					(0x0058)
 #define RSZ_IRQ_RZA_MASK				(0x1fff)

@@ -790,12 +790,12 @@
 #define RSZ_YUV_C_MAX					(0x006c)
 
 #define RSZ_SEQ						(0x0074)
-#define RSZ_SEQ_HRVB					(1 << 2)
-#define RSZ_SEQ_HRVA					(1 << 0)
+#define RSZ_SEQ_HRVB					BIT(2)
+#define RSZ_SEQ_HRVA					BIT(0)
 
 #define RZA_EN						(0x0078)
 #define RZA_MODE					(0x007c)
-#define RZA_MODE_ONE_SHOT				(1 << 0)
+#define RZA_MODE_ONE_SHOT				BIT(0)
 
 #define RZA_420						(0x0080)
 #define RZA_I_VPS					(0x0084)

@@ -859,10 +859,10 @@
 #define RZB_SDR_C_PTR_E					(0x0194)
 
 /* Shared Bitmasks between RZA & RZB */
-#define RSZ_EN_EN					(1 << 0)
+#define RSZ_EN_EN					BIT(0)
 
-#define RSZ_420_CEN					(1 << 1)
-#define RSZ_420_YEN					(1 << 0)
+#define RSZ_420_CEN					BIT(1)
+#define RSZ_420_YEN					BIT(0)
 
 #define RSZ_I_VPS_MASK					(0x1fff)

@@ -878,8 +878,8 @@
 
 #define RSZ_V_DIF_MASK					(0x3fff)
 
-#define RSZ_V_TYP_C					(1 << 1)
-#define RSZ_V_TYP_Y					(1 << 0)
+#define RSZ_V_TYP_C					BIT(1)
+#define RSZ_V_TYP_Y					BIT(0)
 
 #define RSZ_V_LPF_C_MASK				(0x3f << 6)
 #define RSZ_V_LPF_C_SHIFT				6

@@ -890,14 +890,14 @@
 
 #define RSZ_H_DIF_MASK					(0x3fff)
 
-#define RSZ_H_TYP_C					(1 << 1)
-#define RSZ_H_TYP_Y					(1 << 0)
+#define RSZ_H_TYP_C					BIT(1)
+#define RSZ_H_TYP_Y					BIT(0)
 
 #define RSZ_H_LPF_C_MASK				(0x3f << 6)
 #define RSZ_H_LPF_C_SHIFT				6
 #define RSZ_H_LPF_Y_MASK				(0x3f << 0)
 #define RSZ_H_LPF_Y_SHIFT				0
 
-#define RSZ_DWN_EN_DWN_EN				(1 << 0)
+#define RSZ_DWN_EN_DWN_EN				BIT(0)
 
 #endif /* _OMAP4_ISS_REGS_H_ */

drivers/staging/media/omap4iss/iss_resizer.h +1 -2

index 3727498..d2a4968 100644
@@ -22,7 +22,7 @@ enum resizer_input_entity {
 	RESIZER_INPUT_IPIPEIF
 };
 
-#define RESIZER_OUTPUT_MEMORY		(1 << 0)
+#define RESIZER_OUTPUT_MEMORY			BIT(0)
 
 /* Sink and source RESIZER pads */
 #define RESIZER_PAD_SINK			0
--

1.7.9.5

Signature · 1 line

Amarjargal Gundjalam <[email protected]>

Sudip Mukherjee

2015-10-27 08:01 UTC #6 lore raw

Re: [Outreachy kernel] [PATCH 3/6] staging: media: omap4iss: Replaces bit shift on 1 with BIT Macro

Quoted 39 lines · Amarjargal Gundjalam

Quoted 8 lines · On Mon, 26 Oct 2015 15:46:27 +0100 (CET) Julia Lawall <[email protected]>…
Quoted 8 lines
drivers/staging/media/omap4iss/iss_ipipe.h +0 -0
index c22d904..b8c1b8e0 100644
@@ -21,7 +21,7 @@ enum ipipe_input_entity {
 	IPIPE_INPUT_IPIPEIF,
 };
 
Quoted 4 lines
drivers/staging/media/omap4iss/iss_ipipe.h enum ipipe_input_entity { · line 24
Quoted 2 lines
drivers/staging/media/omap4iss/iss_ipipe.h +1 -1
-#define IPIPE_OUTPUT_VP		(1 << 0)
+#define IPIPE_OUTPUT_VP				BIT(0)
Why did the amount of space change?
I tried to align it with the the others below it.
Quoted 12 lines
Quoted 12 lines
drivers/staging/media/omap4iss/iss_ipipe.h +0 -0
 /* Sink and source IPIPE pads */
 #define IPIPE_PAD_SINK				0
drivers/staging/media/omap4iss/iss_ipipeif.h +0 -0
index cbdccb9..cf8a47a 100644
@@ -22,8 +22,8 @@ enum ipipeif_input_entity {
 	IPIPEIF_INPUT_CSI2B
 };
 
Quoted 8 lines
drivers/staging/media/omap4iss/iss_ipipeif.h enum ipipeif_input_entity { · line 26
Quoted 4 lines
drivers/staging/media/omap4iss/iss_ipipeif.h +2 -2
-#define IPIPEIF_OUTPUT_MEMORY		(1 << 0)
-#define IPIPEIF_OUTPUT_VP		(1 << 1)
+#define IPIPEIF_OUTPUT_MEMORY			BIT(0)
+#define IPIPEIF_OUTPUT_VP			BIT(1)
Here, however, you could take advantage of the opportunity to line them up. Maybe these are just a problem with tabs and the patch?

Quoted 1 line

I did aligned them with tabs, maybe it's just a problem with patch formatting?

They looks aligned after applying.

regards
sudip

Amarjargal Gundjalam

author

2015-10-26 13:09 UTC #7 lore raw

PATCH 4/6 staging: media: omap4iss: Removes unnecessary blank lines

In reply to Amarjargal Gundjalam

This patch fixes checkpatch issues:

CHECK: Blank lines aren't necessary before a close brace '}'
CHECK: Please don't use multiple blank lines

Signed-off-by Amarjargal Gundjalam <[email protected]>

---
 drivers/staging/media/omap4iss/iss_resizer.c |    2 --
 drivers/staging/media/omap4iss/iss_video.c   |    1 -
 2 files changed, 3 deletions(-)

drivers/staging/media/omap4iss/iss_resizer.c +0 -2

index 48bed44..bdcab8c 100644
@@ -482,7 +482,6 @@ resizer_try_format(struct iss_resizer_device *resizer,
 		fmt->width &= ~15;
 		fmt->height = clamp_t(u32, height, 32, fmt->height);
 		break;
-
 	}
 
 	fmt->colorspace = V4L2_COLORSPACE_JPEG;

@@ -734,7 +733,6 @@ static int resizer_link_setup(struct media_entity *entity,
 		else if (remote->entity == &iss->ipipe.subdev.entity)
 			resizer->input = RESIZER_INPUT_IPIPE;
 
-
 		break;
 
 	case RESIZER_PAD_SOURCE_MEM | MEDIA_ENT_T_DEVNODE:

drivers/staging/media/omap4iss/iss_video.c +0 -1

index a98991a..97d3faa 100644
@@ -25,7 +25,6 @@
 #include "iss_video.h"
 #include "iss.h"
 
-
 /* -----------------------------------------------------------------------------
  * Helper functions
  */

Signature · 1 line

1.7.9.5

Amarjargal Gundjalam

author

2015-10-26 13:09 UTC #8 lore raw

PATCH 5/6 staging: media: omap4iss: Matches alignment with open parenthesis

In reply to Amarjargal Gundjalam

This patch fixes some of the checkpatch issue:

CHECK: Alignment should match open parenthesis

Signed-off-by Amarjargal Gundjalam <[email protected]>

---
 drivers/staging/media/omap4iss/iss.c         |    8 ++++----
 drivers/staging/media/omap4iss/iss_ipipe.c   |   22 +++++++++++-----------
 drivers/staging/media/omap4iss/iss_ipipe.h   |    2 +-
 drivers/staging/media/omap4iss/iss_ipipeif.c |   16 ++++++++--------
 drivers/staging/media/omap4iss/iss_ipipeif.h |    4 ++--
 drivers/staging/media/omap4iss/iss_resizer.c |   16 ++++++++--------
 drivers/staging/media/omap4iss/iss_resizer.h |    4 ++--
 7 files changed, 36 insertions(+), 36 deletions(-)

drivers/staging/media/omap4iss/iss.c +4 -4

index 104fc58..c143001 100644
@@ -541,7 +541,7 @@ static int iss_pipeline_link_notify(struct media_link *link, u32 flags,
 	}
 
 	if (notification == MEDIA_DEV_NOTIFY_POST_LINK_CH &&
-		(flags & MEDIA_LNK_FL_ENABLED)) {
+	    (flags & MEDIA_LNK_FL_ENABLED)) {
 		ret = iss_pipeline_pm_power(source, sink_use);
 		if (ret < 0)
 			return ret;

@@ -919,7 +919,7 @@ static int __iss_subclk_update(struct iss_device *iss)
 }
 
 int omap4iss_subclk_enable(struct iss_device *iss,
-			    enum iss_subclk_resource res)
+			   enum iss_subclk_resource res)
 {
 	iss->subclk_resources |= res;

@@ -927,7 +927,7 @@ int omap4iss_subclk_enable(struct iss_device *iss,
 }
 
 int omap4iss_subclk_disable(struct iss_device *iss,
-			     enum iss_subclk_resource res)
+			    enum iss_subclk_resource res)
 {
 	iss->subclk_resources &= ~res;

@@ -1137,7 +1137,7 @@ static void iss_unregister_entities(struct iss_device *iss)
  */
 static struct v4l2_subdev *
 iss_register_subdev_group(struct iss_device *iss,
-		     struct iss_subdev_i2c_board_info *board_info)
+			  struct iss_subdev_i2c_board_info *board_info)
 {
 	struct v4l2_subdev *sensor = NULL;
 	unsigned int first;

drivers/staging/media/omap4iss/iss_ipipe.c +11 ~~-11~~

index fcde8a6..dd0abef 100644
@@ -247,8 +247,8 @@ ipipe_try_format(struct iss_ipipe_device *ipipe,
  * return -EINVAL or zero on success
  */
 static int ipipe_enum_mbus_code(struct v4l2_subdev *sd,
-			       struct v4l2_subdev_pad_config *cfg,
-			       struct v4l2_subdev_mbus_code_enum *code)
+				struct v4l2_subdev_pad_config *cfg,
+				struct v4l2_subdev_mbus_code_enum *code)
 {
 	switch (code->pad) {
 	case IPIPE_PAD_SINK:

@@ -274,8 +274,8 @@ static int ipipe_enum_mbus_code(struct v4l2_subdev *sd,
 }
 
 static int ipipe_enum_frame_size(struct v4l2_subdev *sd,
-				struct v4l2_subdev_pad_config *cfg,
-				struct v4l2_subdev_frame_size_enum *fse)
+				 struct v4l2_subdev_pad_config *cfg,
+				 struct v4l2_subdev_frame_size_enum *fse)
 {
 	struct iss_ipipe_device *ipipe = v4l2_get_subdevdata(sd);
 	struct v4l2_mbus_framefmt format;

@@ -353,18 +353,18 @@ static int ipipe_set_format(struct v4l2_subdev *sd,
 	/* Propagate the format from sink to source */
 	if (fmt->pad == IPIPE_PAD_SINK) {
 		format = __ipipe_get_format(ipipe, cfg, IPIPE_PAD_SOURCE_VP,
-					   fmt->which);
+					    fmt->which);
 		*format = fmt->format;
 		ipipe_try_format(ipipe, cfg, IPIPE_PAD_SOURCE_VP, format,
-				fmt->which);
+				 fmt->which);
 	}
 
 	return 0;
 }
 
 static int ipipe_link_validate(struct v4l2_subdev *sd, struct media_link *link,
-				 struct v4l2_subdev_format *source_fmt,
-				 struct v4l2_subdev_format *sink_fmt)
+			       struct v4l2_subdev_format *source_fmt,
+			       struct v4l2_subdev_format *sink_fmt)
 {
 	/* Check if the two ends match */
 	if (source_fmt->format.width != sink_fmt->format.width ||

@@ -440,8 +440,8 @@ static const struct v4l2_subdev_internal_ops ipipe_v4l2_internal_ops = {
  * return -EINVAL or zero on success
  */
 static int ipipe_link_setup(struct media_entity *entity,
-			   const struct media_pad *local,
-			   const struct media_pad *remote, u32 flags)
+			    const struct media_pad *local,
+			    const struct media_pad *remote, u32 flags)
 {
 	struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
 	struct iss_ipipe_device *ipipe = v4l2_get_subdevdata(sd);

@@ -528,7 +528,7 @@ void omap4iss_ipipe_unregister_entities(struct iss_ipipe_device *ipipe)
 }
 
 int omap4iss_ipipe_register_entities(struct iss_ipipe_device *ipipe,
-	struct v4l2_device *vdev)
+				     struct v4l2_device *vdev)
 {
 	int ret;

drivers/staging/media/omap4iss/iss_ipipe.h +1 -1

index b8c1b8e0..d5b441d 100644
@@ -58,7 +58,7 @@ struct iss_ipipe_device {
 struct iss_device;
 
 int omap4iss_ipipe_register_entities(struct iss_ipipe_device *ipipe,
-	struct v4l2_device *vdev);
+				     struct v4l2_device *vdev);
 void omap4iss_ipipe_unregister_entities(struct iss_ipipe_device *ipipe);
 
 int omap4iss_ipipe_init(struct iss_device *iss);

drivers/staging/media/omap4iss/iss_ipipeif.c +8 -8

index 7c78ea1..5f9e449 100644
@@ -446,8 +446,8 @@ ipipeif_try_format(struct iss_ipipeif_device *ipipeif,
  * return -EINVAL or zero on success
  */
 static int ipipeif_enum_mbus_code(struct v4l2_subdev *sd,
-			       struct v4l2_subdev_pad_config *cfg,
-			       struct v4l2_subdev_mbus_code_enum *code)
+				  struct v4l2_subdev_pad_config *cfg,
+				  struct v4l2_subdev_mbus_code_enum *code)
 {
 	struct iss_ipipeif_device *ipipeif = v4l2_get_subdevdata(sd);
 	struct v4l2_mbus_framefmt *format;

@@ -480,8 +480,8 @@ static int ipipeif_enum_mbus_code(struct v4l2_subdev *sd,
 }
 
 static int ipipeif_enum_frame_size(struct v4l2_subdev *sd,
-				struct v4l2_subdev_pad_config *cfg,
-				struct v4l2_subdev_frame_size_enum *fse)
+				   struct v4l2_subdev_pad_config *cfg,
+				   struct v4l2_subdev_frame_size_enum *fse)
 {
 	struct iss_ipipeif_device *ipipeif = v4l2_get_subdevdata(sd);
 	struct v4l2_mbus_framefmt format;

@@ -570,7 +570,7 @@ static int ipipeif_set_format(struct v4l2_subdev *sd,
 					      fmt->which);
 		*format = fmt->format;
 		ipipeif_try_format(ipipeif, cfg, IPIPEIF_PAD_SOURCE_VP, format,
-				fmt->which);
+				   fmt->which);
 	}
 
 	return 0;

@@ -656,8 +656,8 @@ static const struct v4l2_subdev_internal_ops ipipeif_v4l2_internal_ops = {
  * return -EINVAL or zero on success
  */
 static int ipipeif_link_setup(struct media_entity *entity,
-			   const struct media_pad *local,
-			   const struct media_pad *remote, u32 flags)
+			      const struct media_pad *local,
+			      const struct media_pad *remote, u32 flags)
 {
 	struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
 	struct iss_ipipeif_device *ipipeif = v4l2_get_subdevdata(sd);

@@ -778,7 +778,7 @@ void omap4iss_ipipeif_unregister_entities(struct iss_ipipeif_device *ipipeif)
 }
 
 int omap4iss_ipipeif_register_entities(struct iss_ipipeif_device *ipipeif,
-	struct v4l2_device *vdev)
+				       struct v4l2_device *vdev)
 {
 	int ret;

drivers/staging/media/omap4iss/iss_ipipeif.h +2 -2

index cf8a47a..c6bd96d 100644
@@ -80,13 +80,13 @@ struct iss_device;
 int omap4iss_ipipeif_init(struct iss_device *iss);
 void omap4iss_ipipeif_cleanup(struct iss_device *iss);
 int omap4iss_ipipeif_register_entities(struct iss_ipipeif_device *ipipeif,
-	struct v4l2_device *vdev);
+				       struct v4l2_device *vdev);
 void omap4iss_ipipeif_unregister_entities(struct iss_ipipeif_device *ipipeif);
 
 int omap4iss_ipipeif_busy(struct iss_ipipeif_device *ipipeif);
 void omap4iss_ipipeif_isr(struct iss_ipipeif_device *ipipeif, u32 events);
 void omap4iss_ipipeif_restore_context(struct iss_device *iss);
 void omap4iss_ipipeif_max_rate(struct iss_ipipeif_device *ipipeif,
-	unsigned int *max_rate);
+			       unsigned int *max_rate);
 
 #endif	/* OMAP4_ISS_IPIPEIF_H */

drivers/staging/media/omap4iss/iss_resizer.c +8 -8

index bdcab8c..9c8180b 100644
@@ -496,8 +496,8 @@ resizer_try_format(struct iss_resizer_device *resizer,
  * return -EINVAL or zero on success
  */
 static int resizer_enum_mbus_code(struct v4l2_subdev *sd,
-			       struct v4l2_subdev_pad_config *cfg,
-			       struct v4l2_subdev_mbus_code_enum *code)
+				  struct v4l2_subdev_pad_config *cfg,
+				  struct v4l2_subdev_mbus_code_enum *code)
 {
 	struct iss_resizer_device *resizer = v4l2_get_subdevdata(sd);
 	struct v4l2_mbus_framefmt *format;

@@ -541,8 +541,8 @@ static int resizer_enum_mbus_code(struct v4l2_subdev *sd,
 }
 
 static int resizer_enum_frame_size(struct v4l2_subdev *sd,
-				struct v4l2_subdev_pad_config *cfg,
-				struct v4l2_subdev_frame_size_enum *fse)
+				   struct v4l2_subdev_pad_config *cfg,
+				   struct v4l2_subdev_frame_size_enum *fse)
 {
 	struct iss_resizer_device *resizer = v4l2_get_subdevdata(sd);
 	struct v4l2_mbus_framefmt format;

@@ -624,7 +624,7 @@ static int resizer_set_format(struct v4l2_subdev *sd,
 					      fmt->which);
 		*format = fmt->format;
 		resizer_try_format(resizer, cfg, RESIZER_PAD_SOURCE_MEM, format,
-				fmt->which);
+				   fmt->which);
 	}
 
 	return 0;

@@ -710,8 +710,8 @@ static const struct v4l2_subdev_internal_ops resizer_v4l2_internal_ops = {
  * return -EINVAL or zero on success
  */
 static int resizer_link_setup(struct media_entity *entity,
-			   const struct media_pad *local,
-			   const struct media_pad *remote, u32 flags)
+			      const struct media_pad *local,
+			      const struct media_pad *remote, u32 flags)
 {
 	struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
 	struct iss_resizer_device *resizer = v4l2_get_subdevdata(sd);

@@ -820,7 +820,7 @@ void omap4iss_resizer_unregister_entities(struct iss_resizer_device *resizer)
 }
 
 int omap4iss_resizer_register_entities(struct iss_resizer_device *resizer,
-	struct v4l2_device *vdev)
+				       struct v4l2_device *vdev)
 {
 	int ret;

drivers/staging/media/omap4iss/iss_resizer.h +2 -2

index d2a4968..1e145ab 100644
@@ -63,13 +63,13 @@ struct iss_device;
 int omap4iss_resizer_init(struct iss_device *iss);
 void omap4iss_resizer_cleanup(struct iss_device *iss);
 int omap4iss_resizer_register_entities(struct iss_resizer_device *resizer,
-	struct v4l2_device *vdev);
+				       struct v4l2_device *vdev);
 void omap4iss_resizer_unregister_entities(struct iss_resizer_device *resizer);
 
 int omap4iss_resizer_busy(struct iss_resizer_device *resizer);
 void omap4iss_resizer_isr(struct iss_resizer_device *resizer, u32 events);
 void omap4iss_resizer_restore_context(struct iss_device *iss);
 void omap4iss_resizer_max_rate(struct iss_resizer_device *resizer,
-	unsigned int *max_rate);
+			       unsigned int *max_rate);
 
 #endif	/* OMAP4_ISS_RESIZER_H */

Signature · 1 line

1.7.9.5

Amarjargal Gundjalam

author

2015-10-26 13:09 UTC #9 lore raw

PATCH 6/6 staging: media: omap4iss: Fixes line break

In reply to Amarjargal Gundjalam

This patch fixes the checkpatch issue:

CHECK: Logical continuations should be on the previous line

Signed-off-by Amarjargal Gundjalam <[email protected]>

---
 drivers/staging/media/omap4iss/iss.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

drivers/staging/media/omap4iss/iss.c +2 -2

index c143001..bd3662a 100644
@@ -469,8 +469,8 @@ static int iss_pipeline_pm_power(struct media_entity *entity, int change)
 
 	media_entity_graph_walk_start(&graph, first);
 
-	while ((first = media_entity_graph_walk_next(&graph))
-	       && first != entity)
+	while ((first = media_entity_graph_walk_next(&graph)) &&
+	       first != entity)
 		if (media_entity_type(first) != MEDIA_ENT_T_DEVNODE)
 			iss_pipeline_pm_power_one(first, -change);

Signature · 1 line

1.7.9.5