x86/mm: INVPCID support
Subsystems (3)
v3 cover x86/mm: INVPCID support
Boris, I think you already have these prerequisites queued up:
http://lkml.kernel.org/g/[email protected]
http://lkml.kernel.org/g/[email protected]
This is a straightforward speedup on Ivy Bridge and newer, IIRC. (I tested on Skylake. INVPCID is not available on Sandy Bridge. I don't have Ivy Bridge, Haswell or Broadwell to test on, so I could be wrong as to when the feature was introduced.)
I think we should consider these patches separately from the rest of the PCID stuff -- they barely interact, and this part is much simpler and is useful on its own.
Changes from v2:
- Add macros for the INVPCID mode numbers.
- Add a changelog message for the chicken bit.
v1 was exactly identical to patches 2-4 of the PCID RFC series. Andy Lutomirski (3):
x86/mm: Add INVPCID helpers
x86/mm: Add a noinvpcid option to turn off INVPCID x86/mm: If INVPCID is available, use it to flush global mappings
Documentation/kernel-parameters.txt | 2 ++ arch/x86/include/asm/tlbflush.h | 57 +++++++++++++++++++++++++++++++++++++ arch/x86/kernel/cpu/common.c | 16 +++++++++++ 3 files changed, 75 insertions(+)
Signature · 7 lines
2.5.0 -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to [email protected]. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: <a href=mailto:"[email protected]"> [email protected] </a>
PATCH v3 1/3 x86/mm: Add INVPCID helpers
This adds helpers for each of the four currently-specified INVPCID modes.
--- arch/x86/include/asm/tlbflush.h | 48 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+)
arch/x86/include/asm/tlbflush.h +48 -0
@@ -7,6 +7,54 @@#include <asm/processor.h> #include <asm/special_insns.h> +static inline void __invpcid (unsigned long pcid,unsigned long addr, +unsigned long type) +{ +u64 desc[2 ] = { pcid, addr }; + +/* +* The memory clobber is because the whole point is to invalidate +* stale TLB entries and, especially if we're flushing global +* mappings, we don't want the compiler to reorder any subsequent +* memory accesses before the TLB flush. +* +* The hex opcode is invpcid (%ecx), %eax in 32-bit mode and +* invpcid (%rcx), %rax in long mode. +*/ + asmvolatile (".byte 0x66, 0x0f, 0x38, 0x82, 0x01" + : :"m" (desc),"a" (type),"c" (desc) :"memory" ); +} + +#define INVPCID_TYPE_INDIV_ADDR 0 +#define INVPCID_TYPE_SINGLE_CTXT 1 +#define INVPCID_TYPE_ALL_INCL_GLOBAL 2 +#define INVPCID_TYPE_ALL_NON_GLOBAL 3 + +/* Flush all mappings for a given pcid and addr, not including globals. */ +static inline void invpcid_flush_one (unsigned long pcid, +unsigned long addr) +{ +__invpcid (pcid, addr,INVPCID_TYPE_INDIV_ADDR ); +} + +/* Flush all mappings for a given PCID, not including globals. */ +static inline void invpcid_flush_single_context (unsigned long pcid) +{ +__invpcid (pcid,0 ,INVPCID_TYPE_SINGLE_CTXT ); +} + +/* Flush all mappings, including globals, for all PCIDs. */ +static inline void invpcid_flush_all (void ) +{ +__invpcid (0 ,0 ,INVPCID_TYPE_ALL_INCL_GLOBAL ); +} + +/* Flush all mappings for all PCIDs except globals. */ +static inline void invpcid_flush_all_nonglobals (void ) +{ +__invpcid (0 ,0 ,INVPCID_TYPE_ALL_NON_GLOBAL ); +} +#ifdef CONFIG_PARAVIRT #include <asm/paravirt.h> #else
Signature · 7 lines
2.5.0 -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to [email protected]. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: <a href=mailto:"[email protected]"> [email protected] </a>
tip-bot for Andy Lutomirski
merge bot[tip:x86/mm] x86/mm: Add INVPCID helpers
x86/mm: Add INVPCID helpers
Commit-ID: 060a402a1ddb551455ee410de2eadd3349f2801b Gitweb: http://git.kernel.org/tip/060a402a1ddb551455ee410de2eadd3349f2801b Author: Andy Lutomirski <[email protected]> AuthorDate: Fri, 29 Jan 2016 11:42:57 -0800 Committer: Ingo Molnar <[email protected]> CommitDate: Tue, 9 Feb 2016 13:36:10 +0100
x86/mm: Add INVPCID helpers
This adds helpers for each of the four currently-specified INVPCID modes.
--- arch/x86/include/asm/tlbflush.h | 48 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+)
arch/x86/include/asm/tlbflush.h +48 -0
@@ -7,6 +7,54 @@#include <asm/processor.h> #include <asm/special_insns.h> +static inline void __invpcid (unsigned long pcid,unsigned long addr, +unsigned long type) +{ +u64 desc[2 ] = { pcid, addr }; + +/* +* The memory clobber is because the whole point is to invalidate +* stale TLB entries and, especially if we're flushing global +* mappings, we don't want the compiler to reorder any subsequent +* memory accesses before the TLB flush. +* +* The hex opcode is invpcid (%ecx), %eax in 32-bit mode and +* invpcid (%rcx), %rax in long mode. +*/ + asmvolatile (".byte 0x66, 0x0f, 0x38, 0x82, 0x01" + : :"m" (desc),"a" (type),"c" (desc) :"memory" ); +} + +#define INVPCID_TYPE_INDIV_ADDR 0 +#define INVPCID_TYPE_SINGLE_CTXT 1 +#define INVPCID_TYPE_ALL_INCL_GLOBAL 2 +#define INVPCID_TYPE_ALL_NON_GLOBAL 3 + +/* Flush all mappings for a given pcid and addr, not including globals. */ +static inline void invpcid_flush_one (unsigned long pcid, +unsigned long addr) +{ +__invpcid (pcid, addr,INVPCID_TYPE_INDIV_ADDR ); +} + +/* Flush all mappings for a given PCID, not including globals. */ +static inline void invpcid_flush_single_context (unsigned long pcid) +{ +__invpcid (pcid,0 ,INVPCID_TYPE_SINGLE_CTXT ); +} + +/* Flush all mappings, including globals, for all PCIDs. */ +static inline void invpcid_flush_all (void ) +{ +__invpcid (0 ,0 ,INVPCID_TYPE_ALL_INCL_GLOBAL ); +} + +/* Flush all mappings for all PCIDs except globals. */ +static inline void invpcid_flush_all_nonglobals (void ) +{ +__invpcid (0 ,0 ,INVPCID_TYPE_ALL_NON_GLOBAL ); +} +#ifdef CONFIG_PARAVIRT #include <asm/paravirt.h> #else
Borislav Petkov
maintainerRe: [tip:x86/mm] x86/mm: Add INVPCID helpers
Quoted 11 lines · tip-bot for Andy Lutomirski
Commit-ID: 060a402a1ddb551455ee410de2eadd3349f2801b Gitweb: http://git.kernel.org/tip/060a402a1ddb551455ee410de2eadd3349f2801b Author: Andy Lutomirski <[email protected]> AuthorDate: Fri, 29 Jan 2016 11:42:57 -0800 Committer: Ingo Molnar <[email protected]> CommitDate: Tue, 9 Feb 2016 13:36:10 +0100x86/mm: Add INVPCID helpers
This adds helpers for each of the four currently-specified INVPCID modes.
...
Quoted 6 lines
(quoted diff) +6
-0+static inline void __invpcid(unsigned long pcid, unsigned long addr, + unsigned long type) +{ + u64 desc[2] = { pcid, addr }; + + /*
Review
Quoted 10 lines
(quoted diff) +10
-0+ * The memory clobber is because the whole point is to invalidate + * stale TLB entries and, especially if we're flushing global + * mappings, we don't want the compiler to reorder any subsequent + * memory accesses before the TLB flush. + * + * The hex opcode is invpcid (%ecx), %eax in 32-bit mode and + * invpcid (%rcx), %rax in long mode. + */ + asm volatile (".byte 0x66, 0x0f, 0x38, 0x82, 0x01" + : : "m" (desc), "a" (type), "c" (desc) : "memory");
---
From: Borislav Petkov <[email protected]>
Date: Wed, 10 Feb 2016 12:53:48 +0100
Subject: [PATCH] x86/mm: Fix INVPCID asm constraint
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
So we want to specify the dependency on both @pcid and @addr so that the compiler doesn't reorder accesses to them *before* the TLB flush. But for that to work, we need to express this properly in the inline asm and deref the whole desc array, not the pointer to it. See clwb() for an example.
This fixes the build error on 32-bit:
arch/x86/include/asm/tlbflush.h: In function ‘__invpcid’:
arch/x86/include/asm/tlbflush.h:26:18: error: memory input 0 is not directly addressable
which gcc4.7 caught but 5.x didn't. Which is strange. :-\
--- arch/x86/include/asm/tlbflush.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
arch/x86/include/asm/tlbflush.h +1 -1
@@ -23,7 +23,7 @@ static inline void __invpcid(unsigned long pcid, unsigned long addr,* invpcid (%rcx), %rax in long mode. */ asmvolatile (".byte 0x66, 0x0f, 0x38, 0x82, 0x01" - : :"m" (desc),"a" (type),"c" (desc) :"memory" ); + : :"m" (*desc),"a" (type),"c" (desc) :"memory" ); }#define INVPCID_TYPE_INDIV_ADDR 0
Signature · 8 lines
2.3.5
--
Regards/Gruss,
Boris.
ECO tip #101: Trim your mails when you reply.Re: [tip:x86/mm] x86/mm: Add INVPCID helpers
Hi,
arch/x86/include/asm/tlbflush.h static inline void __invpcid(unsigned long pcid, unsigned long addr, · line 26
Quoted 8 lines · Borislav Petkov
arch/x86/include/asm/tlbflush.h +1
-1@@ -23,7 +23,7 @@ static inline void __invpcid(unsigned long pcid, unsigned long addr,* invpcid (%rcx), %rax in long mode. */ asmvolatile (".byte 0x66, 0x0f, 0x38, 0x82, 0x01" - : :"m" (desc),"a" (type),"c" (desc) :"memory" ); + : :"m" (*desc),"a" (type),"c" (desc) :"memory" );
That still doesn't do what you want. Arrays in C are funny. *desc is exactly equivalent to desc[0], _not_ to the whole array, indeed there's no C syntax to name an lvalue of array type in normal expressions. You need to jump through hoops for this:
"m" (*(struct {unsigned long x[2];} *)desc)
It'd probably be easier to simply declare the descriptor as a struct, rather than an array, then the original syntax would have been mostly correct:
struct {u64 d[2];} desc = { pcid, addr };
asm ... "m" (desc), "c" (&desc)Ciao,
Michael.
Borislav Petkov
maintainerPATCH 1/1 x86/mm: Fix INVPCID asm constraint
Quoted 4 lines · Michael Matz
Hi,
On Wed, 10 Feb 2016, Borislav Petkov wrote:
Quoted 11 lines
arch/x86/include/asm/tlbflush.h static inline void __invpcid(unsigned long pcid, unsigned long addr, · line 26
Quoted 8 lines
arch/x86/include/asm/tlbflush.h +1
-1@@ -23,7 +23,7 @@ static inline void __invpcid(unsigned long pcid, unsigned long addr,* invpcid (%rcx), %rax in long mode. */ asmvolatile (".byte 0x66, 0x0f, 0x38, 0x82, 0x01" - : :"m" (desc),"a" (type),"c" (desc) :"memory" ); + : :"m" (*desc),"a" (type),"c" (desc) :"memory" );That still doesn't do what you want. Arrays in C are funny. *desc is exactly equivalent to desc[0], _not_ to the whole array,
Doh!
Quoted 4 lines
indeed there's no C syntax to name an lvalue of array type in normal expressions. You need to jump through hoops for this:
"m" (*(struct {unsigned long x[2];} *)desc)
Aha! That's why we wrapped the array in clwb() in a struct too, btw:
static inline void clwb(volatile void *__p)
{
volatile struct { char x[64]; } *p = __p;
...Quoted 6 lines
It'd probably be easier to simply declare the descriptor as a struct, rather than an array, then the original syntax would have been mostly correct:
struct {u64 d[2];} desc = { pcid, addr }; asm ... "m" (desc), "c" (&desc)
Sounds better. Done. How does that below look like?
Thanks Micha!
---
From: Borislav Petkov <[email protected]>
Date: Wed, 10 Feb 2016 12:53:48 +0100
Subject: [PATCH -v1.1] x86/mm: Fix INVPCID asm constraint
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
So we want to specify the dependency on both @pcid and @addr so that the compiler doesn't reorder accesses to them *before* the TLB flush. But for that to work, we need to express this properly in the inline asm and deref the whole desc array, not the pointer to it. See clwb() for an example.
This fixes the build error on 32-bit:
arch/x86/include/asm/tlbflush.h: In function ‘__invpcid’:
arch/x86/include/asm/tlbflush.h:26:18: error: memory input 0 is not directly addressable
which gcc4.7 caught but 5.x didn't. Which is strange. :-\
--- arch/x86/include/asm/tlbflush.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
arch/x86/include/asm/tlbflush.h +2 -2
@@ -11,7 +11,7 @@static inline void __invpcid (unsigned long pcid,unsigned long addr,unsigned long type) { -u64 desc[2 ] = { pcid, addr }; +struct {u64 d[2 ]; } desc = { { pcid, addr } };/* * The memory clobber is because the whole point is to invalidate
@@ -23,7 +23,7 @@ static inline void __invpcid(unsigned long pcid, unsigned long addr,* invpcid (%rcx), %rax in long mode. */ asmvolatile (".byte 0x66, 0x0f, 0x38, 0x82, 0x01" - : :"m" (desc),"a" (type),"c" (desc) :"memory" ); + : :"m" (desc),"a" (type),"c" (&desc) :"memory" ); }#define INVPCID_TYPE_INDIV_ADDR 0
Signature · 7 lines
2.3.5
--
Regards/Gruss,
Boris.
ECO tip #101: Trim your mails when you reply.Re: [PATCH -v1.1] x86/mm: Fix INVPCID asm constraint
Quoted 56 lines · Borislav Petkov
Quoted 4 lines · Michael Matz
Hi,
On Wed, 10 Feb 2016, Borislav Petkov wrote:
Quoted 11 lines
arch/x86/include/asm/tlbflush.h static inline void __invpcid(unsigned long pcid, unsigned long addr, · line 26
Quoted 8 lines
arch/x86/include/asm/tlbflush.h +1
-1@@ -23,7 +23,7 @@ static inline void __invpcid(unsigned long pcid, unsigned long addr,* invpcid (%rcx), %rax in long mode. */ asmvolatile (".byte 0x66, 0x0f, 0x38, 0x82, 0x01" - : :"m" (desc),"a" (type),"c" (desc) :"memory" ); + : :"m" (*desc),"a" (type),"c" (desc) :"memory" );That still doesn't do what you want. Arrays in C are funny. *desc is exactly equivalent to desc[0], _not_ to the whole array,
Doh!
Quoted 4 lines
indeed there's no C syntax to name an lvalue of array type in normal expressions. You need to jump through hoops for this:
"m" (*(struct {unsigned long x[2];} *)desc)
Aha! That's why we wrapped the array in
clwb()in a struct too, btw:static inline void
clwb(volatile void *__p){ volatile struct { char x[64]; } *p = __p; ...Quoted 6 lines
It'd probably be easier to simply declare the descriptor as a struct, rather than an array, then the original syntax would have been mostly correct:
struct {u64 d[2];} desc = { pcid, addr }; asm ... "m" (desc), "c" (&desc)Sounds better. Done. How does that below look like?
Thanks Micha!
---
From: Borislav Petkov <[email protected]>
Date: Wed, 10 Feb 2016 12:53:48 +0100
Subject: [PATCH -v1.1] x86/mm: Fix INVPCID asm constraint
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bitSo we want to specify the dependency on both @pcid and @addr so that the compiler doesn't reorder accesses to them *before* the TLB flush. But for that to work, we need to express this properly in the inline asm and deref the whole desc array, not the pointer to it. See
clwb()for an example.
Quoted 5 lines
This fixes the build error on 32-bit:
arch/x86/include/asm/tlbflush.h: In function ‘__invpcid’:
arch/x86/include/asm/tlbflush.h:26:18: error: memory input 0 is not directly addressable
PATCH v3 2/3 x86/mm: Add a noinvpcid option to turn off INVPCID
In reply to Andy LutomirskiThis adds a chicken bit to turn off INVPCID in case something goes wrong. It's an early_param because we do TLB flushes before we parse __setup parameters.
--- Documentation/kernel-parameters.txt | 2 ++ arch/x86/kernel/cpu/common.c | 16 ++++++++++++++++ 2 files changed, 18 insertions(+)
Documentation/kernel-parameters.txt +2 -0
@@ -2508,6 +2508,8 @@ bytes respectively. Such letter suffixes can also be entirely omitted. nointroute [IA-64] + noinvpcid [X86] Disable the INVPCID cpu feature. + nojitter [IA-64] Disables jitter checking for ITC timers. no-kvmclock [X86,KVM] Disable paravirtualized KVM clock driver
arch/x86/kernel/cpu/common.c +16 -0
@@ -162,6 +162,22 @@ static int __init x86_mpx_setup(char *s) }__setup ("nompx" , x86_mpx_setup); +static int __init x86_noinvpcid_setup (char *s) +{ +/* noinvpcid doesn't accept parameters */ +if (s) +return -EINVAL ; + +/* do not emit a message if the feature is not present */ +if (!boot_cpu_has (X86_FEATURE_INVPCID )) +return 0 ; + +setup_clear_cpu_cap (X86_FEATURE_INVPCID ); +pr_info ("noinvpcid: INVPCID feature disabled\n" ); +return 0 ; +} +early_param ("noinvpcid" , x86_noinvpcid_setup); +#ifdef CONFIG_X86_32 static int cachesize_override =-1 ;static int disable_x86_serial_nr =1 ;
Signature · 7 lines
2.5.0 -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to [email protected]. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: <a href=mailto:"[email protected]"> [email protected] </a>
tip-bot for Andy Lutomirski
merge bot[tip:x86/mm] x86/mm: Add a 'noinvpcid' boot option to turn off INVPCID
x86/mm: Add a 'noinvpcid' boot option to turn off INVPCID
Commit-ID: d12a72b844a49d4162f24cefdab30bed3f86730e Gitweb: http://git.kernel.org/tip/d12a72b844a49d4162f24cefdab30bed3f86730e Author: Andy Lutomirski <[email protected]> AuthorDate: Fri, 29 Jan 2016 11:42:58 -0800 Committer: Ingo Molnar <[email protected]> CommitDate: Tue, 9 Feb 2016 13:36:10 +0100
x86/mm: Add a 'noinvpcid' boot option to turn off INVPCID
This adds a chicken bit to turn off INVPCID in case something goes wrong. It's an early_param() because we do TLB flushes before we parse __setup() parameters.
--- Documentation/kernel-parameters.txt | 2 ++ arch/x86/kernel/cpu/common.c | 16 ++++++++++++++++ 2 files changed, 18 insertions(+)
Documentation/kernel-parameters.txt +2 -0
@@ -2566,6 +2566,8 @@ bytes respectively. Such letter suffixes can also be entirely omitted. nointroute [IA-64] + noinvpcid [X86] Disable the INVPCID cpu feature. + nojitter [IA-64] Disables jitter checking for ITC timers. no-kvmclock [X86,KVM] Disable paravirtualized KVM clock driver
arch/x86/kernel/cpu/common.c +16 -0
@@ -162,6 +162,22 @@ static int __init x86_mpx_setup(char *s) }__setup ("nompx" , x86_mpx_setup); +static int __init x86_noinvpcid_setup (char *s) +{ +/* noinvpcid doesn't accept parameters */ +if (s) +return -EINVAL ; + +/* do not emit a message if the feature is not present */ +if (!boot_cpu_has (X86_FEATURE_INVPCID )) +return 0 ; + +setup_clear_cpu_cap (X86_FEATURE_INVPCID ); +pr_info ("noinvpcid: INVPCID feature disabled\n" ); +return 0 ; +} +early_param ("noinvpcid" , x86_noinvpcid_setup); +#ifdef CONFIG_X86_32 static int cachesize_override =-1 ;static int disable_x86_serial_nr =1 ;
PATCH v3 3/3 x86/mm: If INVPCID is available, use it to flush global mappings
In reply to Andy LutomirskiOn my Skylake laptop, INVPCID function 2 (flush absolutely everything) takes about 376ns, whereas saving flags, twiddling CR4.PGE to flush global mappings, and restoring flags takes about 539ns.
--- arch/x86/include/asm/tlbflush.h | 9 +++++++++ 1 file changed, 9 insertions(+)
arch/x86/include/asm/tlbflush.h +9 -0
@@ -152,6 +152,15 @@ static inline void __native_flush_tlb_global(void) {unsigned long flags; +if (static_cpu_has_safe (X86_FEATURE_INVPCID )) { +/* +* Using INVPCID is considerably faster than a pair of writes +* to CR4 sandwiched inside an IRQ flag save/restore. +*/ +invpcid_flush_all (); +return ; + } +/* * Read-modify-write to CR4 - protect it from preemption and * from interrupts. (Use the raw variant because this code can
Signature · 7 lines
2.5.0 -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to [email protected]. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: <a href=mailto:"[email protected]"> [email protected] </a>
tip-bot for Andy Lutomirski
merge bot[tip:x86/mm] x86/mm: If INVPCID is available, use it to flush global mappings
x86/mm: If INVPCID is available, use it to flush global mappings
Commit-ID: d8bced79af1db6734f66b42064cc773cada2ce99 Gitweb: http://git.kernel.org/tip/d8bced79af1db6734f66b42064cc773cada2ce99 Author: Andy Lutomirski <[email protected]> AuthorDate: Fri, 29 Jan 2016 11:42:59 -0800 Committer: Ingo Molnar <[email protected]> CommitDate: Tue, 9 Feb 2016 13:36:11 +0100
x86/mm: If INVPCID is available, use it to flush global mappings
On my Skylake laptop, INVPCID function 2 (flush absolutely everything) takes about 376ns, whereas saving flags, twiddling CR4.PGE to flush global mappings, and restoring flags takes about 539ns.
--- arch/x86/include/asm/tlbflush.h | 9 +++++++++ 1 file changed, 9 insertions(+)
arch/x86/include/asm/tlbflush.h +9 -0
@@ -152,6 +152,15 @@ static inline void __native_flush_tlb_global(void) {unsigned long flags; +if (static_cpu_has (X86_FEATURE_INVPCID )) { +/* +* Using INVPCID is considerably faster than a pair of writes +* to CR4 sandwiched inside an IRQ flag save/restore. +*/ +invpcid_flush_all (); +return ; + } +/* * Read-modify-write to CR4 - protect it from preemption and * from interrupts. (Use the raw variant because this code can
Quoted 24 lines · Andy Lutomirski
Boris, I think you already have these prerequisites queued up:
http://lkml.kernel.org/g/[email protected]
http://lkml.kernel.org/g/[email protected]This is a straightforward speedup on Ivy Bridge and newer, IIRC. (I tested on Skylake. INVPCID is not available on Sandy Bridge. I don't have Ivy Bridge, Haswell or Broadwell to test on, so I could be wrong as to when the feature was introduced.)
I think we should consider these patches separately from the rest of the PCID stuff -- they barely interact, and this part is much simpler and is useful on its own.
Changes from v2:
- Add macros for the INVPCID mode numbers.
- Add a changelog message for the chicken bit.v1 was exactly identical to patches 2-4 of the PCID RFC series. Andy Lutomirski (3):
x86/mm: Add INVPCID helpers
x86/mm: Add a noinvpcid option to turn off INVPCID x86/mm: If INVPCID is available, use it to flush global mappings
Quoted 4 lines
Documentation/kernel-parameters.txt | 2 ++ arch/x86/include/asm/tlbflush.h | 57 +++++++++++++++++++++++++++++++++++++ arch/x86/kernel/cpu/common.c | 16 +++++++++++ 3 files changed, 75 insertions(+)
All 5 (3 INVPCID + 2 KASAN ones at the URLs above):
Signature · 4 lines
Regards/Gruss,
Boris.
ECO tip #101: Trim your mails when you reply.