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arm: Add Artpec-6 SoC

PATCH Superseded Lars Persson 2 participants 15 messages Feb 10, 2016

Subsystems (6)
Device tree bindings Arm (32-bit) Arm sub-architectures Common clk +2 more subsystems

v1 of 3 Superseded Latest is v3 →

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Lars Persson

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#0 lore raw

cover arm: Add Artpec-6 SoC

Basic support for the Axis Artpec-6 ARM SoC. Timers, interrupts, UARTs and ethernet are wired up.

Lars Persson (8):
clk: add device tree binding for artpec-6 pll1 clock
clk: add artpec-6 pll1 clock driver
arm: add device-tree SoC bindings for Axis Artpec-6
arm: dts: add Artpec-6 soc dtsi file
arm: dts: add Artpec-6 development board dts
arm: initial machine port for artpec-6 SoC
arm: multi_v7_defconfig: add MACH_ARTPEC6
arm: mach-artpec: add entry to MAINTAINERS

 Documentation/devicetree/bindings/arm/axis.txt     |   8 +
 .../devicetree/bindings/clock/artpec6.txt          |  14 ++
 MAINTAINERS                                        |  10 +
 arch/arm/Kconfig                                   |   2 +
 arch/arm/Makefile                                  |   1 +
 arch/arm/boot/dts/Makefile                         |   2 +
 arch/arm/boot/dts/artpec6-devboard.dts             |  57 +++++
 arch/arm/boot/dts/artpec6.dtsi                     | 238 +++++++++++++++++++++
 arch/arm/configs/multi_v7_defconfig                |   2 +
 arch/arm/mach-artpec/Kconfig                       |  22 ++
 arch/arm/mach-artpec/Makefile                      |   1 +
 arch/arm/mach-artpec/board-artpec6.c               |  66 ++++++
 drivers/clk/Makefile                               |   1 +
 drivers/clk/clk-artpec6.c                          |  70 ++++++
 14 files changed, 494 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/axis.txt
 create mode 100644 Documentation/devicetree/bindings/clock/artpec6.txt
 create mode 100644 arch/arm/boot/dts/artpec6-devboard.dts
 create mode 100644 arch/arm/boot/dts/artpec6.dtsi
 create mode 100644 arch/arm/mach-artpec/Kconfig
 create mode 100644 arch/arm/mach-artpec/Makefile
 create mode 100644 arch/arm/mach-artpec/board-artpec6.c
 create mode 100644 drivers/clk/clk-artpec6.c
Signature · 1 line
2.1.4
author maintainer
#1 lore raw

PATCH 1/8 clk: add device tree binding for artpec-6 pll1 clock

Signed-off-by Lars Persson <[email protected]>
---
 Documentation/devicetree/bindings/clock/artpec6.txt | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/artpec6.txt
Documentation/devicetree/bindings/clock/artpec6.txt new file +14 -0
new file mode 100644
index 0000000..e50f7a5
@@ -0,0 +1,14 @@
+* Clock bindings for Axis ARTPEC-6 chip
+
+Required properties:
+- compatible: Should be "axis,artpec6-pll1-clock"
+- #clock-cells: Should be <1>
+
+Examples:
+
+pll1_clk: pll1_clk {
+	#clock-cells = <1>;
+	compatible = "axis,artpec6-pll1-clock";
+	clocks = <&ext_clk>;
+	status = "okay";
+};
Signature · 1 line
2.1.4
maintainer
#2 lore raw

Re: [PATCH 1/8] clk: add device tree binding for artpec-6 pll1 clock

Quoted 2 lines · On Wednesday 10 February 2016 13:41:50 Lars Persson wrote:
Signed-off-by Lars Persson <[email protected]>

---

Always write a changelog comment.

Documentation/devicetree/bindings/clock/artpec6.txt line 5

Quoted 5 lines
Documentation/devicetree/bindings/clock/artpec6.txt new file +5 -0
+* Clock bindings for Axis ARTPEC-6 chip
+
+Required properties:
+- compatible: Should be "axis,artpec6-pll1-clock"
+- #clock-cells: Should be <1>

What is the clock cell used for?

Quoted 9 lines
Documentation/devicetree/bindings/clock/artpec6.txt new file +8 -0
+Examples:
+
+pll1_clk: pll1_clk {
+	#clock-cells = <1>;
+	compatible = "axis,artpec6-pll1-clock";
+	clocks = <&ext_clk>;
+	status = "okay";
+};
author maintainer
#3 lore raw

PATCH 2/8 clk: add artpec-6 pll1 clock driver

In reply to Lars Persson

The PLL1 clock is a fixed-factor clock with factors derived from boot mode pins. This driver is a simple wrapper to register the fixed factor clock according to the pin settings.

Signed-off-by Lars Persson <[email protected]>
---
 drivers/clk/Makefile      |  1 +
 drivers/clk/clk-artpec6.c | 70 +++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 71 insertions(+)
 create mode 100644 drivers/clk/clk-artpec6.c
drivers/clk/Makefile +1 -0
index b038e36..388f0cf 100644
@@ -17,6 +17,7 @@ endif
 
 # hardware specific clock types
 # please keep this section sorted lexicographically by file/directory path name
+obj-$(CONFIG_MACH_ARTPEC6)		+= clk-artpec6.o
 obj-$(CONFIG_MACH_ASM9260)		+= clk-asm9260.o
 obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN)	+= clk-axi-clkgen.o
 obj-$(CONFIG_ARCH_AXXIA)		+= clk-axm5516.o
drivers/clk/clk-artpec6.c new file +70 -0

70 lines not on this page · raw message

Signature · 1 line
2.1.4
author maintainer
#4 lore raw

PATCH 3/8 arm: add device-tree SoC bindings for Axis Artpec-6

In reply to Lars Persson
Signed-off-by Lars Persson <[email protected]>
---
 Documentation/devicetree/bindings/arm/axis.txt | 8 ++++++++
 1 file changed, 8 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/axis.txt
Documentation/devicetree/bindings/arm/axis.txt new file +8 -0
new file mode 100644
index 0000000..4c98701
@@ -0,0 +1,8 @@
+Axis Communications AB
+ARTPEC series SoC Device Tree Bindings
+
+
+ARTPEC-6 ARM SoC
+
+Required root node properties:
+    - compatible = "axis,artpec6-dev-board", "axis,artpec6";
Signature · 1 line
2.1.4
maintainer
#5 lore raw

Re: [PATCH 3/8] arm: add device-tree SoC bindings for Axis Artpec-6

Quoted 1 line · On Wednesday 10 February 2016 13:41:52 Lars Persson wrote:
Signed-off-by Lars Persson <[email protected]>

Add a changelog

Quoted 11 lines
 Documentation/devicetree/bindings/arm/axis.txt | 8 ++++++++
 1 file changed, 8 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/axis.txt
Documentation/devicetree/bindings/arm/axis.txt new file +0 -0
new file mode 100644
index 0000000..4c98701

Documentation/devicetree/bindings/arm/axis.txt line 8

Quoted 8 lines
Documentation/devicetree/bindings/arm/axis.txt new file +8 -0
@@ -0,0 +1,8 @@
+Axis Communications AB
+ARTPEC series SoC Device Tree Bindings
+
+
+ARTPEC-6 ARM SoC
+
+Required root node properties:
+    - compatible = "axis,artpec6-dev-board", "axis,artpec6";

Requiring "axis,artpec6-dev-board" to be used for all boards somewhat misses the point of board specific compatibility values.

Arnd

author maintainer
#6 lore raw

PATCH 4/8 arm: dts: add Artpec-6 soc dtsi file

In reply to Lars Persson
Signed-off-by Lars Persson <[email protected]>
---
 arch/arm/boot/dts/artpec6.dtsi | 238 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 238 insertions(+)
 create mode 100644 arch/arm/boot/dts/artpec6.dtsi
arch/arm/boot/dts/artpec6.dtsi new file +238 -0
new file mode 100644
index 0000000..c1790d8
@@ -0,0 +1,238 @@
+/*
+ * Device Tree Source for the Axis ARTPEC-6 SoC
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "axis,artpec6";
+	interrupt-parent = <&intc>;
+
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <0>;
+			next-level-cache = <&pl310>;
+		};
+
+		cpu1: cpu at 1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <1>;
+			next-level-cache = <&pl310>;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2", "arm,psci";
+		method = "smc";
+		psci_version = <0x84000000>;
+		cpu_on = <0x84000003>;
+		system_reset = <0x84000009>;
+	};
+
+	scu at faf00000 {
+		compatible = "arm,cortex-a9-scu";
+		reg = <0xfaf00000 0x58>;
+	};
+
+	/* Main external clock driving CPU and peripherals */
+	ext_clk: ext_clk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <50000000>;
+	};
+
+	/* PLL1 is used by CPU and some peripherals */
+	pll1_clk: pll1_clk at f8000000 {
+		#clock-cells = <0>;
+		compatible = "axis,artpec6-pll1-clock";
+		reg = <0xf8000000 4>;
+		clocks = <&ext_clk>;
+	};
+
+	cpu_clk: cpu_clk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clock-div = <1>;
+		clock-mult = <1>;
+		clocks = <&pll1_clk>;
+		clock-output-names = "cpu_clk";
+	};
+
+	cpu_clkdiv2: cpu_clkdiv2 {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clock-div = <2>;
+		clock-mult = <1>;
+		clocks = <&cpu_clk>;
+	};
+
+	cpu_clkdiv4: cpu_clkdiv4 {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clock-div = <4>;
+		clock-mult = <1>;
+		clocks = <&cpu_clk>;
+	};
+
+	apb_pclk: apb_pclk {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clock-div = <8>;
+		clock-mult = <1>;
+		clocks = <&cpu_clk>;
+		clock-output-names = "apb_pclk";
+	};
+
+	/* PLL2 is used by a number of peripherals, including UDL */
+	pll2: pll2 {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clock-div = <1>;
+		clock-mult = <24>;
+		clocks = <&ext_clk>;
+	};
+
+	/* PLL2DIV2 is used by the Fractional Clock Divider, for i2s */
+	pll2div2: pll2div2 {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clock-div = <2>;
+		clock-mult = <1>;
+		clocks = <&pll2>;
+	};
+
+	pll2div12: pll2div12 {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clock-div = <12>;
+		clock-mult = <1>;
+		clocks = <&pll2>;
+	};
+
+	pll2div24: pll2div24 {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clock-div = <24>;
+		clock-mult = <1>;
+		clocks = <&pll2>;
+		clock-output-names = "uart_clk";
+	};
+
+
+	gtimer at faf00200 {
+		compatible = "arm,cortex-a9-global-timer";
+		reg = <0xfaf00200 0x20>;
+		interrupts = <GIC_PPI 11 0xf01>;
+		clocks = <&cpu_clkdiv2>;
+	};
+
+	timer at faf00600 {
+		compatible = "arm,cortex-a9-twd-timer";
+		reg = <0xfaf00600 0x20>;
+		interrupts = <GIC_PPI 13 0xf04>;
+		clocks = <&cpu_clkdiv2>;
+		status = "disabled";
+	};
+
+	intc: interrupt-controller at faf01000 {
+		interrupt-controller;
+		compatible = "arm,cortex-a9-gic";
+		#interrupt-cells = <3>;
+		reg = < 0xfaf01000 0x1000 >, < 0xfaf00100 0x0100 >;
+	};
+
+	pl310: cache-controller at faf10000 {
+		compatible = "arm,pl310-cache";
+		cache-unified;
+		cache-level = <2>;
+		reg = <0xfaf10000 0x1000>;
+		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+		arm,data-latency = <1 1 1>;
+		arm,tag-latency = <1 1 1>;
+		arm,filter-ranges = <0x0 0x80000000>;
+	};
+
+	pmu {
+		compatible = "arm,cortex-a9-pmu";
+		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-parent = <&intc>;
+	};
+
+	amba at 0 {
+		compatible = "simple-bus";
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		interrupt-parent = <&intc>;
+		ranges;
+		dma-ranges = <0x80000000 0x00000000 0x40000000>;
+		dma-coherent;
+
+		ethernet: ethernet at f8010000 {
+			clock-names = "phy_ref_clk", "apb_pclk";
+			clocks = <&ext_clk>, <&apb_pclk>;
+			compatible = "snps,dwc-qos-ethernet-4.10";
+			interrupt-parent = <&intc>;
+			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+			reg = <0xf8010000 0x4000>;
+
+			snps,write-requests = <2>;
+			snps,read-requests = <16>;
+			snps,txpbl = <8>;
+			snps,rxpbl = <2>;
+
+			status = "disabled";
+		};
+
+		uart0: uart at f8036000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0xf8036000 0x1000>;
+			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pll2div24>, <&apb_pclk>;
+			clock-names = "uart_clk", "apb_pclk";
+			status = "disabled";
+		};
+		uart1: uart at f8037000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0xf8037000 0x1000>;
+			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pll2div24>, <&apb_pclk>;
+			clock-names = "uart_clk", "apb_pclk";
+			status = "disabled";
+		};
+		uart2: uart at f8038000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0xf8038000 0x1000>;
+			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pll2div24>, <&apb_pclk>;
+			clock-names = "uart_clk", "apb_pclk";
+			status = "disabled";
+		};
+		uart3: uart at f8039000 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0xf8039000 0x1000>;
+			interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pll2div24>, <&apb_pclk>;
+			clock-names = "uart_clk", "apb_pclk";
+			status = "disabled";
+		};
+	};
+};
Signature · 1 line
2.1.4
maintainer
#7 lore raw

Re: [PATCH 4/8] arm: dts: add Artpec-6 soc dtsi file

Quoted 2 lines · On Wednesday 10 February 2016 13:41:53 Lars Persson wrote:
Signed-off-by Lars Persson <[email protected]>

---

Missing changelog

Quoted 21 lines
 arch/arm/boot/dts/artpec6.dtsi | 238 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 238 insertions(+)
 create mode 100644 arch/arm/boot/dts/artpec6.dtsi
arch/arm/boot/dts/artpec6.dtsi new file +11 -0
new file mode 100644
index 0000000..c1790d8
@@ -0,0 +1,238 @@
+/*
+ * Device Tree Source for the Axis ARTPEC-6 SoC
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "skeleton.dtsi"
+

arch/arm/boot/dts/artpec6.dtsi line 21

Quoted 10 lines
arch/arm/boot/dts/artpec6.dtsi new file +10 -0
+/ {
+	compatible = "axis,artpec6";
+	interrupt-parent = <&intc>;
+
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+	};

Move the aliases into the board, not all boards might use all four uarts, or some board might assign different numbers.

arch/arm/boot/dts/artpec6.dtsi line 205

Quoted 1 line
arch/arm/boot/dts/artpec6.dtsi new file +1 -0
+		uart0: uart at f8036000 {

make this "serial at f8036000"

Arnd

author maintainer
#8 lore raw

PATCH 5/8 arm: dts: add Artpec-6 development board dts

In reply to Lars Persson
Signed-off-by Lars Persson <[email protected]>
---
 arch/arm/boot/dts/Makefile             |  2 ++
 arch/arm/boot/dts/artpec6-devboard.dts | 57 ++++++++++++++++++++++++++++++++++
 2 files changed, 59 insertions(+)
 create mode 100644 arch/arm/boot/dts/artpec6-devboard.dts
arch/arm/boot/dts/Makefile +2 -0
index a4a6d70..2ebe99c 100644
@@ -2,6 +2,8 @@ ifeq ($(CONFIG_OF),y)
 
 dtb-$(CONFIG_ARCH_ALPINE) += \
 	alpine-db.dtb
+dtb-$(CONFIG_MACH_ARTPEC6) += \
+	artpec6-devboard.dtb
 dtb-$(CONFIG_MACH_ASM9260) += \
 	alphascale-asm9260-devkit.dtb
 # Keep at91 dtb files sorted alphabetically for each SoC
arch/arm/boot/dts/artpec6-devboard.dts new file +57 -0

57 lines not on this page · raw message

Signature · 1 line
2.1.4
author maintainer
#9 lore raw

PATCH 6/8 arm: initial machine port for artpec-6 SoC

In reply to Lars Persson

Basic machine port for the Artpec-6 SoC from Axis
Communications.

Signed-off-by Lars Persson <[email protected]>
---
 arch/arm/Kconfig                     |  2 ++
 arch/arm/Makefile                    |  1 +
 arch/arm/mach-artpec/Kconfig         | 22 ++++++++++++
 arch/arm/mach-artpec/Makefile        |  1 +
 arch/arm/mach-artpec/board-artpec6.c | 66 ++++++++++++++++++++++++++++++++++++
 5 files changed, 92 insertions(+)
 create mode 100644 arch/arm/mach-artpec/Kconfig
 create mode 100644 arch/arm/mach-artpec/Makefile
 create mode 100644 arch/arm/mach-artpec/board-artpec6.c
arch/arm/Kconfig +2 -0
index 4f799e5..e1565dd 100644
@@ -724,6 +724,8 @@ source "arch/arm/mach-mvebu/Kconfig"
 
 source "arch/arm/mach-alpine/Kconfig"
 
+source "arch/arm/mach-artpec/Kconfig"
+
 source "arch/arm/mach-asm9260/Kconfig"
 
 source "arch/arm/mach-at91/Kconfig"
arch/arm/Makefile +1 -0
index fe25410..4eb24c6 100644
@@ -154,6 +154,7 @@ textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
 # Machine directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
 machine-$(CONFIG_ARCH_ALPINE)		+= alpine
+machine-$(CONFIG_ARCH_ARTPEC)		+= artpec
 machine-$(CONFIG_ARCH_AT91)		+= at91
 machine-$(CONFIG_ARCH_AXXIA)		+= axxia
 machine-$(CONFIG_ARCH_BCM)		+= bcm
arch/arm/mach-artpec/Kconfig new file +22 -0
new file mode 100644
index 0000000..eaa73d6
@@ -0,0 +1,22 @@
+menuconfig ARCH_ARTPEC
+	bool "Axis Communications ARM based ARTPEC SoCs" if ARCH_MULTI_V7
+
+if ARCH_ARTPEC
+
+config MACH_ARTPEC6
+	bool "Axis ARTPEC-6 ARM Cortex A9 Platform" if ARCH_MULTI_V7
+	select ARM_AMBA
+	select ARM_GIC
+	select ARM_GLOBAL_TIMER
+	select ARM_PSCI
+	select COMMON_CLK
+	select GENERIC_CLOCKEVENTS
+	select HAVE_ARM_ARCH_TIMER
+	select HAVE_ARM_SCU
+	select HAVE_ARM_TWD if SMP
+	select SPARSE_IRQ
+	select USE_OF
+	help
+	  Support for Axis ARTPEC-6 ARM Cortex A9 Platform
+
+endif
arch/arm/mach-artpec/Makefile new file +1 -0
new file mode 100644
index 0000000..78325f0
@@ -0,0 +1 @@
+obj-$(CONFIG_MACH_ARTPEC6)		:= board-artpec6.o
arch/arm/mach-artpec/board-artpec6.c new file +66 -0

66 lines not on this page · raw message

Signature · 1 line
2.1.4
maintainer
#10 lore raw

Re: [PATCH 6/8] arm: initial machine port for artpec-6 SoC

arch/arm/mach-artpec/Kconfig line 7

Quoted 8 lines · On Wednesday 10 February 2016 13:41:55 Lars Persson wrote:
arch/arm/mach-artpec/Kconfig new file +7 -0
@@ -0,0 +1,22 @@
+menuconfig ARCH_ARTPEC
+	bool "Axis Communications ARM based ARTPEC SoCs" if ARCH_MULTI_V7
+
+if ARCH_ARTPEC
+
+config MACH_ARTPEC6
+	bool "Axis ARTPEC-6 ARM Cortex A9 Platform" if ARCH_MULTI_V7

Change both to use

depends on ARCH_MULTI_V7

like we changed all other platforms in 4.5

arch/arm/mach-artpec/Kconfig line 18

Quoted 11 lines
arch/arm/mach-artpec/Kconfig new file +11 -0
+	select ARM_AMBA
+	select ARM_GIC
+	select ARM_GLOBAL_TIMER
+	select ARM_PSCI
+	select COMMON_CLK
+	select GENERIC_CLOCKEVENTS
+	select HAVE_ARM_ARCH_TIMER
+	select HAVE_ARM_SCU
+	select HAVE_ARM_TWD if SMP
+	select SPARSE_IRQ
+	select USE_OF

No need for GENERIC_CLOCKEVENTS, COMMON_CLK, USE_OF or SPARSE_IRQ to be selected, they are always enabled with ARCH_MULTIPLATFORM. Check the others as well to see if you can drop more of them.

Quoted 6 lines
arch/arm/mach-artpec/board-artpec6.c new file +6 -0
+
+#define ARTPEC6_DMACFG 0xf8000010
+#define ARTPEC6_DMACFG_UARTS_BURST 0xff
+
+#define SECURE_OP_L2C_WRITEREG 0xb4000001
+

arch/arm/mach-artpec/board-artpec6.c line 39

Quoted 10 lines
arch/arm/mach-artpec/board-artpec6.c new file +10 -0
+static void __init artpec6_init_machine(void)
+{
+	void __iomem *dmacfg;
+
+	/* Use PL011 DMA Burst Request signal instead of DMA Single Request */
+	dmacfg = ioremap(ARTPEC6_DMACFG, 4);
+	if (dmacfg) {
+		__raw_writel(ARTPEC6_DMACFG_UARTS_BURST, dmacfg);
+		iounmap(dmacfg);
+	}

Can you do this in the bootloader?

If not, please use a DT node to pass the address rather than hardcoding it, and use writel() instead of __raw_writel() so it works with on big-endian kernels.

arch/arm/mach-artpec/board-artpec6.c line 66

Quoted 9 lines
arch/arm/mach-artpec/board-artpec6.c new file +8 -0
+DT_MACHINE_START(ARTPEC6, "Axis ARTPEC-6 Platform")
+	.l2c_aux_val	= 0x0C000000,
+	.l2c_aux_mask	= 0xF3FFFFFF,
+	.l2c_write_sec  = artpec6_l2c310_write_sec,
+	.init_irq	= irqchip_init,
+	.init_machine	= artpec6_init_machine,
+	.dt_compat	= artpec6_dt_match,
+MACHINE_END

You can drop the irqchip_init.

Arnd

author maintainer
#11 lore raw

PATCH 7/8 arm: multi_v7_defconfig: add MACH_ARTPEC6

In reply to Lars Persson
Signed-off-by Lars Persson <[email protected]>
---
 arch/arm/configs/multi_v7_defconfig | 2 ++
 1 file changed, 2 insertions(+)
arch/arm/configs/multi_v7_defconfig +2 -0
index 8e8b2ac..bf3840e 100644
@@ -16,6 +16,8 @@ CONFIG_ARCH_MULTI_V7=y
 # CONFIG_ARCH_MULTI_V4 is not set
 CONFIG_ARCH_VIRT=y
 CONFIG_ARCH_ALPINE=y
+CONFIG_ARCH_ARTPEC=y
+CONFIG_MACH_ARTPEC6=y
 CONFIG_ARCH_MVEBU=y
 CONFIG_MACH_ARMADA_370=y
 CONFIG_MACH_ARMADA_375=y
Signature · 1 line
2.1.4
maintainer
#12 lore raw

Re: [PATCH 7/8] arm: multi_v7_defconfig: add MACH_ARTPEC6

Quoted 11 lines · On Wednesday 10 February 2016 13:41:56 Lars Persson wrote:
Signed-off-by Lars Persson <[email protected]>
---
 arch/arm/configs/multi_v7_defconfig | 2 ++
 1 file changed, 2 insertions(+)
arch/arm/configs/multi_v7_defconfig +0 -0
index 8e8b2ac..bf3840e 100644

arch/arm/configs/multi_v7_defconfig CONFIG_ARCH_MULTI_V7=y · line 23

Quoted 8 lines
arch/arm/configs/multi_v7_defconfig +2 -0
@@ -16,6 +16,8 @@ CONFIG_ARCH_MULTI_V7=y
 # CONFIG_ARCH_MULTI_V4 is not set
 CONFIG_ARCH_VIRT=y
 CONFIG_ARCH_ALPINE=y
+CONFIG_ARCH_ARTPEC=y
+CONFIG_MACH_ARTPEC6=y
 CONFIG_ARCH_MVEBU=y
 CONFIG_MACH_ARMADA_370=y
 CONFIG_MACH_ARMADA_375=y

No other drivers that you need here?

Arnd

author maintainer
#13 lore raw

PATCH 8/8 arm: mach-artpec: add entry to MAINTAINERS

In reply to Lars Persson
Signed-off-by Lars Persson <[email protected]>
Signed-off-by Jesper Nilsson <[email protected]>
---
 MAINTAINERS | 10 ++++++++++
 1 file changed, 10 insertions(+)
MAINTAINERS +10 -0
index 7f1fa4f..d32c1aa 100644
@@ -932,6 +932,16 @@ M:	Tsahee Zidenberg <[email protected]>
 S:	Maintained
 F:	arch/arm/mach-alpine/
 
+ARM/ARTPEC MACHINE SUPPORT
+M:	Jesper Nilsson <[email protected]>
+M:	Lars Persson <[email protected]>
+M:	Niklas Cassel <[email protected]>
+S:	Maintained
+L:	linux-arm-kernel at axis.com
+F:	arch/arm/mach-artpec
+F:	arch/arm/boot/dts/artpec6*
+F:	drivers/clk/clk-artpec6.c
+
 ARM/ATMEL AT91RM9200, AT91SAM9 AND SAMA5 SOC SUPPORT
 M:	Nicolas Ferre <[email protected]>
 M:	Alexandre Belloni <[email protected]>
Signature · 1 line
2.1.4
maintainer
#14 lore raw
In reply to Lars Persson
Quoted 3 lines · On Wednesday 10 February 2016 13:41:49 Lars Persson wrote:

Basic support for the Axis Artpec-6 ARM SoC. Timers, interrupts, UARTs and ethernet are wired up.

Hi Lars,

Looks nice overall, I just have a few small comments on some of the patches. Please also add a patch do add yourself in the MAINTAINERS file.

Arnd