clk: sunxi: Add the clocks used for audio/video on sun8i
Subsystems (4)
cover clk: sunxi: Add the clocks used for audio/video on sun8i
This patch series replaces a part of a previous series about "Add a DRM display driver to the Allwinner H3".
I will resubmit the H3 DRM video driver and also submit the H3 components for audio on HDMI as soon as the HDMI PHY of the H3 (and A64) will be known.
Changes:
- simplify and use the 'recalc' callback (Chen-Yu Tsai)
- add a SoC type in the compatibles (Maxime Ripard)
- audio PLL added
Jean-Francois Moine (3):
clk: sunxi: Add sun6i/8i display support
clk: sunxi: Add sun6i/8i PLL video support
clk: sunxi: Add sun8i PLL audio support
Documentation/devicetree/bindings/clock/sunxi.txt | 3 + drivers/clk/sunxi/clk-sunxi.c | 151 ++++++++++++++++++++++ 2 files changed, 154 insertions(+)
Signature · 1 line
2.8.0
PATCH 1/3 clk: sunxi: Add sun6i/8i display support
Add the clock type which is used by the sun6i/8i families for video display.
--- Documentation/devicetree/bindings/clock/sunxi.txt | 1 + drivers/clk/sunxi/clk-sunxi.c | 38 +++++++++++++++++++++++ 2 files changed, 39 insertions(+)
Documentation/devicetree/bindings/clock/sunxi.txt +1 -0
@@ -81,6 +81,7 @@ Required properties: "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80 "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80 "allwinner,sun4i-a10-ve-clk" - for the Video Engine clock + "allwinner,sun6i-a31-display-clk" - for the display clocks Required properties for all clocks: - reg : shall be the control register address for the clock.
drivers/clk/sunxi/clk-sunxi.c +38 -0
@@ -1127,3 +1127,41 @@ static void __init sun6i_pll6_clk_setup(struct device_node *node) }CLK_OF_DECLARE (sun6i_pll6,"allwinner,sun6i-a31-pll6-clk" , sun6i_pll6_clk_setup); + +/* +* sun6i display +* +* rate = parent_rate / (m + 1); +*/ +static void sun6i_display_factors (struct factors_request *req) +{ +u8 m; + +if (req->rate > req->parent_rate) + req->rate = req->parent_rate; + + m =DIV_ROUND_UP (req->parent_rate, req->rate); + + req->rate = req->parent_rate / m; + req->m = m -1 ; +} + +static const struct clk_factors_config sun6i_display_config = { + .mshift =0 , + .mwidth =4 , +}; + +static const struct factors_data sun6i_display_data__initconst = { + .enable =31 , + .mux =24 , + .muxmask =BIT (2 ) |BIT (1 ) |BIT (0 ), + .table = &sun6i_display_config, + .getter = sun6i_display_factors, +}; + +static void __init sun6i_display_setup (struct device_node *node) +{ +sunxi_factors_clk_setup (node, &sun6i_display_data); +} +CLK_OF_DECLARE (sun6i_display,"allwinner,sun6i-a31-display-clk" , + sun6i_display_setup);
Signature · 1 line
2.8.0
Rob Herring
maintainerPATCH 1/3 clk: sunxi: Add sun6i/8i display support
Quoted 5 lines · Jean-Francois Moine
Add the clock type which is used by the sun6i/8i families for video display.
Signed-off-by Jean-Francois Moine <[email protected]>--- Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
Quoted 2 lines
drivers/clk/sunxi/clk-sunxi.c | 38 +++++++++++++++++++++++ 2 files changed, 39 insertions(+)
Maxime Ripard
AppliedPATCH 1/3 clk: sunxi: Add sun6i/8i display support
In reply to Jean-Francois MoineQuoted 3 lines · Jean-Francois Moine
Add the clock type which is used by the sun6i/8i families for video display.
Signed-off-by Jean-Francois Moine <[email protected]>
Applied, thanks
Maxime
Signature · 10 lines
Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20160410/e5effe89/attachment.sig>
PATCH 2/3 clk: sunxi: Add sun6i/8i PLL video support
In reply to Jean-Francois MoineAdd the PLL type which is used by the sun6i/8i families for video display.
--- Documentation/devicetree/bindings/clock/sunxi.txt | 1 + drivers/clk/sunxi/clk-sunxi.c | 65 +++++++++++++++++++++++ 2 files changed, 66 insertions(+)
Documentation/devicetree/bindings/clock/sunxi.txt +1 -0
@@ -10,6 +10,7 @@ Required properties: "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4 "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31 "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23 + "allwinner,sun6i-a31-pll3-clk" - for the video PLL clock "allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80 "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
drivers/clk/sunxi/clk-sunxi.c +65 -0
77 lines not on this page · raw message
Signature · 1 line
2.8.0
Rob Herring
maintainerPATCH 2/3 clk: sunxi: Add sun6i/8i PLL video support
Quoted 5 lines · Jean-Francois Moine
Add the PLL type which is used by the sun6i/8i families for video display.
Signed-off-by Jean-Francois Moine <[email protected]>--- Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
Quoted 2 lines
drivers/clk/sunxi/clk-sunxi.c | 65 +++++++++++++++++++++++ 2 files changed, 66 insertions(+)
PATCH 2/3 clk: sunxi: Add sun6i/8i PLL video support
In reply to Jean-Francois MoineHi,
Quoted 74 lines · Jean-Francois Moine
Add the PLL type which is used by the sun6i/8i families for video display.
Signed-off-by Jean-Francois Moine <[email protected]>--- Documentation/devicetree/bindings/clock/sunxi.txt | 1 + drivers/clk/sunxi/clk-sunxi.c | 65 +++++++++++++++++++++++ 2 files changed, 66 insertions(+)Documentation/devicetree/bindings/clock/sunxi.txt +1
-0@@ -10,6 +10,7 @@ Required properties: "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4 "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31 "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23 + "allwinner,sun6i-a31-pll3-clk" - for the video PLL clock "allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80 "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clockdrivers/clk/sunxi/clk-sunxi.c +39
-0@@ -23,6 +23,7 @@#include <linux/slab.h> #include <linux/spinlock.h> #include <linux/log2.h> +#include <linux/rational.h> #include "clk-factors.h" @@ -1129,6 +1130,70 @@ CLK_OF_DECLARE(sun6i_pll6, "allwinner,sun6i-a31-pll6-clk", sun6i_pll6_clk_setup);/* +* sun6i pll3 +* +* if (p == 0) rate = k ? 270MHz : 297MHz +* else rate = parent_rate / (m + 1) * (n + 1); +*/ +static void sun6i_pll3_factors (struct factors_request *req) +{ +unsigned long n, m; + +if (req->rate ==270000000 ) { + req->m =0 ; + req->p =0 ; + req->k =0 ; + }else if (req->rate ==297000000 ) { + req->m =0 ; + req->p =0 ; + req->k =1 ; + }else { +rational_best_approximation (req->rate, + req->parent_rate, +1 <<7 ,1 <<4 , &n, &m); + req->rate = req->parent_rate / m * n; + req->p =1 ; + req->m = m -1 ; + req->n = n -1 ; + } +} + +static void sun6i_pll3_recalc (struct factors_request *req) +{ +if (req->p) + req->rate = req->parent_rate / (req->m +1 ) * (req->n +1 ); +else if (req->k) + req->rate =270000000 ; +else + req->rate =297000000 ; +} +
drivers/clk/sunxi/clk-sunxi.c CLK_OF_DECLARE(sun6i_pll6, "allwinner,sun6i-a31-pll6-clk", · line 1180
Quoted 10 lines
drivers/clk/sunxi/clk-sunxi.c +10
-0+static const struct clk_factors_config sun6i_pll3_config = { + .mshift =0 , + .mwidth =4 , + .nshift =8 , + .nwidth =7 , + .pshift =24 ,/* mode selection fractional / integer */ + .pwidth =1 , + .kshift =25 ,/* fraction 270 / 297 MHz */ + .kwidth =1 , +};
That's not what p and k are.
Please add extra parameters to deal with fractional rates in the clk_factors_config (like an extra bit + an array with the two rate exposed.
That way, you can also deal with it in the core, instead of doing a hack.
Maxime
Signature · 10 lines
Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20160410/9bcdf800/attachment.sig>
PATCH 2/3 clk: sunxi: Add sun6i/8i PLL video support
Quoted 10 lines · On Sun, 10 Apr 2016 02:50:06 -0700 Maxime Ripard…
Hi,
Quoted 7 lines · Jean-Francois Moine
Add the PLL type which is used by the sun6i/8i families for video display.
Signed-off-by Jean-Francois Moine <[email protected]>--- Documentation/devicetree/bindings/clock/sunxi.txt | 1 + drivers/clk/sunxi/clk-sunxi.c | 65 +++++++++++++++++++++++ 2 files changed, 66 insertions(+)
[snip]
Quoted 67 lines
Quoted 54 lines
drivers/clk/sunxi/clk-sunxi.c +39
-0@@ -23,6 +23,7 @@#include <linux/slab.h> #include <linux/spinlock.h> #include <linux/log2.h> +#include <linux/rational.h> #include "clk-factors.h" @@ -1129,6 +1130,70 @@ CLK_OF_DECLARE(sun6i_pll6, "allwinner,sun6i-a31-pll6-clk", sun6i_pll6_clk_setup);/* +* sun6i pll3 +* +* if (p == 0) rate = k ? 270MHz : 297MHz +* else rate = parent_rate / (m + 1) * (n + 1); +*/ +static void sun6i_pll3_factors (struct factors_request *req) +{ +unsigned long n, m; + +if (req->rate ==270000000 ) { + req->m =0 ; + req->p =0 ; + req->k =0 ; + }else if (req->rate ==297000000 ) { + req->m =0 ; + req->p =0 ; + req->k =1 ; + }else { +rational_best_approximation (req->rate, + req->parent_rate, +1 <<7 ,1 <<4 , &n, &m); + req->rate = req->parent_rate / m * n; + req->p =1 ; + req->m = m -1 ; + req->n = n -1 ; + } +} + +static void sun6i_pll3_recalc (struct factors_request *req) +{ +if (req->p) + req->rate = req->parent_rate / (req->m +1 ) * (req->n +1 ); +else if (req->k) + req->rate =270000000 ; +else + req->rate =297000000 ; +} +drivers/clk/sunxi/clk-sunxi.c CLK_OF_DECLARE(sun6i_pll6, "allwinner,sun6i-a31-pll6-clk", · line 1180
Quoted 10 lines
drivers/clk/sunxi/clk-sunxi.c +10
-0+static const struct clk_factors_config sun6i_pll3_config = { + .mshift =0 , + .mwidth =4 , + .nshift =8 , + .nwidth =7 , + .pshift =24 ,/* mode selection fractional / integer */ + .pwidth =1 , + .kshift =25 ,/* fraction 270 / 297 MHz */ + .kwidth =1 , +};That's not what p and k are.
Quoted 6 lines
Please add extra parameters to deal with fractional rates in the
clk_factors_config(like an extra bit + an array with the two rate exposed.That way, you can also deal with it in the core, instead of doing a hack.
It is really a good way to add generic code for only one clock? Otherwise, there is no 'P' nor 'K' in the pll3 documentation, what is the trouble of using the variables 'p' and 'k' for other functions? And noone said that the variables should have the same name as those of the documentation.
Anyway, I am stupid and obedient: this code was proposed by Chen-Yu Tsai on Sat, 6 Feb 2016 17:56:00 +0800:
Quoted 16 lines
clk-factors now supports a custom .recalc callback. Along with
get_factors, you can support pretty much any clock that has four variables, not including the mux and clock gate.So for this you'd have the div as factor m, and the integer mode bit as p, and the fraction bit as n, and recalc would be somewhat like this:
if (p) { rate = parent_rate / (m + 1); } else if (n) { rate = 297000000; } else { rate = 270000000; }
get_factorsshould be easy enough to figure out.
Signature · 2 lines
Ken ar c'henta? | ** Breizh ha Linux atav! ** Jef | http://moinejf.free.fr/
PATCH 3/3 clk: sunxi: Add sun8i PLL audio support
In reply to Jean-Francois MoineAdd the PLL type which is used by the sun8i family for audio.
--- Documentation/devicetree/bindings/clock/sunxi.txt | 1 + drivers/clk/sunxi/clk-sunxi.c | 48 +++++++++++++++++++++++ 2 files changed, 49 insertions(+)
Documentation/devicetree/bindings/clock/sunxi.txt +1 -0
@@ -10,6 +10,7 @@ Required properties: "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4 "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31 "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23 + "allwinner,sun8i-pll2-clk" - for the audio PLL clock "allwinner,sun6i-a31-pll3-clk" - for the video PLL clock "allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80 "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
drivers/clk/sunxi/clk-sunxi.c +48 -0
54 lines not on this page · raw message
Signature · 1 line
2.8.0
Rob Herring
maintainerPATCH 3/3 clk: sunxi: Add sun8i PLL audio support
Quoted 5 lines · Jean-Francois Moine
Add the PLL type which is used by the sun8i family for audio.
Signed-off-by Jean-Francois Moine <[email protected]>--- Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
And the 1 by 1 sunxi clock bindings continue...
Quoted 2 lines
drivers/clk/sunxi/clk-sunxi.c | 48 +++++++++++++++++++++++ 2 files changed, 49 insertions(+)
PATCH 3/3 clk: sunxi: Add sun8i PLL audio support
In reply to Jean-Francois MoineHi,
Quoted 13 lines · Jean-Francois Moine
Add the PLL type which is used by the sun8i family for audio.
Signed-off-by Jean-Francois Moine <[email protected]>--- Documentation/devicetree/bindings/clock/sunxi.txt | 1 + drivers/clk/sunxi/clk-sunxi.c | 48 +++++++++++++++++++++++ 2 files changed, 49 insertions(+)Documentation/devicetree/bindings/clock/sunxi.txt +0
-0
Documentation/devicetree/bindings/clock/sunxi.txt Required properties: · line 13
Quoted 4 lines
Documentation/devicetree/bindings/clock/sunxi.txt +1
-0@@ -10,6 +10,7 @@ Required properties: "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4 "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31 "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23 + "allwinner,sun8i-pll2-clk" - for the audio PLL clock
You should mention the name of the first SoC that introduced it.
Quoted 8 lines
Documentation/devicetree/bindings/clock/sunxi.txt +0
-0"allwinner,sun6i-a31-pll3-clk" - for the video PLL clock "allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80 "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clockdrivers/clk/sunxi/clk-sunxi.c +0
-0
drivers/clk/sunxi/clk-sunxi.c CLK_OF_DECLARE(sun6i_pll6, "allwinner,sun6i-a31-pll6-clk", · line 1135
Quoted 6 lines
drivers/clk/sunxi/clk-sunxi.c +3
-0@@ -1130,6 +1130,54 @@ CLK_OF_DECLARE(sun6i_pll6, "allwinner,sun6i-a31-pll6-clk", sun6i_pll6_clk_setup);/* +* sun8i pll2 +* +* rate = parent_rate / (m + 1) * (n + 1) / (p + 1);
^ I'm guessing it's a "*" instead?
Quoted 33 lines
drivers/clk/sunxi/clk-sunxi.c +33
-0+*/ +static void sun8i_pll2_factors (struct factors_request *req) +{ +unsigned long n, m; + +/* set p = 4 so that pll2 = pll2x8 / 8 */ + req->p =4 -1 ; +rational_best_approximation (req->rate, + req->parent_rate /4 , +1 <<7 ,1 <<5 , &n, &m); + req->rate = req->parent_rate / m * n /4 ; + req->m = m -1 ; + req->n = n -1 ; +} + +static void sun8i_pll2_recalc (struct factors_request *req) +{ + req->rate = req->parent_rate / (req->m +1 ) * (req->n +1 ) / + (req->p +1 ); +} + +static const struct clk_factors_config sun8i_pll2_config = { + .mshift =0 , + .mwidth =5 , + .nshift =8 , + .nwidth =7 , + .pshift =16 , + .pwidth =4 , +}; + +static const struct factors_data sun8i_pll2_data__initconst = { + .enable =31 , + .table = &sun8i_pll2_config,
drivers/clk/sunxi/clk-sunxi.c CLK_OF_DECLARE(sun6i_pll6, "allwinner,sun6i-a31-pll6-clk", · line 1178
Quoted 10 lines
drivers/clk/sunxi/clk-sunxi.c +10
-0+ .getter = sun8i_pll2_factors, + .recalc = sun8i_pll2_recalc, +}; + +static void __init sun8i_pll2_setup (struct device_node *node) +{ +sunxi_factors_clk_setup (node, &sun8i_pll2_data); +} +CLK_OF_DECLARE (sun8i_pll2,"allwinner,sun8i-pll2-clk" , + sun8i_pll2_setup);
How do you plan on supporting the multiple pll2 output?
Thanks,
Maxime
Signature · 10 lines
Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20160410/1d3f6c27/attachment.sig>
PATCH 3/3 clk: sunxi: Add sun8i PLL audio support
Quoted 11 lines · On Sun, 10 Apr 2016 02:53:22 -0700 Maxime Ripard…
Hi,
Quoted 8 lines · Jean-Francois Moine
Add the PLL type which is used by the sun8i family for audio.
Signed-off-by Jean-Francois Moine <[email protected]>--- Documentation/devicetree/bindings/clock/sunxi.txt | 1 + drivers/clk/sunxi/clk-sunxi.c | 48 +++++++++++++++++++++++ 2 files changed, 49 insertions(+)
Quoted 11 lines
Documentation/devicetree/bindings/clock/sunxi.txt Required properties: · line 13
Quoted 9 lines
Documentation/devicetree/bindings/clock/sunxi.txt +1
-0@@ -10,6 +10,7 @@ Required properties: "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4 "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31 "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23 + "allwinner,sun8i-pll2-clk" - for the audio PLL clockYou should mention the name of the first SoC that introduced it.
As I know only the pll2 of the H3, is it OK for
"allwinner,sun8i-h3-pll2-clk"
?
Quoted 10 lines
Quoted 10 lines
Documentation/devicetree/bindings/clock/sunxi.txt +0
-0"allwinner,sun6i-a31-pll3-clk" - for the video PLL clock "allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80 "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clockdrivers/clk/sunxi/clk-sunxi.c +0
-0@@ -1130,6 +1130,54 @@ CLK_OF_DECLARE(sun6i_pll6, "allwinner,sun6i-a31-pll6-clk", sun6i_pll6_clk_setup);
Quoted 6 lines
drivers/clk/sunxi/clk-sunxi.c CLK_OF_DECLARE(sun6i_pll6, "allwinner,sun6i-a31-pll6-clk", · line 1135
Quoted 4 lines
drivers/clk/sunxi/clk-sunxi.c +3
-0/* +* sun8i pll2 +* +* rate = parent_rate / (m + 1) * (n + 1) / (p + 1); ^ I'm guessing it's a "*" instead?
No, 'm' is a divider, as 'p'.
Quoted 37 lines
Quoted 37 lines
drivers/clk/sunxi/clk-sunxi.c +37
-0+*/ +static void sun8i_pll2_factors (struct factors_request *req) +{ +unsigned long n, m; + +/* set p = 4 so that pll2 = pll2x8 / 8 */ + req->p =4 -1 ; +rational_best_approximation (req->rate, + req->parent_rate /4 , +1 <<7 ,1 <<5 , &n, &m); + req->rate = req->parent_rate / m * n /4 ; + req->m = m -1 ; + req->n = n -1 ; +} + +static void sun8i_pll2_recalc (struct factors_request *req) +{ + req->rate = req->parent_rate / (req->m +1 ) * (req->n +1 ) / + (req->p +1 ); +} + +static const struct clk_factors_config sun8i_pll2_config = { + .mshift =0 , + .mwidth =5 , + .nshift =8 , + .nwidth =7 , + .pshift =16 , + .pwidth =4 , +}; + +static const struct factors_data sun8i_pll2_data__initconst = { + .enable =31 , + .table = &sun8i_pll2_config, + .getter = sun8i_pll2_factors, + .recalc = sun8i_pll2_recalc, +}; +
Quoted 8 lines
drivers/clk/sunxi/clk-sunxi.c CLK_OF_DECLARE(sun6i_pll6, "allwinner,sun6i-a31-pll6-clk", · line 1178
Quoted 6 lines
drivers/clk/sunxi/clk-sunxi.c +6
-0+static void __init sun8i_pll2_setup (struct device_node *node) +{ +sunxi_factors_clk_setup (node, &sun8i_pll2_data); +} +CLK_OF_DECLARE (sun8i_pll2,"allwinner,sun8i-pll2-clk" , + sun8i_pll2_setup);How do you plan on supporting the multiple pll2 output?
Using fixed-clocks in the DTS if needed.
Signature · 2 lines
Ken ar c'henta? | ** Breizh ha Linux atav! ** Jef | http://moinejf.free.fr/